74CBT16212ADGGRE4 [TI]
24-BIT FET BUS-EXCHANGE SWITCHES; 24位FET总线交换开关系列
| 型号： | 74CBT16212ADGGRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-BIT FET BUS-EXCHANGE SWITCHES |
| 文件： | 总14页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢉ ꢊꢋ ꢀꢁ ꢌꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇꢉꢊ
ꢉ ꢃ ꢍꢅꢎ ꢆ ꢏ ꢐꢆ ꢅꢑꢀ ꢍꢐꢒꢄ ꢓꢊꢁꢔ ꢐ ꢀ ꢕꢎ ꢆꢄ ꢓꢐ ꢀ
SCDS007U − NOVEMBER 1992 − REVISED JUNE 2005
SN54CBT16212A . . . WD PACKAGE
SN74CBT16212A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
D
Members of the Texas Instruments
Widebus Family
D
D
D
D
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
1
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
56
S1
2
55 S2
Latch-Up Performance Exceeds 250 mA Per
JESD 17
3
54 1B1
53 1B2
52 2B1
51 2B2
50 3B1
49 GND
48 3B2
47 4B1
46 4B2
45 5B1
44 5B2
43 6B1
42 6B2
41 7B1
40 7B2
39 8B1
38 GND
37 8B2
36 9B1
35 9B2
4
ESD Protection Exceeds JESD 22
− 200-V Machine Model (A115-A)
5
6
7
description/ordering information
8
The ’CBT16212A devices provide 24 bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Each device operates as a 24-bit bus switch or a
12-bit bus exchanger that provides data
exchanging between the four signal ports via the
data-select (S0, S1, S2) terminals.
V
CC
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
34
33
32
31
30
29
10B1
10B2
11B1
11B2
12B1
12B2
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74CBT16212ADL
SSOP − DL
CBT16212A
Tape and reel
Tape and reel
Tape and reel
SN74CBT16212ADLR
SN74CBT16212ADGGR
SN74CBT16212ADGVR
SN74CBT16212AGQLR
SN74CBT16212AZQLR
SNJ54CBT16212AWD
TSSOP − DGG
TVSOP − DGV
VFBGA − GQL
CBT16212A
CY212A
−40°C to 85°C
−55°C to 125°C
Tape and reel
Tube
CY212A
VFBGA − ZQL (Pb-free)
CFP − WD
SNJ54CBT16212AWD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2005, Texas Instruments Incorporated
ꢘ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢰꢎ ꢱꢍ ꢖꢗ ꢏ ꢍꢲꢳꢂ ꢲꢂꢋ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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ꢤ ꢛꢨ ꢥꢢꢢ ꢝ ꢡꢫꢥ ꢞ ꢭꢚ ꢢꢥ ꢛ ꢝꢡꢥ ꢩꢪ ꢘ ꢛ ꢠꢨ ꢨ ꢝ ꢡꢫꢥ ꢞ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢢ ꢋ ꢦꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝ ꢛ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ ꢉꢊ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢇ ꢉꢊ
ꢉꢃ ꢍꢅꢎ ꢆ ꢏ ꢐꢆ ꢅ ꢑꢀ ꢍꢐ ꢒꢄ ꢓꢊꢁ ꢔꢐ ꢀ ꢕꢎ ꢆ ꢄꢓ ꢐ ꢀ
SCDS007U − NOVEMBER 1992 − REVISED JUNE 2005
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A
B
C
D
E
F
1A2
3A1
4A1
5A2
6A2
7A1
1A1
2A2
GND
4A2
6A1
7A2
GND
9A1
10A2
12A1
S0
S1
S2
1B1
2B2
3B2
5B1
6B1
6B2
7B2
8B2
10B1
11B2
2A1
3A2
5A1
1B2
3B1
4B2
2B1
GND
4B1
5B2
7B1
GND
9B1
10B2
12B1
G
H
J
V
CC
8A1
9A2
8B1
9B2
G
H
J
8A2
10A1
11A2
11A1
12A2
11B1
12B2
K
K
FUNCTION TABLE
INPUTS/OUTPUTS
INPUTS
FUNCTION
S2
L
S1
L
S0
L
A1
A2
Z
Z
Disconnect
L
L
H
L
B1 port
Z
Z
A1 port = B1 port
A1 port = B2 port
A2 port = B1 port
A2 port = B2 port
Disconnect
L
H
H
L
B2 port
L
H
L
Z
Z
Z
B1 port
B2 port
Z
H
H
L
H
A1 port = B1 port
A2 port = B2 port
H
H
H
H
L
B1 port
B2 port
B2 port
B1 port
A1 port = B2 port
A2 port = B1 port
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢇꢉ ꢊ
ꢉ ꢃ ꢍꢅꢎ ꢆ ꢏ ꢐꢆ ꢅꢑꢀ ꢍꢐꢒꢄ ꢓꢊꢁꢔ ꢐ ꢀ ꢕꢎ ꢆꢄ ꢓꢐ ꢀ
SCDS007U − NOVEMBER 1992 − REVISED JUNE 2005
logic diagram (positive logic)
2
54
1A1
1B1
3
53
1A2
1B2
30
27
12A1
12B1
28
29
12B2
12A2
1
S0
56
S1
55
S2
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢇ ꢉꢊ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢇ ꢉꢊ
ꢉꢃ ꢍꢅꢎ ꢆ ꢏ ꢐꢆ ꢅ ꢑꢀ ꢍꢐ ꢒꢄ ꢓꢊꢁ ꢔꢐ ꢀ ꢕꢎ ꢆ ꢄꢓ ꢐ ꢀ
SCDS007U − NOVEMBER 1992 − REVISED JUNE 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54CBT16212A SN74CBT16212A
UNIT
MIN
4
MAX
MIN
4
MAX
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
2
0.8
0.8
85
V
T
A
−55
125
−40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54CBT16212A
SN74CBT16212A
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
‡
‡
MIN TYP
MAX
−1.2
10
MIN TYP
MAX
−1.2
10
V
V
V
V
V
V
= 4.5 V,
= 0,
V
IK
CC
CC
CC
CC
CC
I
V = 5.5 V
I
I
I
µA
µA
I
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
I
1
1
I
O
= 0, V = V
CC
or GND
3.2
3
CC
I
= 5.5 V, One input at 3.4 V,
or GND
§
∆I
CC
Control inputs
2.5
2.5
20
mA
Other inputs at V
CC
C
C
Control inputs V = 3 V or 0
2.5
7.5
2.5
7.5
pF
pF
i
I
V
O
= 3 V or 0,
S0, S1, and S2 = GND
io(off)
V
= 4 V,
CC
V = 2.4 V, I = 15 mA
I
14
20
14
I
TYP at V
= 4 V
CC
¶
I = 64 mA
I
4
4
6
10
10
14
4
4
6
7
7
Ω
r
on
V = 0
I
V
CC
= 4.5 V
I = 30 mA
I
V = 2.4 V, I = 15 mA
12
I
I
‡
§
¶
All typical values are at V
= 5 V (unless otherwise noted), T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢇꢉ ꢊ
ꢉ ꢃ ꢍꢅꢎ ꢆ ꢏ ꢐꢆ ꢅꢑꢀ ꢍꢐꢒꢄ ꢓꢊꢁꢔ ꢐ ꢀ ꢕꢎ ꢆꢄ ꢓꢐ ꢀ
SCDS007U − NOVEMBER 1992 − REVISED JUNE 2005
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54CBT16212A
= 5 V
SN74CBT16212A
= 5 V
V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
0.5 V
CC
0.5 V
V
CC
= 4 V
V
CC
= 4 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
†
t
pd
A or B
B or A
0.8*
0.35
0.25
ns
S
S
S
A or B
A or B
A or B
14
15
1.5
1.5
1.5
13
13.7
13.5
10
10.4
9.2
1.5
1.5
1.5
9.1
9.7
8.8
ns
ns
ns
t
t
t
pd
en
dis
14.2
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
S1
Open
GND
500 Ω
t
Open
7 V
From Output
Under Test
pd
/t
t
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
− 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9852101QXA
ACTIVE
ACTIVE
CFP
WD
56
56
1
TBD
A42 SNPB
N / A for Pkg Type
74CBT16212ADGGRE4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74CBT16212ADGVRE4
SN74CBT16212ADGGR
SN74CBT16212ADGVR
SN74CBT16212ADL
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
TVSOP
TSSOP
TVSOP
SSOP
SSOP
SSOP
SSOP
DGV
DGG
DGV
DL
56
56
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16212ADLG4
SN74CBT16212ADLR
SN74CBT16212ADLRG4
SN74CBT16212AGQLR
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN74CBT16212AZQLR
SNJ54CBT16212AWD
ACTIVE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
WD
56
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
A42 SNPB
CFP
1
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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