74AVCH1T45DBVTE4 [TI]
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION ND 3-STATE OUTPUTS; 可配置电压转换ND三态输出的单位双电源总线收发器
| 型号： | 74AVCH1T45DBVTE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION ND 3-STATE OUTPUTS |
| 文件： | 总34页 (文件大小：1540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
1
FEATURES
2
•
Available in the Texas Instruments NanoStar™
DBV OR DCK PACKAGE
(TOP VIEW)
and NanoFree™ Packages
•
•
Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage
1
2
3
6
5
4
VCCA
GND
A
VCCB
DIR
B
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
•
•
I/Os Are 4.6-V Tolerant
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Ioff Supports Partial-Power-Down Mode
Operation
3
2
1
4
5
6
A
GND
VCCA
B
DIR
VCCB
•
•
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Typical Max Data Rates
–
–
–
–
–
380 Mbps (1.8-V to 3.3-V Translation)
200 Mbps (<1.8-V to 3.3-V Translation)
200 Mbps (Translate to 2.5 V or 1.8 V)
150 Mbps (Translate to 1.5 V)
100 Mbps (Translate to 1.2 V)
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH1T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
The SN74AVCH1T45 is designed so that the DIR input is powered by VCCA
.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
Tape and reel
SN74AVCH1T45YZPR
_ _ _TF_
–40°C to 85°C
Tape and reel
Tape and reel
SN74AVCH1T45DBVR
SN74AVCH1T45DCKR
ET1_
TF_
SOT (SC-70) – DCK
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D–JULY 2004–REVISED JANUARY 2008
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
FUNCTION TABLE
INPUT
OPERATION
DIR
L
B data to A bus
A data to B bus
H
LOGIC DIAGRAM (POSITIVE LOGIC)
5
3
DIR
A
4
B
V
CCA
V
CCB
2
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Product Folder Link(s): SN74AVCH1T45
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
VCCB
–0.5
4.6
V
I/O ports (A port)
I/O ports (B port)
Control inputs
A port
–0.5
–0.5
–0.5
–0.5
–0.5
4.6
4.6
4.6
4.6
4.6
VI
Input voltage range(2)
V
Voltage range applied to any output in the high-impedance or
power-off state(2)
VO
VO
V
V
B port
A port
–0.5 VCCA + 0.5
Voltage range applied to any output in the high or low state(2)(3)
B port
–0.5 VCCB + 0.5
IIK
IOK
IO
Input clamp current
VI < 0
–50
–50
±50
mA
mA
mA
mA
Output clamp current
VO < 0
Continuous output current
Continuous current through VCCA, VCCB, or GND
±100
165
259
123
DBV package
DCK package
YZP package
θJA
Package thermal impedance(4)
°C/W
°C
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2004–2008, Texas Instruments Incorporated
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SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D–JULY 2004–REVISED JANUARY 2008
www.ti.com
Recommended Operating Conditions(1)(2)(3)(4)(5)
VCCI
VCCO
MIN
MAX UNIT
VCCA
VCCB
Supply voltage
Supply voltage
1.2
3.6
3.6
V
V
1.2
CCI × 0.65
1.6
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.2 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
V
High-level
input voltage
VIH
VIL
VIH
VIL
Data inputs(4)
Data inputs(4)
V
V
V
V
2
V
CCI × 0.35
Low-level
input voltage
0.7
0.8
V
CCA × 0.65
High-level
input voltage
DIR
1.6
2
(5)
(5)
(referenced to VCCA
)
)
V
CCA × 0.35
Low-level
input voltage
DIR
0.7
0.8
3.6
VCCO
3.6
–3
–6
–8
–9
–12
3
(referenced to VCCA
VI
Input voltage
0
0
0
V
V
Active state
3-state
VO
Output voltage
1.2 V
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
1.2 V
IOH
High-level output current
Low-level output current
mA
mA
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
6
IOL
8
9
12
5
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–40
85
°C
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(4) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
(5) For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
4
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Product Folder Link(s): SN74AVCH1T45
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
Electrical Characteristics(1)(2)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
–40°C to 85°C
MIN MAX
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCCA
VCCB
UNIT
MIN
TYP
MAX
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
1.2 V
VCCO – 0.2 V
IOH = –3 mA
IOH = –6 mA
IOH = –8 mA
IOH = –9 mA
IOH = –12 mA
IOL = 100 A
IOL = 3 mA
IOL = 6 mA
IOL = 8 mA
IOL = 9 mA
IOL = 12 mA
VI = VCCA or GND
VI = 0.42 V
VI = 0.49 V
VI = 0.58 V
VI = 0.7 V
0.95
1.4 V
1.4 V
1.05
1.2
VOH
VI = VIH
V
1.65 V
2.3 V
1.65 V
2.3 V
1.75
2.3
3 V
3 V
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
1.2 V
0.2
0.15
1.4 V
1.4 V
0.35
0.45
0.55
0.7
VOL
VI = VIL
V
1.65 V
2.3 V
1.65 V
2.3 V
3 V
3 V
II
DIR
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
1.2 V
±0.025 ±0.25
25
±1
µA
µA
1.4 V
1.4 V
15
25
(3)
IBHL
1.65 V
2.3 V
1.65 V
2.3 V
45
VI = 0.8 V
3.3 V
3.3 V
100
VI = 0.78 V
VI = 0.91 V
VI = 1.07 V
VI = 1.6 V
1.2 V
1.2 V
–25
1.4 V
1.4 V
–15
–25
(4)
IBHH
1.65 V
2.3 V
1.65 V
2.3 V
µA
µA
µA
–45
VI = 2 V
3.3 V
3.3 V
–100
1.2 V
1.2 V
50
1.6 V
1.6 V
125
200
300
500
(5)
IBHLO
VI = 0 to VCC
1.95 V
2.7 V
1.95 V
2.7 V
3.6 V
3.6 V
1.2 V
1.2 V
–50
1.6 V
1.6 V
–125
–200
–300
–500
(6)
IBHHO
VI = 0 to VCC
1.95 V
2.7 V
1.95 V
2.7 V
3.6 V
3.6 V
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
(3) The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
(4) The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
(5) An external driver must source at least IBHLO to switch this node from low to high.
(6) An external driver must sink at least IBHHO to switch this node from high to low.
Copyright © 2004–2008, Texas Instruments Incorporated
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SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D–JULY 2004–REVISED JANUARY 2008
www.ti.com
Electrical Characteristics(1)(2) (Continued)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
–40°C to 85°C
PARAMETER
TEST CONDITIONS
VCCA
VCCB
UNIT
MIN
MAX
±1
MIN
MAX
±5
±5
5
A port
0 V
0 to 3.6 V
0 V
0 to 3.6 V
0 V
±0.1
Ioff
VI or VO = 0 to 3.6 V
µA
µA
B port
B port
A port
±0.1
±1
3.6 V
0 V
±0.5
±2.5
±2.5
VO = VCCO or GND,
VI = VCCI or GND
IOZ
3.6 V
±0.5
5
1.2 V to 3.6 V 1.2 V to 3.6 V
10
–2
10
10
10
–2
20
ICCA
VI = VCCI or GND,
VI = VCCI or GND,
IO = 0
0 V
3.6 V
0 V
µA
µA
3.6 V
1.2 V to 3.6 V 1.2 V to 3.6 V
ICCB
IO = 0
IO = 0
0 V
3.6 V
0 V
3.6 V
ICCA + ICCB
VI = VCCI or GND,
VI = 3.3 V or GND
1.2 V to 3.6 V 1.2 V to 3.6 V
µA
Control
inputs
Ci
3.3 V
3.3 V
3.3 V
3.3 V
2.5
6
pF
A or B
port
Cio
VO = 3.3 V or GND
pF
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 11)
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
TYP
3.3
3.3
3.3
3.3
5.1
5.1
5.3
5.3
8.5
8.5
8.3
8.3
TYP
2.7
2.7
3.1
3.1
5.2
5.2
4.3
4.3
6.9
6.9
7.8
7.8
TYP
2.4
2.4
2.9
2.9
5.3
5.3
4
TYP
2.3
2.3
2.8
2.8
5.2
5.2
3.3
3.3
5.5
5.5
7.5
7.5
TYP
2.4
2.4
2.7
2.7
3.7
3.7
3.7
3.7
6.1
6.1
5.9
5.9
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
B
ns
DIR
DIR
DIR
DIR
ns
ns
4
(1)
tPZH
6.4
6.4
7.7
7.7
ns
(1)
tPZL
(1)
tPZH
ns
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
6
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Product Folder Link(s): SN74AVCH1T45
SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 11)
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
2.9
2.9
2.6
2.6
3.8
3.8
5.1
5.1
7.7
7.7
6.7
6.7
MIN
0.7
0.7
0.6
0.6
1.6
1.6
1.8
1.8
MAX
5.6
MIN
0.6
0.6
0.4
0.4
1.5
1.5
1.6
1.6
MAX
5.2
5.2
5.3
5.3
6.8
6.8
7.1
7.1
12.4
12.4
12
MIN
0.5
0.5
0.3
0.3
0.3
0.3
1.1
1.1
MAX
4.2
MIN
0.5
0.5
0.3
0.3
0.9
0.9
1.4
1.4
MAX
3.8
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
5.6
4.2
3.8
5.5
4.9
4.8
B
5.5
4.9
4.8
6.7
6.9
6.9
DIR
DIR
DIR
DIR
6.7
6.9
6.9
8.1
4.7
4.5
8.1
4.7
4.5
(1)
tPZH
13.6
13.6
12.3
12.3
9.6
9.3
(1)
tPZL
9.6
9.3
(1)
tPZH
11.1
11.1
10.7
10.7
(1)
tPZL
12
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 11)
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
2.8
2.8
2.3
2.3
3.8
3.8
5
MIN
0.6
0.6
0.5
0.5
1.6
1.6
1.8
1.89
MAX
5.3
MIN
0.5
0.5
0.4
0.4
1.6
1.6
1.4
1.4
MAX
5
MIN
0.4
0.4
0.3
0.3
1.6
1.6
1
MAX
3.9
3.9
4.6
4.6
5.9
5.9
4.4
4.4
9
MIN
0.4
0.4
0.2
0.2
0.5
0.5
1.4
1.4
MAX
3.4
3.4
4.4
4.4
6
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
5.3
5
5.2
5
B
5.2
5
5.9
5.9
5.9
6.8
6.8
11.8
11.8
10.9
10.9
DIR
DIR
DIR
DIR
5.9
6
7.7
4.3
4.3
8.7
8.7
9.4
9.4
5
7.7
1
(1)
tPZH
7.3
7.3
6.5
6.5
12.9
12.9
11.2
11.2
(1)
tPZL
9
(1)
tPZH
9.8
9.8
(1)
tPZL
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Copyright © 2004–2008, Texas Instruments Incorporated
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SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D–JULY 2004–REVISED JANUARY 2008
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 11)
VCCB = 1.5 V
0.1 V
VCCB = 1.8 V
0.15 V
VCCB = 2.5 V
0.2 V
VCCB = 3.3 V
0.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
2.6
2.6
2.2
2.2
2.8
2.8
4.9
4.9
7.1
7.1
5.4
5.4
MIN
0.5
0.5
0.4
0.4
0.3
0.3
2
MAX
4.9
MIN
0.4
0.4
0.3
0.3
0.8
0.8
1.5
1.5
MAX
4.6
MIN
0.3
0.3
0.2
0.2
0.4
0.4
0.6
0.6
MAX
3.4
3.4
3.4
3.4
3.8
3.8
4.1
4.1
7.5
7.5
7
MIN
MAX
3
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
0.3
0.3
0.2
0.2
0.5
0.5
1
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
4.9
4.6
3
4.2
3.8
3.3
3.3
3.8
3.8
4
B
4.2
3.8
3.8
3.8
DIR
DIR
DIR
DIR
3.8
3.8
7.6
6.5
2
7.6
6.5
1
4
(1)
tPZH
11.8
11.8
8.6
10.3
10.3
8.1
7.3
7.3
6.6
6.6
(1)
tPZL
(1)
tPZH
(1)
tPZL
8.6
8.1
7
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 11)
VCCB = 1.5 V
0.1 V
VCCB = 1.8 V
0.15 V
VCCB = 2.5 V
0.2 V
VCCB = 3.3 V
0.3 V
VCCB = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
2.6
2.6
2.2
2.2
3.1
3.1
4
MIN
0.4
0.4
0.4
0.4
1.3
1.3
0.7
0.7
MAX
4.7
MIN
0.3
0.3
0.3
0.3
1.3
1.3
0.6
0.6
MAX
4.4
4.4
3.4
3.4
4.3
4.3
6.5
6.5
9.9
9.9
8.5
8.5
MIN
0.2
0.2
0.2
0.2
1.3
1.3
0.7
0.7
MAX
3.3
3.3
3
MIN
0.2
0.2
0.1
0.1
1.3
1.3
1.5
1.5
MAX
2.8
2.8
2.8
2.8
4.3
4.3
3.9
3.9
6.7
6.7
6.8
6.8
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
4.7
3.8
B
3.8
3
4.3
4.3
4.3
4
DIR
DIR
DIR
DIR
4.3
7.4
4
7.4
4
(1)
tPZH
6.2
6.2
5.7
5.7
11.2
11.2
8.9
7
(1)
tPZL
7
(1)
tPZH
7.2
7.2
(1)
tPZL
8.9
(1) The enable time is a calculated value, derived using the formula shown in the enable times section.
8
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
Operating Characteristics
TA = 25°C
VCCA
=
VCCA
=
VCCA
=
VCCA
=
VCCA =
TEST
CONDITIONS
VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V
PARAMETER
UNIT
TYP
TYP
TYP
TYP
TYP
A-port input,
B-port output
3
3
3
3
4
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
(1)
(1)
CpdA
pF
B-port input,
A-port output
14
14
3
14
14
3
14
14
3
15
15
3
16
16
4
A-port input,
B-port output
CL = 0 pF,
f = 10 MHz,
tr = tf = 1 ns
CpdB
pF
B-port input,
A-port output
(1) Power-dissipation capacitance per transceiver
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA
.
3. VCCB can be ramped up along with or after VCCA
.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB
)
VCCA
VCCB
UNIT
0 V
0
1.2 V
<0.5
<1
1.5 V
<0.5
<1
1.8 V
<0.5
<1
2.5 V
<0.5
<1
3.3 V
<0.5
1
0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
<0.5
<0.5
<0.5
<0.5
<0.5
<1
<1
<1
<1
1
µA
<1
<1
<1
<1
<1
1
<1
<1
<1
<1
1
<1
<1
<1
<1
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SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D–JULY 2004–REVISED JANUARY 2008
www.ti.com
TYPICAL CHARACTERISTICS
xxxx
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.2 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
V
V
CCB
CCB
V
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 1.
Figure 2.
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.5 V
6
5
4
3
2
1
0
6
5
4
3
2
V
= 1.2 V
= 1.5 V
= 1.8 V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
V
V
V
V
CCB
CCB
1
0
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 3.
Figure 4.
10
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
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www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
xxxx
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.8 V
6
5
4
3
2
1
6
5
4
3
2
V
V
= 1.2 V
= 1.5 V
= 1.8 V
V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
CCB
CCB
V
V
1
0
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 5.
Figure 6.
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 2.5 V
6
6
V
= 1.2 V
= 1.5 V
= 1.8 V
V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
V
CCB
CCB
CCB
CCB
V
V
5
4
3
2
1
0
5
4
3
2
1
0
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 7.
Figure 8.
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SN74AVCH1T45
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES598D–JULY 2004–REVISED JANUARY 2008
www.ti.com
TYPICAL CHARACTERISTICS
xxxx
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 3.3 V
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
= 1.2 V
= 1.5 V
= 1.8 V
V
= 1.2 V
= 1.5 V
= 1.8 V
CCB
CCB
CCB
CCB
V
V
V
V
CCB
CCB
V
V
= 2.5 V
= 3.3 V
V
V
= 2.5 V
= 3.3 V
CCB
CCB
CCB
CCB
0
10
20
30
40
50
60
0
10
20
30
40
50
60
C
L
- pF
C - pF
L
Figure 9.
Figure 10.
12
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Product Folder Link(s): SN74AVCH1T45
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SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES598D–JULY 2004–REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
L
Open
GND
t
Open
pd
From Output
Under Test
t
t
/t
/t
2 × V
CCO
GND
PLZ PZL
PHZ PZH
C
L
R
L
(see Note A)
t
w
LOAD CIRCUIT
V
CCI
V
CCI
/2
V
CCI
/2
Input
C
L
V
TP
R
L
V
CCO
0 V
1.2 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
V
CCA
Output
Control
(low-level
enabling)
V /2
CCA
V
CCA
/2
t
0 V
t
PZL
PLZ
V
V
CCO
Output
Waveform 1
V
CCI
V
/2
/2
CCO
Input
V
CCI
/2
V
CCI
/2
V
+ V
OL
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
– V
TP
V
CCO
Output
V /2
CCO
V
CCO
/2
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
pd
PHL
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CCO
CC
Figure 11. Load Circuit and Voltage Waveforms
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www.ti.com
APPLICATION INFORMATION
Figure 12 shows an example of the SN74AVCH1T45 being used in a unidirectional logic level-shifting
application.
V
CC1
V
CC1
V
CC2
V
CC2
1
2
3
6
5
4
SYSTEM-1
SYSTEM-2
PIN
1
NAME
FUNCTION
DESCRIPTION
V
CCA
V
CC1
SYSTEM-1 supply voltage (1.2 V to 3.36 V)
Device GND
GND
A
GND
OUT
IN
2
3
Output level depends on V
voltage.
CC1
B
4
Input threshold value depends on V
voltage.
CC2
DIR
DIR
5
6
GND (low level) determines B-port to A-port direction.
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
V
CCB
V
CC2
Figure 12. Unidirectional Logic Level-Shifting Application
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SCES598D–JULY 2004–REVISED JANUARY 2008
APPLICATION INFORMATION
Figure 13 shows the SN74AVCH1T45 being used in a bidirectional logic level-shifting application. Since the
SN74AVCH1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
V
CC1
V
CC1
V
CC2
V
CC2
I/O-1
I/O-2
1
2
3
6
5
4
DIR CTRL
SYSTEM-1
SYSTEM-2
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1
and I/O-2 are disabled. The bus-line state depends on bus hold.
2
Hi−Z
Hi−Z
DIR bit is flipped. I/O-1 and I/O02 still are disabled. The bus-line
state depends on bus hold.
3
4
L
L
Hi−Z
Out
Hi−Z
In
SYSTEM-2 data to SYSTEM-1
Figure 13. Bidirectional Logic Level-Shifting Application
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
Enable Times
Calculate the enable times for the SN74AVCH1T45 using the following formulas:
•
•
•
•
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH1T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
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PACKAGE OPTION ADDENDUM
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30-Jan-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
74AVCH1T45DBVRE4
74AVCH1T45DBVRG4
74AVCH1T45DBVTE4
74AVCH1T45DBVTG4
74AVCH1T45DCKRE4
74AVCH1T45DCKRG4
74AVCH1T45DCKTE4
74AVCH1T45DCKTG4
SN74AVCH1T45DBVR
SN74AVCH1T45DBVT
SN74AVCH1T45DCKR
SN74AVCH1T45DCKT
SN74AVCH1T45YZPR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DBV
DBV
DCK
DCK
YZP
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SNAGCU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
SC70
250
Green (RoHS
& no Sb/Br)
SOT-23
SOT-23
SC70
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
DSBGA
3000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2012
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVCH1T45DBVR SOT-23
SN74AVCH1T45DBVT SOT-23
DBV
DBV
DCK
DCK
DCK
DCK
YZP
6
6
6
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
9.2
3.23
3.23
2.3
3.17
3.17
2.52
2.4
1.37
1.37
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q1
SN74AVCH1T45DCKR
SN74AVCH1T45DCKR
SN74AVCH1T45DCKT
SN74AVCH1T45DCKT
SC70
SC70
SC70
SC70
3000
3000
250
2.25
2.25
2.3
1.22
1.22
1.2
2.4
250
2.52
1.52
SN74AVCH1T45YZPR DSBGA
3000
1.02
0.63
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Apr-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AVCH1T45DBVR
SN74AVCH1T45DBVT
SN74AVCH1T45DCKR
SN74AVCH1T45DCKR
SN74AVCH1T45DCKT
SN74AVCH1T45DCKT
SN74AVCH1T45YZPR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DCK
DCK
YZP
6
6
6
6
6
6
6
3000
250
202.0
202.0
214.0
202.0
202.0
214.0
220.0
201.0
201.0
199.0
201.0
201.0
199.0
220.0
28.0
28.0
55.0
28.0
28.0
55.0
35.0
3000
3000
250
SC70
SC70
SC70
250
DSBGA
3000
Pack Materials-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2013
PACKAGING INFORMATION
Orderable Device
74AVCH1T45DBVRE4
74AVCH1T45DBVRG4
74AVCH1T45DBVTE4
74AVCH1T45DBVTG4
74AVCH1T45DCKRE4
74AVCH1T45DCKRG4
74AVCH1T45DCKTE4
74AVCH1T45DCKTG4
SN74AVCH1T45DBVR
SN74AVCH1T45DBVT
SN74AVCH1T45DCKR
SN74AVCH1T45DCKT
SN74AVCH1T45YZPR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
(ET1F ~ ET1R)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DBV
DBV
DCK
DCK
YZP
3000
250
Green (RoHS
& no Sb/Br)
(ET1F ~ ET1R)
(ET1F ~ ET1R)
(ET1F ~ ET1R)
(TFF ~ TFR)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
(TFF ~ TFR)
SC70
Green (RoHS
& no Sb/Br)
(TFF ~ TFR)
SC70
250
Green (RoHS
& no Sb/Br)
(TFF ~ TFR)
SOT-23
SOT-23
SC70
3000
250
Green (RoHS
& no Sb/Br)
(ET1F ~ ET1R)
(ET1F ~ ET1R)
(TFF ~ TFR)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
SC70
Green (RoHS
& no Sb/Br)
(TFF ~ TFR)
DSBGA
3000
Green (RoHS
& no Sb/Br)
(TE2 ~ TE7 ~ TEN)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2013
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AVCH1T45DBVR SOT-23
SN74AVCH1T45DBVT SOT-23
DBV
DBV
DCK
DCK
DCK
DCK
YZP
6
6
6
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
9.2
3.23
3.23
2.25
2.3
3.17
3.17
2.4
1.37
1.37
1.22
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q1
SN74AVCH1T45DCKR
SN74AVCH1T45DCKR
SN74AVCH1T45DCKT
SN74AVCH1T45DCKT
SC70
SC70
SC70
SC70
3000
3000
250
2.52
2.4
2.25
2.3
1.22
1.2
250
2.52
1.52
SN74AVCH1T45YZPR DSBGA
3000
1.02
0.63
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AVCH1T45DBVR
SN74AVCH1T45DBVT
SN74AVCH1T45DCKR
SN74AVCH1T45DCKR
SN74AVCH1T45DCKT
SN74AVCH1T45DCKT
SN74AVCH1T45YZPR
SOT-23
SOT-23
SC70
DBV
DBV
DCK
DCK
DCK
DCK
YZP
6
6
6
6
6
6
6
3000
250
202.0
202.0
202.0
214.0
202.0
214.0
220.0
201.0
201.0
201.0
199.0
201.0
199.0
220.0
28.0
28.0
28.0
55.0
28.0
55.0
35.0
3000
3000
250
SC70
SC70
SC70
250
DSBGA
3000
Pack Materials-Page 2
D: Max = 1.418 mm, Min =1.358 mm
E: Max = 0.918 mm, Min =0.858 mm
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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