74ACT11646 [TI]

OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS; 八路总线收发器和具备三态输出寄存器
74ACT11646
型号: 74ACT11646
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
八路总线收发器和具备三态输出寄存器

总线收发器 输出元件
文件: 总11页 (文件大小:255K)
中文:  中文翻译
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ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢁꢆ  
ꢇ ꢃꢄꢂꢈꢉꢊ ꢋꢌꢉ ꢄꢍꢂ ꢎꢌꢃꢏ ꢐꢑꢏ ꢍꢉꢂꢎꢒ ꢉꢍꢏ ꢓ ꢐꢌ ꢄꢏ ꢍ  
ꢔ ꢐꢄ ꢕꢉ ꢖ ꢗꢌꢄꢂꢄ ꢏꢉ ꢇꢋ ꢄꢘ ꢋꢄ ꢌ  
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993  
DW PACKAGE  
(TOP VIEW)  
Independent Registers for A and B Buses  
Multiplexed Real-Time and Stored Data  
Flow-Through Architecture Optimizes  
G
A1  
CAB  
SAB  
B1  
1
28  
27  
26  
25  
24  
PCB Layout  
2
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
A2  
3
CC  
A3  
B2  
4
A4  
B3  
5
EPICt (Enhanced-Performance Implanted  
GND  
GND  
GND  
GND  
A5  
6
23 B4  
CMOS) 1-mm Process  
7
22  
21  
20  
19  
18  
17  
16  
15  
V
V
CC  
CC  
500-mA Typical Latch-Up Immunity at 125°C  
8
9
B5  
description  
10  
11  
12  
13  
14  
B6  
These devices consist of bus transceiver circuits,  
3-state outputs, D-type flip-flops, and control  
circuitry arranged for multiplexed transmission of  
data directly from the data bus or from the internal  
storage registers. Data on the A or B bus will be  
clocked into the registers on the low-to-high  
transition of the appropriate clock pin (CAB or  
CBA). Figure 1 illustrates the four fundamental  
bus-management functions that can be performed  
with the octal bus transceivers and registers.  
A6  
B7  
A7  
B8  
A8  
CBA  
SBA  
DIR  
Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode,  
data present at the high-impedance port may be stored in either register or in both. The select controls (SAB  
and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control will  
eliminate the typical decoding glitch which occurs in a multiplexer during the transition between stored and  
real-time data. The direction control determines which bus will receive data when enable G is active (low). In  
the isolation mode (control G high), A data may be stored in one register and/or B data may be stored in the  
other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, may be driven at a time.  
The 74ACT11646 is characterized for operation from − 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢄꢥ  
Copyright 1993, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆꢁ ꢆ  
ꢇꢃ ꢄꢂ ꢈꢉ ꢊ ꢋꢌ ꢉ ꢄꢍꢂ ꢎꢌ ꢃꢏ ꢐ ꢑꢏ ꢍꢉꢂꢎ ꢒꢉ ꢍꢏꢓ ꢐ ꢌꢄ ꢏꢍ  
ꢔꢐ ꢄ ꢕ ꢉꢖ ꢗꢌ ꢄꢂꢄꢏ ꢉ ꢇ ꢋꢄ ꢘꢋꢄ ꢌ  
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993  
1
G
L
14  
DIR  
L
28  
CAB  
X
16  
CBA  
X
27  
15  
SBA  
L
1
G
L
14  
DIR  
H
28  
CAB  
X
16  
CBA  
X
27  
SAB  
L
15  
SBA  
X
SAB  
X
REAL-TIME TRANSFER BUS B TO BUS A  
REAL-TIME TRANSFER BUS A TO BUS B  
1
G
X
X
H
14  
DIR  
X
28  
CAB  
16  
CBA  
X
27  
SAB  
X
15  
SBA  
X
1
G
L
14  
DIR  
L
28  
CAB  
X
16  
CBA  
H or L  
X
27  
SAB  
X
15  
SBA  
H
X
X
X
X
L
H
H or L  
H
X
X
X
X
STORAGE FROM A, B, OR A AND B  
TRANSFER STORED DATA TO A OR B  
Figure 1. Bus-Management Functions  
2−2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
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ꢔ ꢐꢄ ꢕꢉ ꢖ ꢗꢌꢄꢂꢄ ꢏꢉ ꢇ ꢋꢄ ꢘꢋ ꢄꢌ  
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993  
FUNCTION TABLE  
DATA I/O  
INPUTS  
CBA  
OPERATION OR FUNCTION  
G
DIR  
X
CAB  
SAB  
X
SBA  
X
A1 THRU A8  
B1 THRU B8  
X
X
H
H
L
X
Input  
Unspecified  
Unspecified  
Store A, B unspecified  
Store B, A unspecified  
Input  
X
X
X
X
X
H or L  
X
H or L  
X
X
X
Store A and B Data  
Isolation, hold storage  
Input  
Output  
Input  
Input  
X
X
X
L
X
L
Real-Time B Data to A Bus  
Stored B Data to A Bus  
Input  
L
L
X
H or L  
X
X
H
L
H
H
X
L
X
Real-Time A Data to B Bus  
Stored A Data to B Bus  
Output  
L
H or L  
X
H
X
The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e.,  
data at the bus pins will be stored on every low-to-high transition on the clock inputs.  
logic symbol  
functional block diagram (positive logic)  
1
G1  
1
G
G3  
14  
DIR  
3 EN1 [BA]  
14  
DIR  
16  
3 EN2 [AB]  
CBA  
16  
CBA  
15  
15  
C4  
G5  
SBA  
28  
SBA  
28  
CAB  
27  
CAB  
27  
C6  
SAB  
SAB  
G7  
26  
1 of 8  
Channels  
1  
2
5
5
4D  
B1  
1D  
C1  
1
A1  
1
1  
6D  
7
7
2
1
2
25  
24  
23  
20  
19  
18  
17  
3
A1  
26  
A2  
B2  
B3  
1D  
C1  
B1  
4
A3  
5
A4  
B4  
B5  
10  
A5  
To Seven Other Channels  
11  
A6  
B6  
B7  
B8  
12  
A7  
13  
A8  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
2−3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆꢁ ꢆ  
ꢇꢃ ꢄꢂ ꢈꢉ ꢊ ꢋꢌ ꢉ ꢄꢍꢂ ꢎꢌ ꢃꢏ ꢐ ꢑꢏ ꢍꢉꢂꢎ ꢒꢉ ꢍꢏꢓ ꢐ ꢌꢄ ꢏꢍ  
ꢔꢐ ꢄ ꢕ ꢉꢖ ꢗꢌ ꢄꢂꢄꢏ ꢉ ꢇ ꢋꢄ ꢘꢋꢄ ꢌ  
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to V  
+ 0.5 V  
+ 0.5 V  
CC  
I
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous current through V  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
recommended operating conditions  
MIN  
4.5  
2
MAX  
UNIT  
V
V
V
V
V
V
Supply voltage  
5.5  
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input voltage  
V
0.8  
V
0
0
V
V
V
I
CC  
Output voltage  
V
O
CC  
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Operating free-air temperature  
24  
24  
mA  
mA  
ns/V  
°C  
OH  
OL  
Dt/Dv  
0
10  
T
40  
85  
A
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
PARAMETER  
TEST CONDITIONS  
V
MIN  
MAX  
UNIT  
CC  
MIN  
4.4  
TYP  
MAX  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
4.5 V  
5.5 V  
4.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5.5 V  
5 V  
4.4  
5.4  
I
= − 50 mA  
OH  
5.4  
3.94  
4.94  
3.8  
V
V
OH  
I
I
= − 24 mA  
= − 75 mA  
OH  
4.8  
3.85  
OH  
0.1  
0.1  
0.1  
0.1  
0.44  
0.44  
1.65  
5
I
= 50 mA  
OL  
0.36  
0.36  
V
V
OL  
I
I
= 24 mA  
OL  
= 75 mA  
OL  
§
I
I
I
A or B ports  
V
= V or GND  
0.5  
0.1  
8
mA  
mA  
mA  
mA  
pF  
pF  
OZ  
O
CC  
G or DIR  
V = V  
or GND  
or GND,  
1
I
I
CC  
V = V  
I = 0  
O
80  
CC  
I
CC  
DI  
CC  
One input at 3.4 V, Other inputs at GND or V  
CC  
0.9  
1
C
C
V = V  
CC  
or GND  
or GND  
4.5  
12  
i
I
V
= V  
O CC  
5 V  
o
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.  
For I/O ports, the parameter I includes the leakage current.  
OZ  
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V  
.
CC  
2−4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
ꢀ ꢁ ꢂꢃ ꢄꢅꢅꢆ ꢁꢆ  
ꢇ ꢃꢄꢂꢈꢉꢊ ꢋꢌꢉ ꢄꢍꢂ ꢎꢌꢃꢏ ꢐꢑꢏ ꢍꢉꢂꢎꢒ ꢉꢍꢏ ꢓ ꢐꢌ ꢄꢏ ꢍ  
ꢔ ꢐꢄ ꢕꢉ ꢖ ꢗꢌꢄꢂꢄ ꢏꢉ ꢇ ꢋꢄ ꢘꢋ ꢄꢌ  
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted) (see Figure 2)  
T
= 25°C  
A
MIN  
MAX  
UNIT  
MIN  
0
MAX  
f
t
t
t
Clock frequency  
105  
0
4.8  
4.5  
2.5  
105  
MHz  
ns  
clock  
Pulse duration, CAB or CBA high or low  
Setup time, A before CLKor B before CBA↑  
Hold time, A after CABor B after CBA↑  
4.8  
4.5  
2.5  
w
ns  
su  
h
ns  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted) (see Figure 2)  
T = 25°C  
A
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
MIN  
MAX  
UNIT  
MIN  
105  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
TYP  
MAX  
f
105  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MHz  
max  
PLH  
PHL  
PZH  
t
t
7.3  
7.2  
7.7  
9.2  
8.6  
7.8  
8.8  
10  
10.1  
11  
11.5  
12  
A or B  
B or A  
A or B  
A or B  
A or B  
A or B  
A or B  
A or B  
A or B  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
12.8  
13.8  
10.7  
9.7  
14.4  
15.3  
11.6  
10.6  
13.5  
14.9  
15.3  
16.5  
11.3  
10.3  
11.5  
13.5  
12.4  
13.1  
G
G
t
PZL  
t
PHZ  
t
PLZ  
PLH  
PHL  
PZH  
t
t
11.9  
13.4  
13.7  
14.8  
10.5  
9.5  
CBA or CAB  
DIR  
t
10.2  
10.9  
7.9  
7.3  
6.7  
9.1  
8
t
PZL  
PHZ  
t
DIR  
t
PLZ  
PLH  
PHL  
PLH  
PHL  
t
t
t
t
10.3  
12.1  
10.9  
11.9  
SBA or SAB  
( A or B high)  
SBA or SAB  
( A or B low)  
8.1  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
= 50 pF, f = 1 MHz  
L
TYP  
UNIT  
Outputs enabled  
Outputs disabled  
63  
14  
C
Power dissipation capacitance per transceiver  
C
pF  
pd  
2−5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢆꢁ ꢆ  
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ꢔꢐ ꢄ ꢕ ꢉꢖ ꢗꢌ ꢄꢂꢄꢏ ꢉ ꢇ ꢋꢄ ꢘꢋꢄ ꢌ  
SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
S1  
500 Ω  
Open  
GND  
From Output  
Under Test  
TEST  
/t  
S1  
t
Open  
PLH PHL  
t
/t  
2 × V  
CC  
GND  
PLZ PZL  
C
= 50 pF  
L
500 Ω  
t
/t  
(see Note A)  
PHZ PZH  
LOAD CIRCUIT  
3 V  
0 V  
Timing Input  
(see Note B)  
1.5 V  
t
w
t
h
t
3 V  
su  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Data Input  
0 V  
VOLTAGE WAVEFORMS  
VOLTAGE WAVEFORMS  
Output  
Control  
(low-level  
enabling)  
3 V  
0 V  
3 V  
0 V  
Input  
(see Note B)  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
t
PZL  
t
t
PHL  
PLH  
t
PLZ  
Output  
Waveform 1  
V
OH  
[ V  
CC  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
50% V  
CC  
V
CC  
20% V  
S1 at 2 × V  
(see Note C)  
CC  
CC  
V
OL  
OL  
t
PHZ  
t
PLH  
t
t
PHL  
PZH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
OH  
Out-of-Phase  
Output  
80% V  
CC  
50% V  
50% V  
CC  
CC  
CC  
[ 0 V  
V
OL  
(see Note C)  
VOLTAGE WAVEFORMS  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t = 3 ns, t = 3 ns.  
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
D. The outputs are measured one at a time with one input transition per measurement.  
Figure 2. Load Circuit and Voltage Waveforms  
2−6  
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SOIC  
SOIC  
PDIP  
Drawing  
74ACT11646DW  
74ACT11646DWR  
74ACT11646NT  
OBSOLETE  
OBSOLETE  
OBSOLETE  
DW  
28  
28  
28  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
DW  
NT  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
SOIC  
SOIC  
PDIP  
Drawing  
74ACT11646DW  
74ACT11646DWR  
74ACT11646NT  
OBSOLETE  
OBSOLETE  
OBSOLETE  
DW  
28  
28  
28  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
DW  
NT  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
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