74ACT11534DW [TI]
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 24-SOIC -40 to 85;
| 型号： | 74ACT11534DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 24-SOIC -40 to 85 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54ACT11534, 74ACT11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS038A – D2957, JULY 1987 – REVISED APRIL 1993
• Eight D-Type Flip-Flops in a Single Package
• 3-State Bus Driving Inverting Outputs
• Full Parallel Access for Loading
54ACT11534 . . . JT PACKAGE
74ACT11534 . . . DW OR NT PACKAGE
(TOP VIEW)
• Inputs Are TTL-Voltage Compatible
1Q
2Q
OC
1D
2D
3D
4D
1
24
23
22
21
20
19
18
17
16
15
14
13
2
• Flow-Through Architecture to Optimize
3Q
3
PCB Layout
4Q
4
• Center-Pin V
and GND Configurations to
Minimize High-Speed Switching Noise
CC
GND
GND
GND
GND
5Q
5
6
V
V
CC
CC
• EPIC (Enhanced-Performance Implanted
7
CMOS) 1- m Process
8
5D
• 500-mA Typical Latch-Up Immunity
at 125°C
9
6D
10
11
12
6Q
7D
• Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
7Q
8D
8Q
CLK
54ACT11534 . . . FK PACKAGE
(TOP VIEW)
description
These eight flip-flops feature 3-state outputs
designed for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
4
3
2 1 28 27 26
5
25 7D
2D
1D
OC
NC
1Q
2Q
3Q
6
24
23
22
21
20
19
8D
7
CLK
NC
8Q
7Q
6Q
The eight flip-flops of the ′ACT11534 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
complementofthelogiclevelsattheDinputs. The
′ACT11534 is functionally equivalent to the
′ACT11373 except for having inverted outputs.
8
9
10
11
12 13 14 15 16 17 18
An output-control input (OC) is used to place the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
NC – No internal connection
nor drive the bus lines significantly.
The
FUNCTION TABLE
(each flip-flop)
high-impedance third state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components. The output control (OC)
does not affect the internal operations of the
flip-flops. Old data can be retained, or new data
can be entered while the outputs are in the
high-impedance state.
INPUTS
OUTPUT
Q
OC
CLK
D
L
L
L
↑
↑
L
X
H
L
H
L
X
X
Q
Z
0
H
The 54ACT11534 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The 74ACT11534 is characterized for
operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT11534, 74ACT11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS038A – D2957, JULY 1987 – REVISED APRIL 1993
†
logic symbol
logic diagram (positive logic)
24
24
OC
OC
EN
C1
13
13
CLK
CLK
23
22
21
20
17
16
15
14
1
2
C1
1D
1
2
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
23
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
3
C1
1D
4
22
21
20
17
16
15
14
9
10
11
12
C1
1D
3
C1
1D
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
C1
1D
9
C1
1D
10
11
12
C1
1D
C1
1D
Pin numbers shown are for the DW, JT, and NT packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT11534, 74ACT11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS038A – D2957, JULY 1987 – REVISED APRIL 1993
recommended operating conditions
54ACT11534
74ACT11534
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
mA
mA
ns/V
°C
OH
I
OL
t/ v
0
10
0
10
T
–55
125
– 40
85
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT11534
74ACT11534
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
5.4
3.8
4.8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
I
= – 50
A
OH
5.4
5.4
3.94
4.94
3.7
= – 24 mA
V
OH
V
OH
4.7
3.85
I
I
= – 50 mA
= – 75 mA
OH
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
I
= 50 A
OL
0.36
0.36
0.5
0.44
0.44
= 24 mA
V
OL
V
OL
0.5
1.65
I
I
= 50 mA
= 75 mA
OL
1.65
± 5
± 1
80
OL
I
I
I
V
= V or GND
CC
± 0.5
± 0.1
8
± 10
± 1
A
A
A
OZ
O
V = V
or GND
or GND,
I
I
CC
CC
V = V
I = 0
O
160
CC
I
One input at 3.4 V,
Other inputs at GND or V
5.5 V
0.9
1
1
mA
I
CC
CC
C
C
V = V
or GND
5 V
5 V
4
pF
pF
i
I
CC
= V or GND
CC
V
O
10
o
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT11534, 74ACT11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS038A – D2957, JULY 1987 – REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
54ACT11534
74ACT11534
A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
55
55
55
MHz
ns
clock
Pulse duration, CLK low or CLK high
Setup time, data before CLK ↑
Hold time, data after CLK ↑
9
9
9
w
3
3
3
ns
su
h
5.5
5.5
5.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
70
54ACT11534
74ACT11534
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
55
MAX
MIN
55
MAX
MIN
55
MAX
f
t
t
t
t
t
t
max
PLH
PHL
PZH
PZL
PHZ
PLZ
1.5
1.5
1.5
1.5
1.5
1.5
8.5
8.5
7.5
7.5
11
12.7
13.3
12
1.5
1.5
1.5
1.5
1.5
1.5
15.7
16.3
14.2
14.5
13.9
12.5
1.5
1.5
1.5
1.5
1.5
1.5
14.5
15
CLK
OC
OC
Any Q
Any Q
Any Q
13.3
13.5
13.5
12
ns
ns
12.2
12.9
11.2
8
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
92
82
C
Power dissipation capacitance per flip-flop
C
pF
pd
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT11534, 74ACT11534
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS038A – D2957, JULY 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
/t
S1
t
Open
PLH PHL
t
/t
2 × V
CC
GND
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
(see Note A)
PHZ PZH
LOAD CIRCUIT
3 V
0 V
Timing Input
(see Note B)
1.5 V
t
w
t
h
t
3 V
su
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note C)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note C)
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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