74AC11478NT [TI]
Octal Dual-Rank D-Type Flip-Flops With 3-State Outputs 24-PDIP -40 to 85;
| 型号： | 74AC11478NT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal Dual-Rank D-Type Flip-Flops With 3-State Outputs 24-PDIP -40 to 85 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS182 − APRIL 1989 − REVISED APRIL 1993
DW OR NT PACKAGE
(TOP VIEW)
• Specifically Designed for Data
Synchronization Applications
• 3-State Outputs Drive Bus Lines Directly
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
OE
1
24
• Flow-Through Architecture Optimizes PCB
2
23 1D
22 2D
Layout
3
4
21
20
19
18
17
16
15
14
13
3D
4D
V
• Center-Pin V
and GND Pin
Configurations Minimize High-Speed
Switching Noise
CC
5
6
CC
7
V
CC
•
EPIC (Enhanced-Performance Implanted
CMOS ) 1-µm Process
8
5D
6D
7D
8D
9
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
10
11
12
6Q
7Q
8Q
CLK
description
The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications in which the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output
hangs up in the region between V and V . The metastable condition lasts until the flip-flop recovers into one
IL
IH
of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum
propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank
approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is
exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system
designers in asynchronous applications.
The 74AC11478 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Q
†
CLK
OE
D
H
L
L
L
X
↑
↑
L
X
L
H
X
Z
L
H
Q
0
†
Data presented at the
D inputs
requires two clock cycles to appear at
the Q outputs.
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1993, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS182 − APRIL 1989 − REVISED APRIL 1993
†
logic symbol
logic diagram (positive logic)
24
24
EN
C1
OE
OE
13
CLK
13
23
23
22
21
20
17
16
15
14
1
2
3
4
9
CLK
1D
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
1D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
1D
C1
1D
1
1Q
10
11
12
To 7 Other Channels
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢕ ꢔꢇ ꢖꢉ ꢗ ꢌꢘꢇꢂꢇ ꢒꢉꢆ ꢋ ꢇꢑ ꢋꢇ
SCAS182 − APRIL 1989 − REVISED APRIL 1993
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
High-level input voltage
V
V
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
Low-level input voltage
IL
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
−4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 4.5 V
= 5.5 V
= 3 V
−24
−24
12
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
I
OL
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
−40
85
°C
NOTE 2: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
4.5 V
5.5 V
3 V
2.9
4.4
4.4
I
I
= − 50 µA
OH
5.4
5.4
= − 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= − 24 mA
= −75 mA
OL
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.44
0.44
0.44
1.65
1
4.5 V
5.5 V
3 V
I
I
= 50 µA
OL
0.1
= 12 mA
= 24 mA
0.36
0.36
0.36
V
OL
V
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
I
I
OL
†
= 75 mA
OL
I
I
I
V = V
or GND
0.1
0.5
8
µA
µA
µA
pF
pF
I
I
CC
V
= V
O CC
or GND
5
OZ
CC
V = V
or GND,
or GND
I = 0
O
80
I
CC
C
C
V = V
4.5
10
i
I
CC
V
= V
O CC
or GND
5 V
o
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢕꢔ ꢇ ꢖ ꢉꢗ ꢌꢘ ꢇꢂꢇꢒ ꢉ ꢆ ꢋꢇ ꢑꢋꢇ ꢘ
SCAS182 − APRIL 1989 − REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
MAX
f
t
t
t
Clock frequency
55
55
MHz
ns
clock
su
h
Setup time, data before CLK↑
Hold time, data after CLK↑
Pulse duration, CLK high or low
3
1.5
9
3
1.5
9
ns
ns
w
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
MAX
f
t
t
t
Clock frequency
83
83
MHz
ns
clock
su
h
Setup time, data before CLK↑
Hold time, data after CLK↑
Pulse duration, CLK high or low
2.5
1.5
6
2.5
1.5
6
ns
ns
w
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
55
TYP
MAX
f
t
t
t
t
t
t
55
3.8
5.5
3.7
5.4
3.9
4
MHz
max
PLH
PHL
PZH
PZL
PHZ
PLZ
3.8
5.5
3.7
5.4
3.9
4
10.5
13.2
10.8
14.7
7.1
13.3
16.8
13.9
19.2
9.3
15
18.4
16
CLK
OE
Q
Q
Q
ns
ns
ns
22.5
10.1
9.6
OE
6.9
8.9
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
83
TYP
MAX
f
t
t
t
t
t
t
83
2.9
4.3
2.9
4.1
3.2
3.5
MHz
max
PLH
PHL
PZH
PZL
PHZ
PLZ
2.9
4.3
2.9
4.1
3.2
3.5
6.1
7.9
6.4
8.1
5.7
5.4
8.9
11.2
9.6
12.3
8
10
12.3
10.8
14.0
8.6
CLK
OE
Q
Q
Q
ns
ns
ns
OE
7.4
8
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
46
33
C
Power dissipation capacitance per flip-flop
C
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
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ꢕ ꢔꢇ ꢖꢉ ꢗ ꢌꢘꢇꢂꢇ ꢒꢉꢆ ꢋ ꢇꢑ ꢋꢇ
SCAS182 − APRIL 1989 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2× V
CC
TEST
S1
S1
t
t
/t
Open
500 Ω
Open
GND
PLH PHL
From Output
Under Test
/t
2 × V
PLZ PZL
/t
CC
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT FOR OUTPUTS
V
CC
Input
50%
50%
0 V
V
CC
Timing Input
50%
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
t
su
t
h
V
CC
V
CC
Data Input
50%
50%
Output
0 V
Control
(low-level
enabling)
50%
50%
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
0 V
t
PZL
t
PLZ
≈V
V
CC
CC
Input
(see Note B)
Output
Waveform 1
50%
50%
50%V
CC
20% V
80% V
CC
0 V
S1 at 2 × V
(see Note C)
CC
V
OL
t
t
PLH
PHZ
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Output
(see Note D)
CC
50%V
CC
50% V
50%V
CC
CC
V
OL
(see Note C)
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
For testing pulse duration: t = t = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
PDIP
Drawing
74AC11478DW
74AC11478NT
74AC11478NT
OBSOLETE
OBSOLETE
OBSOLETE
DW
24
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
NT
NT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
PDIP
Drawing
74AC11478DW
74AC11478NT
74AC11478NT
OBSOLETE
OBSOLETE
OBSOLETE
DW
24
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
NT
NT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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