74AC11032 概述
QUADRUPLE 2-INPUT POSITIVE-OR GATE 四路2输入正或门
74AC11032 数据手册
通过下载74AC11032数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
D, DB, OR N PACKAGE
(TOP VIEW)
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
1B
2A
2B
V
1A
1Y
2Y
GND
GND
3Y
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
500-mA Typical Latch-Up Immunity at
125°C
CC
Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic
300-mil DIPs (N)
V
CC
3A
3B
4A
4Y
4B
description
This device contains four independent 2-input OR gates. It performs the Boolean function
B or Y A • B in positive logic.
Y
A
The 74AC11032 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
†
logic symbol
1
1A
1B
2A
2B
3A
3B
4A
4B
≥1
2
3
6
7
16
15
14
11
10
9
1Y
2Y
3Y
4Y
8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
logic diagram (positive logic)
1
1A
2
1Y
16
1B
15
2A
3
6
7
2Y
3Y
4Y
14
2B
11
3A
10
3B
9
4A
8
4B
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . . 1.3 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DB package . . . . . . . . . . . . . . . . . . 0.55 W
N package . . . . . . . . . . . . . . . . . . . . 1.1 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
2.9
4.4
I
I
= –50 µA
4.5 V
5.5 V
3 V
4.4
OH
5.4
5.4
V
OH
= –4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= –24 mA
= –75 mA
OH
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
V = V
or GND
or GND,
or GND
±0.1
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
4
40
CC
I
C
V = V
3.5
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
6.3
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
1.5
MAX
8.7
t
t
1.5
1.5
9.7
8
PLH
A or B
Y
ns
1.5
5.4
7.4
PHL
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
4.3
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
1.5
MAX
6.2
t
t
1.5
1.5
6.7
5.9
PLH
A or B
Y
ns
1.5
3.8
5.5
PHL
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per gate
C
= 50 pF,
L
f = 1 MHz
24
pF
pd
PARAMETER MEASUREMENT INFORMATION
V
CC
Input
(see Note B)
From Output
Under Test
50%
50%
0 V
t
PLH
C
= 50 pF
t
PHL
L
500 Ω
(see Note A)
V
OH
50% V
50% V
Output
CC
CC
V
OL
LOAD CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A.
C includes probe and jig capacitance.
L
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
74AC11032 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
74AC11032D | TI | QUADRUPLE 2-INPUT POSITIVE-OR GATE | 获取价格 | |
74AC11032D | PHILIPS | OR Gate, CMOS, PDSO16 | 获取价格 | |
74AC11032D-T | PHILIPS | OR Gate, CMOS, PDSO16 | 获取价格 | |
74AC11032DB | TI | QUADRUPLE 2-INPUT POSITIVE-OR GATE | 获取价格 | |
74AC11032DBE4 | TI | AC SERIES, QUAD 2-INPUT OR GATE, PDSO16 | 获取价格 | |
74AC11032DBR | TI | Quadruple 2-Input Positive-OR Gates 16-SSOP -40 to 85 | 获取价格 | |
74AC11032DBRE4 | TI | AC SERIES, QUAD 2-INPUT OR GATE, PDSO16, GREEN, PLASTIC, SSOP-16 | 获取价格 | |
74AC11032DBRG4 | TI | AC SERIES, QUAD 2-INPUT OR GATE, PDSO16, GREEN, PLASTIC, SSOP-16 | 获取价格 | |
74AC11032DE4 | TI | Quadruple 2-Input Positive-OR Gates 16-SOIC -40 to 85 | 获取价格 | |
74AC11032DG4 | TI | AC SERIES, QUAD 2-INPUT OR GATE, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16 | 获取价格 |
74AC11032 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6