74221 [TI]
High Speed CMOS Logic Dual Monostable Multivibrator with Reset; 高速CMOS逻辑双路单稳多谐振荡器与重置
| 型号： | 74221 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Dual Monostable Multivibrator with Reset |
| 文件： | 总11页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC221,
CD74HCT221
Data sheet acquired from Harris Semiconductor
SCHS166A
High Speed CMOS Logic
November 1997 - Revised April 1999
Dual Monostable Multivibrator with Reset
Features
Description
• Overriding RESET Terminates Output Pulse
• Triggering from the Leading or Trailing Edge
• Q and Q Buffered Outputs
The CD74HC221, and CH74HCT221 are dual monostable
multivibrators with reset. An external resistor (R ) and an
X
[ /Title
(CD74
HC221
,
CD74
HCT22
1)
external capacitor (C ) control the timing and the accuracy
X
for the circuit. Adjustment of R and C provides a wide
X
X
range of output pulse widths from the Q and Q terminals.
Pulse triggering on the B input occurs at a particular voltage
level and is not related to the rise and fall time of the trigger
pulse.
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on B Inputs
• Fanout (Over Temperature Range)
Once triggered, the outputs are independent of further trigger
inputs on A and B. The output pulse can be terminated by a
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads LOW level on the Reset (R) pin. Trailing Edge triggering (A)
/Sub-
ject
and leading-edge-triggering (B) inputs are provided for
triggering from either edge of the input pulse. On power up,
the IC is reset. If either Mono is not used each input (on the
unused device) must be terminated either high or low.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
(High
Speed
CMOS
Logic
Dual
Monos
table
Multi-
• Significant Power Reduction Compared to LSTTL
Logic ICs
The minimum value of external resistance, R , is typically 500Ω.
X
• HC Types
The minimum value of external capacitance, C , is 0pF. The
X
calculation for the pulse width is t = 0.7 R C at V = 4.5V.
- 2V to 6V Operation
W
X X
CC
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
Ordering Information
at V
= 5V
CC
PKG.
NO.
• HCT Types
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
- 4.5V to 5.5V Operation
CD74HC221E
CD74HCT221E
CD74HC221M
CD74HCT221M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
E16.3
E16.3
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
16 Ld SOIC M16.15
16 Ld SOIC M16.15
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die are available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC221, CD74HCT221
(PDIP, SOIC)
TOP VIEW
1A
1B
1R
1Q
2Q
1
2
3
4
5
6
7
8
16 V
CC
15 1C R
X
X
14 1C
X
13 1Q
12 2Q
11 2R
10 2B
2C
X
X
2C R
X
9
2A
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1670.1
Copyright © Harris Corporation 1997
1
CD74HC221, CD74HCT221
Functional Diagram
1C
1R
X
X
V
CC
14
15
1C R
1C
X
X
X
13
4
1A
1Q
1Q
1
2
MONO 1
1B
1R
3
11
2R
2A
5
9
2Q
2Q
MONO 2
12
10
2B
2C
2C R
X
X
X
6
7
V
CC
2C
2R
X
X
TRUTH TABLE
INPUTS
OUTPUTS
A
H
X
L
B
X
L
↑
R
H
H
H
Q
Q
H
H
L
L
↓
H
H
X
L
X
H
L
L
H
↑
(Note 3)
(Note 3)
NOTE:
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low
↓
to High Level, = Transition from High to Low Level,
= One High Level Pulse,
= One Low Level Pulse
3. For this combination the reset input must be low and the following sequence must
be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9)
must be low and pin 2 (or 10) set high. Now the reset input goes from low-to-high
and the device will be triggered.
2
CD74HC221, CD74HCT221
Logic Diagram
V
CC
16
C
P
R
N
X
A
B
R
1 (9)
2 (10)
3 (11)
P
V
CC
P
OP
AMP
R2
R3
R
D
C
RESET
FF
15 (7)
R C
-
+
X
X
Q
C
S
R
V
CC
MIRROR VOLTAGE
QM
QM
P P
C
X
R
Q
MASK
FF
R1
S
MAIN
FF
R4
Q
PULLDOWN
FF
14 (6)
N
V
CC
C
8
X
D
C
C
Q
N
GND
Q
4 (12)
(13) 5
R
Q
Q
+
-
OP AMP
3
CD74HC221, CD74HCT221
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 4)
θ
( C/W)
θ
( C/W)
CC
DC Input Diode Current, I
JA
JC
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
100
180
N/A
N/A
IK
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
(SOIC - Lead Tips Only)
O
CC
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time, t , t on Inputs A and R
r
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Input Rise and Fall Time, t , t on Input B
r
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
4. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
3.15
-
3.15
-
3.15
4.2
-
0.5
1.35
1.8
-
4.2
-
0.5
1.35
1.8
-
4.2
-
Low Level Input
Voltage
V
-
2
-
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
1.9
4.4
5.9
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
-
5.9
-
5.9
-
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
5.2
-
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
0.1
0.1
0.1
-
0.1
0.1
0.1
-
OL
4.5
6
-
-
Low Level Output
Voltage
TTL Loads
-
-
4
4.5
6
0.26
0.26
0.33
0.33
-
0.4
0.4
5.2
-
4
CD74HC221, CD74HCT221
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
Input Leakage
SYMBOL
V (V)
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
O
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
Current
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All Inputs
UNIT LOADS
0.3
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite For Switching Function
o
o
o
o
o
25 C
TYP
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Input Pulse Width
A
t
2
70
14
12
70
14
12
-
-
-
-
-
-
-
-
-
-
-
-
90
18
15
90
18
15
-
-
-
-
-
-
105
21
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
WL
4.5
6
2
18
Input Pulse Width
B
t
105
21
WH
4.5
6
18
5
CD74HC221, CD74HCT221
Prerequisite For Switching Function (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Pulse Width
SYMBOL
V
(V)
MIN
70
14
12
0
TYP
MAX
MIN
90
18
15
0
MAX
MIN
105
21
18
0
MAX
UNITS
ns
CC
t
2
-
-
-
-
-
-
-
-
-
-
WL
Reset
4.5
-
-
-
ns
6
2
-
-
-
ns
Recovery Time
R to A or B
t
-
-
-
ns
SU
4.5
6
0
-
-
0
-
-
0
-
-
ns
0
0
0
ns
Output Pulse Width Q or Q
t
5
630
770
602
798
595
805
µs
W
C
= 0.1µF R = 10kΩ
X
X
Output Pulse Width Q or Q
t
4.5
-
140
-
-
-
-
-
ns
W
C
C
C
= 28pF, R = 2kΩ
X
X
X
X
= 1000pF, R = 2kΩ
t
t
4.5
4.5
-
-
1.5
7
-
-
-
-
-
-
-
-
-
-
µs
µs
X
W
= 1000pF, R = 10kΩ
X
W
HCT TYPES
Input Pulse Width
A
t
4.5
4.5
4.5
4.5
5
14
14
18
0
-
-
18
18
23
0
-
21
21
27
0
-
ns
ns
ns
ns
µs
ns
WL
Input Pulse Width
B
t
-
-
-
-
WH
Input Pulse Width
Reset
t
-
-
-
-
WL
Recovery Time
R to A or B
t
-
-
-
770
-
-
798
-
-
805
-
SU
Output Pulse Width Q or Q
t
630
-
602
-
595
-
W
W
C
= 0.1µF R = 10kΩ
X
X
Output Pulse Width Q or Q
t
4.5
140
C
C
C
= 28pF, R = 2kΩ
X
X
X
X
= 1000pF, R = 2kΩ
t
t
4.5
4.5
-
-
1.5
7
-
-
-
-
-
-
-
-
-
-
µs
µs
X
W
= 1000pF, R = 10kΩ
X
W
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay,
Trigger A, B, R to Q
t
C = 50pF
2
-
-
-
210
42
36
-
-
-
-
-
-
-
-
-
265
53
45
-
-
-
-
-
-
-
-
-
315
63
54
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH
PHL
L
C = 50pF
4.5
6
-
-
-
-
-
-
-
L
C = 50pF
-
L
C = 15pF
5
18
-
L
Propagation Delay,
Trigger A, B, R to Q
t
C = 50pF
2
170
34
29
-
215
43
37
-
255
51
43
-
L
C = 50pF
4.5
6
-
L
C = 50pF
-
L
C = 15pF
5
14
L
6
CD74HC221, CD74HCT221
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
Propagation Delay,
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
C = 50pF
2
-
-
-
160
32
27
180
36
31
75
15
13
10
-
-
-
-
-
-
-
-
-
-
-
-
200
40
34
225
45
38
95
19
16
10
-
-
-
-
-
-
-
-
-
-
-
-
240
48
41
270
54
46
110
22
19
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
%
PLH
L
R to Q
4.5
6
-
-
-
-
-
-
-
-
-
-
-
Propagation Delay,
R to Q
t
C = 50pF
2
-
PHL
L
4.5
6
-
-
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
IN
Pulse Width Match Between
Circuits in the Same Package
4.5 to
5.5
±2
C
= 1000pF, R = 10kΩ
X
X
Power Dissipation Capacitance
(Notes 5, 6)
CPD
-
5
-
166
-
-
-
-
-
pF
HCT TYPES
Propagation Delay,
Trigger A, B, R to Q
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
18
-
42
-
-
-
-
-
-
-
-
-
-
-
-
-
63
-
ns
ns
ns
ns
ns
PLH
L
C = 15pF
L
Propagation Delay,
Trigger A, B, R to Q
C = 50pF
4.5
5
34
-
43
-
51
-
PHL
L
C = 15pF
14
-
L
Propagation Delay,
R to Q
t
t
C = 50pF
4.5
38
-
57
PLH
L
Propagation Delay,
R to Q
C = 50pF
4.5
-
-
37
-
-
-
56
ns
PHL
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
95
19
16
10
-
-
-
-
-
-
110
22
19
10
-
ns
ns
ns
pF
%
-
C
-
-
-
-
IN
Pulse Width Match Between
Circuits in the Same Package
4.5 to
5.5
±2
C
= 1000pF, R = 10kΩ
X
X
Power Dissipation Capacitance
(Notes 5, 6)
CPD
-
5
-
166
-
-
-
-
-
pF
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per multivibrator.
2
6. P = (C
PD
+ C ) V
CC
f + Σ where f = input frequency, f = output frequency, C = output load capacitance, V
= supply voltage.
CC
D
L
i
i
o
L
7
CD74HC221, CD74HCT221
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
8
CD74HC221, CD74HCT221
Typical Performance Curves
685
R
V
= 10K
= 5V
R
= 10K
o
X
X
T
= 25 C
CC
A
680
675
0.9
0.8
HCT
C
= 1µF
X
670
665
0.7
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
o
0
2
4
6
8
10
T , AMBIENT TEMPERATURE ( C)
V
, SUPPLY VOLTAGE (V)
A
CC
FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs
TEMPERATURE
FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE
6
6
10
10
V
= 4.5V
CC
V
= 2V
CC
5
4
3
2
5
10
10
10
10
10
10
10
10
4
3
2
R
= 100K
R
= 100K
X
X
R
R
= 50K
= 10K
X
R
R
= 50K
= 10K
X
X
10
1
X
10
1
R
= 2K
X
R
= 2K
X
0.1
0.1
2
3
4
5
6
7
8
10
2
3
4
5
6
7
8
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
C , TIMING CAPACITANCE (pF)
C , TIMING CAPACITANCE (pF)
X
X
FIGURE 7. HC221 OUTPUT PULSE WIDTH vs C
FIGURE 8. HC/HCT221 OUTPUT PULSE WIDTH vs C
X
X
9
Typical Performance Curves (Continued)
685
R
V
= 10K
= 5V
R
= 10K
o
X
X
T
= 25 C
CC
A
680
675
0.9
0.8
HCT
C
= 1µF
X
670
665
0.7
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
o
0
2
4
6
8
10
T , AMBIENT TEMPERATURE ( C)
V
, SUPPLY VOLTAGE (V)
A
CC
FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs
TEMPERATURE
FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE
6
10
V
= 6V
CC
5
10
4
3
2
10
10
10
R
= 100K
X
R
R
= 50K
= 10K
X
X
10
R
= 2K
X
1
0.1
2
3
4
5
6
7
8
10
10
10
10
10
10
10
10
C , TIMING CAPACITANCE (pF)
X
FIGURE 9. HC221 OUTPUT PULSE WIDTH vs C
X
10
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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