66AK2E02ABDA4 [TI]
66AK2E0x Multicore DSPARM KeyStone II System-on-Chip (SoC);
| 型号： | 66AK2E02ABDA4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 66AK2E0x Multicore DSPARM KeyStone II System-on-Chip (SoC) |
| 文件： | 总282页 (文件大小：1546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
1 66AK2E0x Features and Description
1.1 Features
1
• ARM® Cortex®-A15 MPCore™ CorePac
Interface, and SSL/TLS Security
•
•
ECB, CBC, CTR, F8, A5/3, CCM, GCM,
HMAC, CMAC, GMAC, AES, DES, 3DES,
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
Hash), MD5
Up to 6.4 Gbps IPSec and 3 Gbps Air
Ciphering
– Up to Four ARM Cortex-A15 Processor Cores at
up to 1.4-GHz
– 4MB L2 Cache Memory Shared by all Cortex-
A15 Processor Cores
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction and Data Caches per Core
– AMBA 4.0 AXI Coherency Extension (ACE)
Master Port, Connected to MSMC (Multicore
Shared Memory Controller) for Low Latency
Access to SRAM and DDR3
– Ethernet Subsystem
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•
•
Eight SGMII Ports with Wire Rate Switching
IEEE1588 v2 (with Annex D/E/F) Support
8 Gbps Total Ingress/Egress Ethernet BW
from Core
• One TMS320C66x DSP Core Subsystem (C66x
CorePacs), Each With
•
•
•
Audio/Video Bridging (802.1Qav/D6.0)
QOS Capability
DSCP Priority Mapping
– 1.4 GHz C66x Fixed/Floating-Point DSP Core
•
•
38.4 GMacs/Core for Fixed Point @ 1.2 GHz
19.2 GFlops/Core for Floating Point @
1.2 GHz
• Peripherals
– Two PCIe Gen2 Controllers with Support for
•
•
Two Lanes per Controller
Supports Up to 5 GBaud
– Memory
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32K Byte L1P Per CorePac
32K Byte L1D Per CorePac
512K Byte Local L2 Per CorePac
– One HyperLink
•
Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
• Multicore Shared Memory Controller (MSMC)
– 2 MB SRAM Memory Shared by DSP CorePacs
and ARM CorePac
•
Supports Up to 50 GBaud
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem
– Memory Protection Unit for Both SRAM and
DDR3_EMIF
• Multicore Navigator
•
Two SGMII/XFI Ports with Wire Rate
Switching and MACSEC Support
IEEE1588 v2 (with Annex D/E/F) Support
•
– 8k Multi-Purpose Hardware Queues with Queue
Manager
– One 72-Bit DDR3/DDR3L Interface with Speeds
Up to 1600 MTPS in DDR3 Mode
– One Packet-Based DMA Engine for Zero-
Overhead Transfers
• Network Coprocessor
– EMIF16 Interface
– Two USB 2.0/3.0 Controllers
– USIM Interface
– Two UART Interfaces
– Three I2C Interfaces
– 32 GPIO Pins
– Packet Accelerator Enables Support for
•
Transport Plane IPsec, GTP-U, SCTP,
PDCP
•
•
L2 User Plane PDCP (RoHC, Air Ciphering)
1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
– Three SPI Interfaces
– One TSIP
•
•
Support 1024 DS0s
Support 2 Lanes at 32.768/16.3848.192
Mbps Per Lane
– Security Accelerator Engine Enables Support for
IPSec, SRTP, 3GPP and WiMAX Air
•
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
• System Resources
– Five Enhanced Direct Memory Access (EDMA)
Modules
– Three On-Chip PLLs
• Commercial Case Temperature:
– 0ºC to 85ºC
– SmartReflex Automatic Voltage Scaling
– Semaphore Module
• Extended Case Temperature:
– -40ºC to 100ºC
– Thirteen 64-Bit Timers
1.2 Applications
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•
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Avionics and Defense
Communications
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Servers
Enterprise Networking
Cloud Infrastructure
Industrial Automation
Automation and Process Control
1.3 KeyStone II Architecture
TI's KeyStone II Multicore Architecture provides a unified platform for integrating RISC and DSP
processing cores along with both hardware/firmware based application-specific acceleration and high
performance I/Os. The KeyStone II Multicore Architecture is a proven device architecture to achieve the
full performance entitlement through the following major components: TeraNet, Multicore Shared Memory
Controller, Multicore Navigator, and HyperLink.
TeraNet is a multipoint to multipoint non-blocking switch fabric. Its distributed arbiter provides multiple
duplex communication channels in parallel between the master and slave ports without interference. The
priority based arbitration mechanism ensures the delivery of the critical traffic delivery in the system.
The Multicore Shared Memory Controller (MSMC) is the center of the KeyStone II memory architecture. It
provides multiple fast and high-bandwidth channels for processor cores to access DDR and minimizes the
access latency by directly connecting to the DDR. The MSMC also provides the flexibility to expand
processor cores with little impact at the device level. In addition, it provides multi-bank based fast on-chip
SRAM shared among processor cores and IOs. It also provides the I/O cache coherency for the device
when the Cortex-A15 processor core is integrated.
The Multicore Navigator provides a packet-based IPC mechanism among processing cores and packet
based peripherals. The hardware-managed queues supports multiple-in-multiple-out mode without using
mutex. Coupled with the packet-based DMA, the Multicore Navigator provides a highly efficient and
software-friendly tool to offload the processing core to achieve other critical tasks.
HyperLink provides a 50-GBaud chip-level interconnect that allows devices to work in tandem. Its low
latency, low overhead and high throughput makes it an ideal interface for chip-to-chip interconnections.
There are two generations of KeyStone architecture. The 66AK2E0x device is based on KeyStone II,
which integrates a Cortex-A15 processor CorePac.
1.4 Device Description
The 66AK2E0x is a high performance device based on TI's KeyStone II Multicore SoC Architecture,
incorporating the most performance-optimized Cortex-A15 processor single-core or quad-core CorePac
and C66x DSP core, that can run at a core speed of up to 1.4 GHz. TI's 66AK2E0x device enables a high
performance, power-efficient and easy to use platform for developers of a broad range of applications
such as enterprise grade networking end equipment, data center networking, avionics and defense,
medical imaging, test and automation.
TI's KeyStone II Architecture provides a programmable platform integrating various subsystems (for
example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), C66x CorePac, network
processing, and uses a queue-based communication system that allows the device resources to operate
efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the
wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum
efficiency with no blocking or stalling.
2
66AK2E0x Features and Description
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TI's C66x core launches a new era of DSP technology by combining fixed-point and floating point
computational capability in the processor without sacrificing speed, size, or power consumption. The raw
computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz
operating frequency). It can execute 8 single precision floating point MAC operations per cycle and can
perform double- and mixed-precision operations and is IEEE754 compliant. For fixed-point use, the C66x
core has 4× the multiply accumulate (MAC) capability of C64x+ cores. The C66x CorePac incorporates 90
new instructions targeted for floating point and vector math oriented processing. These enhancements
yield sizeable performance improvements in popular DSP kernels used in signal processing,
mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's
previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened
software development cycles for applications migrating to faster hardware.
The 66AK2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15
processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15
cores in the ARM CorePac share a 4MB L2 Cache. In the DSP CorePac, in addition to 32KB of L1
program and 32KB of L1 data cache, there is 512KB of dedicated memory per core that can be configured
as cache or as memory mapped RAM. The device also integrates 2MB of Multicore Shared Memory
(MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection
and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with
ECC support) external memory interface (EMIF) running at 1600 MTPS.
The device enables developers to use a variety of development and debugging tools that include GNU
GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space
debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
1.5 Enhancements in KeyStone II
The KeyStone II architecture provides many major enhancements over the previous KeyStone I
generation of devices. The KeyStone II architecture integrates an ARM Cortex-A15 processor quad-core
cluster to enable Layer 2 (MAC/RLC) and higher layer processing. The number of DSP cores has been
doubled for 2× improvement in Layer 1 processing. The external memory bandwidth has been doubled
with the integration of dual DDR3 1600 EMIFs. MSMC internal memory bandwidth is quadrupled with
MSMC V2 architecture improvements. Multicore Navigator supports 2× the number of queues, descriptors
and packet DMA, 4× the number of micro RISC engines and a significant increase in the number of
push/pops per second, compared to the previous generation. The new peripherals that have been added
include the USB 3.0 controller and Asynchronous EMIF controller for NAND/NOR memory access. The 2-
port Gigabit Ethernet switch in KeyStone I has been replaced with an 8-port Gigabit Ethernet switch and a
10 GbE switch in KeyStone II. Time synchronization support has been enhanced to reduce software
workload and support additional standards like IEEE1588 Annex D/E and SyncE. The number of GPIOs
and serial interface peripherals like I2C and SPI have been increased to enable more board level control
functionality.
Copyright © 2012–2015, Texas Instruments Incorporated
66AK2E0x Features and Description
3
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1.6 Functional Block Diagram
The figures below show the functional block diagrams of the 66AK2E0x devices.
66AK2E05
Memory Subsystem
2MB
MSM
SRAM
72-Bit
DDR3 EMIF
C66x™
CorePac
MSMC
32KB L1 32KB L1
P-Cache D-Cache
Debug & Trace
Boot ROM
512KB L2 Cache
32KB L1 32KB L1 32KB L1 32KB L1
P-Cache D-Cache P-Cache D-Cache
Semaphore
Secure Mode
ARM
A15
ARM
A15
Power
Management
4MB L2 Cache
ARM
A15
ARM
A15
32KB L1 32KB L1 32KB L1 32KB L1
PLL
3´
5´
P-Cache D-Cache P-Cache D-Cache
EDMA
1 C66x DSP Core @ up to 1.4 GHz
4 ARM Cores @ up to 1.4 GHz
TeraNet
HyperLink
Multicore Navigator
Queue
Manager
Packet
DMA
Network Coprocessor
3-Port
Ethernet
Switch
9-Port
Ethernet
Switch
Security
Accelerator
Packet
Accelerator
Figure 1-1. 66AK2E05 Functional Block Diagram
4
66AK2E0x Features and Description
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
66AK2E02
Memory Subsystem
2MB
MSM
SRAM
72-Bit
DDR3 EMIF
MSMC
Debug & Trace
Boot ROM
Semaphore
Secure Mode
C66x™
CorePac
4MB L2 Cache
ARM
A15
32KB L1 32KB L1
P-Cache D-Cache
Power
Management
32KB L1 32KB L1
P-Cache D-Cache
PLL
512KB L2 Cache
3´
5´
EDMA
1 C66x DSP Core and 1 ARM Core
@ up to 1.4 GHz
TeraNet
HyperLink
Multicore Navigator
Queue
Manager
Packet
DMA
Network Coprocessor
9-Port
Ethernet
Switch
Security
Accelerator
Packet
Accelerator
Figure 1-2. 66AK2E02 Functional Block Diagram
Table of Contents
1
2
66AK2E0x Features and Description ................ 1
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 KeyStone II Architecture.............................. 2
1.4 Device Description ................................... 2
1.5 Enhancements in KeyStone II........................ 3
1.6 Functional Block Diagram ............................ 4
Revision History ......................................... 7
3
Device Characteristics.................................. 8
3.1 C66x DSP CorePac .................................. 9
3.2 ARM CorePac ........................................ 9
3.3 Development Tools.................................. 10
3.4 Device Nomenclature ............................... 10
3.5
Related Documentation from Texas Instruments ... 12
3.6 Related Links........................................ 13
3.7 Community Resources.............................. 13
Copyright © 2012–2015, Texas Instruments Incorporated
Table of Contents
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3.8 Trademarks.......................................... 13
3.9 Electrostatic Discharge Caution..................... 13
3.10 Glossary ............................................. 13
10.2 Recommended Operating Conditions ............. 205
10.3 Electrical Characteristics........................... 206
10.4 Power Supply to Peripheral I/O Mapping.......... 207
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5
C66x CorePac ........................................... 14
4.1 Memory Architecture ................................ 15
4.2 Memory Protection .................................. 18
4.3 Bandwidth Management ............................ 18
4.4 Power-Down Control ................................ 19
4.5 C66x CorePac Revision............................. 20
4.6 C66x CorePac Register Descriptions ............... 20
ARM CorePac ........................................... 21
5.1 Features ............................................. 23
5.2 System Integration .................................. 23
5.3 ARM Cortex-A15 Processor......................... 23
5.4 CFG Connection .................................... 25
5.5 Main TeraNet Connection........................... 25
5.6 Clocking and Reset ................................. 26
Terminals ................................................ 27
6.1 Package Terminals.................................. 27
6.2 Pin Map ............................................. 27
6.3 Terminal Functions.................................. 32
6.4 Pullup/Pulldown Resistors .......................... 59
Memory, Interrupts, and EDMA for 66AK2E0x ... 61
7.1 Memory Map Summary66AK2E0x.................. 61
11 66AK2E0x Peripheral Information and Electrical
Specifications ......................................... 208
11.1 Recommended Clock and Control Signal Transition
Behavior............................................ 208
11.2 Power Supplies .................................... 208
11.3 Power Sleep Controller (PSC) ..................... 216
11.4 Reset Controller.................................... 222
11.5 Core PLL (Main PLL), DDR3 PLL, NETCP PLL and
the PLL Controllers ................................ 227
11.6 DDR3 PLL.......................................... 241
11.7 NETCP PLL ........................................ 243
11.8 External Interrupts ................................. 245
11.9 DDR3 Memory Controller .......................... 245
11.10 I2C Peripheral..................................... 246
11.11 SPI Peripheral .................................... 250
11.12 HyperLink Peripheral ............................. 253
11.13 UART Peripheral ................................. 255
11.14 PCIe Peripheral................................... 256
11.15 Packet Accelerator ............................... 256
11.16 Security Accelerator .............................. 257
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11.17 Network Coprocessor Gigabit Ethernet (GbE)
Switch Subsystem ................................. 257
11.18 SGMII/XFI Management Data Input/Output
(MDIO) ............................................. 259
11.19 Ten-Gigabit Ethernet (10GbE) Switch
7.2
Memory Protection Unit (MPU) for 66AK2E0x ...... 71
7.3 Interrupts for 66AK2E0x............................. 84
7.4
Enhanced Direct Memory Access (EDMA3)
Subsystem ......................................... 260
Controller........................................... 129
11.20 Timers............................................. 260
11.21 General-Purpose Input/Output (GPIO) ........... 261
11.22 Semaphore2 ...................................... 262
11.23 Universal Serial Bus 3.0 (USB 3.0)............... 262
11.24 TSIP Peripheral................................... 263
11.25 Universal Subscriber Identity Module (USIM) .... 265
11.26 EMIF16 Peripheral................................ 265
11.27 Emulation Features and Capability ............... 268
11.28 Debug Port (EMUx)............................... 271
12 Mechanical Data ...................................... 278
12.1 Thermal Data ...................................... 278
12.2 Packaging Information ............................. 278
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System Interconnect ................................. 140
8.1 Internal Buses and Switch Fabrics ................ 140
8.2
Switch Fabric Connections Matrix - Data Space .. 140
Switch Fabric Connections Matrix - Configuration
Space .............................................. 146
8.3
8.4 Bus Priorities....................................... 154
Device Boot and Configuration .................... 155
9.1 Device Boot ........................................ 155
9.2 Device Configuration............................... 175
10 Device Operating Conditions ...................... 204
10.1 Absolute Maximum Ratings........................ 204
6
Table of Contents
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2014) to Revision D
Page
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Added Top Navigation links to front page of the document..................................................................... 1
Changed Product Status to Production Data ..................................................................................... 1
Changed Mission Critical Systems to Avionics and Defense in Section 1.2.................................................. 2
Changed mission critical to avionics and defense in first paragraph of Section 3.3.1 ...................................... 2
Changed Product Status to PD and changed footnote (3) in Table 3-1....................................................... 8
Changed second list item under Software Development Tools in Section 3.3.1 ........................................... 10
Added Related Links, Community Resources, Trademarks, Electrostatic Discharge Caution, and Glossary
sections to Section 3................................................................................................................ 13
Added Figure 5-1.................................................................................................................... 21
Changed DDR3A to DDR3 in Table 5-1 ......................................................................................... 23
Changed All instances of DDR3A to DDR3 in Table 6-2 ...................................................................... 32
Changed Supply DDR3AREFSSTL to DDR3REFSSTL in Table 6-3 ........................................................ 45
Changed the DVDD15 Volts and Supply Description in Table 6-3 ........................................................... 45
Changed Start Address for PCIe1SerDes Config to 00 0232 6000, End Address for USB 0 MMR CFG to 00
026F FFFF, USB 1 MMR CFG and USB 1 PHY CFG to Reserved, and all instances of DDR3A to DDR3 in
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Table 7-1 ............................................................................................................................. 61
Changed CPT_DDR3A to CPT_DDR3 in Table 7-6............................................................................ 72
Changed DDR3A to DDR3 in Event No. 388 Name and Description in Table 7-23 ....................................... 88
Changed DDR3A to DDR3 in Event No. 77 and 100 Descriptions in Table 7-24 .......................................... 98
Changed DDR3A to DDR3 in Section 7.4...................................................................................... 130
Changed DDR3A to DDR3 in Section 8 ........................................................................................ 140
Changed DDR3A to DDR3 in Figure 8-3 ....................................................................................... 143
Changed DDR3A to DDR3 in Figure 8-7 ....................................................................................... 148
Changed Start Address 0x87_fd20 Description to DDR3 Configuration Structure in Table 9-1 ........................ 155
Added EMIF and NAND to Description in Table 9-3.......................................................................... 158
Changed DDR3A to DDR3 in Section 9.1.4.................................................................................... 174
Changed DDR3APLLCTL0 and DDR3APLLCTL1 to DDR3PLLCTL0 and DDR3PLLCTL1 in Table 9-27 ............ 176
Changed AVSIFSEL Description value 11 to Reserved in Table 9-28 ..................................................... 180
Changed ARMENDIAN_CFG4_0 Default Value to 0x00023A00 in Table 9-47........................................... 193
Changed ARMENDIAN_CFG5_1 Default Value to 0x00000006 in Table 9-49 ........................................... 194
Changed DDR3AVREFSSTL to DDR3VREFSSTL and DDR3A to DDR3 in Section 10.1 .............................. 204
Changed MIN, NOM, and MAX values for CVDD Initial and CVDD1; changed DVDD15 to DDR3 I/O voltage and
added values; changed DDR3A to DDR3 and DDR3AVREFSSTL to DDR3VREFSSTL; changed DSP to SOC in
footnote (4) in Section 10.2....................................................................................................... 205
Changed DDR3A to DDR3 in Section 10.3 .................................................................................... 206
Changed DDR3A to DDR3 and changed DVDD15 to DDR3 memory I/O voltage and DDR3 (1.5/1.35 V) I/O
Buffer Type in Table 10-1......................................................................................................... 207
Changed DDR3A to DDR3 and added 1.35 V to Voltage for DVDD15 in Table 11-1.................................... 208
Changed EMIF(DDR3A) to EMIF(DDR3) in Table 11-6 ...................................................................... 216
Changed DDR3A EMIF to DDR3 EMIF in Table 11-7 ........................................................................ 217
Changed DDR3A in Section 11.4.3 ............................................................................................. 224
Changed DDR3A in Section 11.5................................................................................................ 227
Changed Figure 11-7.............................................................................................................. 228
Deleted second sentence from Section 11.5.1.1 .............................................................................. 229
Changed DDR3A to DDR3 in Table 11-13 ..................................................................................... 230
Changed Address Range 00 0231 0128 to Reserved in Table 11-15...................................................... 231
Changed OUTPUT DIVIDE Field Description in Table 11-16 ............................................................... 232
Changed MAX value for tj(CORECLKN) and tj(CORECLKP) in Table 11-27 ............................................. 238
Changed Figure 11-26 ............................................................................................................ 243
Changed PAPLL Field Description in Table 11-32 ............................................................................ 244
Changed MAX value for tc(NETCPCLKN) and tc(NETCPCLKP) in Table 11-33 ......................................... 244
Changed DDR3A Memory Controller to DDR3 Memory Controller in Section 11.9 ...................................... 245
Changed MIN and MAX values for tc(CEL) in Table 11-57 .................................................................. 265
Changed DDR3A to DDR3 in Table 11-63 ..................................................................................... 274
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Copyright © 2012–2015, Texas Instruments Incorporated
Revision History
7
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3 Device Characteristics
Table 3-1 provides an overview of the 66AK2E0x device. The table shows the significant features of the
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.
Table 3-1. Characteristics of the 66AK2E0x Processor
HARDWARE FEATURES
C66x DSP core
66AK2E02
66AK2E05
1
DSP L1P cache memory size (per core)
32KB
32KB
512KB
DSP Cores
ARM Cores
DSP L1D cache/RAM memory size (per core)
DSP L2 Unified cache/RAM memory size (per core)
ARM Cortex A15 Cores
1
4
ARM L1 instruction cache memory size (per core)
ARM L1 data cache memory size (per core)
ARM L2 unified cache memory size (shared by all cores)
32KB
32KB
4MB
1
DDR3 memory controller (72-bit bus width) [1.5 V/1.35V] (clock source =
DDRREFCLKN|P)
EDMA3 (64 independent channels) [CPU/3 clock rate]
5
1
2
1
3
3
2
2
Hyperlink
USB 3.0
USIM(1)
I2C
SPI
Peripherals
PCIe (2 lanes per instance)
UART
10/100/1000/10000 Ethernet ports
10/100/1000 Ethernet ports
Management Data Input/Output (MDIO)
64-bit timers (configurable)
General-Purpose Input/Output port (GPIO)
TSIP
0
8
2
8
3
Thirteen 64-bit or Twenty six 32-bit
32
1
Packet Accelerator
Security Accelerator(2)
1
Accelerators
1
2MB MSM SRAM
256 KB L3 ROM
On-Chip L3 Memory
Organization
C66x CorePac Revision CorePac Revision ID Register (address location: 0181 2000h)
ID
0x0009_0003
JTAG BSDL_ID
JTAGID Register (address location: 0x02620018)
0x0B9A_602F
1.25 GHz
1.4 GHz
Frequency
C66x DSP and ARM-A15 Processor
Core (V)
SmartReflex variable supply
1.35 V, 1.5 V, 1.8 V, and 3.3 V
Voltage
I/O (V)
27 mm x 27 mm
1089-Pin Flip-Chip Plastic BGA
(ABD)
BGA Package
Process Technology
Product Status(3)
nm
28 nm
PD
Product Preview (PP), Advance Information (AI), or Production Data (PD)
(1) The USIM is implemented for support of secure devices only. Contact your local technical sales representative for further details.
(2) The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
(3) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
8
Device Characteristics
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3.1 C66x DSP CorePac
The C66x DSP CorePac extends the performance of the C64x+ and C674x CPUs through enhancements
and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-
bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the
SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. The C66x CPU
also supports SIMD for floating-point operations. Improved vector processing capability (each instruction
can process multiple data in parallel) combined with the natural instruction level parallelism of C6000™
architecture (e.g., execution of up to 8 instructions per cycle) results in a very high level of parallelism that
can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.
For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see
the following documents:
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•
TMS320C66x DSP CPU and Instruction Set Reference Guide (SPRUGH7)
TMS320C66x DSP Cache User's Guide (SPRUGY8)
TMS320C66x DSP CorePac User's Guide (SPRUGW0)
3.2 ARM CorePac
The ARM CorePac of the 66AK2E0x integrates a Cortex-A15 Cluster (4 Cortex-A15 processors) with
additional logic for bus protocol conversion, emulation, interrupt handling, and debug related
enhancements. The Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order, superscalar
pipeline with integrated L1 caches. The implementation also supports advanced SIMDV2 (Neon
technology) and VFPv4 (Vector Floating Point) architecture extensions, security, virtualization, LPAE
(Large Physical Address Extension), and multiprocessing extensions. The quad core cluster includes a
4MB L2 cache and support for AMBA4 AXI and AXI Coherence Extension (ACE) protocols. For more
information see the KeyStone II Architecture ARM CorePac User's Guide User Guide (SPRUHJ4).
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3.3 Development Tools
3.3.1 Development Support
In case the customer would like to develop their own features and software on the 66AK2E0x device, TI
offers an extensive line of development tools for the KeyStone II platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tool's support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of KeyStone devices:
•
Software Development Tools:
–
Code Composer Studio Integrated Development Environment (IDE), including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
–
Scalable, Real-Time foundation software, which provides the basic run-time target software needed
to support any application
•
Hardware Development Tools:
–
–
Extended Development System (XDS™) Emulator (supports multiprocessor system debug) XDS™
EVM (Evaluation Module)
3.4 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
devices and support tools. Each family member has one of two prefixes: X or [blank]. These prefixes
represent evolutionary stages of product development from engineering prototypes through fully qualified
production devices/tools.
3.4.1 Device Development Evolutionary Flow
The device development evolutionary flow is as follows:
•
X: Experimental device that is not necessarily representative of the final device's electrical
specifications
•
[Blank]: Fully qualified production device
Support tool development evolutionary flow:
•
X: Development-support product that has not yet completed Texas Instruments internal qualification
testing.
•
[Blank]: Fully qualified development-support product
Experimental (X) and fully qualified [Blank] devices and development-support tools are shipped with the
following disclaimer:
Developmental product is intended for internal evaluation purposes.
Fully qualified and production devices and development-support tools have been characterized fully, and
the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that experimental devices (X) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ABD), the temperature range (for example, blank is the default case
temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).
For device part numbers and further ordering information for 66AK2E0x in the ABD package type, see the
TI website www.ti.com or contact your TI sales representative.
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3.4.2 Part Number Legend
The following figures provide a legend for reading the complete device name for a KeyStone II device.
( _ )
( _ ) ( _ )
( _ ) ( _ )
ABD
66A K2
E
02
PREFIX
MAXIMUM DEVICE SPEED
25 = 1.25 GHz
4 = 1.4 GHz
X = Experimental device
Blank = Qualified device
DEVICE FAMILY
TEMPERATURE RANGE
66A = DSP + ARM SoC
Blank = Commercial temperature range (0°C to +85°C)
A = Extended temperature range (-40°C to +100°C)
ARCHITECTURE
K2 = KeyStone II
PACKAGE TYPE
ABD = 1089-pin plastic ball grid array,
with Pb-free solder balls and die bumps
PLATFORM
E
SECURITY
DEVICE NUMBER
Blank = Security Accelerator disabled / General Purpose device
X = Security Accelerator enabled / General Purpose device
D = Security Accelerator enabled / High Security device
with TI developmental keys
02
SILICON REVISION
Blank = Initial 1.0 silicon
S = Security Accelerator enabled / High Security device
with production keys
Figure 3-1. Device Nomenclature for 66AK2E02
( _ )
( _ ) ( _ )
( _ ) ( _ )
ABD
66A K2
E
05
PREFIX
MAXIMUM DEVICE SPEED
25 = 1.25 GHz
4 = 1.4 GHz
X = Experimental device
Blank = Qualified device
DEVICE FAMILY
TEMPERATURE RANGE
66A = DSP + ARM SoC
Blank = Commercial temperature range (0°C to +85°C)
A = Extended temperature range (-40°C to +100°C)
ARCHITECTURE
K2 = KeyStone II
PACKAGE TYPE
ABD = 1089-pin plastic ball grid array,
with Pb-free solder balls and die bumps
PLATFORM
E
SECURITY
DEVICE NUMBER
Blank = Security Accelerator disabled / General Purpose device
X = Security Accelerator enabled / General Purpose device
D = Security Accelerator enabled / High Security device
with TI developmental keys
05
SILICON REVISION
Blank = Initial 1.0 silicon
S = Security Accelerator enabled / High Security device
with production keys
Figure 3-2. Device Nomenclature for 66AK2E05
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3.5 Related Documentation from Texas Instruments
These documents describe the 66AK2E0x Multicore ARM+DSP KeyStone II System-on-Chip (SoC).
Copies of these documents are available on the Internet at www.ti.com.
KeyStone Architecture Timer 64P User's Guide
SPRUGV5
SPRUHJ3
SPRUHJ4
SPRUGY5
SPRUGW0
SPRUGH7
SPRUGY8
SPRUGW4
SPRUGZ2
SPRABI1
KeyStone II Architecture ARM Bootloader User's Guide
KeyStone II Architecture ARM CorePac User's Guide
KeyStone Architecture DSP Bootloader User's Guide
TMS320C66x DSP CorePac User's Guide
TMS320C66x DSP CPU and Instruction Set Reference Guide
TMS320C66x DSP Cache User's Guide
KeyStone Architecture Chip Interrupt Controller (CIC) User's Guide
KeyStone I Architecture Debug and Trace User's Guide
DDR3 Design Requirements for KeyStone Devices application report
KeyStone Architecture DDR3 Memory Controller User's Guide
Power Consumption Summary for KeyStone TCI66x Devices application report
KeyStone Architecture External Memory Interface (EMIF16) User's Guide
Emulation and Trace Headers Technical Reference Manual
SPRUGV8
SPRABL4
SPRUGZ3
SPRU655
SPRUGS5
SPRUGV1
SPRUGV9
SPRUHJ5
SPRUGW8
SPRABV0
SPRUGV3
SPRUGW5
SPRUGR9
SPRUGW7
SPRUHJ6
SPRAB27
SPRUHZ0
SPRABG8
SPRABG7
SPRUHZ2
SPRUGS6
SPRUGV2
SPRUGV4
SPRUHZ1
SPRABS4
SPRUGS3
SPRUHO3
SPRUGP2
SPRUGY4
SPRUGP1
SPRUHJ7
SPRUH06
KeyStone Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide
KeyStone Architecture General Purpose Input/Output (GPIO) User's Guide
Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide
KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User's Guide
KeyStone Architecture HyperLink User's Guide
Hardware Design Guide for KeyStone II Devices application report
KeyStone Architecture Inter-IC control Bus (I2C) User's Guide
KeyStone Architecture Memory Protection Unit (MPU) User's Guide
KeyStone Architecture Multicore Navigator User's Guide
KeyStone Architecture Multicore Shared Memory Controller (MSMC) User's Guide
KeyStone II Architecture Multicore Shared Memory Controller (MSMC) User's Guide
Multicore Programming Guide application report
KeyStone II Architecture Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide
Optimizing Application Software on KeyStone Devices application report
Optimizing Loops on the C66x DSP application report
KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide
KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User's Guide
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
KeyStone Architecture Power Sleep Controller (PSC) User's Guide
KeyStone II Architecture Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide
Security Addendum for KeyStone II Devices application report(1)
KeyStone Architecture Semaphore2 Hardware Module User's Guide
KeyStone II Architecture Serializer/Deserializer (SerDes) User's Guide
KeyStone Architecture Serial Peripheral Interface (SPI) User's Guide
KeyStone Architecture Telecom Serial Interface Port (TSIP) User's Guide
KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User's Guide
KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide
KeyStone II Architecture IQN2 User's Guide
(1) Contact a TI sales office to obtain this document.
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3.6 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
66AK2E05
66AK2E02
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
3.7 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
3.8 Trademarks
C6000, Code Composer Studio, XDS, E2E are trademarks of Texas Instruments.
MPCore is a trademark of ARM Ltd or its subsidiaries.
ARM, Cortex are registered trademarks of ARM Ltd or its subsidiaries.
All other trademarks are the property of their respective owners.
3.9 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
3.10 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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4 C66x CorePac
The C66x CorePac consists of several components:
•
•
•
•
•
•
•
•
Level-one and level-two memories (L1P, L1D, L2)
Data Trace Formatter (DTF)
Embedded Trace Buffer (ETB)
Interrupt controller
Power-down controller
External memory controller
Extended memory controller
A dedicated local power/sleep controller (LPSC)
The C66x CorePac also provides support for big and little endianness, memory protection, and bandwidth
management (for resources local to the CorePac). Figure 4-1 shows a block diagram of the C66x
CorePac.
32KB L1P
Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
L2 Cache/
SRAM
512KB
C66x DSP Core
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
MSM
SRAM
2048KB
In-Circuit Emulation
Boot
Controller
Instruction Decode
Data Path A
A Register File
Data Path B
B Register File
DDR3
SRAM
PLLC
LPSC
GPSC
A31-A16
A15-A0
B31-B16
B15-B0
DMA Switch
Fabric
.M1
.L1 .S1 xx .D1
xx
.M2
.D2 xx .S2 .L2
xx
CFG Switch
Fabric
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
32KB L1D
Figure 4-1. C66x CorePac Block Diagram
For more detailed information on the C66x CorePac in the 66AK2E0x device, see theTMS320C66x DSP
CorePac User's Guide (SPRUGW0).
14
C66x CorePac
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4.1 Memory Architecture
Each C66x CorePac of the 66AK2E0x device contains a 512KB level-2 memory (L2), a 32KB level-1
program memory (L1P), and a 32KB level-1 data memory (L1D). The device also contains a 2048KB
multicore shared memory (MSM). All memory on the 66AK2E0x has a unique location in the memory map
(see Section 7).
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache
can be reconfigured via software through the L1PMODE field of the L1P Configuration Register
(L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac.
L1D is a two-way set-associative cache, while L1P is a direct-mapped cache.
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the
KeyStone Architecture DSP Bootloader User's Guide (SPRUGY5).
For more information on the operation L1 and L2 caches, see the TMS320C66x DSP Cache User's Guide
(SPRUGY8).
4.1.1 L1P Memory
The L1P memory configuration for the 66AK2E0x device is as follows:
•
•
Region 0 size is 0K bytes (disabled)
Region 1 size is 32K bytes with no wait states
Figure 4-2 shows the available SRAM/cache configurations for L1P.
L1P Mode Bits
Block Base
Address
000
001
010
011
100
L1P Memory
16K bytes
00E0 0000h
1/2
SRAM
3/4
SRAM
7/8
SRAM
Direct
Mapped
Cache
All
SRAM
00E0 4000h
8K bytes
Direct
Mapped
Cache
00E0 6000h
00E0 7000h
00E0 8000h
4K bytes
4K bytes
Direct
Mapped
Cache
DM
Cache
Figure 4-2. L1P Memory Configurations
4.1.2 L1D Memory
The L1D memory configuration for the 66AK2E0x device is as follows:
•
•
Region 0 size is 0K bytes (disabled)
Region 1 size is 32K bytes with no wait states
Figure 4-3 shows the available SRAM/cache configurations for L1D.
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L1D Mode Bits
010
Block Base
Address
000
001
011
100
L1D Memory
16K bytes
00F0 0000h
1/2
SRAM
3/4
SRAM
7/8
SRAM
2-Way
Cache
All
SRAM
00F0 4000h
8K bytes
2-Way
Cache
00F0 6000h
00F0 7000h
00F0 8000h
4K bytes
4K bytes
2-Way
Cache
2-Way
Cache
Figure 4-3. L1D Memory Configurations
4.1.3 L2 Memory
The L2 memory configuration for the 66AK2E0x device is as follows:
•
•
•
Total memory size is 512KB
Each CorePac contains 512KB of memory
Local starting address for each CorePac is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The
amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2
Configuration Register (L2CFG) of the C66x CorePac. Figure 4-4 shows the available SRAM/cache
configurations for L2. By default, L2 is configured as all SRAM after device reset.
16
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L2 Mode Bits
011
Block Base
Address
000
001
010
100
101
110
L2 Memory
0080 0000h
1/2
SRAM
256K bytes
3/4
SRAM
7/8
SRAM
15/16
SRAM
31/32
SRAM
ALL
SRAM
4-Way
Cache
0084 0000h
128K bytes
4-Way
Cache
0086 0000h
64K bytes
4-Way
Cache
0087 0000h
32K bytes
4-Way
Cache
0087 8000h
16K bytes
0087 C000h
4-Way
Cache
16K bytes
4-Way
Cache
0087 FFFFh
Figure 4-4. L2 Memory Configurations
Global addresses that are accessible to all masters in the system are in all memory local to the
processors. In addition, local memory can be accessed directly by the associated processor through
aliased addresses, where the eight MSBs are masked to 0.
4.1.4 Multicore Shared Memory SRAM
The MSM SRAM configuration for the 66AK2E0x device is as follows:
•
•
•
•
Memory size of 2048KB
Can be configured as shared L2 or shared L3 memory
Allows extension of external addresses from 2GB up to 8GB
Has built-in memory protection features
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The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be
cached in L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For
more details on external memory address extension and memory protection features, see the KeyStone
Architecture Multicore Shared Memory Controller (MSMC) User's Guide (SPRUGW7).
4.1.5 L3 Memory
The L3 ROM on the device is 256KB. The ROM contains software used to boot the device. There is no
requirement to block accesses from this portion to the ROM.
4.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (32KB each). The L1D, L1P,
and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the
permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. In addition, a page may be marked as either (or both) locally accessible or globally
accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated
by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers
programmed by the DSP count as global accesses. On a secure device, pages can be restricted to secure
access only (default) or opened up for public, non-secure access.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to
specify only whether memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page
protection scheme, see Table 4-1.
Table 4-1. Available Memory Page Protection Schemes
AIDx BIT(1)
LOCAL BIT DESCRIPTION
0
0
1
0
1
0
No access to memory page is permitted.
Only direct access by DSP is permitted.
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by
the DSP).
1
1
All accesses permitted.
(1) x = 0, 1, 2, 3, 4, 5
Faults are handled by software in an interrupt (or an exception, programmable within the CorePac
interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:
•
•
•
Block the access — reads return 0, writes are ignored
Capture the initiator in a status register — ID, address, and access type are stored
Signal the event to the DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error
status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the
TMS320C66x DSP CorePac User's Guide (SPRUGW0).
4.3 Bandwidth Management
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting
access to the highest priority requestor. The following four resources are managed by the bandwidth
management control hardware:
•
•
Level 1 Program (L1P) SRAM/Cache
Level 1 Data (L1D) SRAM/Cache
18
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•
•
Level 2 (L2) SRAM/Cache
Memory-mapped registers configuration bus
The priority level for operations initiated within the C66x CorePac are declared through registers in the
CorePac. These operations are:
•
•
•
DSP-initiated transfers
User-programmed cache coherency operations
IDMA-initiated transfers
The priority level for operations initiated outside the CorePac by system peripherals is declared through
the Priority Allocation Register (PRI_ALLOC). System peripherals with no fields in PRI_ALLOC have their
own registers to program their priorities.
More information on the bandwidth management features of the CorePac can be found in
theTMS320C66x DSP CorePac User's Guide (SPRUGW0).
4.4 Power-Down Control
The C66x CorePac supports the ability to power-down various parts of the CorePac. The power-down
controller (PDC) of the CorePac can be used to power down L1P, the cache control hardware, the DSP,
and the entire CorePac. These power-down features can be used to design systems for lower overall
system power requirements.
NOTE
The 66AK2E0x does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the TMS320C66x
DSP CorePac User's Guide (SPRUGW0).
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4.5 C66x CorePac Revision
The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register
(MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 4-5 and
described in Table 4-2. The C66x CorePac revision is dependent on the silicon revision being used.
Figure 4-5. CorePac Revision ID Register (MM_REVID)
31
16
15
0
VERSION
R-n
REVISION
R-n
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4-2. CorePac Revision ID Register (MM_REVID) Field Descriptions
Bit
Name
Value
Description
31-16 VERSION
xxxxh
Version of the C66x CorePac implemented on the device will depend on the silicon being
used.
15-0
REVISION
0000h
Revision of the C66x CorePac version implemented on this device.
4.6 C66x CorePac Register Descriptions
See the TMS320C66x DSP CorePac User's Guide (SPRUGW0) for register offsets and definitions.
20
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5 ARM CorePac
The ARM CorePac is added in the 66AK2E0x to enable the ability for layer 2 and layer 3 processing on-
chip. Operations such as traffic control, local O&M, NBAP/FP termination, and SCTP processing can all
be performed with the Cortex-A15 processor core.
The ARM CorePac of the 66AK2E0x integrates one or more Cortex-A15 processor clusters with additional
logic for bus protocol conversion, emulation, interrupt handling, and debug related enhancements. The
Cortex-A15 processor is an ARMv7A-compatible, multi-issue out-of-order superscalar execution engine
with integrated L1 caches. The implementation also supports advanced SIMDv2 (NEON technology) and
VFPv4 (vector floating point) architecture extensions, security, virtualization, LPAE (large physical address
extension), and multiprocessing extensions. The ARM CorePac includes an L2 cache and support for
AMBA4 AXI and AXI coherence extension (ACE) protocols. An interrupt controller is included in the ARM
CorePac to handle host interrupt requests in the system.
The ARM CorePac has three functional clock domains, including a high-frequency clock domain used by
the Cortex-A15. The high-frequency domain is isolated from the rest of the device by asynchronous
bridges.
The following figures show the ARM CorePac.
KeyStone II ARM CorePac (Quad Core)
ARM
ARM Cluster
STM
ATB
IRQ,
FIQ,
VIRQ,
VFIQ
VBUSP
OCP
TeraNet
(DMA)
ARM
A15
32KB L1 32KB L1
ARM INTC
ARM
Generic
Interrupt
Controller
400
Trace
P-Cache D-Cache
480 SPI
Interrupts
ATB
APB
APB MUX
ARM
A15
32KB L1 32KB L1
APB
ATB
16
PPI
Debug
SubSystem
PTM (´4)
Debug
P-Cache D-Cache
APB
VBUSP2AXI
Bridge
TeraNet
(CFG)
ARM
A15
32KB L1 32KB L1
CTI/CTM
P-Cache D-Cache
ARM
VBUSP
Registers
VBUSP
64
Bits
TeraNet
(CFG)
CTM
ARM
A15
32KB L1 32KB L1
Global
Time Base
Counter
CTI (´4)
P-Cache D-Cache
256b
VBUSM
AXI-VBUS
Master
MSMC
DDR3
ARM
CorePac
Clock
ARM
A15 Core
Clock
Endian
CFG
Boot Config
Main PLL
ARM PLL
PSC
66AK2E05
Figure 5-1. 66AK2E05 ARM CorePac Block Diagram
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KeyStone II ARM CorePac (Single Core)
ARM
ARM Cluster
STM
ATB
IRQ,
FIQ,
VBUSP
OCP
TeraNet
(DMA)
VIRQ,
VFIQ
ARM INTC
ARM
Trace
Generic
Interrupt
Controller
400
480 SPI
Interrupts
ATB
APB
APB MUX
APB
ATB
4
PPI
Debug
SubSystem
PTM (´4)
Debug
ARM
A15
32KB L1 32KB L1
APB
VBUSP2AXI
Bridge
TeraNet
(CFG)
P-Cache D-Cache
CTI/CTM
ARM
VBUSP
Registers
VBUSP
64
Bits
TeraNet
(CFG)
CTM
Global
Time Base
Counter
CTI (´4)
256b
VBUSM
AXI-VBUS
Master
MSMC
DDR3
ARM
CorePac
Clock
ARM
A15 Core
Clock
Endian
CFG
Boot Config
Main PLL
PSC
66AK2E02
Figure 5-2. 66AK2E02 ARM CorePac Block Diagram
22
ARM CorePac
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5.1 Features
The key features of the Quad Core ARM CorePac are as follows:
•
One or more Cortex-A15 processors, each containing:
–
–
–
–
–
–
Cortex-A15 processor revision R2P4.
ARM architecture version 7 ISA.
Multi-issue, out-of-order, superscalar pipeline.
L1 and L2 instruction and data cache of 32KB, 2-way, 16 word line with 128-bit interface.
Integrated L2 cache of 4MB, 16-way, 16-word line, 128-bit interface to L1 along with ECC/parity.
Includes the NEON media coprocessor (NEON™), which implements the advanced SIMDv2 media
processing architecture and the VFPv4 Vector Floating Point architecture.
–
–
–
The external interface uses the AXI protocol configured to 128-bit data width.
Includes the System Trace Macrocell (STM) support for non-invasive debugging.
Implements the ARMv7 debug with watchpoint and breakpoint registers and 32-bit advanced
peripheral bus (APB) slave interface to CoreSight™ debug systems.
•
•
Interrupt controller
–
–
Supports up to 480 interrupt requests
An integrated Global Time Base Counter (clocked by the SYSCLK divided by 6)
Emulation/debug
Compatible with CoreSight™ architecture
–
5.2 System Integration
The ARM CorePac integrates the following group of submodules.
•
Cortex-A15 Processors: Provides a high processing capability, including the NEON™ technology for
mobile multimedia acceleration. The Cortex-A15 communicates with the rest of the ARM CorePac
through an AXI bus with an AXI2VBUSM bridge and receives interrupts from the ARM CorePac
interrupt controller (ARM INTC).
•
•
•
Interrupt Controller: Handles interrupts from modules outside of the ARM CorePac (for details, see
Section 5.3.3).
Clock Divider: Provides the required divided clocks to the internal modules of the ARM CorePac and
has a clock input from the Main PLL.
In-Circuit Emulator: Fully compatible with CoreSight™ architecture and enables debugging
capabilities.
5.3 ARM Cortex-A15 Processor
5.3.1 Overview
The ARM Cortex-A15 processor incorporates the technologies available in the ARM7™ architecture.
These technologies include NEON™ for media and signal processing and Jazelle™ RCT for acceleration
of real-time compilers, Thumb®-2 technology for code density, and the VFPv4 floating point architecture.
For details, see the ARM Cortex-A15 Processor Technical Reference Manual.
5.3.2 Features
Table 5-1 shows the features supported by the Cortex-A15 processor core.
Table 5-1. Cortex-A15 Processor Core Supported Features
FEATURES
DESCRIPTION
ARM version 7-A ISA
Standard Cortex-A15 processor instruction set + Thumb2, ThumbEE, JazelleX Java accelerator, and
media extensions
Backward compatible with previous ARM ISA versions
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Table 5-1. Cortex-A15 Processor Core Supported Features (continued)
FEATURES
DESCRIPTION
Cortex-A15 processor version
Integer core
R2P4
Main core for processing integer instructions
Gives greatly enhanced throughput for media workloads and VFP-Lite support
Security, virtualization and LPAE (40-bit physical address) extensions
32KB, 2-way, 16 word line, 128 bit interface
NEON core
Architecture Extensions
L1 Lcache and Dcache
L2 cache
4096KB, 16-way, 16 word line, 128 bit interface to L1, ECC/Parity is supported shared between cores
L2 valid bits cleared by software loop or by hardware
Cache Coherency
Support for coherent memory accesses between A15 cores and other non-core master peripherals
(Ex: EDMA) in the DDR3 and MSMC SRAM space. (Cache coherency is not supported between
Cortex-A15 and DSP cores or between DSP cores.)
Branch target address cache
Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return
stack, and an indirect predictor
Enhanced memory management
unit
Mapping sizes are 4KB, 64KB, 1MB, and 16MB
Buses
128b AXI4 internal bus from Cortex-A15 converted to a 256b VBUSM to interface (through the
MSMC) with MSMC SRAM, DDR EMIF, ROM, Interrupt controller and other system peripherals
Non-invasive Debug Support
Processor instruction trace using 4x Program Trace Macrocell (Coresight™ PTM), Data trace (print-f
style debug) using System Trace Macrocell (Coresight™ STM) and Performance Monitoring Units
(PMU)
Misc Debug Support
Voltage
JTAG based debug and Cross triggering
SmartReflex voltage domain for automatic voltage scaling
Power
Support for standby modes and separate core power domains for additional leakage power reduction
5.3.3 ARM Interrupt Controller
The ARM CorePac interrupt controller (AINTC) is responsible for prioritizing all service requests from the
system peripherals and the secondary interrupt controller CIC2 and then generating either nIRQ or nFIQ
to the Cortex-A15 processor. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt
inputs are programmable. The AINTC interfaces to the Cortex-A15 processor via the AXI port through an
VBUS2AXI bridge and runs at half the processor speed. It has the capability to handle up to 480 requests,
which can be steered/prioritized as A15 nFIQ or nIRQ interrupt requests.
The general features of the AINTC are:
•
•
•
•
•
Up to 480 level sensitive shared peripheral interrupts (SPI) inputs
Individual priority for each interrupt input
Each interrupt can be steered to nFIQ or nIRQ
Independent priority sorting for nFIQ and nIRQ
Secure mask flag
On the chip level, there is a dedicated chip level interrupt controller to serve the ARM interrupt controller.
See Section 7.3 for more details.
The figures below show an overall view of the ARM CorePac Interrupt Controller.
24
ARM CorePac
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FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
ARM INTC
480 SPI
Interrupts
Peripherals
CIC2
Generic
Interrupt
Controller
400
4 PPIs
64 Bits
Cortex
A15
CPU/6 Clock
Global
Time Base
Counter
GTB Counter Clock
Power On Reset
VBUSP2AXI
Bridge
VBUSP Interface
16 Software
Generated
Inputs
Figure 5-3. ARM Interrupt Controller for One Cortex-A15 Processor Core
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
ARM INTC
480 SPI
Interrupts
Peripherals
CIC2
Generic
Interrupt
Controller
400
16 PPIs
64 Bits
Cortex
A15
CPU/6 Clock
Global
Time Base
Counter
GTB Counter Clock
Power On Reset
VBUSP2AXI
Bridge
VBUSP Interface
16 Software
Generated
Inputs
Figure 5-4. ARM Interrupt Controller for Four Cortex-A15 Processor Cores
5.3.4 Endianess
The ARM CorePac can operate in either little endian or big endian mode. When the ARM CorePac is in
little endian mode and the rest of the system is in big endian mode, the bridges in the ARM CorePac are
responsible for performing the endian conversion.
5.4 CFG Connection
The ARM CorePac has two slave ports. The 66AK2E0x masters cannot access the ARM CorePac internal
memory space.
1. Slave port 0 (TeraNet 3P_A) is a 32 bit wide port used for the ARM Trace module.
2. Slave port 1 (TeraNet 3P_B) is a 32 bit wide port used to access the rest of the system configuration.
5.5 Main TeraNet Connection
There is one master port coming out of the ARM CorePac. The master port is a 256 bit wide port for the
transactions going to the MSMC and DDR_EMIF data spaces.
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5.6 Clocking and Reset
5.6.1 Clocking
The Cortex-A15 processor core clocks are sourced from the Main PLL Controller. The Cortex-A15
processor core clock has a maximum frequency of 1.4 GHz. The ARM CorePac subsytem also uses the
SYSCLK1 clock source from the main PLL which is locally divided (/1, /3 and /6) and provided to certain
sub-modules inside the ARM CorePac. AINTC sub module runs at a frequency of SYSCLK1/6.
5.6.2 Reset
The ARM CorePac does not support local reset. It is reset whenever the device is under reset. In addition,
the interrupt controller (AINTC) can only be reset during POR and RESETFULL. AINTC also resets
whenever device is under reset.
For the complete programming model, refer to the KeyStone II Architecture ARM CorePac User's Guide
(SPRUHJ4).
26
ARM CorePac
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6 Terminals
6.1 Package Terminals
Figure 6-1 shows the ABD 1089-ball grid array package (bottom view).
32 30 28 26 24 22 20 18 16 14 12 10
33 31 29 27 25 23 21 19 17 15 13 11
8
6
4
2
9
7
5
3
1
A
C
B
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
AA
AC
AE
AG
AJ
AL
AN
Y
AB
AD
AF
AH
AK
AM
Figure 6-1. ABD 1089-Pin BGA Package (Bottom View)
6.2 Pin Map
The following figures show the 66AK2E0x pin assignments in four panels (A, B, C, and D).
C
A B D
Figure 6-2. Pin Map Panels (Bottom View)
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NOTE
XFI pins are associated with the 10-GbE feature and are supported only in the 66AK2E05
part.
33
32
DVDD15
DDRD63
DDRD61
DDRD62
DDRD59
DDRD58
VCNTL4
RSV000
RSV001
TIMI1
31
DDRDQM7
DDRD50
DVDD15
VSS
30
DDRDQS6P
DDRDQS6N
DDRD53
DDRD55
DDRD54
VSS
29
28
DDRD49
DDRD44
DDRD42
DDRD41
DDRD40
VSS
27
DDRDQS5P
DDRDQS5N
VSS
26
DDRD45
DDRD46
DDRD47
DDRDQM5
DDRDQM4
VSS
A
B
VSS
DDRD48
DDRD52
VSS
DVDD15
DDRDQS7P
DDRDQS7N
DDRD60
DDRD57
VCNTL1
USIMIO
USIMCLK
TIMI0
C
D
DVDD15
DDRD51
DVDD15
VSS
DVDD15
DDRD43
DVDD15
VSS
E
DDRDQM6
DDRD56
VSS
F
G
DVDD15
VCNTL3
RSV013
TIMO1
DVDD15
VSS
DVDD15
VSS
H
VCNTL2
VCNTL5
TIMO0
VCNTL0
RSV014
USIMRST
SPI0SCS2
SPI0SCS1
SPI0DOUT
SPI1SCS0
SPI2SCS1
UART0RXD
UART1RXD
VCL
DVDD15
VSS
J
DVDD18
VSS
CVDD
K
DVDD18
VSS
VSSTMON
CVDDTMON
VSS
L
SPI2CLK
SPI1CLK
SPI1SCS3
SPI2SCS2
UART0CTS
UART1RTS
UART0DTR
GPIO03
GPIO09
GPIO14
GPIO16
GPIO18
GPIO21
GPIO28
GPIO30
LRESET
NMI
SPI0SCS3
SPI1SCS1
VSS
SPI0SCS0
SPI0DIN
DVDD18
SPI2SCS0
SPI2DOUT
UART1CTS
DVDD18
GPIO07
GPIO08
GPIO15
DVDD18
GPIO19
GPIO23
GPIO29
DVDD18
BOOTCOMPLETE
TDI
SPI2SCS3
SPI0CLK
SPI1SCS2
SPI2DIN
SPI1DIN
UART0TXD
VD
DVDD18
VSS
M
DVDD18
VSS
N
DVDD18
VSS
CVDD
P
SPI1DOUT
UART0RTS
UART1TXD
VSS
DVDD18
VSS
VSS
R
DVDD18
VSS
CVDD
T
DVDD18
VSS
VSS
U
DVDD18
VSS
CVDD
V
GPIO04
GPIO06
GPIO12
VSS
GPIO00
GPIO05
GPIO11
GPIO13
GPIO25
GPIO26
GPIO31
LRESETNMIEN
HOUT
DVDD18
VSS
VSS
W
Y
UART0DSR
GPIO02
DVDD18
VSS
CVDD
DVDD18
VSS
VSS
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
GPIO01
DVDD18
VSS
CVDD
GPIO17
GPIO24
GPIO27
VSS
GPIO10
DVDD18
VSS
VSS
GPIO20
DVDD18
VSS
CVDD
GPIO22
DVDD18
VSS
VSS
RESET
DVDD18
VSS
DVDD18
VSS
RESETFULL
TRST
TDO
DVDD18
VSS
SCL0
SDA2
SDA0
DVDD18
VSS
POR
TMS
SCL2
SCL1
RESETSTAT
VSS
VSS
DVDD18
SGMII00REFRES
VSS
TCK
SDA1
TSIP0FSA
TSIP0CLKA
VSS
DVDD18
VSS
RSV018
SGMII0TXP1
VSS
RSV019
SGMII0TXN3
SGMII0TXP2
SGMII0RXP3
SGMII0RXN2
26
TSIP0CLKB
TSIP0TR1
DVDD18
VSS
TSIP0FSB
TSIP0TX0
TSIP0TX1
DVDD18
32
SGMII0TXN1
SGMII0TXP0
SGMII0RXP1
SGMII0RXN0
29
SGMII0TXN0
VSS
SGMII0TXN2
VSS
TSIP0TR0
VSS
SGMII0RXN1
VSS
SGMII0RXP0
30
SGMII0RXP2
27
33
31
28
Figure 6-3. 66AK2Ex Left End Panel (A) — Bottom View
28
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25
24
DDRDQS4P
DDRDQS4N
DDRD35
DDRD34
DDRD36
VSS
23
DDRCB00
DDRD32
VSS
22
DDRDQS8N
DDRDQS8P
DDRCB04
DDRCB01
DDRCB02
VSS
21
DDRCB07
DDRCB05
DVDD15
VSS
20
DDRCB06
DDRDQM8
DDRCKE0
DDRRESET
RSV022
VSS
19
DDRCKE1
RSV021
VSS
18
DDRA08
DDRBA2
DDRA14
DDRA11
DDRA12
VSS
A
B
DDRD39
DDRD38
DVDD15
VSS
C
D
DVDD15
DDRD33
DVDD15
VSS
DVDD15
DDRA15
DVDD15
VSS
E
DDRD37
DVDD15
VSS
DDRCB03
DVDD15
VSS
F
G
AVDDA10
VSS
AVDDA9
VSS
DVDD15
VSS
DDRRZQ2
VSS
H
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
J
VNWA2
VSS
CVDD
CVDD
CVDD
VSS
K
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
L
CVDD1
VSS
VSS
CVDD
CVDD
CVDD
VSS
M
CVDD
VSS
CVDD1
VSS
VSS
CVDD
VSS
VSS
CVDD
VSS
N
CVDD1
VSS
CVDD
CVDD
CVDD
VSS
P
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
R
CVDD
VSS
CVDD
CVDD
CVDD
VSS
T
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
U
CVDD
VSS
CVDD
CVDD
CVDD
VSS
V
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
W
Y
CVDD
VSS
CVDD
CVDD
CVDD
VSS
CVDD
VSS
VSS
CVDD1
VSS
VSS
CVDD
VSS
VSS
CVDD
VSS
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
CVDD1
VSS
CVDD
CVDD
CVDD
VSS
CVDD
VSS
CVDD1
VSS
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
CVDD
CVDD
CVDD
VSS
CVDD
VSS
VSS
VNWA3
VSS
VSS
CVDD
VSS
VSS
CVDD
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDAHV
SGMII0CLKN
SGMII0TXP3
VSS
VDDAHV
VSS
VDDAHV
VSS
VDDAHV
VSS
SGMII0CLKP
VSS
SGMII01REFRES
SGMII0TXP5
VSS
RSV016
SGMII0TXN7
SGMII0TXP6
SGMII0RXP7
SGMII0RXN6
20
PCIE0CLKN
VSS
SGMII0TXN5
SGMII0TXP4
SGMII0RXP5
SGMII0RXN4
23
VSS
SGMII0TXP7
VSS
SGMII0TXN4
VSS
SGMII0TXN6
VSS
PCIE0TXN0
VSS
SGMII0RXN3
VSS
SGMII0RXN5
VSS
SGMII0RXN7
VSS
SGMII0RXP4
24
SGMII0RXP6
21
PCIE0RXP0
18
25
22
19
Figure 6-4. 66AK2Ex Left Center Panel (B) — Bottom View
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9
17
DDRA06
DDRA09
DVDD15
VSS
16
DDRCLKOUTP1
DDRA02
DDRA03
DDRA04
DDRA05
VSS
15
DDRCLKOUTN1
DDRCLKOUTP0
DDRA01
DDRA00
DDRRZQ0
DDRVREFSSTL
VSS
14
RSV023
DDRCLKOUTN0
VSS
13
DDRA10
DDRRAS
DDRBA1
DDRBA0
DDRWE
DVDD15
VSS
12
DDRCE0
DDRCAS
DDRCE1
DDRODT0
DDRA13
VSS
11
DDRD26
DDRD25
DVDD15
VSS
10
DDRDQS3P
DDRDQS3N
DDRD27
DDRD28
DDRD24
VSS
DDRD31
A
DDRD29
VSS
B
C
DVDD15
AVDDA7
VSS
DVDD15
DDRD30
DVDD15
VSS
D
DDRA07
DVDD15
VSS
DDRODT1
DVDD15
VSS
E
F
AVDDA8
VSS
DVDD15
VSS
DDRRZQ1
VSS
DVDD15
VSS
G
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSSCMON
VPP0
H
CVDD
VSS
CVDD
CVDD
VSS
CVDDCMON
VSS
J
CVDD
CVDD
VSS
CVDD
VSS
CVDD
K
VSS
CVDD
VSS
VSS
CVDD
CVDD
VSS
VSS
CVDD
VSS
L
CVDD
CVDD
VSS
CVDD1
VSS
CVDD1
VSS
VSS
VPP1
M
VSS
CVDD
VSS
VSS
CVDD
CVDD1
VSS
CVDD
VSS
N
CVDD
CVDD
VSS
CVDD
VSS
USB1DVDD33
VSS
VSS
VNWA1
VSS
P
VSS
CVDD
VSS
VSS
CVDD
VDDUSB1
VSS
USB1VPH
VSS
R
CVDD
CVDD
VSS
CVDD
VSS
VDDUSB1
VSS
USB1VPTX
VSS
T
VSS
CVDD
VSS
VSS
CVDD
CVDD
VSS
VDDUSB0
VSS
U
CVDD
CVDD
VSS
CVDD
VSS
VDDUSB0
VSS
USB0VPTX
VSS
V
VSS
CVDD
VSS
VSS
CVDD
CVDD
VSS
USB0VPH
VSS
W
Y
CVDD
CVDD
VSS
CVDD1
VSS
USB0DVDD33
VSS
CVDD
VSS
VSS
CVDD
VSS
VSS
CVDD1
VSS
CVDD1
VSS
CVDD
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
CVDD
CVDD
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
VSS
CVDD
CVDD
VSS
VSS
CVDD
CVDD
CVDD
VSS
CVDD
VSS
CVDD
VSS
VNWA4
VSS
VSS
VDDALV
VSS
VSS
VDDALV
VSS
VDDALV
VSS
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
VDDALV
VSS
PCIE0REFRES
VSS
RSV017
VSS
XFIREFRES0
VSS
VDDAHV
PCIE0CLKP
PCIE0TXN1
PCIE0TXP0
PCIE0RXP1
PCIE0RXN0
17
VDDAHV
PCIE1CLKN
VSS
VDDAHV
VSS
VDDAHV
XFICLKP
XFITXN1
XFITXP0
XFIRXP1
XFIRXN0
11
RSV020
VSS
VSS
PCIE1CLKP
PCIE1TXN1
PCIE1TXP0
PCIE1RXP1
PCIE1RXN0
14
XFICLKN
VSS
PCIE1REFRES
XFITXP1
VSS
PCIE0TXP1
VSS
PCIE1TXP1
VSS
VSS
PCIE1TXN0
VSS
XFITXN0
VSS
HYPLNK0TXN0 AL
VSS AM
PCIE0RXN1
VSS
PCIE1RXN1
VSS
XFIRXN1
VSS
PCIE1RXP0
15
XFIRXP0
12
HYPLNK0RXP0 AN
16
13
10
9
Figure 6-5. 66AK2Ex Right Center Panel (C) — Bottom View
30
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8
DDRD22
DDRD23
DDRD21
DDRDQM2
DDRDQM3
VSS
7
DDRDQS2N
DDRDQS2P
DVDD15
VSS
6
DDRD09
5
DDRD08
4
DDRDQS1P
DDRDQS1N
DDRD12
DDRD13
DDRD14
VSS
3
DDRDQM0
DDRD15
DVDD15
VSS
2
DVDD15
DDRD07
DDRDQS0N
DDRD05
DDRD00
DDRD02
RSV004
EMIFD08
DVDD18
EMIFA19
EMIFA16
DVDD18
VSS
1
VSS
A
DDRD19
DDRD10
DVDD15
DDRDQS0P
DDRD01
DDRD03
DDRD04
RSV005
B
DDRD20
VSS
C
DDRD16
DVDD15
D
DDRD18
DVDD15
VSS
DDRD17
DDRD11
DDRDQM1
DDRD06
DDRCLKN
EMIFD11
VSS
E
VSS
DVDD15
F
AVDDA6
VSS
EMIFD09
EMIFD06
EMIFD05
EMIFD14
EMIFA23
EMIFA18
EMIFA05
EMIFA04
EMIFBE1
EMIFWAIT0
EMIFA02
EMIFA03
USB1ID0
USB0RESREF
EMU01
EMIFD00
EMIFD04
EMIFD15
EMIFD10
EMIFA17
EMIFA09
EMIFA08
EMIFA01
EMIFWE
DDRCLKP
EMIFD13
EMIFD12
EMIFD02
EMIFA21
EMIFA10
EMIFA07
USB1DM
USB1DP
USBCLKM
USBCLKP
USB1VBUS
USB0ID0
EMIFCE1
VSS
G
H
DVDD15
VSS
EMIFD07
EMIFD03
EMIFA20
EMIFA11
VSS
RSV010
RSV009
DVDD18
VSS
J
AVDDA2
VSS
EMIFD01
EMIFA14
EMIFA06
EMIFWAIT1
EMIFA00
EMIFA22
EMIFA15
VSS
K
L
DVDD18
VSS
M
N
DVDD18
VSS
USB1RX0M
USB1RX0P
VSS
DVDD18
VSS
USB1TX0P
USB1TX0M
VSS
P
USB1VP
VSS
R
DVDD18
VSS
EMIFA13
EMIFA12
USB1RESREF
USB0VBUS
EMU17
USB0RX0M
USB0RX0P
VSS
T
USB0VP
VSS
USB0TX0M
USB0TX0P
VSS
U
DVDD18
RSV012
DVDD18
VSS
USB0DP
USB0DM
EMIFRW
DVDD18
EMU14
V
RSV011
VSS
EMIFCE2
EMIFCE3
EMIFCE0
USB0DRVVBUS
USB1DRVVBUS
W
Y
EMIFOE
EMIFBE0
EMU16
DVDD18
VSS
EMU15
AA
AB
AC
DVDD18
VSS
HYPLNK0TXPMCLK
HYPLNK0TXFLCLK
EMU04
EMU06
EMU08
DVDD18
VSS
EMU00
EMU02
EMU07
EMU13
AVDDA3
XFIMDIO
AVDDA1
VSS
VSS
DVDD18
SYSCLKOUT
TSCOMPOUT
EMU11
EMU05
EMU12
HYPLNK0RXPMDAT AD
HYPLNK0RXPMCLK AE
DVDD18
VSS
EMU03
TSSYNCEVT
HYPLNK0TXPMDAT
RSV008
HYPLNK0RXFLDAT
EMU10
RSV002
RSV003
TSRXCLKOUT1P
EMU18
XFIMDCLK
NETCPCLKSEL
MDCLK0
VSS
CORECLKP
CORECLKN
TSRXCLKOUT1N
TSRXCLKOUT0P
TSREFCLKN
TSPUSHEVT1
VSS
AF
AG
AH
AJ
RSV015
VSS
TSPUSHEVT0
EMU09
XFIREFRES1
HYPLNK0CLKP
HYPLNK0TXP1
VSS
MDIO0
HYPLNK0TXFLDAT
VSS
HYPLNK0CLKN
HYPLNK0TXN1
HYPLNK0TXP0
HYPLNK0RXP1
HYPLNK0RXN0
8
HYPLNK0REFRES
HYPLNK0TXN3
HYPLNK0TXP2
HYPLNK0RXP3
HYPLNK0RXN2
5
HYPLNK0RXFLCLK TSRXCLKOUT0N
VSS
HYPLNK0TXP3
VSS
VSS
RSV006
VSS
TSREFCLKP
RSV007
NETCPCLKP
VSS
AK
AL
AM
AN
HYPLNK0TXN2
VSS
HYPLNK0RXN1
VSS
HYPLNK0RXN3
VSS
HYPLNK0RXP2
6
NETCPCLKN
3
VSS
7
4
2
1
Figure 6-6. 66AK2Ex Right End Panel (D) — Bottom View
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6.3 Terminal Functions
The terminal functions table (Table 6-2) identifies the external signal names, the associated pin (ball)
numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and
gives functional pin descriptions. This table is arranged by function. The power terminal functions table
(Table 6-3) lists the various power supply pins and ground pins and gives functional pin descriptions.
Table 6-4 shows all pins arranged by signal name. Table 6-5 shows all pins arranged by ball number.
Some pins have additional functions beyond their primary functions. There are 21 pins that have a
secondary function and 15 pins that have a tertiary function. Secondary functions are indicated with a
superscript 2 (2) and tertiary functions are indicated with a superscript 3 (3).
For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and
pullup/pulldown resistors, see Section 9.2.
Use the symbol definitions in Table 6-1 when reading Table 6-2.
Table 6-1. I/O Functional Symbol Definitions
FUNCTIONAL
SYMBOL
Table 6-2 COLUMN
HEADING
DEFINITION
Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ
resistor can be used to oppose the IPD/IPU.
IPD or IPU
IPD/IPU
A
GND
I
Analog signal
Type
Type
Type
Type
Type
Type
Ground
Input terminal
O
Output terminal
P
Power supply voltage
Three-state terminal or high impedance
Z
Table 6-2. Terminal Functions — Signals and Control by Function
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
DESCRIPTION
Boot Configuration Pins
ARM Big Endian Configuration pin. Secondary function for GPIO15.
BOOTMODE_RSVD2
AVSIFSEL[0]2
Y31
I
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Up
K33
I
Default value (bootstrapped) for SR PINMUX Register (SR_PINCTL). Secondary function for TIMI0
Default value (bootstrapped) for SR PINMUX Register (SR_PINCTL). Secondary function for TIMI1
Boot progress indication output
AVSIFSEL[1]2
K32
I
BOOTCOMPLETE
BOOTMODE002
BOOTMODE012
BOOTMODE022
BOOTMODE032
BOOTMODE042
BOOTMODE052
BOOTMODE062
BOOTMODE072
BOOTMODE082
BOOTMODE092
BOOTMODE102
BOOTMODE112
BOOTMODE122
BOOTMODE132
BOOTMODE142
BOOTMODE152
LENDIAN2
AF31
AA29
Y29
OZ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
User defined Boot Mode pin. Secondary function for GPIO01.
User defined Boot Mode pin. Secondary function for GPIO02.
User defined Boot Mode pin. Secondary function for GPIO03.
User defined Boot Mode pin. Secondary function for GPIO04.
User defined Boot Mode pin. Secondary function for GPIO05.
User defined Boot Mode pin. Secondary function for GPIO06.
User defined Boot Mode pin. Secondary function for GPIO07.
User defined Boot Mode pin. Secondary function for GPIO08.
User defined Boot Mode pin. Secondary function for GPIO09.
User defined Boot Mode pin. Secondary function for GPIO10.
User defined Boot Mode pin. Secondary function for GPIO11.
User defined Boot Mode pin. Secondary function for GPIO12.
User defined Boot Mode pin. Secondary function for GPIO13.
User defined Boot Mode pin. Secondary function for GPIO16.
User defined Boot Mode pin. Secondary function for GPIO17.
User defined Boot Mode pin. Secondary function for GPIO18.
Little Endian Configuration pin. Secondary function for GPIO00.
V33
V32
W30
W32
V31
W31
W33
AB29
Y30
Y32
AA30
AA33
AB32
AB33
V30
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
DESCRIPTION
MAINPLLODSEL2
Y33
I
Down
Post divider select for main PLL.. Secondary function for GPIO14.
Clock / Reset
CORECLKN
CORECLKP
DDRCLKN
DDRCLKP
AG1
AF1
I
System clock input to main PLL
I
G3
I
DDR3 reference clock input to DDR PLL
G4
I
HOUT
AF30
AJ8
OZ
Up
Interrupt output pulse created by IPCGRH
HyperLink reference clock to drive HyperLink SerDes
HYPLNK0CLKN
HYPLNK0CLKP
LRESETNMIEN
LRESET
I
AJ7
I
AE30
AF33
AN3
AM2
AG6
AG33
AJ18
AJ17
AJ15
AJ14
AH33
AF32
AH29
I
Up
Up
Enable for DSP core
Warm reset
I
NETCPCLKN
NETCPCLKP
NETCPCLKSEL
NMI
I
NETCP sub-system reference clock
I
I
Down
Up
NETCP clock select to choose between core clock and NETCPCLK pins
Non-maskable interrupt
I
PCIE0CLKN
PCIE0CLKP
PCIE1CLKN
PCIE1CLKP
POR
I
PCIe Clock input to drive PCIe0 SerDes
PCIe Clock Input to drive PCIe1 SerDes
I
I
I
I
Power-on reset
Full reset
RESETFULL
RESETSTAT
I
Up
Up
O
Reset Status Output. Drives low during Power-on Reset (No HHV override). Available after core
and IOs are completely powered-up.
RESET
AE29
AJ25
AJ24
AE4
AK1
AK2
AJ2
I
Up
Warm reset of non-isolated portion of the device
SGMII0CLKN
SGMII0CLKP
SYSCLKOUT
TSREFCLKN
TSREFCLKP
TSRXCLKOUT0N
TSRXCLKOUT0P
TSRXCLKOUT1N
TSRXCLKOUT1P
USBCLKM
I
SGMII reference clock to drive both SGMII0 SerDes SGMII reference clock to drive the SGMII
SerDes
I
OZ
I
Down
System clock output to be used as a general purpose output clock for debug purposes
Clock from external OCXO/VCXO for SyncE
I
O
O
O
O
I
SERDES recovered clock output for SyncE
SERDES recovered clock output for SyncE
USB0_3.0 reference clock
AJ1
AH1
AG2
T4
USBCLKP
U4
I
XFICLKN
AJ12
AJ11
I
XFI reference clock to drive the XFI SerDes
XFICLKP
I
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
DESCRIPTION
DDR3
DDRA00
D15
C15
B16
C16
D16
E16
A17
E17
A18
B17
A13
D18
E18
E12
C18
E19
D13
C13
B18
B12
A23
D22
E22
E21
C22
B21
A20
A21
A12
C12
C20
A19
B14
B15
A15
A16
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
DDRA01
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDR3 EMIF address bus
DDRA08
DDRA09
DDRA10
DDRA11
DDRA12
DDRA13
DDRA14
DDRA15
DDRBA0
DDRBA1
DDR3 EMIF bank address
DDRBA2
DDRCAS
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRCB04
DDRCB05
DDRCB06
DDRCB07
DDRCE0
DDR3 EMIF column address strobe
DDR3 EMIF check bits
DDR3 EMIF chip enable0
DDR3 EMIF chip enable1
DDR3 EMIF clock enable0
DDR3 EMIF clock enable1
DDRCE1
DDRCKE0
DDRCKE1
DDRCLKOUTN0
DDRCLKOUTP0
DDRCLKOUTN1
DDRCLKOUTP1
DDR3 EMIF Output Clocks to drive SDRAMs for Rank0
DDR3 EMIF Output Clocks to drive SDRAMs for Rank1
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
DDRD00
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
DDRD06
DDRD07
DDRD08
DDRD09
DDRD10
DDRD11
DDRD12
DDRD13
DDRD14
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD39
DDRD40
DDRD41
DDRD42
DDRD43
DDRD44
DDRD45
DDRD46
DDRD47
BALL NO. TYPE
IPD/IPU
DESCRIPTION
E2
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
D1
F2
E1
F1
D2
F3
B2
DDR3 EMIF data bus
A5
A6
B5
E5
C4
D4
E4
B3
D6
E6
E7
B6
C6
C8
A8
B8
DDR3 EMIF data bus
E10
B11
A11
C10
D10
B9
E9
A9
B23
E23
D24
C24
E24
E25
B25
A25
E28
D28
C28
E27
B28
A26
B26
C26
DDR3 EMIF data bus
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
DDRD48
BALL NO. TYPE
IPD/IPU
DESCRIPTION
A29
A28
B31
E29
B29
C30
E30
D30
F31
F33
F32
E32
E33
C32
D32
B32
A3
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
DDRD49
DDRD50
DDRD51
DDRD52
DDRD53
DDRD54
DDRD55
DDR3 EMIF data bus
DDRD56
DDRD57
DDRD58
DDRD59
DDRD60
DDRD61
DDRD62
DDRD63
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
DDRDQS0N
DDRDQS0P
DDRDQS1N
DDRDQS1P
DDRDQS2N
DDRDQS2P
DDRDQS3N
DDRDQS3P
DDRDQS4N
DDRDQS4P
DDRDQS5N
DDRDQS5P
DDRDQS6N
DDRDQS6P
DDRDQS7N
DDRDQS7P
DDRDQS8N
DDRDQS8P
DDRODT0
DDRODT1
DDRRAS
E3
OZ
D8
OZ
E8
OZ
E26
D26
E31
A31
B20
C2
OZ
DDR3 EMIF Data Masks
OZ
OZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
Up/Dn
C1
B4
A4
A7
B7
B10
A10
B24
A24
B27
A27
B30
A30
D33
C33
A22
B22
D12
E11
B13
D20
E15
G12
G18
E13
DDR3 EMIF data strobe. Programmable pull-up/dn 350-650 ohm.
DDR3 EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3 EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3 EMIF row address strobe
OZ
OZ
DDRRESET
DDRRZQ0
DDRRZQ1
DDRRZQ2
DDRWE
OZ
DDR3 reset signal. IO will work in LVCMOS mode to comply with JEDEC standard.
PTV compensation reference resistor pin for DDR3
A
A
PTV compensation reference resistor pin for DDR3
A
PTV compensation reference resistor pin for DDR3
OZ
DDR3 EMIF write enable
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
DESCRIPTION
EMIF
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFBE0
EMIFBE1
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
EMIFOE
P3
P5
U6
V6
P6
N6
M3
N4
N5
M5
M4
L1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Up
EMIF address
U5
T5
L3
T3
L2
L5
EMIF address
M6
K2
K1
L4
R3
L6
AA2
R6
AA1
Y4
W1
Y1
Y2
Y3
T6
N3
R5
Up
Up
Up
Up
Up
EMIF control signals
Up
EMIFRW
EMIFWAIT0
EMIFWAIT1
EMIFWE
Up
Down
Down
Up
I
O
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
EMIFD00
EMIFD01
EMIFD02
EMIFD03
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
BALL NO. TYPE
IPD/IPU
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
DESCRIPTION
G5
K3
K4
J1
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
H5
J6
H6
H1
H2
G6
K5
H3
J4
EMIF data
H4
K6
J5
EMU
EMU00
EMU01
EMU02
EMU03
EMU04
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
EMU193
EMU203
EMU213
EMU223
EMU233
EMU243
EMU253
EMU263
EMU273
EMU283
EMU293
EMU303
EMU313
EMU323
AC5
AA6
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Up
Up
AC4
AE6
Up
Up
AD6
AD3
AB5
Up
Up
Up
AC3
AB4
Up
Up
AH3
AF3
Up
Emulation and trace port
Up
AG4
AD2
AC2
AB3
Up
Up
Up
Up
AA5
Up
AB2
Up
Y5
Up
AH2
AB32
AB33
AB31
AC29
AC33
AD29
AC31
AC32
AB30
AC30
AD32
AD33
AD31
AE33
Up
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO17.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO18.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO19.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO20.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO21.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO22.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO23.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO24.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO25.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO26.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO27.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO28.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO29.
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO30.
38
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
DESCRIPTION
EMU333
AD30
IOZ
Down
EMU (Unique select for EMU muxing on each GPIO pin.) Tertiary function for GPIO31.
General Purpose Input/Output (GPIO)
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
V30
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Up
AA29
Y29
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
V33
V32
W30
W32
V31
GPIOs
W31
W33
AB29
Y30
Y32
AA30
Y33
Y31
AA33
AB32
AB33
AB31
AC29
AC33
AD29
AC31
AC32
AB30
AC30
AD32
AD33
AD31
AE33
AD30
GPIOs
HyperLink
HYPLNK0RXN0
HYPLNK0RXN1
HYPLNK0RXN2
HYPLNK0RXN3
HYPLNK0RXP0
HYPLNK0RXP1
HYPLNK0RXP2
HYPLNK0RXP3
HYPLNK0TXN0
HYPLNK0TXN1
HYPLNK0TXN2
HYPLNK0TXN3
HYPLNK0TXP0
HYPLNK0TXP1
HYPLNK0TXP2
HYPLNK0TXP3
AN8
AM7
AN5
AM4
AN9
AM8
AN6
AM5
AL9
AK8
AL6
AK5
AL8
AK7
AL5
AK4
I
I
I
I
HyperLink receive data
I
I
I
I
O
O
O
O
O
O
O
O
HyperLink transmit data
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
down
down
down
down
down
down
down
down
DESCRIPTION
HYPLNK0RXFLCLK
HYPLNK0RXFLDAT
HYPLNK0RXPMCLK
HYPLNK0RXPMDAT
HYPLNK0TXFLCLK
HYPLNK0TXFLDAT
HYPLNK0TXPMCLK
HYPLNK0TXPMDAT
HYPLNK0REFRES
AJ3
AE3
AE1
AD1
AC6
AH4
AB6
AF5
AJ5
O
O
I
I
HyperLink sideband signals
I
I
O
O
A
HyperLink SerDes reference resistor input (3 kΩ ±1%)
I2C
I2C0 clock
SCL0
SCL1
SCL2
SDA0
SDA1
SDA2
AG30
AH30
AH31
AG28
AJ32
AG29
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
I2C1 clock
I2C2 clock
I2C0 data
I2C1 data
I2C2 data
JTAG
TCK
TDI
AJ33
AG31
AF29
AH32
AG32
I
Up
JTAG clock input
I
Up
JTAG data input
TDO
TMS
TRST
OZ
Up
JTAG data output
I
I
Up
JTAG test mode input
Down
JTAG reset
MDIO
MDCLK0
MDIO0
AH6
AH5
AF6
AE7
O
Down
Up
MDIO0 Clock
IOZ
O
MDIO0 Data
XFIMDCLK
XFIMDIO
Down
Up
XFI MDIO Clock
IOZ
XFI MDIO Data
PCIe
PCIE0REFRES
PCIE0RXN0
PCIE0RXP0
PCIE0RXN1
PCIE0RXP1
PCIE0TXN0
PCIE0TXP0
PCIE0TXN1
PCIE0TXP1
PCIE1REFRES
PCIE1RXN0
PCIE1RXP0
PCIE1RXN1
PCIE1RXP1
PCIE1TXN0
PCIE1TXP0
PCIE1TXN1
PCIE1TXP1
AG14
AN17
AN18
AM16
AM17
AL18
AL17
AK17
AK16
AJ10
AN14
AN15
AM13
AM14
AL15
AL14
AK14
AK13
A
I
PCIexpress0 SerDes reference resistor input (3 kΩ ±1%)
PCIexpress0 lane 0 receive data
PCIexpress0 lane 1 receive data
PCIexpress0 lane 0 transmit data
I
I
I
O
O
O
O
A
I
PCIexpress0 lane 1 transmit data
PCIexpress1 SerDes reference resistor input (3 kΩ ±1%)
PCIexpress1lane 0 receive data
I
I
PCIexpress1lane 1 receive data
PCIexpress1 lane 0 transmit data
PCIexpress1 lane 1 transmit data
I
O
O
O
O
SGMII
SGMII00REFRES
SGMII01REFRES
SGMII0RXN0
AJ27
AJ22
AN29
AN30
A
A
I
SGMII0 SerDes reference resistor input (3 kΩ ±1%)
SGMII1 SerDes reference resistor input (3 kΩ ±1%)
Ethernet MAC SGMII0 port 0 receive data
SGMII0RXP0
I
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
SGMII0RXN1
SGMII0RXP1
SGMII0RXN2
SGMII0RXP2
SGMII0RXN3
SGMII0RXP3
SGMII0RXN4
SGMII0RXP4
SGMII0RXN5
SGMII0RXP5
SGMII0RXN6
SGMII0RXP6
SGMII0RXN7
SGMII0RXP7
SGMII0TXN0
SGMII0TXP0
SGMII0TXN1
SGMII0TXP1
SGMII0TXN2
SGMII0TXP2
SGMII0TXN3
SGMII0TXP3
SGMII0TXN4
SGMII0TXP4
SGMII0TXN5
SGMII0TXP5
SGMII0TXN6
SGMII0TXP6
SGMII0TXN7
SGMII0TXP7
BALL NO. TYPE
IPD/IPU
DESCRIPTION
AM28
AM29
AN26
AN27
AM25
AM26
AN23
AN24
AM22
AM23
AN20
AN21
AM19
AM20
AL30
AL29
AK29
AK28
AL27
AL26
AK26
AK25
AL24
AL23
AK23
AK22
AL21
AL20
AK20
AK19
I
Ethernet MAC SGMII0 port 1 receive data
I
I
Ethernet MAC SGMII0 port 2 receive data
Ethernet MAC SGMII0 port 3 receive data
Ethernet MAC SGMII1 port 4 receive data
I
I
I
I
I
I
Ethernet MAC SGMII1 port 5 receive data
Ethernet MAC SGMII1 port 6 receive data
I
I
I
I
Ethernet MAC SGMII1 port 7 receive data
Ethernet MAC SGMII0 port 0 transmit data
Ethernet MAC SGMII0 port 1 transmit data
Ethernet MAC SGMII0 port 2 transmit data
Ethernet MAC SGMII0 port 3 transmit data
Ethernet MAC SGMII1 port 4 transmit data
Ethernet MAC SGMII1 port 5 transmit data
Ethernet MAC SGMII1 port 6 transmit data
Ethernet MAC SGMII1 port 7 transmit data
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SmartReflex
Voltage control I2C clock
VCL
V29
H29
G33
H31
H30
G32
J31
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
IOZ
VCNTL0
VCNTL1
VCNTL2
VCNTL3
VCNTL4
VCNTL5
VD
Voltage control outputs to variable core power supply
Voltage control I2C data
SPI0
U30
SPI0CLK
M30
M31
N29
L31
M29
L29
L32
OZ
I
Down
Down
Down
Up
SPI0 clock
SPI0DIN
SPI0 data in
SPI0DOUT
SPI0SCS0
SPI0SCS1
SPI0SCS2
SPI0SCS3
OZ
OZ
OZ
OZ
OZ
SPI0 data out
SPI0 interface enable 0
SPI0 interface enable 1
SPI0 interface enable 2
SPI0 interface enable 3
SPI1
Up
Up
Up
SPI1CLK
SPI1DIN
M33
R30
P32
OZ
I
Down
Down
Down
SPI1 clock
SPI1 data in
SPI1DOUT
OZ
SPI1 data out
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
SPI1SCS0
SPI1SCS1
SPI1SCS2
SPI1SCS3
BALL NO. TYPE
IPD/IPU
Up
DESCRIPTION
P29
M32
N30
N33
OZ
OZ
OZ
OZ
SPI1 interface enable 0
SPI1 interface enable 1
SPI1 interface enable 2
SPI1 interface enable 3
SPI2
Up
Up
Up
SPI2CLK
L33
P30
R31
P31
R29
P33
L30
OZ
I
Down
Down
Down
Up
SPI2 clock
SPI2DIN
SPI2 data in
SPI2DOUT
SPI2SCS0
SPI2SCS1
SPI2SCS2
SPI2SCS3
OZ
OZ
OZ
OZ
OZ
SPI2 data out
SPI2 interface enable 0
SPI2 interface enable 1
SPI2 interface enable 2
SPI2 interface enable 3
Sync-Ethernet / IEEE1588
IEEE1588 compare output
PPS push event from GPS for IEEE1588
Push event from BCN for IEEE1588
IEEE1588 sync event output
Timer
Up
Up
Up
TSCOMPOUT
TSPUSHEVT0
TSPUSHEVT1
TSSYNCEVT
AF4
AG3
AL1
AE5
O
I
Down
Down
Down
Down
I
O
TIMI0
TIMO0
TIMI1
TIMO1
K33
K31
K32
K30
I
Down
Down
Down
Down
Timer 0 input
OZ
I
Timer 0 output
Timer 1 input
OZ
Timer 1 output
TSIP
TSIP0CLKA
TSIP0CLKB
TSIP0FSA
TSIP0FSB
TSIP0TR0
TSIP0TR1
TSIP0TX0
TSIP0TX1
AK31
AK33
AJ31
AK32
AM31
AL33
AL32
AM32
I
Down
Down
Down
Down
Down
Down
Down
Down
CLKA0 TSIP0 external clock A
CLKB0 TSIP0 external clock B
FSA0 TSIP0 frame sync A
FSB0 TSIP0 frame sync B
I
I
I
I
TR00 TR01 TSIP0 receive data
TX00 TX01 TSIP0 transmit data
I
OZ
OZ
UART0
UART0CTS
UART0DSR
UART0DTR
UART0RTS
UART0RXD
UART0TXD
R33
W29
U33
R32
T29
T30
I
Down
Down
Down
Down
Down
Down
UART0 clear to send
I
UART0 data set ready
OZ
OZ
I
UART0 data terminal ready
UART0 request to send
UART0 serial data in
OZ
UART0 serial data out
UART1
UART1CTS
UART1RTS
UART1RXD
UART1TXD
T31
T33
U29
T32
I
Down
Down
Down
Down
UART1 clear to send
OZ
I
UART1 request to send
UART1 serial data in
OZ
UART1 serial data out
USB0 (USB_3.0)
USB0DM
W3
V3
IOZ
IOZ
O
USB0 D-
USB0DP
USB0 D+
USB0DRVVBUS
USB0ID0
AB1
W4
Y6
Down
USB0 DRVVBUS output
A
USB0 ID
USB0RESREF
USB0RX0M
USB0RX0P
A
Reference resistor connection for USB0 PHY (200 Ω +- 1% resistor to ground)
T1
I
USB0_3.0 receive data
U1
I
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
USB0TX0M
USB0TX0P
BALL NO. TYPE
IPD/IPU
DESCRIPTION
U2
V2
W5
O
O
A
USB0_3.0 transmit data
USB0VBUS
USB0 5-V analog input. Connect to VBUS pin on USB connector through protection switch
USB1 (USB_3.0)
USB1DM
P4
R4
AC1
W6
V5
N1
P1
R2
P2
V4
IOZ
IOZ
O
A
USB1 D-
USB1DP
USB1 D+
USB1DRVVBUS
USB1ID0
Down
USB1 DRVVBUS output
USB1 ID
USB1RESREF
USB1RX0M
USB1RX0P
USB1TX0M
USB1TX0P
USB1VBUS
A
Reference resistor connection for USB1 PHY (200Ω +- 1% resistor to ground)
I
USB1_3.0 receive data
USB1_3.0 transmit data
I
O
O
A
USB1 5-V analog input. Connect to VBUS pin on USB connector through protection switch
USIM
USIM clock
USIMCLK
USIMIO
J33
H33
K29
OZ
IOZ
OZ
Down
Up
USIM data
USIMRST
Down
USIM reset
XFI (66AK2E05 only)
XFIRXN0
XFIRXP0
XFIRXN1
XFIRXP1
XFITXN0
AN11
AN12
AM10
AM11
AL12
AL11
AK11
AK10
AG10
AH7
I
Ethernet MAC XFI port 0 receive data
Ethernet MAC XFI port 1 receive data
Ethernet MAC XFI port 0 transmit data
Ethernet MAC XFI port 1 transmit data
I
I
I
O
O
O
O
A
A
XFITXP0
XFITXN1
XFITXP1
XFIREFRES0
XFIREFRES1
XFI port 0 SerDes reference resistor input (3 kΩ ±1%)
XFI port 1 SerDes reference resistor input (3 kΩ ±1%)
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Table 6-2. Terminal Functions — Signals and Control by Function (continued)
SIGNAL NAME
BALL NO. TYPE
IPD/IPU
DESCRIPTION
Reserved
RSV000
RSV001
RSV002
RSV003
RSV004
RSV005
RSV006
RSV007
RSV008
RSV009
RSV010
RSV011
RSV012
RSV013
RSV014
RSV015
RSV016
RSV017
RSV018
RSV019
RSV020
RSV021
RSV022
RSV023
H32
J32
AE2
AF2
G2
OZ
OZ
O
O
O
O
O
O
OZ
A
Down
Down
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Connect to GND
G1
AL3
AL2
AG5
K8
Down
J8
A
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
Leave unconnected
W8
A
W7
A
J30
J29
AG8
AJ20
AG12
AJ28
AJ26
AH9
B19
E20
A14
A
A
A
A
A
A
A
A
OZ
OZ
A
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-3. Terminal Functions — Power and Ground
SUPPLY
AVDDA1
AVDDA2
AVDDA3
AVDDA6
AVDDA7
AVDDA8
AVDDA9
AVDDA10
CVDD
BALL NO.
AF7
VOLTS
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
AVS
DESCRIPTION
COREPLL supply
NETCPPLL supply
DDRPLL supply
K7
AD7
G8
DDRA DLL supply
DDRA DLL supply
DDRA DLL supply
DDRA DLL supply
DDRA DLL supply
Smart Reflex core supply voltage
E14
G16
G22
G24
J12, J14, J16, J18, J20, J22, J26, K11, K13, K15, K17, K19,
K21, K23, K25, L10, L12, L14, L16, L18, L20, L22, M15, M17,
M19, M21, M25, N10, N14, N16, N18, N20, N22, N26, P13,
P15, P17, P19, P21, P23, P25, R14, R16, R18, R20, R22, R24,
R26, T13, T15, T17, T19, T21, T23, T25, U12, U14, U16, U18,
U20, U22, U24, U26, V13, V15, V17, V19, V21, V23, V25, W12,
W14, W16, W18, W20, W22, W24, W26, Y9, Y15, Y17, Y19,
Y21, Y25, AA10, AA16, AA18, AA20, AA22, AA26, AB9, AB11,
AB13, AB15, AB17, AB19, AB21, AB25, AC10, AC12, AC14,
AC16, AC18, AC20, AC22, AC24, AC26, AD11, AD13, AD15,
AD17, AD19, AD21, AD25
CVDD1
L24, M11, M13, M23, N12, N24, Y13, Y23, AA12, AA14, AA24, 0.95 V
AB23
Core supply voltage for memory array
CVDDCMON
CVDDTMON
DDR3VREFSSTL
DVDD15
J10
L26
F15
AVS
CVDD Supply Monitor
CVDD Supply Monitor
DDR3 reference voltage
DDR IO supply
AVS
DVDD15/2
1.5 V/1.35 V
A2, A32, B1, B33, C3, C7, C11, C17, C21, C25, C31, D5, D9,
D14, D19, D23, D27, D29, F5, F7, F9, F11, F13, F17, F19, F21,
F23, F25, F27, F29, G10, G14, G20, G26, G28, G30, H7, H9,
H11, H13, H15, H17, H19, H21, H23, H25, H27
DVDD18
J2, J28, K27, L8, L28, M2, M7, M27, N8, N28, N31, P7, P27,
R28, T7, T27, U28, U31, V7, V27, W28, Y7, Y27, AA3, AA8,
AA28, AA31, AB7, AB27, AC8, AC28, AD4, AD27, AE8, AE26,
AE28, AE31, AF27, AG26, AH27, AJ30, AM33, AN32
1.8 V
1.8-V IO supply
USB0DVDD33
USB0VP
Y11
U8
3.3 V
3.3-V USB0 high supply High-speed
0.85 V
0.85-V USB0 PHY analog and digital Super-speed
supply
USB0VPH
USB0VPTX
USB1DVDD33
USB1VP
W10
V9
3.3 V
3.3-V USB0 high supply Super-speed
0.85-V USB0 PHY transmit supply
3.3-V USB1 high supply High-speed
0.85 V
3.3 V
P11
R8
0.85 V
0.85-V USB1 PHY analog and digital Super-speed
supply
USB1VPH
USB1VPTX
VDDAHV
VDDALV
R10
3.3 V
3.3-V USB1 high supply Super-speed
0.85-V USB1 PHY transmit supply
1.8-V high analog supply
T9
0.85 V
1.8 V
AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25
AE10, AE12, AE14, AE16, AE18, AE20, AE22, AE24, AF9,
AF11, AF13, AF15, AF17, AF19, AF21, AF23, AF25, AG16,
AG18, AG20, AG22, AG24
0.85 V
SerDes low voltage
VDDUSB0
VDDUSB1
VNWA1
VNWA2
VNWA3
VNWA4
VPP0
U10, V11
R12, T11
P9
0.85 V
0.85 V
0.95 V
0.95 V
0.95 V
0.95 V
USB0 PHY analog and digital High-speed supply
USB1 PHY analog and digital High-speed supply
Fixed Nwell supply - connect to CVDD1
Fixed Nwell supply - connect to CVDD1
Fixed Nwell supply - connect to CVDD1
Fixed Nwell supply - connect to CVDD1
Leave unconnected
J24
AD23
AD9
K9
VPP1
M9
Leave unconnected
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Table 6-3. Terminal Functions — Power and Ground (continued)
SUPPLY
BALL NO.
VOLTS
DESCRIPTION
VSS
A1, A33, C5, C9, C14, C19, C23, C27, C29, D3, D7, D11, D17, GND
D21, D25, D31, F4, F6, F8, F10, F12, F14, F16, F18, F20, F22,
F24, F26, F28, F30, G7, G9, G11, G13, G15, G17, G19, G21,
G23, G25, G27, G29, G31, H8, H10, H12, H14, H16, H18, H20,
H22, H24, H26, H28, J3, J7, J11, J13, J15, J17, J19, J21, J23,
J25, J27, K10, K12, K14, K16, K18, K20, K22, K24, K28, L7,
L9, L11, L13, L15, L17, L19, L21, L23, L25, L27, M1, M8, M10,
M12, M14, M16, M18, M20, M22, M24, M26, M28, N2, N7, N9,
N11, N13, N15, N17, N19, N21, N23, N25, N27, N32, P8, , P10,
P12, P14, P16, P18, P20, P22, P24, P26, P28, R1, R7, R9,
R11, R13, R15, R17, R19, R21, R23, R25, R27, T2, T8, T10,
T12, T14, T16, T18, T20, T22, T24, T26, T28, U3, U7, U9, U11,
U13, U15, U17, U19, U21, U23, U25, U27, U32, V1, V8, V10,
V12, V14, V16, V18, V20, V22, V24, V26, V28, W2, W9, W11,
W13, W15, W17, W19, W21, W23, W25, W27, Y8, Y10, Y12,
Y14, Y16, Y18, Y20, Y22, Y24, Y26, Y28, AA4, AA7, AA9,
AA11, AA13, AA15, AA17, AA19, AA21, AA23, AA25, AA27,
AA32, AB8, AB10, AB12, AB14, AB16, AB18, AB20, AB22,
AB24, AB26, AB28, AC7, AC9, AC11, AC13, AC15, AC17,
AC19, AC21, AC23, AC25, AC27, AD5, AD8, AD10, AD12,
AD14, AD16, AD18, AD20, AD22, AD24, AD26, AD28, AE9,
AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE25, AE27,
AE32, AF8, AF10, AF12, AF14, AF16, AF18, AF20, AF22,
AF24, AF26, AF28, AG7, AG9, AG11, AG13, AG15, AG17,
AG19, AG21, AG23, AG25, AG27, AH8, AH10, AH12, AH14,
AH16, AH18, AH20, AH22, AH24, AH26, AH28, AJ4, AJ6, AJ9,
AJ13, AJ16, AJ19, AJ21, AJ23, AJ29, AK3, AK6, AK9, AK12,
AK15, AK18, AK21, AK24, AK27, AK30, AL4, AL7, AL10, AL13,
AL16, AL19, AL22, AL25, AL28, AL31, AM1, AM3, AM6, AM9,
AM12, AM15, AM18, AM21, AM24, AM27, AM30, AN1, AN2,
AN4, AN7, AN10, AN13, AN16, AN19, AN22, AN25, AN28,
AN31, AN33
Ground
VSSCMON
VSSTMON
J9
GND
GND
GND Monitor
GND Monitor
K26
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SIGNAL NAME
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-4. Terminal Functions — By Signal Name
BALL NUMBER
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
BALL NUMBER
BOOTMODE_RSVD2
AVDDA1
Y31
DDRA02
B16
DDRD15
B3
AF7
K7
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDRA08
DDRA09
DDRA10
DDRA11
C16
D16
E16
A17
E17
A18
B17
A13
D18
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
D6
E6
E7
B6
C6
C8
A8
B8
E10
AVDDA2
AVDDA3
AD7
G8
AVDDA6
AVDDA7
E14
G16
G22
G24
K33
AVDDA8
AVDDA9
AVDDA10
AVSIFSEL[0]2
AVSIFSEL[1]2
K32
DDRA12
E18
DDRD25
B11
BOOTCOMPLETE
AF31
AA29
DDRA13
DDRA14
E12
C18
DDRD26
DDRD27
A11
C10
BOOTMODE002
BOOTMODE012
BOOTMODE022
BOOTMODE032
BOOTMODE042
BOOTMODE052
BOOTMODE062
BOOTMODE072
BOOTMODE082
BOOTMODE092
BOOTMODE102
BOOTMODE112
BOOTMODE122
BOOTMODE132
BOOTMODE142
Y29
DDRA15
E19
D13
C13
B18
B12
A23
D22
E22
E21
C22
B21
A20
A21
A12
C12
DDRD28
DDRD29
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD39
DDRD40
DDRD41
DDRD42
D10
B9
V33
DDRBA0
DDRBA1
DDRBA2
DDRCAS
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRCB04
DDRCB05
DDRCB06
DDRCB07
DDRCE0
DDRCE1
V32
E9
W30
W32
V31
A9
B23
E23
D24
C24
E24
E25
B25
A25
E28
D28
C28
W31
W33
AB29
Y30
Y32
AA30
AA33
AB32
AB33
BOOTMODE152
CORECLKN
CORECLKP
CVDD
AG1
AF1
DDRCKE0
C20
A19
G3
DDRD43
DDRD44
DDRD45
DDRD46
DDRD47
DDRD48
E27
B28
A26
B26
C26
A29
DDRCKE1
J12, J14, J16, J18, J20, J22,
J26, K11, K13, K15, K17, K19,
K21, K23, K25, L10, L12, L14,
L16, L18, L20, L22, M15, M17,
M19, M21, M25, N10, N14, N16,
N18, N20, N22
DDRCLKN
DDRCLKOUTN0
DDRCLKOUTN1
DDRCLKOUTP0
B14
A15
B15
CVDD
CVDD
N26, P13, P15, P17, P19, P21,
P23, P25, R14, R16, R18, R20,
R22, R24, R26, T13, T15, T17,
T19, T21, T23, T25, U12, U14,
U16, U18, U20, U22, U24, U26,
V13, V15
DDRCLKOUTP1
DDRCLKP
DDRD00
A16
G4
E2
DDRD49
DDRD50
DDRD51
DDRD52
A28
B31
E29
B29
DDRD01
D1
V17, V19, V21, V23, V25, W12,
W14, W16, W18, W20, W22,
W24, W26, Y9, Y15, Y17, Y19,
Y21, Y25, AA10, AA16, AA18,
AA20, AA22, AA26, AB9, AB11,
AB13, AB15
DDRD02
DDRD03
DDRD04
DDRD05
F2
E1
F1
D2
DDRD53
DDRD54
DDRD55
DDRD56
C30
E30
D30
F31
CVDD
AB17, AB19, AB21, AB25, AC10, DDRD06
AC12, AC14, AC16, AC18,
AC20, AC22, AC24, AC26,
F3
B2
A5
DDRD57
DDRD58
DDRD59
F33
F32
E32
DDRD07
AD11, AD13, AD15, AD17,
AD19, AD21, AD25
DDRD08
CVDD1
L24, M11, M13, M23, N12, N24,
Y13, Y23, AA12, AA14, AA24,
AB23
DDRD09
DDRD10
A6
B5
DDRD60
DDRD61
E33
C32
CVDDCMON
CVDDTMON
DDRA00
J10
L26
D15
C15
DDRD11
DDRD12
DDRD13
DDRD14
E5
C4
D4
E4
DDRD62
D32
B32
A3
DDRD63
DDRDQM0
DDRDQM1
DDRA01
E3
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Table 6-4. Terminal Functions — By Signal Name (continued)
SIGNAL NAME
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
DDRDQS0N
DDRDQS0P
DDRDQS1N
DDRDQS1P
DDRDQS2N
DDRDQS2P
DDRDQS3N
DDRDQS3P
BALL NUMBER
SIGNAL NAME
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
BALL NUMBER
SIGNAL NAME
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
BALL NUMBER
AD3
D8
N6
M3
N4
N5
M5
M4
L1
E8
AB5
E26
D26
E31
A31
B20
C2
AC3
AB4
AH3
AF3
AG4
U5
T5
L3
AD2
C1
AC2
B4
AB3
A4
T3
L2
AA5
A7
AB2
B7
L5
Y5
B10
A10
M6
K2
AH2
EMU193
EMU203
EMU213
EMU223
EMU233
EMU243
EMU253
EMU263
EMU273
EMU283
EMU293
EMU303
EMU313
EMU323
AB32
DDRDQS4N
DDRDQS4P
DDRDQS5N
DDRDQS5P
DDRDQS6N
DDRDQS6P
DDRDQS7N
DDRDQS7P
DDRDQS8N
DDRDQS8P
DDRODT0
B24
A24
B27
A27
B30
A30
D33
C33
A22
B22
D12
E11
B13
D20
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFBE0
EMIFBE1
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
EMIFD00
EMIFD01
EMIFD02
EMIFD03
K1
L4
AB33
AB31
AC29
AC33
AD29
AC31
AC32
AB30
AC30
AD32
AD33
AD31
AE33
AD30
R3
L6
AA2
R6
AA1
Y4
W1
Y1
G5
K3
K4
J1
DDRODT1
DDRRAS
EMU333
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
DDRRESET
DDRRZQ0
DDRRZQ1
DDRRZQ2
DDRVREFSSTL
DDRWE
E15
G12
G18
F15
E13
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
EMIFOE
EMIFRW
EMIFWAIT0
EMIFWAIT1
EMIFWE
EMU00
H5
J6
V30
AA29
Y29
H6
H1
H2
G6
K5
V33
V32
DVDD15
A2, A32, B1, B33, C3, C7, C11,
C17, C21, C25, C31, D5, D9,
D14, D19, D23, D27, D29, F5,
F7, F9, F11, F13, F17, F19, F21
W30
W32
V31
H3
J4
DVDD15
DVDD18
DVDD18
F23, F25, F27, F29, G10, G14,
G20, G26, G28, G30, H7, H9,
H11, H13, H15, H17, H19, H21,
H23, H25, H27
W31
W33
AB29
Y30
H4
K6
J2, J28, K27, L8, L28, M2, M7,
M27, N8, N28, N31, P7, P27,
R28, T7, T27, U28, U31, V7,
V27, W28, Y7, Y27, AA3, AA8
J5
Y2
Y32
Y3
AA30
Y33
AA28, AA31, AB7, AB27, AC8,
AC28, AD4, AD27, AE8, AE26,
AE28, AE31, AF27, AG26, AH27,
AJ30, AM33, AN32
T6
N3
R5
AC5
AA6
AC4
AE6
AD6
Y31
AA33
AB32
AB33
AB31
AC29
AC33
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
P3
P5
U6
V6
P6
EMU01
EMU02
EMU03
EMU04
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-4. Terminal Functions — By Signal Name (continued)
SIGNAL NAME
GPIO22
BALL NUMBER
AD29
AC31
AC32
AB30
AC30
AD32
AD33
AD31
AE33
AD30
AF30
AJ8
SIGNAL NAME
PCIE0RXN0
PCIE0RXN1
PCIE0RXP0
PCIE0RXP1
PCIE0TXN0
PCIE0TXN1
PCIE0TXP0
PCIE0TXP1
PCIE1CLKN
PCIE1CLKP
PCIE1REFRES
PCIE1RXN0
PCIE1RXN1
PCIE1RXP0
PCIE1RXP1
PCIE1TXN0
PCIE1TXN1
PCIE1TXP0
PCIE1TXP1
POR
BALL NUMBER
AN17
AM16
AN18
AM17
AL18
AK17
AL17
AK16
AJ15
AJ14
AJ10
AN14
AM13
AN15
AM14
AL15
AK14
AL14
AK13
AH33
AF32
AH29
AE29
H32
SIGNAL NAME
BALL NUMBER
AJ32
SDA1
GPIO23
SDA2
AG29
AJ27
GPIO24
SGMII00REFRES
SGMII01REFRES
SGMII0CLKN
SGMII0CLKP
SGMII0RXN0
SGMII0RXN1
SGMII0RXN2
SGMII0RXN3
SGMII0RXN4
SGMII0RXN5
SGMII0RXN6
SGMII0RXN7
SGMII0RXP0
SGMII0RXP1
SGMII0RXP2
SGMII0RXP3
SGMII0RXP4
SGMII0RXP5
SGMII0RXP6
SGMII0RXP7
SGMII0TXN0
SGMII0TXN1
SGMII0TXN2
SGMII0TXN3
SGMII0TXN4
SGMII0TXN5
SGMII0TXN6
SGMII0TXN7
SGMII0TXP0
SGMII0TXP1
SGMII0TXP2
SGMII0TXP3
SGMII0TXP4
SGMII0TXP5
SGMII0TXP6
SGMII0TXP7
SPI0CLK
GPIO25
AJ22
GPIO26
AJ25
GPIO27
AJ24
GPIO28
AN29
AM28
AN26
AM25
AN23
AM22
AN20
AM19
AN30
AM29
AN27
AM26
AN24
AM23
AN21
AM20
AL30
AK29
AL27
AK26
AL24
AK23
AL21
AK20
AL29
AK28
AL26
AK25
AL23
AK22
AL20
AK19
M30
GPIO29
GPIO30
GPIO31
HOUT
HYPLNK0CLKN
HYPLNK0CLKP
HYPLNK0REFRES
HYPLNK0RXFLCLK
HYPLNK0RXFLDAT
HYPLNK0RXN0
HYPLNK0RXN1
HYPLNK0RXN2
HYPLNK0RXN3
HYPLNK0RXP0
HYPLNK0RXP1
HYPLNK0RXP2
HYPLNK0RXP3
HYPLNK0RXPMCLK
HYPLNK0RXPMDAT
HYPLNK0TXFLCLK
HYPLNK0TXFLDAT
HYPLNK0TXN0
HYPLNK0TXN1
HYPLNK0TXN2
HYPLNK0TXN3
HYPLNK0TXP0
HYPLNK0TXP1
HYPLNK0TXP2
HYPLNK0TXP3
HYPLNK0TXPMCLK
HYPLNK0TXPMDAT
AJ7
AJ5
AJ3
AE3
AN8
AM7
AN5
AM4
AN9
RESETFULL
RESETSTAT
RESET
AM8
AN6
AM5
AE1
RSV000
RSV001
J32
AD1
RSV002
AE2
AC6
RSV003
AF2
AH4
RSV004
G2
AL9
RSV005
G1
AK8
RSV006
AL3
AL6
RSV007
AL2
AK5
RSV008
AG5
AL8
RSV009
K8
AK7
RSV010
J8
AL5
RSV011
W8
AK4
RSV012
W7
AB6
RSV013
J30
AF5
RSV014
J29
LENDIAN2
V30
RSV015
AG8
LRESETNMIEN
LRESET
AE30
AF33
Y33
RSV016
RSV017
RSV018
AJ20
AG12
AJ28
SPI0DIN
M31
N29
L31
SPI0DOUT
SPI0SCS0
MAINPLLODSEL2
MDCLK0
AH6
RSV019
RSV020
RSV021
RSV022
RSV023
SCL0
AJ26
AH9
SPI0SCS1
SPI0SCS2
SPI0SCS3
SPI1CLK
M29
L29
L32
M33
R30
P32
P29
M32
N30
MDIO0
AH5
NETCPCLKN
NETCPCLKP
NETCPCLKSEL
NMI
AN3
B19
AM2
AG6
AG33
AJ18
AJ17
AG14
E20
A14
SPI1DIN
AG30
AH30
AH31
AG28
SPI1DOUT
SPI1SCS0
SPI1SCS1
SPI1SCS2
PCIE0CLKN
PCIE0CLKP
PCIE0REFRES
SCL1
SCL2
SDA0
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www.ti.com
Table 6-4. Terminal Functions — By Signal Name (continued)
SIGNAL NAME
SPI1SCS3
SPI2CLK
BALL NUMBER
SIGNAL NAME
TSRXCLKOUT0P
TSRXCLKOUT1N
TSRXCLKOUT1P
TSSYNCEVT
UART0CTS
UART0DSR
UART0DTR
UART0RTS
UART0RXD
UART0TXD
UART1CTS
UART1RTS
UART1RXD
UART1TXD
USB0DM
BALL NUMBER
AJ1
AH1
AG2
AE5
R33
W29
U33
R32
T29
T30
T31
T33
U29
T32
W3
SIGNAL NAME
USB1RESREF
USB1RX0M
USB1RX0P
USB1TX0M
USB1TX0P
USB1VBUS
USB1VP
BALL NUMBER
N33
V5
L33
N1
SPI2DIN
P30
P1
SPI2DOUT
SPI2SCS0
SPI2SCS1
SPI2SCS2
SPI2SCS3
SYSCLKOUT
TCK
R31
R2
P31
P2
R29
V4
P33
R8
L30
USB1VPH
USB1VPTX
USBCLKM
USBCLKP
USIMCLK
USIMIO
R10
T9
AE4
AJ33
AG31
AF29
K33
T4
TDI
U4
TDO
J33
H33
K29
V29
H29
G33
H31
H30
G32
J31
U30
TIMI0
TIMI1
K32
USIMRST
VCL
TIMO0
K31
TIMO1
K30
USB0DP
V3
VCNTL0
TMS
AH32
AG32
AF4
USB0DRVVBUS
USB0DVDD33
USB0ID0
AB1
Y11
W4
VCNTL1
TRST
VCNTL2
TSCOMPOUT
TSIP0CLKA
TSIP0CLKB
TSIP0FSA
TSIP0FSB
TSIP0TR0
TSIP0TR1
TSIP0TX0
TSIP0TX1
TSPUSHEVT0
TSPUSHEVT1
TSREFCLKN
TSREFCLKP
TSRXCLKOUT0N
VCNTL3
AK31
AK33
AJ31
AK32
AM31
AL33
AL32
AM32
AG3
USB0RESREF
USB0RX0M
USB0RX0P
USB0TX0M
USB0TX0P
USB0VBUS
USB0VP
Y6
VCNTL4
T1
VCNTL5
U1
VD
U2
VDDAHV
AH11, AH13, AH15, AH17,
AH19, AH21, AH23, AH25
V2
W5
VDDALV
AE10, AE12, AE14, AE16, AE18,
AE20, AE22, AE24, AF9, AF11,
AF13, AF15, AF17, AF19, AF21,
AF23, AF25, AG16, AG18,
AG20, AG22, AG24
U8
USB0VPH
W10
V9
USB0VPTX
USB1DM
AL1
P4
AK1
USB1DP
R4
VDDUSB0
VDDUSB1
VNWA1
U10, V11
R12, T11
P9
AK2
USB1DRVVBUS
USB1DVDD33
USB1ID0
AC1
P11
W6
AJ2
VNWA2
J24
50
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-4. Terminal Functions — By Signal Name (continued)
SIGNAL NAME
VNWA3
VNWA4
VPP0
BALL NUMBER
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
BALL NUMBER
AD23
AD9
K9
VSS
W11, W13, W15, W17, W19,
W21, W23, W25, W27, Y8, Y10,
Y12, Y14, Y16, Y18, Y20, Y22,
Y24, Y26, Y28, AA4, AA7, AA9,
AA11, AA13, AA15, AA17, AA19,
AA21, AA23
VSS
AN4, AN7, AN10, AN13, AN16,
AN19, AN22, AN25, AN28,
AN31, AN33
VPP1
M9
VSSCMON
J9
VSS
VSS
VSS
VSS
VSS
A1, A33, C5, C9, C14, C19, C23, VSS
C27, C29, D3, D7, D11, D17,
D21, D25, D31, F4, F6, F8, F10,
F12, F14, F16, F18, F20, F22,
F24, F26, F28, F30, G7, G9,
G11, G13, G15, G17
AA25, AA27, AA32, AB8, AB10,
AB12, AB14, AB16, AB18, AB20,
AB22, AB24, AB26, AB28, AC7,
AC9, AC11, AC13, AC15, AC17,
AC19, AC21, AC23, AC25
VSSTMON
XFICLKN
XFICLKP
K26
AJ12
AJ11
AF6
XFIMDCLK
G19, G21, G23, G25, G27, G29,
G31, H8, H10, H12, H14, H16,
H18, H20, H22, H24, H26, H28,
J3, J7, J11, J13, J15, J17, J19,
J21, J23, J25, J27, K10, K12,
K14, K16, K18
VSS
VSS
VSS
VSS
AC27, AD5, AD8, AD10, AD12,
AD14, AD16, AD18, AD20,
AD22, AD24, AD26, AD28, AE9,
AE11, AE13, AE15, AE17, AE19,
AE21, AE23, AE25, AE27, AE32
XFIMDIO
AE7
XFIREFRES0
XFIREFRES1
XFIRXN0
AG10
AH7
AN11
K20, K22, K24, K28, L7, L9, L11,
L13, L15, L17, L19, L21, L23,
L25, L27, M1, M8, M10, M12,
M14, M16, M18, M20, M22, M24,
M26, M28, N2, N7, N9, N11,
N13, N15, N17
AF8, AF10, AF12, AF14, AF16,
AF18, AF20, AF22, AF24, AF26,
AF28, AG7, AG9, AG11, AG13,
AG15, AG17, AG19, AG21,
XFIRXN1
XFIRXP0
XFIRXP1
XFITXN0
AM10
AN12
AM11
AL12
AG23, AG25, AG27, AH8, AH10
N19, N21, N23, N25, N27, N32,
P8, P10, P12, P14, P16, P18,
P20, P22, P24, P26, P28, R1,
R7, R9, R11, R13, R15, R17,
R19, R21, R23, R25, R27, T2,
T8, T10, T12, T14
AH12, AH14, AH16, AH18,
AH20, AH22, AH24, AH26,
AH28, AJ4, AJ6, AJ9, AJ13,
AJ16, AJ19, AJ21, AJ23, AJ29,
AK3, AK6, AK9, AK12, AK15,
AK18, AK21, AK24
XFITXN1
XFITXP0
XFITXP1
AK11
AL11
AK10
T16, T18, T20, T22, T24, T26,
T28, U3, U7, U9, U11, U13, U15,
U17, U19, U21, U23, U25, U27,
U32, V1, V8, V10, V12, V14,
V16, V18, V20, V22, V24, V26,
V28, W2, W9
AK27, AK30, AL4, AL7, AL10,
AL13, AL16, AL19, AL22, AL25,
AL28, AL31, AM1, AM3, AM6,
AM9, AM12, AM15, AM18,
AM21, AM24, AM27, AM30, AN1,
AN2
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 6-5. Terminal Functions — By Ball Number
BALL NUMBER
A1
SIGNAL NAME
VSS
BALL NUMBER
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
C1
SIGNAL NAME
DDRDQM8
DDRCB05
DDRDQS8P
DDRD32
DDRDQS4N
DDRD38
DDRD46
DDRDQS5N
DDRD44
DDRD52
DDRDQS6N
DDRD50
DDRD63
DVDD15
DDRDQS0P
DDRDQS0N
DVDD15
DDRD12
VSS
BALL NUMBER
D6
SIGNAL NAME
DDRD16
VSS
A2
DVDD15
D7
A3
DDRDQM0
DDRDQS1P
DDRD08
D8
DDRDQM2
DVDD15
DDRD28
VSS
A4
D9
A5
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
E1
A6
DDRD09
A7
DDRDQS2N
DDRD22
DDRODT0
DDRBA0
DVDD15
DDRA00
DDRA04
VSS
A8
A9
DDRD31
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
B1
DDRDQS3P
DDRD26
DDRCE0
DDRA10
DDRA11
DVDD15
DDRRESET
VSS
RSV023
DDRCLKOUTN1
DDRCLKOUTP1
DDRA06
C2
C3
DDRCB01
DVDD15
DDRD34
VSS
DDRA08
C4
DDRCKE1
DDRCB06
DDRCB07
DDRDQS8N
DDRCB00
DDRDQS4P
DDRD39
C5
C6
DDRD20
DVDD15
DDRD21
VSS
C7
DDRDQM5
DVDD15
DDRD41
DVDD15
DDRD55
VSS
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
D1
DDRD27
DVDD15
DDRCE1
DDRBA1
VSS
DDRD45
DDRDQS5P
DDRD49
DDRD62
DDRDQS7N
DDRD03
DDRD00
DDRDQM1
DDRD14
DDRD11
DDRD17
DDRD18
DDRDQM3
DDRD30
DDRD24
DDRODT1
DDRA13
DDRWE
AVDDA7
DDRRZQ0
DDRA05
DDRA07
DDRA12
DDRA15
RSV022
DDRCB03
DDRCB02
DDRD33
DDRD36
DDRD48
DDRA01
DDRA03
DVDD15
DDRA14
VSS
DDRDQS6P
DDRDQM7
DVDD15
E2
E3
E4
VSS
E5
DVDD15
DDRCKE0
DVDD15
DDRCB04
VSS
E6
B2
DDRD07
E7
B3
DDRD15
E8
B4
DDRDQS1N
DDRD10
E9
B5
DDRD35
DVDD15
DDRD47
VSS
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
B6
DDRD19
B7
DDRDQS2P
DDRD23
B8
B9
DDRD29
DDRD42
VSS
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
DDRDQS3N
DDRD25
DDRD53
DVDD15
DDRD61
DDRDQS7P
DDRD01
DDRD05
VSS
DDRCAS
DDRRAS
DDRCLKOUTN0
DDRCLKOUTP0
DDRA02
D2
DDRA09
D3
DDRBA2
D4
DDRD13
DVDD15
RSV021
D5
52
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
E25
E26
E27
E28
E29
E30
E31
E32
E33
F1
SIGNAL NAME
DDRD37
DDRDQM4
DDRD43
DDRD40
DDRD51
DDRD54
DDRDQM6
DDRD59
DDRD60
DDRD04
DDRD02
DDRD06
VSS
BALL NUMBER
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
H1
SIGNAL NAME
BALL NUMBER
H30
H31
H32
H33
J1
SIGNAL NAME
VCNTL3
VCNTL2
RSV000
USIMIO
EMIFD03
DVDD18
VSS
VSS
DDRRZQ1
VSS
DVDD15
VSS
AVDDA8
VSS
J2
J3
DDRRZQ2
VSS
J4
EMIFD12
EMIFD15
EMIFD05
VSS
J5
DVDD15
VSS
J6
F2
J7
F3
AVDDA9
VSS
J8
RSV010
VSSCMON
CVDDCMON
VSS
F4
J9
F5
DVDD15
VSS
AVDDA10
VSS
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
J31
J32
J33
K1
F6
F7
DVDD15
VSS
DVDD15
VSS
CVDD
F8
VSS
F9
DVDD15
VSS
DVDD15
VSS
CVDD
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
G1
VSS
DVDD15
VSS
DVDD15
VSS
CVDD
VSS
DVDD15
VSS
VCNTL4
VCNTL1
EMIFD07
EMIFD08
EMIFD11
EMIFD13
EMIFD04
EMIFD06
DVDD15
VSS
CVDD
VSS
DDRVREFSSTL
VSS
CVDD
H2
VSS
DVDD15
VSS
H3
CVDD
H4
VSS
DVDD15
VSS
H5
VNWA2
VSS
H6
DVDD15
VSS
H7
CVDD
H8
VSS
DVDD15
VSS
H9
DVDD15
VSS
DVDD18
RSV014
RSV013
VCNTL5
RSV001
USIMCLK
EMIFA20
EMIFA19
EMIFD01
EMIFD02
EMIFD10
EMIFD14
AVDDA2
RSV009
VPP0
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
K2
DDRD56
DDRD58
DDRD57
RSV005
RSV004
DDRCLKN
DDRCLKP
EMIFD00
EMIFD09
VSS
DVDD15
VSS
K3
K4
DVDD15
VSS
K5
K6
G2
DVDD15
VSS
K7
G3
K8
G4
DVDD15
VSS
K9
G5
K10
K11
K12
K13
K14
K15
VSS
G6
DVDD15
VSS
CVDD
G7
VSS
G8
AVDDA6
VSS
DVDD15
VSS
CVDD
G9
VSS
G10
DVDD15
VCNTL0
CVDD
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Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
K16
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
SPI2CLK
VSS
BALL NUMBER
SIGNAL NAME
VSS
VSS
L33
M1
N19
K17
CVDD
VSS
N20
CVDD
K18
M2
DVDD18
EMIFA06
EMIFA10
EMIFA09
EMIFA18
DVDD18
VSS
N21
VSS
K19
CVDD
VSS
M3
N22
CVDD
K20
M4
N23
VSS
K21
CVDD
VSS
M5
N24
CVDD1
VSS
K22
M6
N25
K23
CVDD
VSS
M7
N26
CVDD
K24
M8
N27
VSS
K25
CVDD
VSSTMON
DVDD18
VSS
M9
VPP1
N28
DVDD18
SPI0DOUT
SPI1SCS2
DVDD18
VSS
K26
M10
M11
M12
M13
M14
M15
M16
M17
VSS
N29
K27
CVDD1
VSS
N30
K28
N31
K29
USIMRST
TIMO1
TIMO0
TIMI1
CVDD1
VSS
N32
K30
N33
SPI1SCS3
USB1RX0P
USB1TX0P
EMIFA00
K31
CVDD
P1
K32
VSS
P2
AVSIFSEL[1]2
TIMI0
K32
CVDD
P3
K33
K33
M18
M19
VSS
P4
P5
USB1DM
EMIFA01
AVSIFSEL[0]2
EMIFA11
EMIFA16
EMIFA14
EMIFA21
EMIFA17
EMIFA23
VSS
CVDD
L1
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
N1
VSS
P6
EMIFA04
DVDD18
VSS
L2
CVDD
P7
L3
VSS
P8
L4
CVDD1
VSS
P9
VNWA1
VSS
L5
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
R1
L6
CVDD
USB1DVDD33
VSS
L7
VSS
L8
DVDD18
VSS
DVDD18
VSS
CVDD
L9
VSS
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
L30
L31
L32
CVDD
SPI0SCS1
SPI0CLK
SPI0DIN
SPI1SCS1
SPI1CLK
USB1RX0M
VSS
CVDD
VSS
VSS
CVDD
CVDD
VSS
VSS
CVDD
CVDD
VSS
VSS
CVDD
N2
CVDD
VSS
N3
EMIFWAIT1
EMIFA07
EMIFA08
EMIFA05
VSS
VSS
CVDD
N4
CVDD
VSS
N5
VSS
CVDD
N6
CVDD
VSS
N7
VSS
CVDD
N8
DVDD18
VSS
DVDD18
VSS
VSS
N9
CVDD1
VSS
N10
N11
N12
N13
N14
N15
N16
N17
N18
CVDD
SPI1SCS0
SPI2DIN
SPI2SCS0
SPI1DOUT
SPI2SCS2
VSS
VSS
CVDDTMON
VSS
CVDD1
VSS
DVDD18
SPI0SCS2
SPI2SCS3
SPI0SCS0
SPI0SCS3
CVDD
VSS
CVDD
R2
USB1TX0M
EMIFA22
USB1DP
VSS
R3
CVDD
R4
54
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
R5
SIGNAL NAME
EMIFWE
EMIFBE1
VSS
BALL NUMBER
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
VSS
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
U1
VSS
V10
R6
CVDD
V11
VDDUSB0
VSS
R7
VSS
V12
R8
USB1VP
VSS
DVDD18
VSS
V13
CVDD
VSS
R9
V14
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
USB1VPH
VSS
UART0RXD
UART0TXD
UART1CTS
UART1TXD
UART1RTS
USB0RX0P
USB0TX0M
VSS
V15
CVDD
VSS
V16
VDDUSB1
VSS
V17
CVDD
VSS
V18
CVDD
VSS
V19
CVDD
VSS
V20
CVDD
VSS
U2
V21
CVDD
VSS
U3
V22
CVDD
VSS
U4
USBCLKP
EMIFA12
EMIFA02
VSS
V23
CVDD
VSS
U5
V24
CVDD
VSS
U6
V25
CVDD
VSS
U7
V26
CVDD
VSS
U8
USB0VP
VSS
V27
DVDD18
VSS
U9
V28
CVDD
VSS
U10
U11
U12
VDDUSB0
VSS
V29
VCL
V30
GPIO00
LENDIAN2
GPIO07
CVDD
CVDD
V30
R27
R28
VSS
U13
U14
VSS
V31
V31
BOOTMODE062
GPIO04
DVDD18
CVDD
R29
R30
SPI2SCS1
SPI1DIN
U15
U16
VSS
V32
V32
BOOTMODE032
GPIO03
CVDD
R31
R32
SPI2DOUT
UART0RTS
U17
U18
VSS
V33
V33
BOOTMODE022
EMIFCE2
VSS
CVDD
R33
T1
UART0CTS
USB0RX0M
VSS
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
U30
U31
U32
U33
V1
VSS
W1
CVDD
W2
T2
VSS
W3
USB0DM
USB0ID0
USB0VBUS
USB1ID0
RSV012
RSV011
VSS
T3
EMIFA15
USBCLKM
EMIFA13
EMIFWAIT0
DVDD18
VSS
CVDD
W4
T4
VSS
W5
T5
CVDD
W6
T6
VSS
W7
T7
CVDD
W8
T8
VSS
W9
T9
USB1VPTX
VSS
DVDD18
UART1RXD
VD
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
USB0VPH
VSS
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
VDDUSB1
VSS
CVDD
DVDD18
VSS
VSS
CVDD
CVDD
VSS
UART0DTR
VSS
VSS
CVDD
CVDD
VSS
V2
USB0TX0P
USB0DP
USB1VBUS
USB1RESREF
EMIFA03
DVDD18
VSS
VSS
CVDD
V3
CVDD
VSS
V4
VSS
CVDD
V5
CVDD
VSS
V6
VSS
CVDD
V7
CVDD
VSS
V8
VSS
CVDD
V9
USB0VPTX
CVDD
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Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
W25
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
EMIFBE0
DVDD18
VSS
BALL NUMBER
SIGNAL NAME
VSS
VSS
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AB18
W26
CVDD
AB19
CVDD
VSS
W27
VSS
AB20
W28
DVDD18
UART0DSR
GPIO05
EMU15
AB21
CVDD
VSS
W29
EMU01
AB22
W30
VSS
AB23
CVDD1
VSS
BOOTMODE042
GPIO08
W30
DVDD18
AB24
W31
W31
AA9
VSS
AB25
AB26
CVDD
VSS
BOOTMODE072
GPIO06
AA10
CVDD
W32
W32
AA11
AA12
VSS
AB27
AB28
DVDD18
VSS
BOOTMODE052
GPIO09
CVDD1
W33
W33
AA13
AA14
VSS
AB29
AB29
GPIO10
BOOTMODE082
EMIFCE3
BOOTMODE092
GPIO25
CVDD1
Y1
Y2
AA15
AA16
VSS
AB30
AB30
EMU273
GPIO19
EMIFOE
CVDD
Y3
Y4
EMIFRW
EMIFCE1
AA17
AA18
VSS
AB31
AB31
EMU213
GPIO17
CVDD
Y5
Y6
EMU17
AA19
AA20
VSS
AB32
AB32
EMU193
USB0RESREF
CVDD
BOOTMODE142
GPIO18
Y7
DVDD18
AA21
VSS
AB32
Y8
Y9
VSS
AA22
AA23
CVDD
VSS
AB33
AB33
EMU203
CVDD
BOOTMODE152
USB1DRVVBUS
EMU13
Y10
VSS
AA24
CVDD1
AB33
Y11
Y12
Y13
Y14
Y15
Y16
USB0DVDD33
VSS
AA25
AA26
AA27
AA28
AA29
AA29
VSS
AC1
AC2
AC3
AC4
AC5
AC6
CVDD
VSS
CVDD1
VSS
EMU07
DVDD18
GPIO01
EMU02
CVDD
EMU00
BOOTMODE002
GPIO13
VSS
HYPLNK0TXFLCLK
Y17
Y18
CVDD
VSS
AA30
AA30
AC7
AC8
VSS
BOOTMODE122
DVDD18
VSS
DVDD18
Y19
Y20
Y21
Y22
CVDD
VSS
AA31
AA32
AA33
AA33
AC9
VSS
AC10
AC11
AC12
CVDD
VSS
CVDD
VSS
GPIO16
BOOTMODE132
USB0DRVVBUS
EMU16
CVDD
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y29
CVDD1
VSS
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
VSS
CVDD
VSS
CVDD
VSS
EMU14
EMU08
CVDD
VSS
DVDD18
VSS
EMU06
HYPLNK0TXPMCLK
DVDD18
CVDD
VSS
GPIO02
BOOTMODE012
GPIO11
VSS
CVDD
Y30
Y30
AB9
CVDD
VSS
AC21
AC22
VSS
BOOTMODE102
GPIO15
AB10
CVDD
Y31
Y31
AB11
AB12
CVDD
VSS
AC23
AC24
VSS
BOOTMODE_RSVD2
GPIO12
CVDD
Y32
Y32
AB13
AB14
CVDD
VSS
AC25
AC26
VSS
BOOTMODE112
GPIO14
CVDD
Y33
Y33
AB15
AB16
CVDD
VSS
AC27
AC28
VSS
MAINPLLODSEL2
EMIFCE0
DVDD18
AA1
AB17
CVDD
AC29
GPIO20
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
EMU223
GPIO26
AC29
AE6
EMU03
AF24
VSS
AC30
AC30
AE7
AE8
XFIMDIO
DVDD18
AF25
AF26
VDDALV
VSS
EMU283
GPIO23
AC31
AC31
AE9
VSS
AF27
AF28
DVDD18
VSS
EMU253
GPIO24
AE10
VDDALV
AC32
AC32
AE11
AE12
VSS
AF29
AF30
TDO
EMU263
GPIO21
VDDALV
HOUT
AC33
AC33
AE13
AE14
VSS
AF31
AF32
BOOTCOMPLETE
RESETFULL
EMU233
HYPLNK0RXPMDAT
EMU12
EMU05
DVDD18
VSS
VDDALV
AD1
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE31
AE32
AE33
AE33
VSS
AF33
AG1
LRESET
CORECLKN
TSRXCLKOUT1P
TSPUSHEVT0
EMU11
AD2
VDDALV
VSS
AD3
AG2
AD4
VDDALV
VSS
AG3
AD5
AG4
AD6
EMU04
AVDDA3
VSS
VDDALV
VSS
AG5
RSV008
NETCPCLKSEL
VSS
AD7
AG6
AD8
VDDALV
VSS
AG7
AD9
VNWA4
VSS
AG8
RSV015
VSS
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
VDDALV
VSS
AG9
CVDD
VSS
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
XFIREFRES0
VSS
DVDD18
VSS
CVDD
VSS
RSV017
VSS
DVDD18
RESET
LRESETNMIEN
DVDD18
VSS
CVDD
VSS
PCIE0REFRES
VSS
CVDD
VSS
VDDALV
VSS
CVDD
VSS
GPIO30
VDDALV
VSS
EMU323
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD29
CVDD
VSS
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
CORECLKP
RSV003
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
VDDALV
VSS
VNWA3
VSS
EMU10
VDDALV
VSS
TSCOMPOUT
HYPLNK0TXPMDAT
XFIMDCLK
AVDDA1
CVDD
VSS
VDDALV
VSS
DVDD18
VSS
DVDD18
VSS
VSS
GPIO22
VDDALV
SDA0
EMU243
GPIO31
VSS
SDA2
AD30
AD30
AF11
AF12
VDDALV
VSS
AG30
AG31
SCL0
TDI
EMU333
GPIO29
AD31
AD31
AF13
AF14
VDDALV
VSS
AG32
AG33
TRST
NMI
EMU313
GPIO27
AD32
AD32
AF15
AF16
VDDALV
VSS
AH1
AH2
TSRXCLKOUT1N
EMU18
EMU293
GPIO28
AD33
AD33
AF17
AF18
VDDALV
VSS
AH3
AH4
EMU09
EMU303
HYPLNK0TXFLDAT
AE1
AE2
AE3
AE4
AE5
HYPLNK0RXPMCLK
RSV002
AF19
AF20
AF21
AF22
AF23
VDDALV
VSS
AH5
AH6
AH7
AH8
AH9
MDIO0
MDCLK0
XFIREFRES1
VSS
HYPLNK0RXFLDAT
SYSCLKOUT
TSSYNCEVT
VDDALV
VSS
VDDALV
RSV020
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Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AH30
AH31
AH32
AH33
AJ1
SIGNAL NAME
BALL NUMBER
AJ29
AJ30
AJ31
AJ32
AJ33
AK1
SIGNAL NAME
BALL NUMBER
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AL32
AL33
AM1
SIGNAL NAME
PCIE1TXN0
VSS
VSS
VSS
VDDAHV
VSS
DVDD18
TSIP0FSA
SDA1
PCIE0TXP0
PCIE0TXN0
VSS
VDDAHV
VSS
TCK
VDDAHV
VSS
TSREFCLKN
TSREFCLKP
VSS
SGMII0TXP6
SGMII0TXN6
VSS
AK2
VDDAHV
VSS
AK3
AK4
HYPLNK0TXP3
HYPLNK0TXN3
VSS
SGMII0TXP4
SGMII0TXN4
VSS
VDDAHV
VSS
AK5
AK6
VDDAHV
VSS
AK7
HYPLNK0TXP1
HYPLNK0TXN1
VSS
SGMII0TXP2
SGMII0TXN2
VSS
AK8
VDDAHV
VSS
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AK25
AK26
AK27
AK28
AK29
AK30
AK31
AK32
AK33
AL1
XFITXP1
SGMII0TXP0
SGMII0TXN0
VSS
VDDAHV
VSS
XFITXN1
VSS
DVDD18
VSS
PCIE1TXP1
PCIE1TXN1
VSS
TSIP0TX0
TSIP0TR1
VSS
RESETSTAT
SCL1
PCIE0TXP1
PCIE0TXN1
VSS
AM2
NETCPCLKP
VSS
SCL2
AM3
TMS
AM4
HYPLNK0RXN3
HYPLNK0RXP3
VSS
POR
SGMII0TXP7
SGMII0TXN7
VSS
AM5
TSRXCLKOUT0P
TSRXCLKOUT0N
HYPLNK0RXFLCLK
VSS
AM6
AJ2
AM7
HYPLNK0RXN1
HYPLNK0RXP1
VSS
AJ3
SGMII0TXP5
SGMII0TXN5
VSS
AM8
AJ4
AM9
AJ5
HYPLNK0REFRES
VSS
AM10
AM11
AM12
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AM32
AM33
XFIRXN1
XFIRXP1
VSS
AJ6
SGMII0TXP3
SGMII0TXN3
VSS
AJ7
HYPLNK0CLKP
HYPLNK0CLKN
VSS
AJ8
PCIE1RXN1
PCIE1RXP1
VSS
AJ9
SGMII0TXP1
SGMII0TXN1
VSS
AJ10
AJ11
AJ12
AJ13
AJ14
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
PCIE1REFRES
XFICLKP
XFICLKN
VSS
PCIE0RXN1
PCIE0RXP1
VSS
TSIP0CLKA
TSIP0FSB
TSIP0CLKB
TSPUSHEVT1
RSV007
PCIE1CLKP
PCIE1CLKN
VSS
SGMII0RXN7
SGMII0RXP7
VSS
AL2
PCIE0CLKP
PCIE0CLKN
VSS
AL3
RSV006
SGMII0RXN5
SGMII0RXP5
VSS
AL4
VSS
AL5
HYPLNK0TXP2
HYPLNK0TXN2
VSS
RSV016
AL6
SGMII0RXN3
SGMII0RXP3
VSS
VSS
AL7
SGMII01REFRES
VSS
AL8
HYPLNK0TXP0
HYPLNK0TXN0
VSS
AL9
SGMII0RXN1
SGMII0RXP1
VSS
SGMII0CLKP
SGMII0CLKN
RSV019
AL10
AL11
AL12
AL13
AL14
XFITXP0
XFITXN0
VSS
TSIP0TR0
TSIP0TX1
DVDD18
SGMII00REFRES
RSV018
PCIE1TXP0
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 6-5. Terminal Functions — By Ball Number (continued)
BALL NUMBER
AN1
SIGNAL NAME
BALL NUMBER
SIGNAL NAME
XFIRXP0
VSS
BALL NUMBER
SIGNAL NAME
SGMII0RXN4
SGMII0RXP4
VSS
VSS
AN12
AN23
AN2
VSS
AN13
AN24
AN3
NETCPCLKN
VSS
AN14
PCIE1RXN0
PCIE1RXP0
VSS
AN25
AN4
AN15
AN26
SGMII0RXN2
SGMII0RXP2
VSS
AN5
HYPLNK0RXN2
HYPLNK0RXP2
VSS
AN16
AN27
AN6
AN17
PCIE0RXN0
PCIE0RXP0
VSS
AN28
AN7
AN18
AN29
SGMII0RXN0
SGMII0RXP0
VSS
AN8
HYPLNK0RXN0
HYPLNK0RXP0
VSS
AN19
AN30
AN9
AN20
SGMII0RXN6
SGMII0RXP6
VSS
AN31
AN10
AN11
AN21
AN32
DVDD18
XFIRXN0
AN22
AN33
VSS
6.4 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Device Configuration Pins: If the pin is both routed out and not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the device configuration pins (listed in Table 9-26), if they are both routed out and are not driven (in
Hi-Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented.
Although, internal pullup/pulldown resistors exist on these pins and they may match the desired
configuration value, providing external connectivity can help ensure that valid logic levels are latched on
these device configuration pins. In addition, applying external pullup/pulldown resistors on the device
configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Be sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value that still ensures that the net will reach
the target pulled value when maximum current from all devices on the net is flowing through the
resistor. The current to be considered includes leakage current plus, any other internal and external
pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value
of the external resistor. Verify that the resistance is small enough that the weakest output buffer can
drive the net to the opposite logic level (including margin).
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems:
•
A 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should
confirm this resistor value is correct for their specific application.
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•
A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while
meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH)
for the 66AK2E0x device, see Section 10.3. To determine which pins on the device include internal
pullup/pulldown resistors, see Table 6-2.
60
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
7 Memory, Interrupts, and EDMA for 66AK2E0x
7.1 Memory Map Summary66AK2E0x
The following table shows the memory map address ranges of the device.
Table 7-1. Device Memory Map Summary 66AK2E0x
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
ARM VIEW
ARM ROM
Reserved
DSP VIEW
Reserved
SOC VIEW
ARM ROM
Reserved
00 0000 0000
00 0004 0000
00 0080 0000
00 0088 0000
00 0090 0000
00 00E0 0000
00 00E0 8000
00 00F0 0000
00 00F0 8000
00 0100 0000
00 0101 0000
00 0110 0000
00 0101 0000
00 01C0 0000
00 01D0 0000
00 01D0 0080
00 01D0 8000
00 01D0 8080
00 01D1 0000
00 01D1 0080
00 01D1 8000
00 01D1 8080
00 01D2 0000
00 01D2 0080
00 01D2 8000
00 01D2 8080
00 01D3 0000
00 01D3 0080
00 01D3 8000
00 01D3 8080
00 01D4 0000
00 01D4 0080
00 01D4 8000
00 01D4 8080
00 01D5 0000
00 01D5 0080
00 01D5 8000
00 01D5 8080
00 01D6 0000
00 01D6 0080
00 01D6 8000
00 01D6 8080
00 01D7 0000
00 01D7 0080
00 01D7 8000
00 0003 FFFF
256K
00 007F FFFF 8M-256K
00 0087 FFFF 512K
Reserved
Reserved
L2 SRAM
L2 SRAM
00 008F FFFF 512K
00 00DF FFFF 5M
00 00E0 7FFF 32K
00 00EF FFFF 1M-32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
L1P SRAM
Reserved
L1P SRAM
Reserved
Reserved
00 00F0 7FFF
00 00FF FFFF 1M-32K
00 0100 FFFF 64K
00 010F FFFF 1M-64K
00 0110 FFFF 64K
32K
Reserved
L1D SRAM
Reserved
L1D SRAM
Reserved
Reserved
ARM AXI2VBUSM registers
Reserved
C66x CorePac registers
C66x CorePac registers
C66x CorePac registers
C66x CorePac registers
Reserved
C66x CorePac registers
C66x CorePac registers
C66x CorePac registers
C66x CorePac registers
Reserved
ARM STM Stimulus Ports
Reserved
00 01BF FFFF 11M-64K
00 01CF FFFF 1M
Reserved
00 01D0 007F
00 01D0 7FFF 32K-128
00 01D0 807F 128
00 01D0 FFFF 32K-128
00 01D1 007F 128
00 01D1 7FFF 32K-128
00 01D1 807F 128
00 01D1 FFFF 32K-128
00 01D2 007F 128
00 01D2 7FFF 32K-128
00 01D2 807F 128
00 01D2 FFFF 32K-128
00 01D3 007F 128
00 01D3 7FFF 32K-128
00 01D3 807F 128
00 01D3 FFFF 32K-128
00 01D4 007F 128
00 01D4 7FFF 32K-128
00 01D4 807F 128
00 01D4 FFFF 32K-128
00 01D5 007F 128
00 01D5 7FFF 32K-128
00 01D5 807F 128
00 01D5 FFFF 32K-128
00 01D6 007F 128
00 01D6 7FFF 32K-128
00 01D6 807F 128
00 01D6 FFFF 32K-128
00 01D7 007F 128
00 01D7 7FFF 32K-128
00 01D7 807F 128
128
Tracer CFG0
Reserved
Tracer CFG0
Reserved
Tracer CFG0
Reserved
Tracer CFG1
Reserved
Tracer CFG1
Reserved
Tracer CFG1
Reserved
Tracer CFG2
Reserved
Tracer CFG2
Reserved
Tracer CFG2
Reserved
Tracer CFG3
Reserved
Tracer CFG3
Reserved
Tracer CFG3
Reserved
Tracer CFG4
Reserved
Tracer CFG4
Reserved
Tracer CFG4
Reserved
Tracer CFG5
Reserved
Tracer CFG5
Reserved
Tracer CFG5
Reserved
Tracer CFG6
Reserved
Tracer CFG6
Reserved
Tracer CFG6
Reserved
Tracer CFG7
Reserved
Tracer CFG7
Reserved
Tracer CFG7
Reserved
Tracer CFG8
Reserved
Tracer CFG8
Reserved
Tracer CFG8
Reserved
Tracer CFG9
Reserved
Tracer CFG9
Reserved
Tracer CFG9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
00 01D7 FFFF 32K-128
00 01D8 007F 128
00 01D8 7FFF 32K-128
00 01D8 807F 128
00 01D8 8FFF 32K-128
00 01D9 007F 128
00 01D9 7FFF 32K-128
00 01D9 807F 128
00 01D9 FFFF 32K-128
BYTES
ARM VIEW
Reserved
DSP VIEW
Reserved
SOC VIEW
Reserved
00 01D7 8080
00 01D8 0000
00 01D8 0080
00 01D8 8000
00 01D8 8080
00 01D9 0000
00 01D9 0080
00 01D9 8000
00 01D9 8080
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 01DA 0000 00 01DA 007F 128
00 01DA 0080 00 01DA 7FFF 32K-128
00 01DA 8000 00 01DA 807F 128
00 01DA 8080 00 01DA FFFF 32K-128
00 01DB 0000 00 01DB 007F 128
00 01DB 0080 00 01DB 7FFF 32K-128
00 01DB 8000 00 01DB 807F 128
00 01DB 8080 00 01DB 8FFF 32K-128
00 01DC 0000 00 01DC 007F 128
00 01DC 0080 00 01DC 7FFF 32K-128
00 01DC 8000 00 01DC 807F 128
00 01DC 8080 00 01DC FFFF 32K-128
00 01DD 0000 00 01DD 007F 128
00 01DD 0080 00 01DD 7FFF 32K-128
00 01DD 8000 00 01DD 807F 128
00 01DD 8080 00 01DD FFFF 32K-128
00 01DE 0000 00 01DE 007F 128
00 01DE 0080 00 01DE 03FF 1K-128
00 01DE 0400 00 01DE 047F 128
00 01DD 0480 00 01DD 07FF 1K-128
00 01DE 0800 00 01DE 087F 128
00 01DE 0880 00 01DE 7FFF 30K-128
00 01DE 8000 00 01DE 807F 128
00 01DE 8080 00 01DF FFFF 64K-128
Tracer CFG20
Reserved
Tracer CFG20
Reserved
Tracer CFG20
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer CFG22
Reserved
Tracer CFG22
Reserved
Tracer CFG22
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Tracer CFG24
Reserved
Tracer CFG24
Reserved
Tracer CFG24
Reserved
Tracer CFG25
Reserved
Tracer CFG25
Reserved
Tracer CFG25
Reserved
Tracer CFG26
Reserved
Tracer CFG26
Reserved
Tracer CFG26
Reserved
Tracer CFG27
Reserved
Tracer CFG27
Reserved
Tracer CFG27
Reserved
Tracer CFG28
Reserved
Tracer CFG28
Reserved
Tracer CFG28
Reserved
Tracer CFG29
Reserved
Tracer CFG29
Reserved
Tracer CFG29
Reserved
Tracer CFG30
Reserved
Tracer CFG30
Reserved
Tracer CFG30
Reserved
Tracer CFG31
Reserved
Tracer CFG31
Reserved
Tracer CFG31
Reserved
00 01E0 0000
00 01E4 0000
00 01E8 0000
00 01E8 4000
00 01E3 FFFF 256K
00 01E7FFFF 256k
Reserved
Reserved
Reserved
TSIP_CFG
ARM CorePac_CFG
Reserved
TSIP_CFG
ARM CorePac_CFG
Reserved
TSIP_CFG
ARM CorePac_CFG
Reserved
00 01E8 3FFF 16K
00 01EB FFFF 240k
00 01EC 0000 00 01EF FFFF 256K
Reserved
Reserved
Reserved
00 01F0 0000
00 01F8 0000
00 01F9 0000
00 01FA 0000
00 01FC 0000
00 01FE 0000
00 0200 0000
00 01F7 FFFF 512K
00 01F8 FFFF 64K
00 01F9 FFFF 64K
00 01FB FFFF 128K
00 01FD FFFF 128K
00 01FF FFFF 128K
00 020F FFFF 1M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Network Coprocessor 0(Packet
Accelerator, 1-gigabit Ethernet
switch subsystem and Security
Accelerator)
Network Coprocessor 0(Packet
Accelerator, 1-gigabit Ethernet
switch subsystem and Security
Accelerator)
Network Coprocessor 0(Packet
Accelerator, 1-gigabit Ethernet
switch subsystem and Security
Accelerator)
00 0210 0000
00 0211 0000
00 0212 0000
00 0210 FFFF
00 0211 FFFF
00 0213 FFFF
64K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64K
128K
62
Memory, Interrupts, and EDMA for 66AK2E0x
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66AK2E05, 66AK2E02
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
128K
128K
32k
ARM VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 15
Tracer CFG32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer0
DSP VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 15
Tracer CFG32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer0
SOC VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Memory protection unit (MPU) 15
Tracer CFG32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer0
00 0214 0000
00 0216 0000
00 0218 0000
00 0218 8000
00 0219 0000
00 021A 0000
00 021B 0000
00 021C 0000
00 021C 0400
00 021C 4000
00 021C 4400
00 021C 6000
00 021C 6400
00 021C 8000
00 021C 8400
00 021D 0000
00 021D 0400
00 021D 0100
00 021D 4000
00 021D 4100
00 021D 8000
00 021D 8100
00 0215 FFFF
00 0217 FFFF
00 0218 7FFF
00 0218 FFFF
00 0219 FFFF
32k
64k
00 021A FFFF 64K
00 021B FFFF 64K
00 021C 03FF 1K
00 021C 3FFF 15K
00 021C 43FF 1K
00 021C 5FFF 7K
00 021C 63FF 1K
00 021C 7FFF 7K
00 021C 83FF 1K
00 021C FFFF 31K
00 021D 03FF 1K
00 021D 047F
128
00 021D 3FFF 15K-128
00 021D 40FF 256
00 021D 7FFF 16K-256
00 021D 80FF 256
00 021D BFFF 16K-256
00 021D C000 00 021D C0FF 256
00 021D C100 00 021D EFFF 12K-256
00 021D F000
00 021D F080
00 021E 0000
00 021F 0000
00 021F 0800
00 021F 1000
00 021F 1800
00 021F 4000
00 021F 4800
00 021F 8000
00 021F 8800
00 021F C000
00 021F C800
00 0220 0000
00 0220 0080
00 0221 0000
00 0221 0080
00 0222 0000
00 0222 0080
00 0223 0000
00 0223 0080
00 0224 0000
00 0224 0080
00 0225 0000
00 0225 0080
00 0226 0000
00 021D F07F 128
00 021D FFFF 4K-128
00 021E FFFF 64K
00 021F 07FF
00 021F 0FFF
00 021F 17FF
00 021F 3FFF
00 021F 47FF
00 021F 7FFF
00 021F 87FF
2K
2K
2K
10K
2K
14K
2K
00 021F BFFF 14K
00 021F C7FF 2K
00 021F FFFF 14K
00 0220 007F
00 0220 FFFF
00 0221 007F
00 0221 FFFF
00 0222 007F
00 0222 FFFF
00 0223 007F
00 0223 FFFF
00 0224 007F
00 0224 FFFF
00 0225 007F
00 0225 FFFF
00 0226 007F
128
64K-128
128
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
128
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for 66AK2E0x
63
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
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Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
64K-128
128
ARM VIEW
Reserved
DSP VIEW
Reserved
SOC VIEW
Reserved
Reserved
Reserved
Timer 8
00 0226 0080
00 0227 0000
00 0227 0080
00 0228 0000
00 0228 0080
00 0229 0000
00 0229 0080
00 022A 0000
00 022A 0080
00 022B 0000
00 022B 0080
00 022C 0000
00 022C 0080
00 022D 0000
00 022D 0080
00 022E 0000
00 022E 0080
00 022F 0000
00 022F 0080
00 022F 0100
00 022F 0180
00 022F 0200
00 0230 0000
00 0231 0000
00 0231 0200
00 0231 A000
00 0231 C000
00 0231 E000
00 0232 0000
00 0232 4000
00 0232 6000
00 0232 8000
00 0232 9000
00 0232 A000
00 0232 C000
00 0232 D000
00 0232 E000
00 0233 0000
00 0233 0400
00 0233 0400
00 0234 0000
00 0234 0100
00 0234 4000
00 0234 4100
00 0234 8000
00 0234 8100
00 0234 C000
00 0234 C100
00 0235 0000
00 0235 1000
00 0226 FFFF
00 0227 007F
00 0227 FFFF
00 0228 007F
00 0228 FFFF
00 0229 007F
00 0229 FFFF
00 022A 007F
Reserved
Reserved
64K-128
128
Reserved
Reserved
Timer 8
Timer 8
64K-128
128
Reserved
Reserved
Reserved
Timer 9
Timer 9
Timer 9
64K-128
128
Reserved
Reserved
Reserved
Timer 10
Reserved
Timer 11
Reserved
Timer 12
Reserved
Timer 13
Reserved
Timer 14
Reserved
Timer 15
Timer 16
Timer 17
Timer 18
Timer 19
Reserved
PLL Controller
Reserved
Timer 10
Timer 10
00 022A FFFF 64K-128
00 022B 007F 128
00 022B FFFF 64K-128
00 022C 007F 128
00 022C FFFF 64K-128
00 022D 007F 128
00 022D FFFF 64K-128
00 022E 007F 128
00 022E FFFF 64K-128
Reserved
Reserved
Timer 11
Timer 11
Reserved
Reserved
Timer 12
Timer 12
Reserved
Reserved
Timer 13
Timer 13
Reserved
Reserved
Timer 14
Timer 14
Reserved
Reserved
00 022F 007F
00 022F 00FF
00 022F 017F
00 022F 01FF
00 022F 027F
00 0230 FFFF
00 0231 01FF
00 0231 9FFF
128
Timer 15
Timer 15
128
Timer 16
Timer 16
128
Timer 17
Timer 17
128
Timer 18
Timer 18
128
Timer 19
Timer 19
64K
512
Reserved
Reserved
PLL Controller
Reserved
PLL Controller
Reserved
40K-512
00 0231 BFFF 8K
00 0231 DFFF 8K
HyperLink0 SerDes Config
Reserved
HyperLink0 SerDes Config
Reserved
HyperLink0 SerDes Config
Reserved
00 0231 FFFF
00 0232 3FFF
00 0232 5FFF
00 0232 7FFF
00 0232 8FFF
00 0232 9FFF
8K
16K
8K
8K
4K
4K
10GbE SerDes Config
PCIe0 SerDes Config
SGMII 1 SerDes Config
PCIe1SerDes Config
Reserved
10GbE SerDes Config
PCIe0 SerDes Config
SGMII 1 SerDes Config
PCIe1SerDes Config
Reserved
10GbE SerDes Config
PCIe0 SerDes Config
SGMII 1 SerDes Config
PCIe1SerDes Config
Reserved
DDRA PHY Config
SGMII 0 SerDes Config
Reserved
DDRA PHY Config
SGMII 0 SerDes Config
Reserved
DDRA PHY Config
SGMII 0 SerDes Config
Reserved
00 0232 BFFF 8K
00 0232 CFFF 4K
00 0232 DFFF 4K
Reserved
Reserved
Reserved
00 0232 FFFF
00 0233 03FF
00 0233 07FF
00 0233 FFFF
00 0234 00FF
00 0234 3FFF
00 0234 40FF
00 0234 7FFF
00 0234 80FF
4K
Reserved
Reserved
Reserved
1K
SmartReflex0
Reserved
SmartReflex0
Reserved
SmartReflex0
Reserved
1K
62K
256
16K
256
16K
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 0234 BFFF 16K
00 0234 C0FF 256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 0234 FFFF
00 0235 0FFF
00 0235 FFFF
16K
Reserved
Reserved
Reserved
4K
Power sleep controller (PSC)
Reserved
Power sleep controller (PSC)
Reserved
Power sleep controller (PSC)
Reserved
64K-4K
64
Memory, Interrupts, and EDMA for 66AK2E0x
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Copyright © 2012–2015, Texas Instruments Incorporated
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
1K
ARM VIEW
DSP VIEW
SOC VIEW
00 0236 0000
00 0236 0400
00 0236 8000
00 0236 8400
00 0237 0000
00 0237 0400
00 0237 8000
00 0237 8400
00 0238 0000
00 0238 8000
00 0238 8400
00 0238 8800
00 0238 8C00
00 0238 9000
00 0238 9400
00 0238 9800
00 0238 9C00
00 0238 A000
00 0238 A400
00 0238 A800
00 0240 0000
00 0244 0000
00 0244 4000
00 0245 0000
00 0245 4000
00 0246 0000
00 0246 4000
00 0247 0000
00 0247 4000
00 0248 0000
00 0248 4000
00 0249 0000
00 0249 4000
00 024A 0000
00 024A 4000
00 024B 0000
00 024B 4000
00 024C 0000
00 024C 0200
00 024C 0400
00 024C 0800
00 024D 0000
00 0250 0000
00 0250 0080
00 0250 8000
00 0251 0000
00 0252 0000
00 0252 0400
00 0253 0000
00 0253 0080
00 0236 03FF
00 0236 7FFF
00 0236 83FF
00 0236 FFFF
00 0237 03FF
00 0237 7FFF
00 0237 83FF
00 0237 FFFF
00 0238 03FF
00 0238 83FF
00 0238 87FF
00 0238 8BFF
00 0238 8FFF
00 0238 93FF
00 0238 97FF
00 0238 9BFF
00 0238 9FFF
00 0238 A3FF
00 0238 A7FF
Memory protection unit (MPU) 0
Reserved
Memory protection unit (MPU) 0
Reserved
Memory protection unit (MPU) 0
Reserved
31K
1K
Memory protection unit (MPU) 1
Reserved
Memory protection unit (MPU) 1
Reserved
Memory protection unit (MPU) 1
Reserved
31K
1K
Memory protection unit (MPU) 2
Reserved
Memory protection unit (MPU) 2
Reserved
Memory protection unit (MPU) 2
Reserved
31K
1K
Reserved
Reserved
Reserved
31K
1K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1K
Memory protection unit (MPU) 5
Reserved
Memory protection unit (MPU) 5
Reserved
Memory protection unit (MPU) 5
Reserved
1K
1K
Memory protection unit (MPU) 7
Memory protection unit (MPU) 8
Memory protection unit (MPU) 9
Memory protection unit (MPU) 10
Memory protection unit (MPU) 11
Memory protection unit (MPU) 12
Memory protection unit (MPU) 13
Memory protection unit (MPU) 14
Reserved
Memory protection unit (MPU) 7
Memory protection unit (MPU) 8
Memory protection unit (MPU) 9
Memory protection unit (MPU) 10
Memory protection unit (MPU) 11
Memory protection unit (MPU) 12
Memory protection unit (MPU) 13
Memory protection unit (MPU) 14
Reserved
Memory protection unit (MPU) 7
Memory protection unit (MPU) 8
Memory protection unit (MPU) 9
Memory protection unit (MPU) 10
Memory protection unit (MPU) 11
Memory protection unit (MPU) 12
Memory protection unit (MPU) 13
Memory protection unit (MPU) 14
Reserved
1K
1K
1K
1K
1K
1K
1K
00 023F FFFF 471K
00 0243 FFFF
00 0244 3FFF
00 0244 FFFF
00 0245 3FFF
00 0245 FFFF
00 0246 3FFF
00 0246 FFFF
00 0247 3FFF
00 0247 FFFF
00 0248 3FFF
00 0248 FFFF
00 0249 3FFF
00 0249 FFFF
256K
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
Reserved
Reserved
Reserved
DSP trace formatter 0
Reserved
DSP trace formatter 0
Reserved
DSP trace formatter 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 024A 3FFF 16K
00 024A FFFF 48K
00 024B 3FFF 16K
00 024B FFFF 48K
00 024C 01FF 512
00 024C 03FF 1K-512
00 024C 07FF 1K
00 024C FFFF 62K
00 024F FFFF 192K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 0250 007F
00 0250 7FFF
00 0250 FFFF
00 0251 FFFF
00 0252 03FF
00 0252 FFFF
00 0253 007F
00 0253 03FF
128
Reserved
Reserved
Reserved
32K-128
32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64K
Reserved
Reserved
Reserved
1K
Reserved
Reserved
Reserved
64K-1K
128
Reserved
Reserved
Reserved
I2C0
I2C0
I2C0
1K-128
Reserved
Reserved
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for 66AK2E0x
65
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
128
ARM VIEW
I2C1
DSP VIEW
I2C1
SOC VIEW
I2C1
00 0253 0400
00 0253 0480
00 0253 0800
00 0253 0880
00 0253 0C00
00 0253 0C40
00 0253 1000
00 0253 1040
00 0254 0000
00 0256 0080
00 0258 0000
00 0260 0000
00 0253 047F
00 0253 07FF
00 0253 087F
00 0253 0BFF
00 0253 0C3F
00 0253 FFFF
00 0253 103F
00 0253 FFFF
00 0255 FFFF
00 0257 FFFF
1K-128
128
Reserved
I2C2
Reserved
I2C2
Reserved
I2C2
1K-128
64
Reserved
UART0
Reserved
UART0
Reserved
UART0
1K-64
64
Reserved
UART1
Reserved
UART1
Reserved
UART1
60K-64
128K
128K
Reserved
Reserved
ARM CorePac INTC
Reserved
Reserved
Reserved
ARM CorePac INTC
Reserved
Reserved
Reserved
ARM CorePac INTC
Reserved
00 025F FFFF 512K
00 0260 1FFF
8K
Secondary interrupt controller
(CIC) 0
Secondary interrupt controller
(CIC) 0
Secondary interrupt controller
(CIC) 0
00 0260 2000
00 0260 4000
00 0260 6000
00 0260 8000
00 0260 3FFF
00 0260 5FFF
00 0260 7FFF
00 0260 9FFF
8K
8K
8K
8K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Secondary interrupt controller
(CIC) 2
Secondary interrupt controller
(CIC) 2
Secondary interrupt controller
(CIC) 2
00 0260 A000
00 0260 BF00
00 0260 C000
00 0261 C000
00 0262 0000
00 0262 1000
00 0263 0000
00 0264 0000
00 0264 0800
00 0265 0000
00 0268 0000
00 0270 0000
00 0270 8000
00 0271 0000
00 0272 0000
00 0272 8000
00 0273 0000
00 0274 0000
00 0274 8000
00 0276 0000
00 0260 BEFF 8K-256
00 0260 BFFF 256
00 0261 BFFF 64K
Reserved
Reserved
Reserved
GPIO Config
GPIO Config
GPIO Config
Reserved
Reserved
Reserved
00 0261 FFFF
00 0262 0FFF
00 0262 FFFF
00 0263 FFFF
00 0264 07FF
00 0264 FFFF
00 0267 FFFF
16K
4K
Reserved
Reserved
Reserved
BOOTCFG chip-level registers
Reserved
BOOTCFG chip-level registers
Reserved
BOOTCFG chip-level registers
Reserved
60K
64K
2K
USB 0 PHY CFG
Semaphore Config
Reserved
USB 0 PHY CFG
Semaphore Config
Reserved
USB 0 PHY CFG
Semaphore Config
Reserved
62K
192K
Reserved
Reserved
Reserved
00 026F FFFF 512K
USB 0 MMR CFG
USB 0 MMR CFG
USB 0 MMR CFG
00 0270 7FFF
00 0270 FFFF
00 0271 FFFF
00 0272 7FFF
00 0272 FFFF
00 0273 FFFF
00 0274 7FFF
00 0275 FFFF
00 0276 03FF
32K
32K
64K
32K
32K
64K
32K
96K
1K
EDMA channel controller (TPCC) 0 EDMA channel controller (TPCC) 0 EDMA channel controller (TPCC) 0
EDMA channel controller (TPCC) 4 EDMA channel controller (TPCC) 4 EDMA channel controller (TPCC) 4
Reserved
Reserved
Reserved
EDMA channel controller (TPCC) 1 EDMA channel controller (TPCC) 1 EDMA channel controller (TPCC) 1
EDMA channel controller (TPCC) 3 EDMA channel controller (TPCC) 3 EDMA channel controller (TPCC) 3
Reserved
Reserved
Reserved
EDMA channel controller (TPCC) 2 EDMA channel controller (TPCC) 2 EDMA channel controller (TPCC) 2
Reserved
Reserved
Reserved
EDMA TPCC0 transfer controller
(TPTC) 0
EDMA TPCC0 transfer controller
(TPTC) 0
EDMA TPCC0 transfer controller
(TPTC) 0
00 0276 0400
00 0276 8000
00 0276 7FFF
00 0276 83FF
31K
1K
Reserved
Reserved
Reserved
EDMA TPCC0 transfer controller
(TPTC) 1
EDMA TPCC0 transfer controller
(TPTC) 1
EDMA TPCC0 transfer controller
(TPTC) 1
00 0276 8400
00 0277 0000
00 0276 FFFF
00 0277 03FF
31K
1K
Reserved
Reserved
Reserved
EDMA TPCC1 transfer controller
(TPTC) 0
EDMA TPCC1 transfer controller
(TPTC) 0
EDMA TPCC1 transfer controller
(TPTC) 0
00 0277 0400
00 0277 8000
00 0277 7FFF
00 0277 83FF
31K
1K
Reserved
Reserved
Reserved
EDMA TPCC1 transfer controller
(TPTC) 1
EDMA TPCC1 transfer controller
(TPTC) 1
EDMA TPCC1 transfer controller
(TPTC) 1
00 0278 0000
00 0278 03FF
1K
EDMA TPCC1 transfer controller
(TPTC) 2
EDMA TPCC1 transfer controller
(TPTC) 2
EDMA TPCC1 transfer controller
(TPTC) 2
00 0278 0400
00 0278 8000
00 0278 7FFF
00 0278 83FF
31K
1K
Reserved
Reserved
Reserved
EDMA TPCC1 transfer controller
(TPTC) 3
EDMA TPCC1 transfer controller
(TPTC) 3
EDMA TPCC1 transfer controller
(TPTC) 3
66
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
31K
ARM VIEW
DSP VIEW
SOC VIEW
00 0278 8400
00 0279 0000
00 0278 FFFF
00 0279 03FF
Reserved
Reserved
Reserved
1K
EDMA TPCC2 transfer controller
(TPTC) 0
EDMA TPCC2 transfer controller
(TPTC) 0
EDMA TPCC2 transfer controller
(TPTC) 0
00 0279 0400
00 0279 8000
00 0279 7FFF
00 0279 83FF
31K
1K
Reserved
Reserved
Reserved
EDMA TPCC2 transfer controller
(TPTC) 1
EDMA TPCC2 transfer controller
(TPTC) 1
EDMA TPCC2 transfer controller
(TPTC) 1
00 0279 8400
00 027A 0000
00 0279 FFFF
00 027A 03FF
31K
1K
Reserved
Reserved
Reserved
EDMA TPCC2 transfer controller
(TPTC) 2
EDMA TPCC2 transfer controller
(TPTC) 2
EDMA TPCC2 transfer controller
(TPTC) 2
00 027A 0400
00 027A 8000
00 027A 7FFF 31K
00 027A 83FF 1K
Reserved
Reserved
Reserved
EDMA TPCC2 transfer controller
(TPTC) 3
EDMA TPCC2 transfer controller
(TPTC) 3
EDMA TPCC2 transfer controller
(TPTC) 3
00 027A 8400
00 027B 0000
00 027A FFFF 31K
00 027B 03FF 1K
Reserved
Reserved
Reserved
EDMA TPCC3 transfer controller
(TPTC) 0
EDMA TPCC3 transfer controller
(TPTC) 0
EDMA TPCC3 transfer controller
(TPTC) 0
00 027B 0400
00 027B 8000
00 027B 7FFF 31K
Reserved
Reserved
Reserved
00 027B 83FF
1K
EDMA TPCC3 transfer controller
(TPTC) 1
EDMA TPCC3 transfer controller
(TPTC) 1
EDMA TPCC3 transfer controller
(TPTC) 1
00 027B 8400
00 027B 8800
00 027B 87FF
1K
EDMA TPCC4 transfer controller
(TPTC) 0
EDMA TPCC4 transfer controller
(TPTC) 0
EDMA TPCC4 transfer controller
(TPTC) 0
00 027B 8BFF 1K
EEDMA TPCC4 transfer controller EEDMA TPCC4 transfer controller EEDMA TPCC4 transfer controller
(TPTC) 1
Reserved
Reserved
Reserved
(TPTC) 1
Reserved
Reserved
Reserved
(TPTC) 1
Reserved
Reserved
Reserved
00 027B 8C00 00 027B FFFF 29K
00 027C 0000
00 027C 0400
00 027D 0000
00 027C 03FF 1K
00 027C FFFF 63K
00 027D 3FFF 16K
TI embedded trace buffer (TETB) - TI embedded trace buffer (TETB) - TI embedded trace buffer (TETB) -
CorePac0 CorePac0 CorePac0
00 027D 4000
00 027D 7FFF 16K
TBR_ARM CorePac - Trace buffer TBR_ARM CorePac - Trace buffer TBR_ARM CorePac - Trace buffer
- ARM CorePac
- ARM CorePac
- ARM CorePac
00 027D 8000
00 027E 0000
00 027E 4000
00 027F 0000
00 027F 4000
00 0280 0000
00 0280 4000
00 0281 0000
00 0281 4000
00 0282 0000
00 0282 4000
00 0283 0000
00 0283 4000
00 0284 0000
00 0284 4000
00 0285 0000
00 0285 8000
00 0286 0000
00 0290 0000
00 0294 0000
00 02A0 0000
00 02B0 0000
00 02C0 0000
00 02C1 0000
00 02C2 0000
00 027D FFFF 32K
00 027E 3FFF 16K
00 027E FFFF 48K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 027F 3FFF
16K
Reserved
Reserved
Reserved
00 027F FFFF 48K
Reserved
Reserved
Reserved
00 0280 3FFF
00 0280 FFFF
00 0281 3FFF
00 0281 FFFF
00 0282 3FFF
00 0282 FFFF
00 0283 3FFF
00 0283 FFFF
00 0284 3FFF
00 0284 FFFF
00 0285 7FFF
00 0285 FFFF
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
32K
32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TBR_SYS- Trace buffer - System
Reserved
TBR_SYS- Trace buffer - System
Reserved
TBR_SYS- Trace buffer - System
Reserved
00 028F FFFF 640K
00 0293 FFFF 256K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 029F FFFF 768K
00 02AF FFFF 1M
00 02BF FFFF 1M
00 02C0 FFFF 64K
00 02C1 FFFF 64K
00 02C3 FFFF 128K
Reserved
Reserved
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Navigator configuration
Navigator linking RAM
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
Memory, Interrupts, and EDMA for 66AK2E0x
67
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Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
ARM VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE Config
DBG Config
Reserved
Reserved
Reserved
DSP VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE Config
DBG Config
Reserved
Reserved
Reserved
SOC VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE Config
DBG Config
Reserved
Reserved
Reserved
00 02C4 0000
00 02C6 0000
00 02C8 0000
00 02C9 0000
00 02C5 FFFF 128K
00 02C7 FFFF 128K
00 02C8 FFFF 64K
00 02C9 FFFF 64K
00 02CA 0000 00 02CB FFFF 128K
00 02CC 0000 00 02CD FFFF 128K
00 02CE 0000 00 02EF FFFF 15M-896K
00 02F0 0000
00 0300 0000
00 0310 0000
00 0800 0000
00 0802 0000
00 02FF FFFF 1M
00 030F FFFF 1M
00 07FF FFFF 79M
00 0801 FFFF
128K
00 0BBF FFFF 60M-128K
00 0BC0 0000 00 0BCF FFFF 1M
Multicore shared memory
controller (MSMC) config
Multicore shared memory
controller (MSMC) config
Multicore shared memory
controller (MSMC) config
00 0BD0 0000 00 0BFF FFFF 3M
Reserved
Reserved
Reserved
00 0C00 0000
00 0C20 0000
00 0C60 0000
00 1000 0000
00 1080 0000
00 1088 0000
00 1090 0000
00 10E0 0000
00 10E0 8000
00 10F0 0000
00 10F0 8000
00 1180 0000
00 1190 0000
00 11E0 0000
00 11E0 8000
00 11F0 0000
00 11F0 8000
00 1280 0000
00 1290 0000
00 12E0 0000
00 12E0 8000
00 12F0 0000
00 12F0 8000
00 1380 0000
00 1390 0000
00 13E0 0000
00 13E0 8000
00 13F0 0000
00 13F0 8000
00 1480 0000
00 1490 0000
00 14E0 0000
00 14E0 8000
00 14F0 0000
00 14F0 8000
00 1580 0000
00 0C1F FFFF 2M
00 0C5F FFFF 4M
00 0FFF FFFF 58M
00 107F FFFF 8M
Multicore shared memory (MSM)
Reserved
Multicore shared memory (MSM)
Reserved
Multicore shared memory (MSM)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 1087 FFFF
512K
CorePac0 L2 SRAM
Reserved
CorePac0 L2 SRAM
Reserved
CorePac0 L2 SRAM
Reserved
00 108F FFFF 512K
00 10DF FFFF 5M
00 10E0 7FFF 32K
00 10EF FFFF 1M-32K
Reserved
Reserved
Reserved
CorePac0 L1P SRAM
Reserved
CorePac0 L1P SRAM
Reserved
CorePac0 L1P SRAM
Reserved
00 10F0 7FFF
32K
CorePac0 L1D SRAM
Reserved
CorePac0 L1D SRAM
Reserved
CorePac0 L1D SRAM
Reserved
00 117F FFFF 9M-32K
00 118F FFFF 1M
00 11DF FFFF 5M
00 11E0 7FFF 32K
00 11EF FFFF 1M-32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 11F0 7FFF
32K
Reserved
Reserved
Reserved
00 127F FFFF 9M-32K
00 128F FFFF 1M
00 12DF FFFF 5M
00 12E0 7FFF 32K
00 12EF FFFF 1M-32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 12F0 7FFF
00 137F FFFF 9M-32K
00 1388 FFFF 1M
32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 13DF FFFF 5M
00 13E0 7FFF 32K
00 13EF FFFF 1M-32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 13F0 7FFF
32K
Reserved
Reserved
Reserved
00 147F FFFF 9M-32K
00 148F FFFF 1M
00 14DF FFFF 5M
00 14E0 7FFF 32K
00 14EF FFFF 1M-32K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 14F0 7FFF
32K
Reserved
Reserved
Reserved
00 157F FFFF 9M-32K
00 158F FFFF 1M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
68
Memory, Interrupts, and EDMA for 66AK2E0x
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
ARM VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DSP VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SOC VIEW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 1590 0000
00 15E0 0000
00 15E0 8000
00 15F0 0000
00 15F0 8000
00 1680 0000
00 1690 0000
00 16E0 0000
00 16E0 8000
00 16F0 0000
00 16F0 8000
00 1780 0000
00 1790 0000
00 17E0 0000
00 17E0 8000
00 17F0 0000
00 17F0 8000
00 2000 0000
00 15DF FFFF 5M
00 15E0 7FFF 32K
00 15EF FFFF 1M-32K
00 15F0 7FFF
32K
00 167F FFFF 9M-32K
00 168F FFFF 1M
00 16DF FFFF 5M
00 16E0 7FFF 32K
00 16EF FFFF 1M-32K
00 16F0 7FFF
32K
00 177F FFFF 9M-32K
00 178F FFFF 1M
00 17DF FFFF 5M
00 17E0 7FFF 32K
00 17EF FFFF 1M-32K
00 17F0 7FFF
32K
00 1FFF FFFF 129M-32K
00 200F FFFF 1M
System trace manager (STM)
configuration
System trace manager (STM)
configuration
System trace manager (STM)
configuration
00 2010 0000
00 2020 0000
00 2060 0000
00 201F FFFF 1M
00 205F FFFF 4M
00 206F FFFF 1M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Network Coprocessor 1 (Packet
Accelerator, 1-gigabit Ethernet
switch subsystem and Security
Accelerator)
Network Coprocessor 1 (Packet
Accelerator, 1-gigabit Ethernet
switch subsystem and Security
Accelerator)
Network Coprocessor 1 (Packet
Accelerator, 1-gigabit Ethernet
switch subsystem and Security
Accelerator)
00 2070 0000
00 2078 0000
00 2079 0000
00 2080 0000
00 2090 0000
00 20A0 0000
00 20A4 0000
00 20A5 0000
00 20B0 0000
00 20B4 0000
00 20BF 0000
00 20C0 0000
00 2100 0000
00 2100 0400
00 2100 0600
00 2100 0800
00 2100 0A00
00 2100 0B00
00 2101 0000
00 2101 0200
00 2101 0800
00 2101 0A00
00 2101 1000
00 2102 0000
00 2102 8000
00 2104 0000
00 2140 0000
00 2077 FFFF
00 2078 FFFF
512K
64K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Boot ROM
Reserved
Reserved
Reserved
Reserved
SPI0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Boot ROM
Reserved
Reserved
Reserved
Reserved
SPI0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Boot ROM
Reserved
Reserved
Reserved
Reserved
SPI0
00 207F FFFF 448K
00 208F FFFF 1M
00 209F FFFF 1M
00 20A3 FFFF 256K
00 20A4 FFFF 64K
00 20AF FFFF 704K
00 20B3 FFFF 256K
00 20BE FFFF 704K
00 20BF 01FF 64K
00 20FF FFFF 4M
00 2100 03FF
00 2100 05FF
00 2100 07FF
00 2100 09FF
00 2100 0AFF
00 2100 FFFF
00 2101 01FF
00 2101 07FF
00 2101 09FF
00 2101 0FFF
00 2101 FFFF
00 2102 7FFF
00 2103 FFFF
1K
512
512
SPI1
SPI1
SPI1
512
SPI2
SPI2
SPI2
256
EMIF Config
Reserved
DDR3 EMIF Config
Reserved
Reserved
Reserved
Reserved
PCIe 1 config
Reserved
Reserved
HyperLink0 config
EMIF Config
Reserved
DDR3 EMIF Config
Reserved
Reserved
Reserved
Reserved
PCIe 1 config
Reserved
Reserved
HyperLink0 config
EMIF Config
Reserved
DDR3 EMIF Config
Reserved
Reserved
Reserved
Reserved
PCIe 1 config
Reserved
Reserved
HyperLink0 config
62K-768
512
2K-512
512
2K-512
60K
32K
96K
00 217F FFFF 4M-256K
00 2140 00FF 256
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Memory, Interrupts, and EDMA for 66AK2E0x
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Table 7-1. Device Memory Map Summary 66AK2E0x (continued)
PHYSICAL 40 BIT ADDRESS
START
END
BYTES
ARM VIEW
Reserved
DSP VIEW
Reserved
SOC VIEW
Reserved
00 2140 0100
00 2140 0400
00 2180 0000
00 2180 8000
00 21C0 0000
00 2200 0000
00 22A0 0000
00 22A1 0000
00 22B0 0000
00 22B1 0000
00 22C0 0000
00 22C1 0000
00 22D0 0000
00 22D1 0000
00 22E0 0000
00 22E1 0000
00 22F0 0000
00 22F1 0000
00 2300 0000
00 2301 0000
00 2310 0000
00 2311 0000
00 2320 0000
00 2325 0000
00 23A0 0000
00 23C0 0000
00 2400 0000
00 2500 0000
00 2508 0000
00 2500 0000
00 2800 0000
00 3000 0000
00 3400 0000
00 3800 0000
00 3C00 0000
00 4000 0000
00 5000 0000
00 6000 0000
00 7000 0000
01 0000 0000
01 2101 0000
01 2101 0200
08 0000 0000
0A 0000 0000
00 2140 01FF
256
00 217F FFFF 4M-512
00 2180 7FFF 32K
Reserved
Reserved
Reserved
PCIe 0 config
Reserved
PCIe 0 config
Reserved
PCIe 0 config
Reserved
00 21BF FFFF 4M-32K
00 21FF FFFF 4M
Reserved
Reserved
Reserved
00 229F FFFF 10M
00 22A0 FFFF 64K
00 22AF FFFF 1M-64K
00 22B0 FFFF 64K
00 22BF FFFF 1M-64K
00 22C0 FFFF 64K
00 22CF FFFF 1M-64K
00 22D0 FFFF 64K
00 22DF FFFF 1M-64K
00 22E0 FFFF 64K
00 22EF FFFF 1M-64K
00 22F0 FFFF 64K
00 22FF FFFF 1M-64K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 2300 FFFF
00 230F FFFF 1M-64K
00 2310 FFFF 64K
00 231F FFFF 1M-64K
00 2324 FFFF 384K
64K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00 239F FFFF 8M-384K
00 23BF FFFF 2M
00 23FF FFFF 4M
00 24FF FFFF 16M
Reserved
Reserved
Reserved
Navigator
Navigator
Navigator
Reserved
Reserved
Reserved
NETCP15 config
USB1 MMR config
USB1 PHY config
Reserved
NETCP15 config
USB1 MMR config
USB1 PHY config
Reserved
NETCP15 config
USB1 MMR config
USB1 PHY config
Reserved
00 2507 FFFF
00 2508 FFFF
512K
64K
00 27FF FFFF 48M-576K
00 2FFF FFFF 128M
00 33FF FFFF 64M
00 37FF FFFF 64M
00 3BFF FFFF 64M
00 3FFF FFFF 64M
00 4FFF FFFF 256M
00 5FFF FFFF 256M
00 6FFF FFFF 256M
00 FFFF FFFF 2304M
01 20FF FFFF 528M
Reserved
Reserved
Reserved
EMIF16 CS2
EMIF16 CS3
EMIF16 CS4
EMIF16 CS5
HyperLink0 data
PCIe 0 data
PCIe 1data
Reserved
EMIF16 CS2
EMIF16 CS3
EMIF16 CS4
EMIF16 CS5
HyperLink0 data
PCIe 0 data
PCIe 1data
Reserved
EMIF16 CS2
EMIF16 CS3
EMIF16 CS4
EMIF16 CS5
HyperLink0 data
PCIe 0 data
PCIe 1data
Reserved
Reserved
DDR3 EMIF configuration(1)
Reserved
DDR3 EMIF configuration(2)
Reserved
DDR3 EMIF configuration(3)
01 2101 01FF
512
07 FFFF FFFF 32G-512
09 FFFF FFFF 8G
Reserved
Reserved
Reserved
DDR3 data(3)
DDR3 data
Reserved
DDR3 data(2)
Reserved
FF FFFF FFFF 984G
Reserved
(1) This region is aliased to 00 2101 0000-00 2101 01FF
(2) Access to 40-bit address requires XMC MPAX programmation
(3) Access to 40-bit address requires MSMC MPAX programmation. MPAX from SES port need to re-map the region of 00 2101 0000-00
2101 01FF to this region.
70
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
7.2 Memory Protection Unit (MPU) for 66AK2E0x
CFG (configuration) space of all slave devices on the TeraNet is protected by the MPU. The 66AK2E0x
contains sixteen MPUs of which thirteen MPUs are used:
•
•
MPU0 is used to protect main CORE/3 CFG TeraNet_3P_B (SCR_3P (B)).
MPU1/2/5 are used for QM_SS (one for VBUSM port and one each for the two configuration VBUSP
port).
•
•
•
•
•
•
•
•
MPU3/4/6 are not used.
MPU7 is used for PCIe1.
MPU8 is used for peripherals connected to TeraNet_6P_A (SCR_6P (A)).
MPU9 is used for interrupt controllers connected to TeraNet_3P (SCR_3P).
MPU10 is used for semaphore.
MPU11 is used to protect TeraNet_6P_B (SCR_6P (B)) CPU/6 CFG TeraNet.
MPU12/13/14 are used for SPI0/1/2.
MPU15 is used for USB1.
This section contains MPU register map and details of device-specific MPU registers only. For MPU
features and details of generic MPU registers, see the KeyStone Architecture Memory Protection Unit
(MPU) User's Guide (SPRUGW5).
The following tables show the configuration of each MPU and the memory regions protected by each
MPU.
Table 7-2. MPU0-MPU5 Default Configuration
MPU0
MPU1
MPU2
MPU5
MAIN SCR_3P QM_SS DATA
QM_SS CFG1
PORT
QM_SS CFG2
PORT
SETTING
(B)
PORT
MPU3
MPU4
Default permission
Assume
allowed
Assume allowed
Assume allowed
Reserved
Reserved
Assume
allowed
Number of allowed IDs
supported
16
16
16
16
16
Number of programmable 16
ranges supported
16
16
Compare width
1KB granularity 1KB granularity
1KB granularity
1KB granularity
Table 7-3. MPU6-MPU11 Default Configuration
MPU7
PCIe1
MPU8
EMIF16
MPU9
CIC
MPU10
SM
MPU11
SCR_6P (B)
SETTING
MPU6
Default permission
Reserved
Assume allowed
Assume allowed
Assume
allowed
Assume
allowed
Assume
allowed
Number of allowed IDs
supported
16
16
16
16
16
Number of programmable
ranges supported
16
8
4
2
16
Compare width
1KB granularity
1KB granularity
1KB granularity 1KB granularity 1KB granularity
Table 7-4. MPU12-MPU15 Default Configuration
MPU12
SPI0
MPU13
SPI1
MPU14
SPI2
MPU15
USB1
SETTING
Default permission
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Number of allowed IDs supported
16
2
16
2
16
2
16
8
Number of programmable ranges
supported
Compare width
1KB granularity
1KB granularity
1KB granularity
1KB granularity
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Table 7-5. MPU Memory Regions
MEMORY PROTECTION
Main CFG SCR
QM_SS DATA PORT
QM_SS CFG1 PORT
Reserved
START ADDRESS
0x01D0_0000
0x23A0_0000
0x02A0_0000
N/A
END ADDRESS
0X01E7_FFFF
0x23BF_FFFF
0x02AF_FFFF
N/A
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
MPU6
MPU7
MPU8
MPU9
MPU10
MPU11
MPU12
MPU13
MPU14
MPU15
Reserved
N/A
N/A
QM_SS CFG2 PORT
Reserved
0x02A0_4000
N/A
0x02BF_FFFF
N/A
PCIe1
0x2101_0000
0x20B0_0000
0x0264_0000
0x0260_0000
0x0220_0000
0x2100_0400
0x2100_0400
0x2100_0800
0x2400_0000
0xFFFF_FFFF
0x3FFF_FFFF
0x0264_07FF
0x0260_9FFF
0x03FF_FFFF
0x2100_07FF
0x2100_07FF
0x2100_0AFF
0x2508_FFFF
SPIROM/EMIF16
CIC/AINTC
Semaphore
SCR_6 and CPU/6 CFG SCR
SPI0
SPI1
SPI2
USB1
Table 7-6 shows the unique Master ID assigned to each CorePac and peripherals on the device.
Table 7-6. Master ID Settings
Master ID
66AK2E0x
C66x CorePac0
Reserved
0
1
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
ARM CorePac 0
ARM CorePac1
ARM CorePac 2
ARM CorePac 3
Reserved
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Reserved
Reserved
Reserved
C66x CorePac0 CFG
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EDMA0_TC0 read
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Table 7-6. Master ID Settings (continued)
Master ID
26
66AK2E0x
EDMA0_TC0 write
EDMA0_TC1 read
Hyperlink0
27
28
29
USB1
30
Reserved
31
PCIe0
32
EDMA0_TC1 write
EDMA1_TC0 read
EDMA1_TC0 write
EDMA1_TC1 read
EDMA1_TC1write
EDMA1_TC2 read
EDMA1_TC2 write
EDMA1_TC3 read
EDMA1_TC3 write
EDMA2_TC0 read
EDMA2_TC0 write
EDMA2_TC1 read
EDMA2_TC1 write
EDMA2_TC2 read
EDMA2_TC2 write
EDMA2_TC3 read
EDMA2_TC3 write
EDMA3_TC0 read
EDMA3_TC0 write
EDMA3_TC1 read
Reserved
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
EDMA3_TC1 write
Reserved
54-55
56
USB0
57
Reserved
58
Reserved
59
Reserved
60
Reserved
61
Reserved
62
EDMA3CC0
63
EDMA3CC1
64
EDMA3CC2
65
Reserved
66
Reserved
67
Reserved
68-71
72-75
76-79
80
Queue Manager
NETCP_GLOBAL1
Reserved
TSIP
81
Reserved
82
Reserved
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Table 7-6. Master ID Settings (continued)
Master ID
83
66AK2E0x
Reserved
10GbE
84-87
88-91
92-95
96-99
100-101
102
Reserved
Reserved
Packet DMA MST1
Reserved
PCIe1
103
Reserved
104
Reserved
105
Reserved
106
Reserved
107
DBG_DAP
108-111
112-119
120-139
140
Reserved
NETCP_LOCAL
Reserved
CPT_L2_0
141
Reserved
142
Reserved
143
Reserved
144
Reserved
145
Reserved
146
Reserved
147
Reserved
148
CPT_MSMC0
CPT_MSMC1
CPT_MSMC2
CPT_MSMC3
CPT_DDR3
CPT_SM
149
150
151
152
153
154
CPT_QM_CFG1
CPT_QM_M
CPT_CFG
155
156
157
Reserved
158
Reserved
159
Reserved
160
CPT_QM_CFG2
CPT_PCIe1
Reserved
161
162
163
Reserved
164
CPT_EDMA3CC0_4
CPT_EDMA3CC1_2_3
CPT_CIC
165
166
167
CPT_SPI_ROM_EMIP16
Reserved
168
169
EDMA4_TC0 read
EDMA4_TC0 write
EDMA4_TC1 read
170
171
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Table 7-6. Master ID Settings (continued)
Master ID
172
66AK2E0x
EDMA4_TC1 write
EDMA4_CC_TR
CPT_MSMC7
173
174
175
CPT_MSMC6
176
CPT_MSMC5
177
CPT_MSMC4
178
CPT_NETCP_CFG_MST
Reserved
179
180-183
184-255
NETCP_GLOBAL0
Reserved
Table 7-7 shows the privilege ID of each C66x CorePac and everymastering peripheral. The table also
shows the privilege level (supervisor vs. user), security level (secure vs. non-secure), and access type
(instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular
setting depends on software being executed at the time of the access or the configuration of the master
peripheral.
Table 7-7. Privilege ID Settings
PRIVILEGE ID MASTER
PRIVILEGE LEVEL
ACCESS TYPE
0
1
2
3
4
5
6
7
8
9
C66x CorePac0
User/Supervisor (S/W dependant)
Instruction/Data
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ARM CorePac
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
User/Supervisor (S/W dependent)
User
Instruction/Data
Data
All packet DMA masters
(Both NetCP, Both
QM_CDMA) Both USB
10
11
12
13
14
15
QM_SECOND
PCIe0
User
Data
Data
Data
Data
Data
Data
User/Supervisor
DAP
User/Supervisor (Emulation S/W dependent)
PCIe1
User/Supervisor
User/Supervisor
User
Hyperlink
TSIP
7.2.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device-specific MPU registers. For
Number of Programmable Ranges supported (PROGx_MPSA, PROGxMPEA) refer to the following tables.
7.2.1.1 MPU Register Map
Table 7-8. MPU Registers
OFFSET
0h
NAME
DESCRIPTION
Revision ID
REVID
4h
CONFIG
IRAWSTAT
Configuration
10h
Interrupt raw status/set
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Table 7-8. MPU Registers (continued)
OFFSET
14h
NAME
DESCRIPTION
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
204h
208h
210h
214h
218h
220h
224h
228h
230h
234h
238h
240h
244h
248h
250h
254h
258h
260h
264h
268h
270h
274h
278h
280h
284h
288h
290h
294h
298h
2A0h
2A4h
2A8h
2B0h
2B4h
2B8h
2C0h
2C4h
2C8h
2D0h
2D4h
2Dh
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPAR
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPAR
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPAR
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPAR
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPAR
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPAR
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPAR
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPAR
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPAR
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPAR
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPAR
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPAR
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPAR
PROG13_MPSAR
PROG13_MPEAR
PROG13_MPPAR
PROG14_MPSAR
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Programmable range 13, start address
Programmable range 13, end address
Programmable range 13, memory page protection attributes
Programmable range 14, start address
2E0h
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Table 7-8. MPU Registers (continued)
OFFSET
2E4h
2E8h
2F0h
2F4h
2F8h
300h
NAME
DESCRIPTION
PROG14_MPEAR
PROG14_MPPAR
PROG15_MPSAR
PROG15_MPEAR
PROG15_MPPAR
FLTADDRR
Programmable range 14, end address
Programmable range 14, memory page protection attributes
Programmable range 15, start address
Programmable range 15, end address
Programmable range 15, memory page protection attributes
Fault address
304h
FLTSTAT
Fault status
308h
FLTCLR
Fault clear
7.2.1.2 Device-Specific MPU Registers
7.2.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Table 7-9. Configuration Register Field Descriptions
Bits
Field
Description
31-24
ADDR_WIDTH
Address alignment for range checking
•
•
0 = 1KB alignment
6 = 64KB alignment
23-20
19-16
15-12
11-1
0
NUM_FIXED
NUM_PROG
NUM_AIDS
Number of fixed address ranges
Number of programmable address ranges
Number of supported AIDs
Reserved
Reserved. Always read as 0.
ASSUME_ALLOWED
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines
whether the transfer is assumed to be allowed or not.
•
•
0 = Assume disallowed
1 = Assume allowed
7.2.2 MPU Programmable Range Registers
7.2.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The Programmable Address Start Register holds the start address for the range. This register is writeable
by a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register, then the
register is also writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the
page determines the width of the address field in MPSAR and MPEAR.
Figure 7-1. Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-10. Programmable Range n Start Address Register Field Descriptions
Bit
Field
Description
31-10
9-0
START_ADDR
Reserved
Start address for range n
Reserved. Always read as 0.
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Table 7-11. MPU0-MPU5 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
REGISTER
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
PROG14_MPSAR
PROG15_MPSAR
0x01D0_0000
0x01F0_0000
0x02F0_0000
0x0200_0000
0x020C_0000
0x021C_0000
0x021D_0000
0x021F_0000
0x0234_0000
0x0254_0000
0x0258_0000
0x0000_0000
0x0290_0000
0x01E8_0000
0x01E8_0800
0x01E0_0000
0x23A0_0000
0x23A0_2000
0x023A_6000
0x23A0_6800
0x23A0_7000
0x23A0_8000
0x23A0_C000
0x23A0_E000
0x23A0_F000
0x23A0_F800
0x23A1_0000
0x23A1_C000
0x23A4_0000
0x23A8_0000
0x23B0_0000
0x23B8_0000
0x02A0_0000
0x02A0_2000
0x02A0_6000
0x02A0_6800
0x02A0_7000
0x02A0_8000
0x02A0_C000
0x02A0_E000
0x02A0_F000
0x02A0_F800
0x02A1_0000
0x02A2_0000
0x02A4_0000
0x02A8_0000
0x02AC_0000
0x02AE_0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x02A0_4000
0x02A0_5000
0x02A0_6400
0x02A0_7400
0x02A0_A000
0x02A0_D000
0x02A0_E000
0x02A0_F000
0x02A0_F800
0x02A1_2000
0x02A1_C000
0x02A2_8000
0x02A6_0000
0x02AA_0000
0x02B0_0000
0x02B8_0000
Table 7-12. MPU6-MPU11 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values
REGISTER
MPU6
MPU7
MPU8
MPU9
MPU10
0x0264_0000
0x0000_0000
N/A
MPU11
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
PROG14_MPSAR
PROG15_MPSAR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x2101_0000
0x0000_0000
0x0800_0000
0x1000_0000
0x1800_0000
0x2000_0000
0x2800_0000
0x3000_0000
0x3800_0000
0x4000_0000
0x4800_0000
0x5000_0000
0x5800_0000
0x6000_0000
0x6800_0000
0x7000_0000
0x3000_0000
0x3200_0000
0x3400_0000
0x3600_0000
0x3800_0000
0x3A00_0000
0x3C00_0000
0x2100_0800
N/A
0x0260_0000
0x0260_4000
0x0260_8000
0x0256_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0220_0000
0x0231_0000
0x0231_A000
0x0233_0000
0x0235_0000
0x0263_0000
0x0244_0000
0x024C_0000
0x0250_0000
0x0253_0000
0x0253_0C00
0x0260_B000
0x0262_0000
0x0300_0000
0x021E_0000
0x0268_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 7-13. MPU12-MPU15 Programmable Range n Start Address Register (PROGn_MPSAR) Reset
Values
REGISTER
MPU12
0x2100_0400
0x0000_0000
N/A
MPU13
0x2100_0400
0x0000_0000
N/A
MPU14
0x2100_0800
0x0000_0000
N/A
MPU15
PROG0_MPSAR
PROG1_MPSAR
PROG2_MPSAR
PROG3_MPSAR
PROG4_MPSAR
PROG5_MPSAR
PROG6_MPSAR
PROG7_MPSAR
0x2400_0000
0x2408_0000
0x2410_0000
0x2500_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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Table 7-13. MPU12-MPU15 Programmable Range n Start Address Register (PROGn_MPSAR) Reset
Values (continued)
REGISTER
MPU12
N/A
MPU13
N/A
MPU14
N/A
MPU15
N/A
PROG8_MPSAR
PROG9_MPSAR
PROG10_MPSAR
PROG11_MPSAR
PROG12_MPSAR
PROG13_MPSAR
PROG14_MPSAR
PROG15_MPSAR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7.2.2.2 Programmable Range n - End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by
a supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPAR register then the register
is also writeable only by a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU
number. The page size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page
determines the width of the address field in MPSAR and MPEAR.
Figure 7-2. Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-14. Programmable Range n End Address Register Field Descriptions
Bit
Field
Description
31-10
9-0
END_ADDR
Reserved
End address for range n
Reserved. Always read as 3FFh.
Table 7-15. MPU0-MPU5 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
REGISTER
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
0x01DF_FFFF
0x01F7_FFFF
0x02FF_FFFF
0x020B_FFFF
0x020F_FFFF
0x021C_83FF
0x021D_C0FF
0x021F_C7FF
0x0234_C0FF
0x0255_FFFF
0x025F_FFFF
0x0000_0000
0x029F_FFFF
0x01E8_07FF
0x01E8_43FF
0x01E7_FFFF
0x23A0_1FFF
0x23A0_5FFF
0x23A0_67FF
0x23A0_6FFF
0x23A0_7FFF
0x23A0_BFFF
0x23A0_DFFF
0x23A0_EFFF
0x23A0_F7FF
0x23A0_FFFF
0x23A1_BFFF
0x23A3_FFFF
0x23A7_FFFF
0x23AF_FFFF
0x23B7_FFFF
0x23BF_FFFF
0x02A0_00FF
0x02A0_3FFF
0x02A0_63FF
0x02A0_6FFF
0x02A0_73FF
0x02A0_9FFF
0x02A0_CFFF
0x02A0_E7FF
0x02A0_F7FF
0x02A0_FFFF
0x02A1_1FFF
0x02A2_5FFF
0x02A5_FFFF
0x02A9_FFFF
0x02AD_FFFF
0x02AF_FFFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x02A0_4FFF
0x02A0_5FFF
0x02A0_67FF
0x02A0_7FFF
0x02A0_BFFF
0x02A0_DFFF
0x02A0_E7FF
0x02A0_F7FF
0x02A0_FFFF
0x02A1_7FFF
0x02A1_FFFF
0x02A3_FFFF
0x02A7_FFFF
0x02AB_FFFF
0x02B7_FFFF
0x02BF_FFFF
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Table 7-16. MPU6-MPU11 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
REGISTER
MPU6
MPU7
MPU8
MPU9
MPU10
0x0264_07FF
0x0000_0000
N/A
MPU11
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x2103_FFFF
0x07FF_FFFF
0x0FFF_FFFF
0x17FF_FFFF
0x1FFF_FFFF
0x27FF_FFFF
0x2FFF_FFFF
0x37FF_FFFF
0x3FFF_FFFF
0x47FF_FFFF
0x4FFF_FFFF
0x57FF_FFFF
0x5FFF_FFFF
0x67FF_FFFF
0x6FFF_FFFF
0x7FFF_FFFF
0x31FF_FFFF
0x33FF_FFFF
0x35FF_FFFF
0x37FF_FFFF
0x39FF_FFFF
0x3BFF_FFFF
0x3FFF_FFFF
0x2100_0AFF
N/A
0x0260_1FFF
0x0260_5FFF
0x0260_9FFF
0x0257_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x022F_027F
0x0231_01FF
0x0232_FFFF
0x0233_07FF
0x0235_0FFF
0x0263_FFFF
0x024B_3FFF
0x024C_0BFF
0x0250_7FFF
0x0253_0BFF
0x0253_FFFF
0x0260_BFFF
0x0262_0FFF
0x03FF_FFFF
0x021E_1FFF
0x026F_FFFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 7-17. MPU12-MPU15 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values
REGISTER
MPU12
0x2100_07FF
0x0000_0000
N/A
MPU13
0x2100_07FF
0x0000_0000
N/A
MPU14
0x2100_0AFF
0x0000_0000
N/A
MPU15
PROG0_MPEAR
PROG1_MPEAR
PROG2_MPEAR
PROG3_MPEAR
PROG4_MPEAR
PROG5_MPEAR
PROG6_MPEAR
PROG7_MPEAR
PROG8_MPEAR
PROG9_MPEAR
PROG10_MPEAR
PROG11_MPEAR
PROG12_MPEAR
PROG13_MPEAR
PROG14_MPEAR
PROG15_MPEAR
0x2407_FFFF
0x240F_FFFF
0x24FF_FFFF
0x2507_FFFF
0x2508FFFF
0x0000_0000
0x0000_0000
0x0000_0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7.2.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
The programmable address memory protection page attribute register holds the permissions for the
region. This register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the
register is also writeable only by a non-debug secure entity. The NS bit is writeable only by a non-debug
secure entity. For debug accesses, the register is writeable only when NS = 1 or EMU = 1.
80
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Figure 7-3. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPAR)
31
26
25
24
23
22
21
20
19
18
AID8
R/W
3
17
AID7
R/W
2
16
AID6
R/W
1
15
AID5
R/W
0
Reserved
R
AID15 AID14 AID13 AID12 AID11 AID10 AID9
R/W
9
R/W
R/W
R/W
7
R/W
6
R/W
5
R/W
4
14
13
12
11
10
8
AID4
R/W
AID3
R/W
AID2
R/W
AID1
R/W
AID0
R/W
AIDX
R/W
Reserved
R
NS
R/W
EMU
R/W
SR
R/W
SW
R/W
SX
UR
UW
R/W
UX
R/W
R/W
R/W
Legend: R = Read only; R/W = Read/Write
Table 7-18. Programmable Range n Memory Protection Page Attribute Register Field Descriptions
Bits
31-26
25
Name
Description
Reserved
AID15
Reserved. Always read as 0.
Controls access from ID = 15
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
24
23
22
21
20
19
18
17
16
15
14
13
AID14
AID13
AID12
AID11
AID10
AID9
Controls access from ID = 14
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID = 13
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID = 12
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID = 11
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID = 10
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID = 9
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
AID8
Controls access from ID = 8
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
AID7
Controls access from ID = 7
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
AID6
Controls access from ID = 6
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
AID5
Controls access from ID = 5
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
AID4
Controls access from ID = 4
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
AID3
Controls access from ID = 3
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
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Table 7-18. Programmable Range n Memory Protection Page Attribute Register Field Descriptions
(continued)
Bits
Name
Description
12
AID2
Controls access from ID = 2
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
11
10
9
AID1
AID0
AIDX
Controls access from ID = 1
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID = 0
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
Controls access from ID > 15
•
•
0 = Access is not checked for permissions
1 = Access is checked for permissions
8
7
Reserved
NS
Reserved. Always reads as 0.
Non-secure access permission
•
•
0 = Only secure access allowed
1 = Non-secure access allowed
6
5
4
3
2
1
0
EMU
SR
Emulation (debug) access permission. This bit is ignored if NS = 1
•
•
0 = Debug access not allowed
1 = Debug access allowed
Supervisor Read permission
•
•
0 = Access not allowed
1 = Access allowed
SW
SX
Supervisor Write permission
•
•
0 = Access not allowed
1 = Access allowed
Supervisor Execute permission
•
•
0 = Access not allowed
1 = Access allowed
UR
UW
UX
User Read permission
•
•
0 = Access not allowed
1 = Access allowed
User Write permission
•
•
0 = Access not allowed
1 = Access allowed
User Execute permission
•
•
0 = Access not allowed
1 = Access allowed
Table 7-19. MPU0-MPU5 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values
REGISTER
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
PROG0_MPPAR
PROG1_MPPAR
PROG2_MPPAR
PROG3_MPPAR
PROG4_MPPAR
PROG5_MPPAR
PROG6_MPPAR
PROG7_MPPAR
PROG8_MPPAR
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCA4
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCA4
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCA4
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCF4
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Table 7-19. MPU0-MPU5 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values (continued)
REGISTER
MPU0
MPU1
MPU2
MPU3
MPU4
MPU5
PROG9_MPPAR
PROG10_MPPAR
PROG11_MPPAR
PROG12_MPPAR
PROG13_MPPAR
PROG14_MPPAR
PROG15_MPPAR
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCA4
0x03FF_FCB6
0x03FF_FCA4
0x03FF_FCA4
0x03FF_FCF4
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCA4
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x03FF_FCB4
0x03FF_FCF4
0x03FF_FCF4
0x03FF_FCA4
0x03FF_FCB6
0x03FF_FCA4
0x03FF_FCA4
Table 7-20. MPU6-MPU11 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values
REGISTER
MPU6
MPU7
MPU8
MPU9
MPU10
MPU11
PROG0_MPPAR
PROG1_MPPAR
PROG2_MPPAR
PROG3_MPPAR
PROG4_MPPAR
PROG5_MPPAR
PROG6_MPPAR
PROG7_MPPAR
PROG8_MPPAR
PROG9_MPPAR
PROG10_MPPAR
PROG11_MPPAR
PROG12_MPPAR
PROG13_MPPAR
PROG14_MPPAR
PROG15_MPPAR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x03FF_FCB6
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCBF
0x03FF_FCB6
N/A
0x03FF_FCB6 0x03FF_FCB6
0x03FF_FCB6 0x03FF_FCB6
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6 N/A
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
0x03FF_FCB0
0x03FF_FCB6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table 7-21. MPU12-MPU15 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values
REGISTER
MPU12
MPU13
MPU14
MPU15
PROG0_MPPAR
PROG1_MPPAR
PROG2_MPPAR
PROG3_MPPAR
PROG4_MPPAR
PROG5_MPPAR
PROG6_MPPAR
PROG7_MPPAR
PROG8_MPPAR
PROG9_MPPAR
PROG10_MPPAR
PROG11_MPPAR
PROG12_MPPAR
PROG13_MPPAR
PROG14_MPPAR
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FCB6
N/A
0x03FF_FCBF
N/A
0x03FF_FCBF
N/A
0x03FF_FCBF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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Table 7-21. MPU12-MPU15 Programmable Range n Memory Protection Page Attribute Register
(PROGn_MPPAR) Reset Values (continued)
REGISTER
MPU12
MPU13
MPU14
MPU15
PROG15_MPPAR
N/A
N/A
N/A
N/A
7.3 Interrupts for 66AK2E0x
This section discusses the interrupt sources, controller, and topology. Also provided are tables describing
the interrupt events.
7.3.1 Interrupt Sources and Interrupt Controller
The ARM CorePac interrupts on the 66AK2E0x device are configured through the ARM CorePac Interrupt
Controller. It allows for up to 480 system events to be programmed to any of the ARM core’s IRQ/FIQ
interrupts. In addition error-class events or infrequently used events are also routed through the system
event router to offload the ARM CorePac interrupt controller. This is accomplished through the CorePac
Interrupt Controller block CIC2. Further, CIC2 provides 8 events each to EDMA3CC0, EDMA3CC1,
EDMA3C2, EDMA3CC3, EDMA3CC4, and Hyperlink.
The DSP CorePac interrupts on the 66AK2E0x device are configured through the C66x CorePac Interrupt
Controller. The Interrupt Controller allows for up to 128 system events to be programmed to any of the 12
CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced
emulation logic. The 128 system events consist of both internally-generated events (within the CorePac)
and chip-level events. In addition, error-class events or infrequently used events are also routed through
the system event router to offload the C66x CorePac interrupt selector. This is accomplished through the
CorePac Interuupt Controller blocks, CIC2 and CIC0. This is clocked using CPU/6.
Modules such as CP_MPU, BOOT_CFG, and CP_Tracer have level interrupts and EOI handshaking
interface. The EOI value is 0 for CP_MPU, BOOT_CFG, and CP_Tracer.
Figure 7-4 shows the 66AK2E0x interrupt topology.
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57 Primary Events
C66x
CorePac
474 Events
38 Secondary Events
CIC0
4 Secondary Events
448 Primary Events
32 Secondary Events †
ARM
INTC
56 Primary Events
8 Secondary Events
HyperLink
56 Primary Events
8 Secondary Events †
EDMA3
CC0
479 Events
56 Primary Events
8 Secondary Events †
CIC2
EDMA3
CC1
56 Primary Events
8 Secondary Events †
EDMA3
CC2
56 Primary Events
8 Secondary Events †
EDMA3
CC3
56 Primary Events
8 Secondary Events †
EDMA3
CC4
66AK2E
† ARM shares two secondary events with every instance of EDMA.
Figure 7-4. Interrupt Topology
Table 7-22 shows the mapping of primary events to C66x Corepac
Table 7-22. System Event Mapping — C66x CorePac Primary Interrupts
EVENT NO.
EVENT NAME
EVT0
DESCRIPTION
0
1
2
3
4
5
6
7
8
9
10
Event combiner 0 output
EVT1
Event combiner 1 output
EVT2
Event combiner 2 output
EVT3
Event combiner 3 output
TETB_HFULLINT0
TETB_FULLINT0
TETB_ACQINT0
TETB_OVFLINT0
TETB_UNFLINT0
EMU_DTDMA
MSMC_MPF_ERROR0
TETB is half full
TETB is full
TETB acquisition complete interrupt
TETB overflow condition interrupt
TETB underflow condition interrupt
Emulation interrupt for host scan, DTDMA transfer complete and AET
Memory protection fault indicators for system master PrivID = 0 (C66x
CorePac)
11
12
13
14
15
16
17
18
19
20
Reserved
Reserved
Reserved
Reserved
IDMA0
IDMA channel 0 interrupt
IDMA channel 1 interrupt
Semaphore error interrupt
Semaphore interrupt
IDMA1
SEM_ERR0
SEM_INT0
PCIe_0_INT4
TSIP_RCV_FINT0
TSIP_XMT_FINT0
TSIP_RCV_SFINT0
PCIe0 MSI interrupt
TSIP receive frame interrupt for channel 0
TSIP transmit frame interrupt for channel 0
TSIP receive super frame interrupt for channel 0
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Table 7-22. System Event Mapping — C66x CorePac Primary Interrupts (continued)
EVENT NO.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
EVENT NAME
DESCRIPTION
TSIP_XMT_SFINT0
TSIP_EINT0
TSIP transmit super frame interrupt for channel 0
TSIP error interrupt for channel 0
CIC_0_OUT35
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
Navigator INTD1 accumulated hi-priority interrupt 0
Navigator INTD1 accumulated hi-priority interrupt 8
Navigator INTD1 accumulated hi-priority interrupt 16
Navigator INTD1 accumulated hi-priority interrupt 32
Navigator INTD2 accumulated hi-priority interrupt 0
Navigator INTD2 accumulated hi-priority interrupt 8
Navigator INTD2 accumulated hi-priority interrupt 16
Navigator INTD2 accumulated hi-priority interrupt 32
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
Local timer interrupt low
CIC_2_OUT102
CIC_2_OUT94
CIC_0_OUT68
CIC_0_OUT69
CIC_0_OUT70
CIC_0_OUT71
CIC_0_OUT72
CIC_0_OUT73
CIC_0_OUT16
CIC_0_OUT17
CIC_0_OUT18
CIC_0_OUT19
CIC_0_OUT20
CIC_0_OUT21
CIC_0_OUT22
CIC_0_OUT23
CIC_0_OUT32
CIC_0_OUT33
CIC_0_OUT13
CIC_0_OUT14
CIC_0_OUT15
CIC_0_OUT64
CIC_0_OUT65
CIC_0_OUT66
QMSS_INTD_1_HIGH_0
QMSS_INTD_1_HIGH_8
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_24
QMSS_INTD_2_HIGH_0
QMSS_INTD_2_HIGH_8
QMSS_INTD_2_HIGH_16
QMSS_INTD_2_HIGH_24
CIC_0_OUT0
CIC_0_OUT1
CIC_0_OUT2
CIC_0_OUT3
CIC_0_OUT4
CIC_0_OUT5
CIC_0_OUT6
CIC_0_OUT7
TIMER_0_INTL
TIMER_0_INTH
TIMER_8_INTL
TIMER_8_INTH
Local timer interrupt high
Timer interrupt low
Timer interrupt high
86
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Table 7-22. System Event Mapping — C66x CorePac Primary Interrupts (continued)
EVENT NO.
68
EVENT NAME
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
CIC_0_OUT8
CIC_0_OUT9
CIC_0_OUT10
CIC_0_OUT11
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
GPIO_INT8
DESCRIPTION
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
69
70
71
72
73
74
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
Timer interrupt low
75
76
77
78
79
Timer interrupt high
80
Timer interrupt low
81
Timer interrupt high
82
Local GPIO interrupt
83
GPIO_INT9
Local GPIO interrupt
84
GPIO_INT10
Local GPIO interrupt
85
GPIO_INT11
Local GPIO interrupt
86
GPIO_INT12
Local GPIO interrupt
87
TSIP_RCV_FINT1
TSIP_XMT_FINT1
TSIP_RCV_SFINT1
TSIP_XMT_SFINT1
TSIP_EINT1
TSIP receive frame interrupt for channel 1
TSIP transmit frame interrupt for channel 1
TSIP receive super frame interrupt for channel 1
TSIP transmit super frame interrupt for channel 1
TSIP error interrupt for channel 1
PCIe1 MSI interrupt
88
89
90
91
92
PCIe_1_INT4
TIMER_12_INTL
TIMER_12_INTH
CIC_0_OUT67
INTERR
93
Timer interrupt low
94
Timer interrupt high
95
C66x CorePac Interrupt Controller output
Dropped C66x CorePac interrupt event
Invalid IDMA parameters
96
97
EMC_IDMAERR
Reserved
98
Reserved
99
CIC_2_OUT68
EFIINT0
C66x CorePac Interrupt Controller output
EFI interrupt from side A
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
EFIINT1
EFI interrupt from side B
GPIO_INT13
Local GPIO interrupt
GPIO_INT14
Local GPIO interrupt
GPIO_INT15
Local GPIO interrupt
IPC_GR0
Boot CFG
GPIO_INT0
GPIO interrupt
CIC_0_OUT12
CIC_0_OUT34
CIC_2_OUT13
MDMAERREVT
Reserved
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
C66x CorePac Interrupt Controller output
VbusM error event
Reserved
EDMACC_0_4_TC_AET_INT
PMC_ED
EDMA3CC0 AET event
Single bit error detected during DMA read
EDMA3CC1_2 AET event
EDMACC_1_TC_AET_INT
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Table 7-22. System Event Mapping — C66x CorePac Primary Interrupts (continued)
EVENT NO.
115
EVENT NAME
EDMACC_1_3_TC_AET_INT
UMC_ED1
DESCRIPTION
EDMA3CC3_4 AET event
Corrected bit error detected
Uncorrected bit error detected
Power down sleep interrupt
SYS CPU MP fault event
CPU memory protection fault
DMA memory protection fault
CPU memory protection fault
DMA memory protection fault
CPU memory protection fault
DMA memory protection fault
CPU memory protection fault
Bus error interrupt
116
117
UMC_ED2
118
PDC_INT
119
SYS_CMPA
120
PMC_CMPA
PMC_DMPA
DMC_CMPA
DMC_DMPA
UMC_CMPA
UMC_DMPA
EMC_CMPA
EMC_BUSERR
121
122
123
124
125
126
127
Table 7-23 lists the ARM CorePac event inputs
Table 7-23. System Event Mapping — ARM CorePac Interrupts
EVENT NO.
EVENT NAME
RSTMUX_INT8
RSTMUX_INT9
RSTMUX_INT10
RSTMUX_INT11
IPC_GR8
DESCRIPTION
0
Boot config watchdog timer expiration (timer 16) event for ARM core 0
Boot config watchdog timer expiration (timer 17) event for ARM core 1
Boot config watchdog timer expiration (timer 18) event for ARM core 2
Boot config watchdog timer expiration (timer 19) event for ARM core 3
Boot config IPCG
1
2
3
4
5
IPC_GR9
Boot config IPCG
6
IPC_GR10
Boot config IPCG
7
IPC_GR11
Boot config IPCG
8
SEM_INT8
Semaphore interrupt
9
SEM_INT9
Semaphore interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SEM_INT10
Semaphore interrupt
SEM_INT11
Semaphore interrupt
SEM_ERR8
Semaphore error interrupt
SEM_ERR9
Semaphore error interrupt
SEM_ERR10
Semaphore error interrupt
SEM_ERR11
Semaphore error interrupt
MSMC_MPF_ERROR8
MSMC_MPF_ERROR9
MSMC_MPF_ERROR10
MSMC_MPF_ERROR11
ARM_NPMUIRQ0
ARM_NPMUIRQ1
ARM_NPMUIRQ2
ARM_NPMUIRQ3
ARM_NINTERRIRQ
ARM_NAXIERRIRQ
PCIE_0_INT0
Memory protection fault indicators for system master PrivID = 8
Memory protection fault indicators for system master PrivID = 9
Memory protection fault indicators for system master PrivID = 10
Memory protection fault indicators for system master PrivID = 11
ARM performance monitoring unit interrupt request
ARM performance monitoring unit interrupt request
ARM performance monitoring unit interrupt request
ARM performance monitoring unit interrupt request
ARM internal memory ECC error interrupt request
ARM bus error interrupt request
PCIE0 legacy INTA interrupt
PCIE_0_INT1
PCIE0 legacy INTB interrupt
PCIE_0_INT2
PCIE0 legacy INTC interrupt
PCIE_0_INT3
PCIE0 legacy INTD interrupt
88
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
EVENT NAME
DESCRIPTION
PCIE_0_INT4
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 error interrupt
PCIE_0_INT5
PCIE_0_INT6
PCIE_0_INT7
PCIE_0_INT8
PCIE_0_INT9
PCIE_0_INT10
PCIE_0_INT11
PCIE_0_INT12
PCIE_0_INT13
PCIE0 power management interrupt
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
QMSS_QUE_PEND_528
QMSS_QUE_PEND_529
QMSS_QUE_PEND_530
QMSS_QUE_PEND_531
QMSS_QUE_PEND_532
QMSS_QUE_PEND_533
QMSS_QUE_PEND_534
QMSS_QUE_PEND_535
QMSS_QUE_PEND_536
QMSS_QUE_PEND_537
QMSS_QUE_PEND_538
QMSS_QUE_PEND_539
QMSS_QUE_PEND_540
QMSS_QUE_PEND_541
QMSS_QUE_PEND_542
QMSS_QUE_PEND_543
QMSS_QUE_PEND_544
QMSS_QUE_PEND_545
QMSS_QUE_PEND_546
QMSS_QUE_PEND_547
QMSS_QUE_PEND_548
QMSS_QUE_PEND_549
QMSS_QUE_PEND_550
QMSS_QUE_PEND_551
QMSS_QUE_PEND_552
QMSS_QUE_PEND_553
QMSS_QUE_PEND_554
QMSS_QUE_PEND_555
QMSS_QUE_PEND_556
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
77
EVENT NAME
DESCRIPTION
QMSS_QUE_PEND_557
QMSS_QUE_PEND_558
QMSS_QUE_PEND_559
TIMER_0_INTL
TIMER_0_INTH
USIM_PONIRQ
USIM_RREQ
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Timer interrupt low
78
79
80
81
Timer interrupt high
82
USIM interrupt
83
USIM read DMA event
84
USIM_WREQ
USIM write DMA event
85
TSIP_RCV_FINT0
TSIP_XMT_FINT0
TSIP_RCV_SFINT0
TSIP_XMT_SFINT0
TSIP_EINT0
TSIP receive frame interrupt for channel 0
TSIP transmit frame interrupt for channel 0
TSIP receive super frame interrupt for channel 0
TSIP transmit super frame interrupt for channel 0
TSIP error interrupt for channel 0
TSIP receive frame interrupt for channel 1
TSIP transmit frame interrupt for channel 1
TSIP receive super frame interrupt for channel 1
TSIP transmit super frame interrupt for channel 1
TSIP error interrupt for channel 1
Reserved
86
87
88
89
90
TSIP_RCV_FINT1
TSIP_XMT_FINT1
TSIP_RCV_SFINT1
TSIP_XMT_SFINT1
TSIP_EINT1
91
92
93
94
95
Reserved
96
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
TIMER_18_INTL
TIMER_18_INTH
TIMER_19_INTL
TIMER_19_INTH
GPIO_INT0
Timer interrupt low
97
Timer interrupt high
98
Timer interrupt low
99
Timer interrupt high
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
GPIO interrupt
GPIO_INT1
GPIO interrupt
GPIO_INT2
GPIO interrupt
GPIO_INT3
GPIO interrupt
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
EVENT NAME
GPIO_INT4
DESCRIPTION
GPIO interrupt
GPIO_INT5
GPIO interrupt
GPIO_INT6
GPIO interrupt
GPIO_INT7
GPIO interrupt
GPIO_INT8
GPIO interrupt
GPIO_INT9
GPIO interrupt
GPIO_INT10
GPIO_INT11
GPIO_INT12
GPIO_INT13
GPIO_INT14
GPIO_INT15
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
USB_0_INT00
USB_0_INT01
USB_0_INT02
USB_0_INT03
USB_0_INT04
USB_0_INT05
USB_0_INT06
USB_0_INT07
USB_0_INT08
USB_0_INT09
USB_0_INT10
USB_0_INT11
USB_0_INT12
USB_0_INT13
USB_0_INT14
USB_0_INT15
USB_0_OABSINT
USB_0_MISCINT
MSMC_DEDC_CERROR
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
USB 0 event ring 0 interrupt
USB 0 event ring 1 interrupt
USB 0 event ring 2 interrupt
USB 0 event ring 3 interrupt
USB 0 event ring 4 interrupt
USB 0 event ring 5 interrupt
USB 0 event ring 6 interrupt
USB 0 event ring 7 interrupt
USB 0 event ring 8 interrupt
USB 0 event ring 9 interrupt
USB 0 event ring 10 interrupt
USB 0 event ring 11 interrupt
USB 0 event ring 12 interrupt
USB 0 event ring 13 interrupt
USB 0 event ring 14 interrupt
USB 0 event ring 15 interrupt
USB 0 OABS interrupt
USB0_misc_int
MSMC interrupt
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
EVENT NAME
DESCRIPTION
MSMC_DEDC_NC_ERROR
MSMC_DEDC_SCRUB_CERROR
MSMC_DEDC_SCRUB_NC_ERROR
Reserved
MSMC interrupt
MSMC interrupt
MSMC interrupt
Reserved
Reserved
Reserved
QMSS1_ECC_INTR
Navigator ECC error interrupt
Navigator interrupt for Packet DMA starvation
Navigator interrupt for Packet DMA starvation
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator interrupt
QMSS_INTD_1_PKTDMA_0
QMSS_INTD_1_PKTDMA_1
QMSS_INTD_1_HIGH_0
QMSS_INTD_1_HIGH_1
QMSS_INTD_1_HIGH_2
QMSS_INTD_1_HIGH_3
QMSS_INTD_1_HIGH_4
QMSS_INTD_1_HIGH_5
QMSS_INTD_1_HIGH_6
QMSS_INTD_1_HIGH_7
QMSS_INTD_1_HIGH_8
QMSS_INTD_1_HIGH_9
QMSS_INTD_1_HIGH_10
QMSS_INTD_1_HIGH_11
QMSS_INTD_1_HIGH_12
QMSS_INTD_1_HIGH_13
QMSS_INTD_1_HIGH_14
QMSS_INTD_1_HIGH_15
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_17
QMSS_INTD_1_HIGH_18
QMSS_INTD_1_HIGH_19
QMSS_INTD_1_HIGH_20
QMSS_INTD_1_HIGH_21
QMSS_INTD_1_HIGH_22
QMSS_INTD_1_HIGH_23
QMSS_INTD_1_HIGH_24
QMSS_INTD_1_HIGH_25
QMSS_INTD_1_HIGH_26
QMSS_INTD_1_HIGH_27
QMSS_INTD_1_HIGH_28
QMSS_INTD_1_HIGH_29
QMSS_INTD_1_HIGH_30
QMSS_INTD_1_HIGH_31
QMSS_INTD_1_LOW_0
QMSS_INTD_1_LOW_1
QMSS_INTD_1_LOW_2
QMSS_INTD_1_LOW_3
QMSS_INTD_1_LOW_4
QMSS_INTD_1_LOW_5
QMSS_INTD_1_LOW_6
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
EVENT NAME
DESCRIPTION
QMSS_INTD_1_LOW_7
QMSS_INTD_1_LOW_8
QMSS_INTD_1_LOW_9
QMSS_INTD_1_LOW_10
QMSS_INTD_1_LOW_11
QMSS_INTD_1_LOW_12
QMSS_INTD_1_LOW_13
QMSS_INTD_1_LOW_14
QMSS_INTD_1_LOW_15
Reserved
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Reserved
Reserved
Reserved
QMSS_INTD_2_HIGH_0
QMSS_INTD_2_HIGH_1
QMSS_INTD_2_HIGH_2
QMSS_INTD_2_HIGH_3
QMSS_INTD_2_HIGH_4
QMSS_INTD_2_HIGH_5
QMSS_INTD_2_HIGH_6
QMSS_INTD_2_HIGH_7
QMSS_INTD_2_HIGH_8
QMSS_INTD_2_HIGH_9
QMSS_INTD_2_HIGH_10
QMSS_INTD_2_HIGH_11
QMSS_INTD_2_HIGH_12
QMSS_INTD_2_HIGH_13
QMSS_INTD_2_HIGH_14
QMSS_INTD_2_HIGH_15
QMSS_INTD_2_HIGH_16
QMSS_INTD_2_HIGH_17
QMSS_INTD_2_HIGH_18
QMSS_INTD_2_HIGH_19
QMSS_INTD_2_HIGH_20
QMSS_INTD_2_HIGH_21
QMSS_INTD_2_HIGH_22
QMSS_INTD_2_HIGH_23
QMSS_INTD_2_HIGH_24
QMSS_INTD_2_HIGH_25
QMSS_INTD_2_HIGH_26
QMSS_INTD_2_HIGH_27
QMSS_INTD_2_HIGH_28
QMSS_INTD_2_HIGH_29
QMSS_INTD_2_HIGH_30
QMSS_INTD_2_HIGH_31
QMSS_INTD_2_LOW_0
QMSS_INTD_2_LOW_1
QMSS_INTD_2_LOW_2
QMSS_INTD_2_LOW_3
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
EVENT NAME
DESCRIPTION
QMSS_INTD_2_LOW_4
QMSS_INTD_2_LOW_5
QMSS_INTD_2_LOW_6
QMSS_INTD_2_LOW_7
QMSS_INTD_2_LOW_8
QMSS_INTD_2_LOW_9
QMSS_INTD_2_LOW_10
QMSS_INTD_2_LOW_11
QMSS_INTD_2_LOW_12
QMSS_INTD_2_LOW_13
QMSS_INTD_2_LOW_14
QMSS_INTD_2_LOW_15
UART_0_UARTINT
UART_0_URXEVT
UART_0_UTXEVT
UART_1_UARTINT
UART_1_URXEVT
UART_1_UTXEVT
I2C_0_INT
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
UART0 interrupt
UART0 receive event
UART0 transmit event
UART1 interrupt
UART1 receive event
UART1 transmit event
I2C interrupt
I2C_0_REVT
I2C receive event
I2C_0_XEVT
I2C transmit event
I2C_1_INT
I2C interrupt
I2C_1_REVT
I2C receive event
I2C_1_XEVT
I2C transmit event
I2C_2_INT
I2C interrupt
I2C_2_REVT
I2C receive event
I2C_2_XEVT
I2C transmit event
SPI_0_INT0
SPI interrupt
SPI_0_INT1
SPI interrupt
SPI_0_XEVT
SPI DMA TX event
SPI_0_REVT
SPI DMA RX event
SPI_1_INT0
SPI interrupt
SPI_1_INT1
SPI interrupt
SPI_1_XEVT
SPI DMA TX event
SPI_1_REVT
SPI DMA RX event
SPI_2_INT0
SPI interrupt
SPI_2_INT1
SPI interrupt
SPI_2_XEVT
SPI DMA TX event
SPI_2_REVT
SPI DMA RX event
DBGTBR_DMAINT
DBGTBR_ACQCOMP
ARM_TBR_DMA
ARM_TBR_ACQ
NETCP_MDIO_LINK_INT0
NETCP_MDIO_LINK_INT1
NETCP_MDIO_USER_INT0
NETCP_MDIO_USER_INT1
Debug trace buffer (TBR) DMA event
Debug Trace buffer (TBR) acquisition has been completed
ARM Trace Buffer (TBR) DMA event
ARM Trace Buffer (TBR) Acquisition has been completed
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
Packet Accelerator 1subsystem MDIO interrupt
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
EVENT NAME
DESCRIPTION
NETCP_MISC_INT
Packet Accelerator 1subsystem MDIO interrupt
Reserved
EDMACC_0_GINT
EDMA3CC0 global completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC1 global completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC2 global completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC3 global completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC4 global completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMACC_0_TC_0_INT
EDMACC_0_TC_1_INT
EDMACC_0_TC_2_INT
EDMACC_0_TC_3_INT
EDMACC_0_TC_4_INT
EDMACC_0_TC_5_INT
EDMACC_0_TC_6_INT
EDMACC_0_TC_7_INT
EDMACC_1_GINT
EDMACC_1_TC_0_INT
EDMACC_1_TC_1_INT
EDMACC_1_TC_2_INT
EDMACC_1_TC_3_INT
EDMACC_1_TC_4_INT
EDMACC_1_TC_5_INT
EDMACC_1_TC_6_INT
EDMACC_1_TC_7_INT
EDMACC_2_GINT
EDMACC_2_TC_0_INT
EDMACC_2_TC_1_INT
EDMACC_2_TC_2_INT
EDMACC_2_TC_3_INT
EDMACC_2_TC_4_INT
EDMACC_2_TC_5_INT
EDMACC_2_TC_6_INT
EDMACC_2_TC_7_INT
EDMACC_3_GINT
EDMACC_3_TC_0_INT
EDMACC_3_TC_1_INT
EDMACC_3_TC_2_INT
EDMACC_3_TC_3_INT
EDMACC_3_TC_4_INT
EDMACC_3_TC_5_INT
EDMACC_3_TC_6_INT
EDMACC_3_TC_7_INT
EDMACC_4_GINT
EDMACC_4_TC_0_INT
EDMACC_4_TC_1_INT
EDMACC_4_TC_2_INT
EDMACC_4_TC_3_INT
EDMACC_4_TC_4_INT
EDMACC_4_TC_5_INT
EDMACC_4_TC_6_INT
EDMACC_4_TC_7_INT
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
359
EVENT NAME
DESCRIPTION
SR_0_PO_VCON_SMPSERR_INT
SR_0_SMARTREFLEX_INTREQ0
SR_0_SMARTREFLEX_INTREQ1
SR_0_SMARTREFLEX_INTREQ2
SR_0_SMARTREFLEX_INTREQ3
SR_0_VPNOSMPSACK
SmartReflex SMPS error interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
360
361
362
363
364
SmartReflex VPVOLTUPDATE has been asserted, but SMPS has not been
responded to in a defined time interval
365
SR_0_VPEQVALUE
SmartReflex SRSINTERUPT is asserted, but the new voltage is not different
from the current SMPS voltage
366
367
368
369
SR_0_VPMAXVDD
SmartReflex. The new voltage required is equal to or greater than MaxVdd
SmartReflex. The new voltage required is equal to or less than MinVdd
SmartReflex indicating that the FSM of voltage processor is in idle
SR_0_VPMINVDD
SR_0_VPINIDLE
SR_0_VPOPPCHANGEDONE
SmartReflex indicating that the average frequency error is within the desired
limit
370
SR_0_VPSMPSACK
SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a
defined time interval
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
SR_0_SR_TEMPSENSOR
SR_0_SR_TIMERINT
PCIE_1_INT0
PCIE_1_INT1
PCIE_1_INT2
PCIE_1_INT3
PCIE_1_INT4
PCIE_1_INT5
PCIE_1_INT6
PCIE_1_INT7
PCIE_1_INT8
PCIE_1_INT9
PCIE_1_INT10
PCIE_1_INT11
PCIE_1_INT12
PCIE_1_INT13
HYPERLINK_0_INT
DDR3_ERR
SmartReflex temperature threshold crossing interrupt
SmartReflex internal timer expiration interrupt
PCIE1 legacy INTA interrupt
PCIE1 legacy INTB interrupt
PCIE1 legacy INTC interrupt
PCIE1 legacy INTD interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 error interrupt
PCIE1 power management interrupt
HyperLink interrupt
DDR3 interrupt
ARM_NCTIIRQ0
ARM_NCTIIRQ1
ARM_NCTIIRQ2
ARM_NCTIIRQ3
Reserved
ARM cross trigger (CTI) IRQ interrupt
ARM cross trigger (CTI) IRQ interrupt
ARM cross trigger (CTI) IRQ interrupt
ARM cross trigger (CTI) IRQ interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE_LINK_INT0
10 Gigabit Ethernet subsystem MDIO interrupt
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
EVENT NAME
DESCRIPTION
10GbE_USER_INT0
10GbE_LINK_INT1
10GbE_USER_INT1
10GbE_MISC_INT
10GbE_INT_PKTDMA_0
Reserved
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet Packet DMA starvation interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
USB_1_INT00
USB 1 event ring 0 interrupt
USB 1 event ring 1 interrupt
USB 1 event ring 2 interrupt
USB 1 event ring 3 interrupt
USB 1 event ring 4 interrupt
USB 1 event ring 5 interrupt
USB 1 event ring 6 interrupt
USB 1 event ring 7 interrupt
USB 1 event ring 8 interrupt
USB 1 event ring 9 interrupt
USB 1 event ring 10 interrupt
USB 1 event ring 11 interrupt
USB 1 event ring 12 interrupt
USB 1 event ring 13 interrupt
USB 1 event ring 14 interrupt
USB 1 event ring 15 interrupt
USB 1 OABS interrupt
USB_1_INT01
USB_1_INT02
USB_1_INT03
USB_1_INT04
USB_1_INT05
USB_1_INT06
USB_1_INT07
USB_1_INT08
USB_1_INT09
USB_1_INT10
USB_1_INT11
USB_1_INT12
USB_1_INT13
USB_1_INT14
USB_1_INT15
USB_1_OABSINT
USB_1_MISCINT
NETCP_GLOBAL_STARVE
NETCP_LOCAL_STARVE
NETCP_PA_ECC_INT
NETCP_SA_ECC_INT
NETCP_SWITCH_ECC_INT
NETCP_SWITCH_STAT_INT0
NETCP_SWITCH_STAT_INT1
NETCP_SWITCH_STAT_INT2
NETCP_SWITCH_STAT_INT3
NETCP_SWITCH_STAT_INT4
NETCP_SWITCH_STAT_INT5
NETCP_SWITCH_STAT_INT6
NETCP_SWITCH_STAT_INT7
NETCP_SWITCH_INT
NETCP_SWITCH_STAT_INT0
Reserved
USB 1 miscellaneous interrupt
NETCP GLOBAL interrupt
NETCP LOCAL interrupt
NETCP PA ECC interrupt
NETCP SA ECC interrupt
NETCP SWITCH ECC interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH interrupt
NETCP SWITCH STAT interrupt
Reserved
CIC_2_OUT29
CIC2 interrupt
CIC_2_OUT30
CIC2 interrupt
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Table 7-23. System Event Mapping — ARM CorePac Interrupts (continued)
EVENT NO.
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
EVENT NAME
CIC_2_OUT31
CIC_2_OUT32
CIC_2_OUT33
CIC_2_OUT34
CIC_2_OUT35
CIC_2_OUT36
CIC_2_OUT37
CIC_2_OUT38
CIC_2_OUT39
CIC_2_OUT40
CIC_2_OUT41
CIC_2_OUT42
CIC_2_OUT43
CIC_2_OUT44
CIC_2_OUT45
CIC_2_OUT46
CIC_2_OUT47
CIC_2_OUT18
CIC_2_OUT19
CIC_2_OUT22
CIC_2_OUT23
CIC_2_OUT50
CIC_2_OUT51
CIC_2_OUT66
CIC_2_OUT67
CIC_2_OUT88
CIC_2_OUT89
CIC_2_OUT90
CIC_2_OUT91
CIC_2_OUT92
DESCRIPTION
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
CIC2 interrupt
Table 7-24 lists the CIC0 event inputs.
Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts
EVENT NO.
EVENT NAME
DESCRIPTION
0
EDMACC_1_ERRINT
EDMACC_1_MPINT
EDMA3CC1 error interrupt
1
EDMA3CC1 memory protection interrupt
EDMA3CC1 TPTC0 error interrupt
EDMA3CC1 TPTC1 error interrupt
EDMA3CC1 TPTC2 error interrupt
EDMA3CC1 TPTC3 error interrupt
EDMA3CC1 GINT
2
EDMACC_1_TC_0_ERRINT
EDMACC_1_TC_1_ERRINT
EDMACC_1_TC_2_ERRINT
EDMACC_1_TC_3_ERRINT
EDMACC_1_GINT
3
4
5
6
7
Reserved
Reserved
8
EDMACC_1_TC_0_INT
EDMACC_1_TC_1_INT
EDMACC_1_TC_2_INT
EDMACC_1_TC_3_INT
EDMACC_1_TC_4_INT
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
9
10
11
12
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
EVENT NAME
DESCRIPTION
EDMACC_1_TC_5_INT
EDMACC_1_TC_6_INT
EDMACC_1_TC_7_INT
EDMACC_2_ERRINT
EDMACC_2_MPINT
EDMACC_2_TC_0_ERRINT
EDMACC_2_TC_1_ERRINT
EDMACC_2_TC_2_ERRINT
EDMACC_2_TC_3_ERRINT
EDMACC_2_GINT
Reserved
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC2 error interrupt
EDMA3CC2 memory protection interrupt
EDMA3CC2 TPTC0 error interrupt
EDMA3CC2 TPTC1 error interrupt
EDMA3CC2 TPTC2 error interrupt
EDMA3CC2 TPTC3 error interrupt
EDMA3CC2 GINT
Reserved
EDMACC_2_TC_0_INT
EDMACC_2_TC_1_INT
EDMACC_2_TC_2_INT
EDMACC_2_TC_3_INT
EDMACC_2_TC_4_INT
EDMACC_2_TC_5_INT
EDMACC_2_TC_6_INT
EDMACC_2_TC_7_INT
EDMACC_0_ERRINT
EDMACC_0_MPINT
EDMACC_0_TC_0_ERRINT
EDMACC_0_TC_1_ERRINT
EDMACC_0_GINT
Reserved
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC0 error interrupt
EDMA3CC0 memory protection interrupt
EDMA3CC0 TPTC0 error interrupt
EDMA3CC0 TPTC1 error interrupt
EDMA3CC0 global completion interrupt
Reserved
EDMACC_0_TC_0_INT
EDMACC_0_TC_1_INT
EDMACC_0_TC_2_INT
EDMACC_0_TC_3_INT
EDMACC_0_TC_4_INT
EDMACC_0_TC_5_INT
EDMACC_0_TC_6_INT
EDMACC_0_TC_7_INT
Reserved
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
Reserved
QMSS_QUE_PEND_652
PCIE_0_INT12
Navigator transmit queue pending event for indicated queue
PCIE0 protocol error interrupt
PCIE_0_INT13
PCIE0 power management interrupt
PCIE0 legacy INTA interrupt
PCIE_0_INT0
PCIE_0_INT1
PCIE0 legacy INTB interrupt
PCIE_0_INT2
PCIE0 legacy INTC interrupt
PCIE_0_INT3
PCIE0 legacy INTD interrupt
SPI_0_INT0
SPI0 interrupt0
SPI_0_INT1
SPI0 interrupt1
SPI_0_XEVT
SPI0 transmit event
SPI_0_REVT
SPI0 receive event
I2C_0_INT
I2C0 interrupt
I2C_0_REVT
I2C0 receive event
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
60
EVENT NAME
DESCRIPTION
I2C_0_XEVT
I2C0 transmit event
Reserved
61
Reserved
62
Reserved
Reserved
63
DBGTBR_DMAINT
MPU_12_INT
Debug trace buffer (TBR) DMA event
64
MPU12 addressing violation interrupt and protection violation interrupt.
Debug trace buffer (TBR) acquisition has been completed
MPU13 addressing violation interrupt and protection violation interrupt.
MPU14 addressing violation interrupt and protection violation interrupt.
Packet Accelerator 0 subsystem MDIO interrupt
65
DBGTBR_ACQCOMP
MPU_13_INT
66
67
MPU_14_INT
68
NETCP_MDIO_LINK_INT0
NETCP_MDIO_LINK_INT1
NETCP_MDIO_USER_INT0
NETCP_MDIO_USER_INT1
NETCP_MISC_INT
TRACER_CORE_0_INT
Reserved
69
Packet Accelerator 0 subsystem MDIO interrupt
70
Packet Accelerator 0 subsystem MDIO interrupt
71
Packet Accelerator 0 subsystem MDIO interrupt
72
Packet Accelerator 0 subsystem misc interrupt
73
Tracer sliding time window interrupt for DSP0 L2
74
Reserved
75
Reserved
Reserved
76
Reserved
Reserved
77
TRACER_DDR_INT
TRACER_MSMC_0_INT
TRACER_MSMC_1_INT
TRACER_MSMC_2_INT
TRACER_MSMC_3_INT
TRACER_CFG_INT
TRACER_QMSS_QM_CFG1_INT
TRACER_QMSS_DMA_INT
TRACER_SEM_INT
PSC_ALLINT
Tracer sliding time window interrupt for MSMC-DDR3
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for Navigator CFG1 slave port
Tracer sliding time window interrupt for Navigator VBUSM slave port
Tracer sliding time window interrupt for Semaphore
Power & Sleep Controller interrupt
78
79
80
81
82
83
84
85
86
87
MSMC_SCRUB_CERROR
BOOTCFG_INT
Correctable (1-bit) soft error detected during scrub cycle
Chip-level MMR Error Register
88
89
SR_0_PO_VCON_SMPSERR_INT
MPU_0_INT
SmartReflex SMPS error interrupt
90
MPU0 addressing violation interrupt and protection violation interrupt.
Navigator transmit queue pending event for indicated queue
MPU1 addressing violation interrupt and protection violation interrupt.
Navigator transmit queue pending event for indicated queue
MPU2 addressing violation interrupt and protection violation interrupt.
Navigator transmit queue pending event for indicated queue
MPU3 addressing violation interrupt and protection violation interrupt.
Navigator transmit queue pending event for indicated queue
Correctable (1-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected during scrub cycle
Memory protection fault indicators for system master PrivID = 0
Memory protection fault indicators for system master PrivID = 8
Memory protection fault indicators for system master PrivID = 9
Memory protection fault indicators for system master PrivID = 10
Memory protection fault indicators for system master PrivID = 11
Memory protection fault indicators for system master PrivID = 12
91
QMSS_QUE_PEND_653
MPU_1_INT
92
93
QMSS_QUE_PEND_654
MPU_2_INT
94
95
QMSS_QUE_PEND_655
MPU_3_INT
96
97
QMSS_QUE_PEND_656
MSMC_DEDC_CERROR
MSMC_DEDC_NC_ERROR
MSMC_SCRUB_NC_ERROR
MSMC_MPF_ERROR0
MSMC_MPF_ERROR8
MSMC_MPF_ERROR9
MSMC_MPF_ERROR10
MSMC_MPF_ERROR11
MSMC_MPF_ERROR12
98
99
100
101
102
103
104
105
106
100
Memory, Interrupts, and EDMA for 66AK2E0x
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
EVENT NAME
DESCRIPTION
MSMC_MPF_ERROR13
MSMC_MPF_ERROR14
MSMC_MPF_ERROR15
DDR3_0_ERR
Memory protection fault indicators for system master PrivID = 13
Memory protection fault indicators for system master PrivID = 14
Memory protection fault indicators for system master PrivID = 15
DDR3_EMIF Error interrupt
HYPERLINK_0_INT
HyperLink interrupt
NETCP_GLOBAL_STARVE
NETCP_LOCAL_STARVE
NETCP_PA_ECC_INT
NETCP_SA_ECC_INT
NETCP_SWITCH_ECC_INT
NETCP_SWITCH_STAT_INT0
NETCP_SWITCH_STAT_INT1
NETCP_SWITCH_STAT_INT2
NETCP_SWITCH_STAT_INT3
NETCP_SWITCH_STAT_INT4
NETCP_SWITCH_STAT_INT5
NETCP_SWITCH_STAT_INT6
NETCP_SWITCH_STAT_INT7
NETCP_SWITCH_STAT_INT8
NETCP_SWITCH_INT
Reserved
NETCP GLOBAL interrupt
NETCP LOCAL interrupt
NETCP PA ECC interrupt
NETCP SA ECC interrupt
NETCP SWITCH ECC interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH interrupt
Reserved
AEMIF_EASYNCERR
Asynchronous EMIF16 error interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
QMSS_INTD_1_PKTDMA_0
QMSS_INTD_1_PKTDMA_1
IPC_GR0
Navigator interrupt for Packet DMA starvation
Navigator interrupt for Packet DMA starvation
IPC interrupt generation
NETCP_0_PKTDMA_INT0
SR_0_SMARTREFLEX_INTREQ0
SR_0_SMARTREFLEX_INTREQ1
SR_0_SMARTREFLEX_INTREQ2
SR_0_SMARTREFLEX_INTREQ3
SR_0_VPNOSMPSACK
Packet Accelerator0 Packet DMA starvation interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex controller interrupt
SmartReflex VPVOLTUPDATE has been asserted but SMPS has not been
responded to in a defined time interval
142
SR_0_VPEQVALUE
SmartReflex SRSINTERUPT is asserted, but the new voltage is not different
from the current SMPS voltage
143
144
145
146
SR_0_VPMAXVDD
SmartReflex The new voltage required is equal to or greater than MaxVdd
SmartReflex The new voltage required is equal to or less than MinVdd
SmartReflex. Indicating that the FSM of voltage processor is in idle
SR_0_VPMINVDD
SR_0_VPINIDLE
SR_0_VPOPPCHANGEDONE
SmartReflex Indicating that the average frequency error is within the desired
limit
147
148
149
150
151
Reserved
Reserved
UART_0_UARTINT
UART_0_URXEVT
UART_0_UTXEVT
QMSS_QUE_PEND_657
UART0 interrupt
UART0 receive event
UART0 transmit event
Navigator transmit queue pending event for indicated queue
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
152
EVENT NAME
DESCRIPTION
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
SR_0_VPSMPSACK
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
153
154
155
156
157
158
159
160
SmartReflex VPVOLTUPDATE asserted and SMPS has acknowledged in a
defined time interval
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
ARM_TBR_DMA
ARM_TBR_ACQ
ARM_NINTERRIRQ
ARM_NAXIERRIRQ
SR_0_SR_TEMPSENSOR
SR_0_SR_TIMERINT
PCIE_1_INT0
ARM trace buffer (TBR) DMA event
ARM trace buffer (TBR) acquisition has been completed
ARM internal memory ECC Error interrupt request
ARM bus error interrupt request
SmartReflex temperature threshold crossing interrupt
SmartReflex internal timer expiration interrupt
PCIE1 legacy INTA interrupt
PCIE1 legacy INTB interrupt
PCIE1 legacy INTC interrupt
PCIE1 legacy INTD interrupt
PCIE1 MSI interrupt
PCIE_1_INT1
PCIE_1_INT2
PCIE_1_INT3
PCIE_1_INT4
PCIE_1_INT5
PCIE1 MSI interrupt
PCIE_1_INT6
PCIE1 MSI interrupt
PCIE_1_INT7
PCIE1 MSI interrupt
PCIE_1_INT8
PCIE1 MSI interrupt
PCIE_1_INT9
PCIE1 MSI interrupt
PCIE_1_INT10
PCIE_1_INT11
PCIE_1_INT12
PCIE_1_INT13
USB_1_INT0
PCIE1 MSI interrupt
PCIE1 MSI interrupt
PCIE1 error interrupt
PCIE1 power management interrupt
USB_1 interrupt
USB_1_INT4
USB_1 interrupt
USB_1_MISCINT
USB_1_OABSINT
USB_0_INT0
USB_1 interrupt
USB_1 interrupt
USB_0 interrupt
USB_0_INT4
USB_0 interrupt
USB_0_MISCINT
USB_0_OABSINT
TIMER_0_INTL
TIMER_0_INTH
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
USB_0 interrupt
USB_0 interrupt
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt High
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
102
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
EVENT NAME
DESCRIPTION
TIMER_16_INTH
Timer interrupt high
Timer interrupt high
Timer interrupt high
Timer interrupt High
Semaphore interrupt
Semaphore error interrupt
TIMER_17_INTH
TIMER_18_INTH
TIMER_19_INTH
SEM_INT0
SEM_ERR0
MPU_15_INT
MPU5 addressing violation interrupt and protection violation interrupt.
Tracer sliding time window interrupt for USB1 CFG port tracer
EDMA3CC4 error interrupt
TRACER_USB11_INT
EDMACC_4_ERRINT
EDMACC_4_MPINT
EDMACC_4_TC_0_ERRINT
EDMACC_4_TC_1_ERRINT
EDMACC_4_GINT
EDMACC_4_TC_0_INT
EDMACC_4_TC_1_INT
EDMACC_4_TC_2_INT
EDMACC_4_TC_3_INT
EDMACC_4_TC_4_INT
EDMACC_4_TC_5_INT
EDMACC_4_TC_6_INT
EDMACC_4_TC_7_INT
EDMACC_3_ERRINT
EDMACC_3_MPINT
EDMACC_3_TC_0_ERRINT
EDMACC_3_TC_1_ERRINT
EDMACC_3_GINT
EDMACC_3_TC_0_INT
EDMACC_3_TC_1_INT
EDMACC_3_TC_2_INT
EDMACC_3_TC_3_INT
EDMACC_3_TC_4_INT
EDMACC_3_TC_5_INT
EDMACC_3_TC_6_INT
EDMACC_3_TC_7_INT
UART_1_UARTINT
UART_1_URXEVT
UART_1_UTXEVT
I2C_1_INT
EDMA3CC4 memory protection interrupt
EDMA3CC4 TPTC0 error interrupt
EDMA3CC4 TPTC1 error interrupt
EDMA3CC4 GINT
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC4 individual completion interrupt
EDMA3CC3 error interrupt
EDMA3CC3 memory protection interrupt
EDMA3CC3 TPTC0 error interrupt
EDMA3CC3 TPTC1 error interrupt
EDMA3CC3 GINT
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
EDMA3CC3 individual completion interrupt
UART1 interrupt
UART1 receive event
UART1 transmit event
I2C1 interrupt
I2C_1_REVT
I2C1 receive event
I2C_1_XEVT
I2C1 transmit event
SPI_1_INT0
SPI1 interrupt0
SPI_1_INT1
SPI1 interrupt1
SPI_1_XEVT
SPI1 transmit event
SPI_1_REVT
SPI1 receive event
MPU_5_INT
MPU5 addressing violation interrupt and protection violation interrupt
MPU8 addressing violation interrupt and protection violation interrupt
MPU9 addressing violation interrupt and protection violation interrupt
MPU_8_INT
MPU_9_INT
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
EVENT NAME
MPU_11_INT
Reserved
DESCRIPTION
MPU11 addressing violation interrupt and protection violation interrupt
Reserved
Reserved
Reserved
MPU_7_INT
MPU_10_INT
SPI_2_INT0
SPI_2_INT1
SPI_2_XEVT
SPI_2_REVT
I2C_2_INT
MPU7 addressing violation interrupt and protection violation interrupt
MPU10 addressing violation interrupt and protection violation interrupt
SPI2 interrupt0
SPI2 interrupt1
SPI2 transmit event
SPI2 receive event
I2C2 interrupt
I2C_2_REVT
I2C_2_XEVT
10GbE_LINK_INT0
10GbE_LINK_INT1
10GbE_USER_INT0
10GbE_USER_INT1
10GbE_MISC_INT
10GbE_INT_PKTDMA_0
USIM_PONIRQ
USIM_RREQ
USIM_WREQ
GPIO_INT0
I2C2 receive event
I2C2 transmit event
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet subsystem MDIO interrupt
10 Gigabit Ethernet Packet DMA starvation interrupt
USIM interrupt
USIM read DMA event
USIM write DMA event
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Reserved
GPIO_INT1
GPIO_INT2
GPIO_INT3
GPIO_INT4
GPIO_INT5
GPIO_INT6
GPIO_INT7
GPIO_INT8
GPIO_INT9
GPIO_INT10
GPIO_INT11
GPIO_INT12
GPIO_INT13
GPIO_INT14
GPIO_INT15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
QMSS_QUE_PEND_666
Navigator transmit queue pending event for indicated queue
104
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
EVENT NAME
DESCRIPTION
QMSS_QUE_PEND_667
QMSS_QUE_PEND_668
QMSS_QUE_PEND_669
QMSS_QUE_PEND_670
QMSS_QUE_PEND_671
QMSS_QUE_PEND_672
QMSS_QUE_PEND_673
QMSS_QUE_PEND_674
QMSS_QUE_PEND_675
QMSS_QUE_PEND_676
QMSS_QUE_PEND_677
QMSS_QUE_PEND_678
QMSS_QUE_PEND_679
QMSS_QUE_PEND_680
QMSS_QUE_PEND_681
QMSS_QUE_PEND_682
QMSS_QUE_PEND_683
QMSS_QUE_PEND_684
QMSS_QUE_PEND_685
QMSS_QUE_PEND_686
QMSS_QUE_PEND_687
QMSS_QUE_PEND_688
QMSS_QUE_PEND_689
QMSS_QUE_PEND_690
QMSS_QUE_PEND_691
Reserved
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Reserved
QMSS1_ECC_INTR
Navigator ECC error interrupt
QMSS_INTD_1_LOW_0
QMSS_INTD_1_LOW_1
QMSS_INTD_1_LOW_2
QMSS_INTD_1_LOW_3
QMSS_INTD_1_LOW_4
QMSS_INTD_1_LOW_5
QMSS_INTD_1_LOW_6
QMSS_INTD_1_LOW_7
QMSS_INTD_1_LOW_8
QMSS_INTD_1_LOW_9
QMSS_INTD_1_LOW_10
QMSS_INTD_1_LOW_11
QMSS_INTD_1_LOW_12
QMSS_INTD_1_LOW_13
QMSS_INTD_1_LOW_14
QMSS_INTD_1_LOW_15
QMSS_INTD_2_LOW_0
QMSS_INTD_2_LOW_1
QMSS_INTD_2_LOW_2
QMSS_INTD_2_LOW_3
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
340
EVENT NAME
DESCRIPTION
QMSS_INTD_2_LOW_4
QMSS_INTD_2_LOW_5
QMSS_INTD_2_LOW_6
QMSS_INTD_2_LOW_7
QMSS_INTD_2_LOW_8
QMSS_INTD_2_LOW_9
QMSS_INTD_2_LOW_10
QMSS_INTD_2_LOW_11
QMSS_INTD_2_LOW_12
QMSS_INTD_2_LOW_13
QMSS_INTD_2_LOW_14
QMSS_INTD_2_LOW_15
TRACER_EDMACC_0
TRACER_EDMACC_123_INT
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Tracer sliding time window interrupt for EDMA3CC0
341
342
343
344
345
346
347
348
349
350
351
352
353
Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2, and
EDMA3CC3
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
TRACER_CIC_INT
Tracer sliding time window interrupt for interrupt controllers (CIC)
Tracer sliding time window interrupt for MSMC SRAM bank4
Tracer sliding time window interrupt for MSMC SRAM bank5
Tracer sliding time window interrupt for MSMC SRAM bank6
Tracer sliding time window interrupt for MSMC SRAM bank7
Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
Tracer sliding time window interrupt for QM2
Reserved
TRACER_MSMC_4_INT
TRACER_MSMC_5_INT
TRACER_MSMC_6_INT
TRACER_MSMC_7_INT
TRACER_SPI_ROM_EMIF_INT
TRACER_QMSS_QM_CFG2_INT
Reserved
Reserved
Reserved
TRACER_PCIE1_INT
Reserved
Tracer sliding time window interrupt for PCIE1
Reserved
Reserved
Reserved
QMSS_INTD_1_HIGH_0
QMSS_INTD_1_HIGH_1
QMSS_INTD_1_HIGH_2
QMSS_INTD_1_HIGH_3
QMSS_INTD_1_HIGH_4
QMSS_INTD_1_HIGH_5
QMSS_INTD_1_HIGH_6
QMSS_INTD_1_HIGH_7
QMSS_INTD_1_HIGH_8
QMSS_INTD_1_HIGH_9
QMSS_INTD_1_HIGH_10
QMSS_INTD_1_HIGH_11
QMSS_INTD_1_HIGH_12
QMSS_INTD_1_HIGH_13
QMSS_INTD_1_HIGH_14
QMSS_INTD_1_HIGH_15
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_17
QMSS_INTD_1_HIGH_18
QMSS_INTD_1_HIGH_19
QMSS_INTD_1_HIGH_20
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
EVENT NAME
DESCRIPTION
QMSS_INTD_1_HIGH_21
QMSS_INTD_1_HIGH_22
QMSS_INTD_1_HIGH_23
QMSS_INTD_1_HIGH_24
QMSS_INTD_1_HIGH_25
QMSS_INTD_1_HIGH_26
QMSS_INTD_1_HIGH_27
QMSS_INTD_1_HIGH_28
QMSS_INTD_1_HIGH_29
QMSS_INTD_1_HIGH_30
QMSS_INTD_1_HIGH_31
QMSS_INTD_2_HIGH_0
QMSS_INTD_2_HIGH_1
QMSS_INTD_2_HIGH_2
QMSS_INTD_2_HIGH_3
QMSS_INTD_2_HIGH_4
QMSS_INTD_2_HIGH_5
QMSS_INTD_2_HIGH_6
QMSS_INTD_2_HIGH_7
QMSS_INTD_2_HIGH_8
QMSS_INTD_2_HIGH_9
QMSS_INTD_2_HIGH_10
QMSS_INTD_2_HIGH_11
QMSS_INTD_2_HIGH_12
QMSS_INTD_2_HIGH_13
QMSS_INTD_2_HIGH_14
QMSS_INTD_2_HIGH_15
QMSS_INTD_2_HIGH_16
QMSS_INTD_2_HIGH_17
QMSS_INTD_2_HIGH_18
QMSS_INTD_2_HIGH_19
QMSS_INTD_2_HIGH_20
QMSS_INTD_2_HIGH_21
QMSS_INTD_2_HIGH_22
QMSS_INTD_2_HIGH_23
QMSS_INTD_2_HIGH_24
QMSS_INTD_2_HIGH_25
QMSS_INTD_2_HIGH_26
QMSS_INTD_2_HIGH_27
QMSS_INTD_2_HIGH_28
QMSS_INTD_2_HIGH_29
QMSS_INTD_2_HIGH_30
QMSS_INTD_2_HIGH_31
Reserved
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
TIMER_12_INTL
Timer interrupt low
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Table 7-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
EVENT NO.
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
EVENT NAME
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
Reserved
DESCRIPTION
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
PCIE_0_INT8
PCIE_0_INT9
PCIE_0_INT10
PCIE_0_INT11
PCIE_0_INT4
PCIE_0_INT5
PCIE_0_INT6
PCIE_0_INT7
SEM_INT12
Reserved
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
PCIE0 MSI interrupt
Semaphore interrupt
Reserved
SEM_ERR12
Reserved
Semaphore error interrupt
Reserved
Table 7-25 lists the CIC2 event inputs.
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink)
EVENT NO.
EVENT NAME
GPIO_INT8
GPIO_INT9
GPIO_INT10
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
0
1
2
108
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
3
EVENT NAME
DESCRIPTION
GPIO interrupt
GPIO_INT11
4
GPIO_INT12
GPIO interrupt
5
GPIO_INT13
GPIO interrupt
6
GPIO_INT14
GPIO interrupt
7
GPIO_INT15
GPIO interrupt
8
DBGTBR_DMAINT
Reserved
Debug trace buffer (TBR) DMA event
Reserved
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Reserved
Reserved
TETB_FULLINT0
TETB_HFULLINT0
TETB_ACQINT0
Reserved
TETB0 is full
TETB0 is half full
TETB0 acquisition has been completed
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DFT_PBIST_CPU_INT
QMSS_INTD_1_HIGH_16
QMSS_INTD_1_HIGH_17
QMSS_INTD_1_HIGH_18
QMSS_INTD_1_HIGH_19
QMSS_INTD_1_HIGH_20
QMSS_INTD_1_HIGH_21
QMSS_INTD_1_HIGH_22
QMSS_INTD_1_HIGH_23
QMSS_INTD_1_HIGH_24
QMSS_INTD_1_HIGH_25
QMSS_INTD_1_HIGH_26
QMSS_INTD_1_HIGH_27
QMSS_INTD_1_HIGH_28
QMSS_INTD_1_HIGH_29
QMSS_INTD_1_HIGH_30
QMSS_INTD_1_HIGH_31
Reserved
Reserved
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRACER_CORE_0_INT
Reserved
Tracer sliding time window interrupt for DSP0 L2
Reserved
Reserved
Reserved
Reserved
Reserved
TRACER_DDR_INT
Tracer sliding time window interrupt for MSMC-DDR3
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Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
EVENT NAME
DESCRIPTION
TRACER_MSMC_0_INT
TRACER_MSMC_1_INT
TRACER_MSMC_2_INT
TRACER_MSMC_3_INT
TRACER_CFG_INT
TRACER_QMSS_QM_CFG1_INT
TRACER_QMSS_DMA_INT
TRACER_SEM_INT
SEM_ERR0
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for TeraNet CFG
Tracer sliding time window interrupt for Navigator CFG1 slave port
Tracer sliding time window interrupt for Navigator VBUSM slave port
Tracer sliding time window interrupt for Semaphore interrupt
Semaphore error interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BOOTCFG_INT
BOOTCFG error interrupt
NETCP_0_PKTDMA_INT0
MPU_0_INT
Packet Accelerator0 Packet DMA starvation interrupt
MPU0 interrupt
MSMC_SCRUB_CERROR
MPU_1_INT
MSMC error interrupt
MPU1 interrupt
Reserved
Reserved
MPU_2_INT
MPU2 interrupt
QMSS_INTD_1_PKTDMA_0
Reserved
Navigator Packet DMA interrupt
Reserved
QMSS_INTD_1_PKTDMA_1
MSMC_DEDC_CERROR
MSMC_DEDC_NC_ERROR
MSMC_SCRUB_NC_ERROR
Reserved
Navigator Packet DMA interrupt
MSMC error interrupt
MSMC error interrupt
MSMC error interrupt
Reserved
MSMC_MPF_ERROR0
Reserved
Memory protection fault indicators for system master PrivID = 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MSMC_MPF_ERROR8
MSMC_MPF_ERROR9
MSMC_MPF_ERROR10
MSMC_MPF_ERROR11
MSMC_MPF_ERROR12
MSMC_MPF_ERROR13
MSMC_MPF_ERROR14
MSMC_MPF_ERROR15
Reserved
Memory protection fault indicators for system master PrivID = 8
Memory protection fault indicators for system master PrivID = 9
Memory protection fault indicators for system master PrivID = 10
Memory protection fault indicators for system master PrivID = 11
Memory protection fault indicators for system master PrivID = 12
Memory protection fault indicators for system master PrivID = 13
Memory protection fault indicators for system master PrivID = 14
Memory protection fault indicators for system master PrivID = 15
Reserved
GPIO_INT16
GPIO interrupt
GPIO_INT17
GPIO interrupt
GPIO_INT18
GPIO interrupt
GPIO_INT19
GPIO interrupt
110
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
97
EVENT NAME
GPIO_INT20
GPIO_INT21
GPIO_INT22
GPIO_INT23
GPIO_INT24
GPIO_INT25
GPIO_INT26
GPIO_INT27
GPIO_INT28
GPIO_INT29
GPIO_INT30
GPIO_INT31
Reserved
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Reserved
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
AEMIF_EASYNCERR
Reserved
Asynchronous EMIF16 error interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
QMSS_INTD_1_HIGH_0
QMSS_INTD_1_HIGH_1
QMSS_INTD_1_HIGH_2
QMSS_INTD_1_HIGH_3
QMSS_INTD_1_HIGH_4
QMSS_INTD_1_HIGH_5
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
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Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
EVENT NAME
DESCRIPTION
QMSS_INTD_1_HIGH_6
QMSS_INTD_1_HIGH_7
QMSS_INTD_1_HIGH_8
QMSS_INTD_1_HIGH_9
QMSS_INTD_1_HIGH_10
QMSS_INTD_1_HIGH_11
QMSS_INTD_1_HIGH_12
QMSS_INTD_1_HIGH_13
QMSS_INTD_1_HIGH_14
QMSS_INTD_1_HIGH_15
QMSS_INTD_2_HIGH_0
QMSS_INTD_2_HIGH_1
QMSS_INTD_2_HIGH_2
QMSS_INTD_2_HIGH_3
QMSS_INTD_2_HIGH_4
QMSS_INTD_2_HIGH_5
QMSS_INTD_2_HIGH_6
QMSS_INTD_2_HIGH_7
QMSS_INTD_2_HIGH_8
QMSS_INTD_2_HIGH_9
QMSS_INTD_2_HIGH_10
QMSS_INTD_2_HIGH_11
QMSS_INTD_2_HIGH_12
QMSS_INTD_2_HIGH_13
QMSS_INTD_2_HIGH_14
QMSS_INTD_2_HIGH_15
QMSS_INTD_2_HIGH_16
QMSS_INTD_2_HIGH_17
QMSS_INTD_2_HIGH_18
QMSS_INTD_2_HIGH_19
QMSS_INTD_2_HIGH_20
QMSS_INTD_2_HIGH_21
QMSS_INTD_2_HIGH_22
QMSS_INTD_2_HIGH_23
QMSS_INTD_2_HIGH_24
QMSS_INTD_2_HIGH_25
QMSS_INTD_2_HIGH_26
QMSS_INTD_2_HIGH_27
QMSS_INTD_2_HIGH_28
QMSS_INTD_2_HIGH_29
QMSS_INTD_2_HIGH_30
QMSS_INTD_2_HIGH_31
MPU_12_INT
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
Navigator second hi interrupt
MPU12 addressing violation interrupt and protection violation interrupt
MPU13 addressing violation interrupt and protection violation interrupt
MPU14 addressing violation interrupt and protection violation interrupt
MPU15 addressing violation interrupt and protection violation interrupt
Reserved
MPU_13_INT
MPU_14_INT
MPU_15_INT
Reserved
112
Memory, Interrupts, and EDMA for 66AK2E0x
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
191
EVENT NAME
Reserved
DESCRIPTION
Reserved
192
Reserved
Reserved
193
Reserved
Reserved
194
Reserved
Reserved
195
Reserved
Reserved
196
Reserved
Reserved
197
Reserved
Reserved
198
Reserved
Reserved
199
TRACER_QMSS_QM_CFG2_INT
TRACER_EDMACC_0
TRACER_EDMACC_123_INT
Tracer sliding time window interrupt for Navigator CFG2 slave port
Tracer sliding time window interrupt foR EDMA3CC0
200
201
Tracer sliding time window interrupt for EDMA3CC1, EDMA3CC2, and
EDMA3CC3
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
TRACER_CIC_INT
Tracer sliding time window interrupt for interrupt controllers (CIC)
Reserved
Reserved
MPU_5_INT
MPU5 addressing violation interrupt and protection violation interrupt
Reserved
Reserved
MPU_7_INT
MPU7 addressing violation interrupt and protection violation interrupt
MPU8 addressing violation interrupt and protection violation interrupt
Reserved
MPU_8_INT
Reserved
Reserved
Reserved
Reserved
Reserved
DDR3_0_ERR
DDR3 error interrupt
HYPERLINK_0_INT
EDMACC_0_ERRINT
EDMACC_0_MPINT
EDMACC_0_TC_0_ERRINT
EDMACC_0_TC_1_ERRINT
EDMACC_1_ERRINT
EDMACC_1_MPINT
EDMACC_1_TC_0_ERRINT
EDMACC_1_TC_1_ERRINT
EDMACC_1_TC_2_ERRINT
EDMACC_1_TC_3_ERRINT
EDMACC_2_ERRINT
EDMACC_2_MPINT
EDMACC_2_TC_0_ERRINT
EDMACC_2_TC_1_ERRINT
EDMACC_2_TC_2_ERRINT
EDMACC_2_TC_3_ERRINT
EDMACC_3_ERRINT
EDMACC_3_MPINT
EDMACC_3_TC_0_ERRINT
EDMACC_3_TC_1_ERRINT
EDMACC_4_ERRINT
EDMACC_4_MPINT
EDMACC_4_TC_0_ERRINT
EDMACC_4_TC_1_ERRINT
QMSS_QUE_PEND_652
HyperLink interrupt
EDMA3CC0 error interrupt
EDMA3CC0 memory protection interrupt
EDMA3CC0 TPTC0 error interrupt
EDMA3CC0 TPTC1 error interrupt
EDMA3CC1 error interrupt
EDMA3CC1 memory protection interrupt
EDMA3CC1 TPTC0 error interrupt
EDMA3CC1 TPTC1 error interrupt
EDMA3CC1 TPTC2 error interrupt
EDMA3CC1 TPTC3 error interrupt
EDMA3CC2 error interrupt
EDMA3CC2 memory protection interrupt
EDMA3CC2 TPTC0 error interrupt
EDMA3CC2 TPTC1 error interrupt
EDMA3CC2 TPTC2 error interrupt
EDMA3CC2 TPTC3 error interrupt
EDMA3CC3 error interrupt
EDMA3CC3 memory protection interrupt
EDMA3CC3 TPTC0 error interrupt
EDMA3CC3 TPTC1 error interrupt
EDMA3CC4 error interrupt
EDMA3CC4 memory protection interrupt
EDMA3CC4 TPTC0 error interrupt
EDMA3CC4 TPTC1 error interrupt
Navigator transmit queue pending event for indicated queue
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Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
EVENT NAME
DESCRIPTION
QMSS_QUE_PEND_653
QMSS_QUE_PEND_654
QMSS_QUE_PEND_655
QMSS_QUE_PEND_656
QMSS_QUE_PEND_657
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
QMSS_QUE_PEND_666
QMSS_QUE_PEND_667
QMSS_QUE_PEND_668
QMSS_QUE_PEND_669
QMSS_QUE_PEND_670
QMSS_QUE_PEND_671
QMSS_QUE_PEND_672
QMSS_QUE_PEND_673
QMSS_QUE_PEND_674
QMSS_QUE_PEND_675
QMSS_QUE_PEND_676
QMSS_QUE_PEND_677
QMSS_QUE_PEND_678
QMSS_QUE_PEND_679
QMSS_QUE_PEND_680
QMSS_QUE_PEND_681
QMSS_QUE_PEND_682
QMSS_QUE_PEND_683
QMSS_QUE_PEND_684
QMSS_QUE_PEND_685
QMSS_QUE_PEND_686
QMSS_QUE_PEND_687
QMSS_QUE_PEND_688
QMSS_QUE_PEND_689
QMSS_QUE_PEND_690
QMSS_QUE_PEND_691
10GbE_LINK_INT0
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
10 Gigabit Ethernet subsystem MDIO interrupt
10GbE_LINK_INT1
10 Gigabit Ethernet subsystem MDIO interrupt
10GbE_USER_INT0
10 Gigabit Ethernet subsystem MDIO interrupt
10GbE_USER_INT1
10 Gigabit Ethernet subsystem MDIO interrupt
10GbE_MISC_INT
10 Gigabit Ethernet subsystem MDIO interrupt
10GbE_INT_PKTDMA_0
SEM_INT0
10 Gigabit Ethernet Packet DMA starvation interrupt
Semaphore interrupt
Reserved
Reserved
114
Memory, Interrupts, and EDMA for 66AK2E0x
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
EVENT NAME
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SEM_INT8
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Reserved
SEM_INT9
SEM_INT10
SEM_INT11
SEM_INT12
Reserved
Reserved
Reserved
Reserved
Reserved
SEM_ERR8
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Navigator ECC error interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
SEM_ERR9
SEM_ERR10
SEM_ERR11
SEM_ERR12
QMSS1_ECC_INTR
QMSS_INTD_1_LOW_0
QMSS_INTD_1_LOW_1
QMSS_INTD_1_LOW_2
QMSS_INTD_1_LOW_3
QMSS_INTD_1_LOW_4
QMSS_INTD_1_LOW_5
QMSS_INTD_1_LOW_6
QMSS_INTD_1_LOW_7
QMSS_INTD_1_LOW_8
QMSS_INTD_1_LOW_9
QMSS_INTD_1_LOW_10
QMSS_INTD_1_LOW_11
QMSS_INTD_1_LOW_12
QMSS_INTD_1_LOW_13
QMSS_INTD_1_LOW_14
QMSS_INTD_1_LOW_15
QMSS_INTD_2_LOW_0
QMSS_INTD_2_LOW_1
QMSS_INTD_2_LOW_2
QMSS_INTD_2_LOW_3
QMSS_INTD_2_LOW_4
QMSS_INTD_2_LOW_5
QMSS_INTD_2_LOW_6
QMSS_INTD_2_LOW_7
QMSS_INTD_2_LOW_8
QMSS_INTD_2_LOW_9
QMSS_INTD_2_LOW_10
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Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
EVENT NAME
DESCRIPTION
QMSS_INTD_2_LOW_11
QMSS_INTD_2_LOW_12
QMSS_INTD_2_LOW_13
QMSS_INTD_2_LOW_14
QMSS_INTD_2_LOW_15
NETCP_MDIO_LINK_INT0
NETCP_MDIO_LINK_INT1
NETCP_MDIO_USER_INT0
NETCP_MDIO_USER_INT1
NETCP_MISC_INT
NETCP_GLOBAL_STARVE_INT
NETCP_LOCAL_STARVE_INT
NETCP_PA_ECC_INT
NETCP_SA_ECC_INT
NETCP_SWITCH_ECC_INT
NETCP_SWITCH_STAT_INT0
NETCP_SWITCH_STAT_INT1
NETCP_SWITCH_STAT_INT2
NETCP_SWITCH_STAT_INT3
NETCP_SWITCH_STAT_INT4
NETCP_SWITCH_STAT_INT5
NETCP_SWITCH_STAT_INT6
NETCP_SWITCH_STAT_INT7
NETCP_SWITCH_STAT_INT8
NETCP_SWITCH_INT
Reserved
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator second interrupt
Navigator interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator subsystem MDIO interrupt
Packet Accelerator interrupt
Packet Accelerator interrupt
Packet Accelerator interrupt
Packet Accelerator interrupt
NETCP SWITCH ECC interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH STAT interrupt
NETCP SWITCH interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PSC_ALLINT
PSC interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPU_9_INT
MPU9 addressing violation interrupt and protection violation interrupt
MPU10 addressing violation interrupt and protection violation interrupt
MPU11 addressing violation interrupt and protection violation interrupt
Tracer sliding time window interrupt for MSMC SRAM bank 4
Tracer sliding time window interrupt for MSMC SRAM bank 4
Tracer sliding time window interrupt for MSMC SRAM bank 4
Tracer sliding time window interrupt for MSMC SRAM bank 4
MPU_10_INT
MPU_11_INT
TRACER_MSMC_4_INT
TRACER_MSMC_5_INT
TRACER_MSMC_6_INT
TRACER_MSMC_7_INT
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
EVENT NAME
TRACER_PCIE1_INT
Reserved
DESCRIPTION
Tracer sliding time window interrupt for PCIE1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TRACER_SPI_ROM_EMIF_INT
Reserved
Tracer sliding time window interrupt for SPI/ROM/EMIF16 modules
Reserved
TRACER_USB1_INT
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
USB_0_INT00
USB_0_INT01
USB_0_INT02
USB_0_INT03
USB_0_INT04
USB_0_INT05
USB_0_INT06
USB_0_INT07
USB_0_INT08
USB_0_INT09
USB_0_INT10
USB_0_INT11
USB_0_INT12
USB_0_INT13
USB_0_INT14
USB_0_INT15
USB_0_MISCINT
USB_0_OABSINT
Reserved
Tracer sliding time window interrupt for USB1 CFG port tracer
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
USB 0 event ring 0 interrupt
USB 0 event ring 1 interrupt
USB 0 event ring 2 interrupt
USB 0 event ring 3 interrupt
USB 0 event ring 4 interrupt
USB 0 event ring 5 interrupt
USB 0 event ring 6 interrupt
USB 0 event ring 7 interrupt
USB 0 event ring 8 interrupt
USB 0 event ring 9 interrupt
USB 0 event ring 10 interrupt
USB 0 event ring 11 interrupt
USB 0 event ring 12 interrupt
USB 0 event ring 13 interrupt
USB 0 event ring 14 interrupt
USB 0 event ring 15 interrupt
USB 0 Miscellaneous interrupt
USB 0 OABS interrupt
Reserved
USB_1_INT00
USB_1_INT01
USB_1_INT02
USB_1_INT03
USB_1_INT04
USB_1_INT05
USB_1_INT06
USB_1_INT07
USB 1 event ring 0 interrupt
USB 1 event ring 1 interrupt
USB 1 event ring 2 interrupt
USB 1 event ring 3 interrupt
USB 1 event ring 4 interrupt
USB 1 event ring 5 interrupt
USB 1 event ring 6 interrupt
USB 1 event ring 7 interrupt
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Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
EVENT NAME
USB_1_INT08
USB_1_INT09
USB_1_INT10
USB_1_INT11
USB_1_INT12
USB_1_INT13
USB_1_INT14
USB_1_INT15
USB_1_MISCINT
USB_1_OABSINT
Reserved
DESCRIPTION
USB 1 event ring 8 interrupt
USB 1 event ring 9 interrupt
USB 1 event ring 10 interrupt
USB 1 event ring 11 interrupt
USB 1 event ring 12 interrupt
USB 1 event ring 13 interrupt
USB 1 event ring 14 interrupt
USB 1 event ring 15 interrupt
USB 1 miscellaneous interrupt
USB 1 OABS interrupt
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TETB_OVFLINT0
TETB_UNFLINT0
TIMER_0_INTL
TIMER_0_INTH
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
TIMER_18_INTL
TIMER_18_INTH
TIMER_19_INTL
TIMER_19_INTH
Reserved
ETB0 overflow (emulation trace buffer)
ETB0 underflow
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Reserved
RSTMUX_INT8
RSTMUX_INT9
RSTMUX_INT10
RSTMUX_INT11
GPIO_INT0
Boot config watchdog timer expiration event for ARM Core 0
Boot config watchdog timer expiration event for ARM Core 1
Boot config watchdog timer expiration event for ARM Core 2
Boot config watchdog timer expiration event for ARM Core 3
GPIO interrupt
GPIO_INT1
GPIO interrupt
GPIO_INT2
GPIO interrupt
GPIO_INT3
GPIO interrupt
GPIO_INT4
GPIO interrupt
GPIO_INT5
GPIO interrupt
GPIO_INT6
GPIO interrupt
GPIO_INT7
GPIO interrupt
IPC_GR0
IPC interrupt generation
Reserved
Reserved
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-25. CIC2 Event Inputs (Secondary Events for EDMA3CC and Hyperlink) (continued)
EVENT NO.
473
EVENT NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
474
475
476
477
478
7.3.2 CIC Registers
This section includes the CIC memory map information and registers.
7.3.2.1 CIC0 Register Map
Table 7-26. CIC0 Registers
ADDRESS
OFFSET
REGISTER MNEMONIC
REVISION_REG
REGISTER NAME
0x0
Revision Register
0x4
CONTROL_REG
Control Register
0xC
HOST_CONTROL_REG
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
RAW_STATUS_REG5
RAW_STATUS_REG6
RAW_STATUS_REG7
RAW_STATUS_REG8
RAW_STATUS_REG9
RAW_STATUS_REG10
RAW_STATUS_REG11
RAW_STATUS_REG12
RAW_STATUS_REG13
RAW_STATUS_REG14
RAW_STATUS_REG15
ENA_STATUS_REG0
Host Control Register
0x10
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Raw Status Register 5
Raw Status Register 6
Raw Status Register 7
Raw Status Register 8
Raw Status Register 9
Raw Status Register 10
Raw Status Register 11
Raw Status Register 12
Raw Status Register 13
Raw Status Register 14
Raw Status Register 15
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enabled Status Register 5
0x20
0x24
0x28
0x2C
0x34
0x38
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x280
0x284
0x288
0x28C
0x290
0x294
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENA_STATUS_REG5
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Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
ENA_STATUS_REG6
ENA_STATUS_REG7
ENA_STATUS_REG8
ENA_STATUS_REG9
ENA_STATUS_REG10
ENA_STATUS_REG11
ENA_STATUS_REG12
ENA_STATUS_REG13
ENA_STATUS_REG14
ENA_STATUS_REG15
ENABLE_REG0
REGISTER NAME
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8
0x2BC
0x300
0x304
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
0x334
0x338
0x33C
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
0x39C
0x3A0
0x3A4
0x3A8
0x3AC
0x3B0
0x3B4
0x3B8
0x38C
0x400
0x404
0x408
0x40C
0x410
Enabled Status Register 6
Enabled Status Register 7
Enabled Status Register 8
Enabled Status Register 9
Enabled Status Register10
Enabled Status Register 11
Enabled Status Register 12
Enabled Status Register 13
Enabled Status Register 14
Enabled Status Register 15
Enable Register 0
ENABLE_REG1
Enable Register 1
ENABLE_REG2
Enable Register 2
ENABLE_REG3
Enable Register 3
ENABLE_REG4
Enable Register 4
ENABLE_REG5
Enable Register 5
ENABLE_REG6
Enable Register 6
ENABLE_REG7
Enable Register 7
ENABLE_REG8
Enable Register 8
ENABLE_REG9
Enable Register 9
ENABLE_REG10
Enable Register 10
ENABLE_REG11
Enable Register 11
ENABLE_REG12
Enable Register 12
ENABLE_REG13
Enable Register 13
ENABLE_REG14
Enable Register 14
ENABLE_REG15
Enable Register 15
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
ENABLE_CLR_REG5
ENABLE_CLR_REG6
ENABLE_CLR_REG7
ENABLE_CLR_REG8
ENABLE_CLR_REG9
ENABLE_CLR_REG10
ENABLE_CLR_REG11
ENABLE_CLR_REG12
ENABLE_CLR_REG13
ENABLE_CLR_REG14
ENABLE_CLR_REG15
CH_MAP_REG0
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Enable Clear Register 5
Enable Clear Register 6
Enable Clear Register 7
Enable Clear Register 8
Enable Clear Register 9
Enable Clear Register 10
Enable Clear Register 11
Enable Clear Register 12
Enable Clear Register 13
Enable Clear Register 14
Enable Clear Register 15
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
CH_MAP_REG1
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
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Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
CH_MAP_REG5
CH_MAP_REG6
CH_MAP_REG7
CH_MAP_REG8
CH_MAP_REG9
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
CH_MAP_REG16
CH_MAP_REG17
CH_MAP_REG18
CH_MAP_REG19
CH_MAP_REG20
CH_MAP_REG21
CH_MAP_REG22
CH_MAP_REG23
CH_MAP_REG24
CH_MAP_REG25
CH_MAP_REG26
CH_MAP_REG27
CH_MAP_REG28
CH_MAP_REG29
CH_MAP_REG30
CH_MAP_REG31
CH_MAP_REG32
CH_MAP_REG33
CH_MAP_REG34
CH_MAP_REG35
CH_MAP_REG36
CH_MAP_REG37
CH_MAP_REG38
CH_MAP_REG39
CH_MAP_REG40
CH_MAP_REG41
CH_MAP_REG42
CH_MAP_REG43
CH_MAP_REG44
CH_MAP_REG45
CH_MAP_REG46
CH_MAP_REG47
CH_MAP_REG48
CH_MAP_REG49
CH_MAP_REG50
CH_MAP_REG51
REGISTER NAME
0x414
0x418
0x41C
0x420
0x424
0x428
0x42C
0x430
0x434
0x438
0x43C
0x440
0x444
0x448
0x44C
0x450
0x454
0x458
0x45C
0x460
0x464
0x468
0x46C
0x470
0x474
0x478
0x47C
0x480
0x484
0x488
0x48C
0x490
0x494
0x498
0x49C
0x4a0
0x4a4
0x4a8
0x4AC
0x4b0
0x4b4
0x4b8
0x4BC
0x4C0
0x4C4
0x4C8
0x4CC
Interrupt Channel Map Register for 20 to 20+3
Interrupt Channel Map Register for 24 to 24+3
Interrupt Channel Map Register for 28 to 28+3
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Interrupt Channel Map Register for 64 to 64+3
Interrupt Channel Map Register for 68 to 68+3
Interrupt Channel Map Register for 72 to 72+3
Interrupt Channel Map Register for 76 to 76+3
Interrupt Channel Map Register for 80 to 80+3
Interrupt Channel Map Register for 84 to 84+3
Interrupt Channel Map Register for 88 to 88+3
Interrupt Channel Map Register for 92 to 92+3
Interrupt Channel Map Register for 96 to 96+3
Interrupt Channel Map Register for 100 to 100+3
Interrupt Channel Map Register for 104 to 104+3
Interrupt Channel Map Register for 108 to 108+3
Interrupt Channel Map Register for 112 to 112+3
Interrupt Channel Map Register for 116 to 116+3
Interrupt Channel Map Register for 120 to 120+3
Interrupt Channel Map Register for 124 to 124+3
Interrupt Channel Map Register for 128 to 128+3
Interrupt Channel Map Register for 132 to 132+3
Interrupt Channel Map Register for 136 to 136+3
Interrupt Channel Map Register for 140 to 140+3
Interrupt Channel Map Register for 144 to 144+3
Interrupt Channel Map Register for 148 to 148+3
Interrupt Channel Map Register for 152 to 152+3
Interrupt Channel Map Register for 156 to 156+3
Interrupt Channel Map Register for 160 to 160+3
Interrupt Channel Map Register for 164 to 164+3
Interrupt Channel Map Register for 168 to 168+3
Interrupt Channel Map Register for 172 to 172+3
Interrupt Channel Map Register for 176 to 176+3
Interrupt Channel Map Register for 180 to 180+3
Interrupt Channel Map Register for 184 to 184+3
Interrupt Channel Map Register for 188 to 188+3
Interrupt Channel Map Register for 192 to 192+3
Interrupt Channel Map Register for 196 to 196+3
Interrupt Channel Map Register for 200 to 200+3
Interrupt Channel Map Register for 204 to 204+3
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Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
CH_MAP_REG52
CH_MAP_REG53
CH_MAP_REG54
CH_MAP_REG55
CH_MAP_REG56
CH_MAP_REG57
CH_MAP_REG58
CH_MAP_REG59
CH_MAP_REG60
CH_MAP_REG61
CH_MAP_REG62
CH_MAP_REG63
CH_MAP_REG64
CH_MAP_REG65
CH_MAP_REG66
CH_MAP_REG67
CH_MAP_REG68
CH_MAP_REG69
CH_MAP_REG70
CH_MAP_REG71
CH_MAP_REG72
CH_MAP_REG73
CH_MAP_REG74
CH_MAP_REG75
CH_MAP_REG76
CH_MAP_REG77
CH_MAP_REG78
CH_MAP_REG79
CH_MAP_REG80
CH_MAP_REG81
CH_MAP_REG82
CH_MAP_REG83
CH_MAP_REG84
CH_MAP_REG85
CH_MAP_REG86
CH_MAP_REG87
CH_MAP_REG88
CH_MAP_REG89
CH_MAP_REG90
CH_MAP_REG91
CH_MAP_REG92
CH_MAP_REG93
CH_MAP_REG94
CH_MAP_REG95
CH_MAP_REG96
CH_MAP_REG97
CH_MAP_REG98
REGISTER NAME
0X4D0
0X4D4
0X4D8
0X4DC
0X4E0
0X4E4
0X4E8
0X4FC
0X4F0
0X4F4
0X4F8
0X4FC
0X500
0X504
0X508
0X50C
0X510
0X514
0X518
0X51C
0X520
0X524
0X528
0X52C
0X520
0X524
0X528
0x52C
0x530
0x534
0x538
0x53C
0x540
0x544
0x548
0x54C
0x550
0x554
0x558
0x55C
0x560
0x564
0x568
0x56C
0x570
0x574
0x578
Interrupt Channel Map Register for 208 to 208+3
Interrupt Channel Map Register for 212 to 212+3
Interrupt Channel Map Register for 216 to 216+3
Interrupt Channel Map Register for 220 to 220+3
Interrupt Channel Map Register for 224 to 224+3
Interrupt Channel Map Register for 228 to 228+3
Interrupt Channel Map Register for 232 to 232+3
Interrupt Channel Map Register for 236 to 236+3
Interrupt Channel Map Register for 240 to 240+3
Interrupt Channel Map Register for 244 to 244+3
Interrupt Channel Map Register for 248 to 248+3
Interrupt Channel Map Register for 252 to 252+3
Interrupt Channel Map Register for 256 to 256+3
Interrupt Channel Map Register for 260 to 260+3
Interrupt Channel Map Register for 264 to 264+3
Interrupt Channel Map Register for 268 to 268+3
Interrupt Channel Map Register for 272 to 272+3
Interrupt Channel Map Register for 276 to 276+3
Interrupt Channel Map Register for 280 to 280+3
Interrupt Channel Map Register for 284 to 284+3
Interrupt Channel Map Register for 288 to 288+3
Interrupt Channel Map Register for 292 to 292+3
Interrupt Channel Map Register for 296 to 296+3
Interrupt Channel Map Register for 300 to 300+3
Interrupt Channel Map Register for 304 to 304+3
Interrupt Channel Map Register for 308 to 308+3
Interrupt Channel Map Register for 312 to 312+3
Interrupt Channel Map Register for 316 to 316+3
Interrupt Channel Map Register for 320 to 320+3
Interrupt Channel Map Register for 324 to 324+3
Interrupt Channel Map Register for 328 to 328+3
Interrupt Channel Map Register for 332 to332+3
Interrupt Channel Map Register for336 to 336+3
Interrupt Channel Map Register for 340 to 340+3
Interrupt Channel Map Register for 344 to 344+3
Interrupt Channel Map Register for 348 to 348+3
Interrupt Channel Map Register for 352 to 352+3
Interrupt Channel Map Register for 356 to 356+3
Interrupt Channel Map Register for 360 to 360+3
Interrupt Channel Map Register for 364 to 364+3
Interrupt Channel Map Register for 368 to 368+3
Interrupt Channel Map Register for372 to 372+3
Interrupt Channel Map Register for 376 to 376+3
Interrupt Channel Map Register for 380 to 380+3
Interrupt Channel Map Register for 384 to 384+3
Interrupt Channel Map Register for 388 to 388+3
Interrupt Channel Map Register for 392 to 392+3
122
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
CH_MAP_REG99
CH_MAP_REG100
CH_MAP_REG101
CH_MAP_REG102
CH_MAP_REG103
CH_MAP_REG104
CH_MAP_REG105
CH_MAP_REG106
CH_MAP_REG107
CH_MAP_REG108
CH_MAP_REG109
CH_MAP_REG110
CH_MAP_REG111
CH_MAP_REG112
CH_MAP_REG113
CH_MAP_REG114
CH_MAP_REG115
CH_MAP_REG116
CH_MAP_REG117
CH_MAP_REG118
CH_MAP_REG119
CH_MAP_REG120
CH_MAP_REG121
CH_MAP_REG122
CH_MAP_REG123
CH_MAP_REG124
CH_MAP_REG125
CH_MAP_REG126
CH_MAP_REG127
CH_MAP_REG128
CH_MAP_REG129
CH_MAP_REG130
CH_MAP_REG131
CH_MAP_REG132
CH_MAP_REG133
CH_MAP_REG134
CH_MAP_REG135
CH_MAP_REG136
CH_MAP_REG137
CH_MAP_REG138
CH_MAP_REG139
CH_MAP_REG140
CH_MAP_REG141
CH_MAP_REG142
CH_MAP_REG143
CH_MAP_REG144
CH_MAP_REG145
REGISTER NAME
0x57C
0x580
0x584
0x588
0x58C
0x590
0x594
0x598
0x59C
0x5A0
0x5A4
0x5A8
0x5AC
0x5B0
0x5B4
0x5B8
0x5BC
0x5C0
0x5C4
0x5C8
0x5CC
0x5D0
0x5D4
0x5D8
0x5DC
0x5E0
0x5E4
0x5E8
0x5EC
0x5F0
0x5F4
0x5F8
0x5FC
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
Interrupt Channel Map Register for 396 to 396+3
Interrupt Channel Map Register for 400 to 400+3
Interrupt Channel Map Register for 404 to 404+3
Interrupt Channel Map Register for 408 to 408+3
Interrupt Channel Map Register for 412 to412+3
Interrupt Channel Map Register for 416 to 416+3
Interrupt Channel Map Register for 420 to 420+3
Interrupt Channel Map Register for 424 to 424+3
Interrupt Channel Map Register for 428 to 428+3
Interrupt Channel Map Register for 432 to 432+3
Interrupt Channel Map Register for 436 to 436+3
Interrupt Channel Map Register for 440 to 440+3
Interrupt Channel Map Register for 444 to 444+3
Interrupt Channel Map Register for 448 to 448+3
Interrupt Channel Map Register for 452 to 452+3
Interrupt Channel Map Register for 456 to 456+3
Interrupt Channel Map Register for 460 to 460+3
Interrupt Channel Map Register for 464 to 464+3
Interrupt Channel Map Register for 468 to 468+3
Interrupt Channel Map Register for 472 to 472+3
Interrupt Channel Map Register for 476 to 476+3
Interrupt Channel Map Register for 480 to 480+3
Interrupt Channel Map Register for 484 to 484+3
Interrupt Channel Map Register for 488 to 488+3
Interrupt Channel Map Register for 482 to 492+3
Interrupt Channel Map Register for 496 to 496+3
Interrupt Channel Map Register for 500 to 500+3
Interrupt Channel Map Register for 504 to 504+3
Interrupt Channel Map Register for 508 to 508+3
Interrupt Channel Map Register for 512 to 512+3
Interrupt Channel Map Register for 516 to 516+3
Interrupt Channel Map Register for 520 to 520+3
Interrupt Channel Map Register for 524 to 524+3
Interrupt Channel Map Register for 528 to 528+3
Interrupt Channel Map Register for 532 to 532+3
Interrupt Channel Map Register for 536 to 536+3
Interrupt Channel Map Register for 540 to 540+3
Interrupt Channel Map Register for 544 to 544+3
Interrupt Channel Map Register for 548 to 548+3
Interrupt Channel Map Register for 552 to 552+3
Interrupt Channel Map Register for 556 to 556+3
Interrupt Channel Map Register for 560 to 560+3
Interrupt Channel Map Register for 564 to 564+3
Interrupt Channel Map Register for 568 to 568+3
Interrupt Channel Map Register for 572 to 572+3
Interrupt Channel Map Register for 576 to 576+3
Interrupt Channel Map Register for 580 to 580+3
Copyright © 2012–2015, Texas Instruments Incorporated
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Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
CH_MAP_REG146
CH_MAP_REG147
CH_MAP_REG148
CH_MAP_REG149
CH_MAP_REG150
CH_MAP_REG151
CH_MAP_REG152
CH_MAP_REG153
CH_MAP_REG154
CH_MAP_REG155
CH_MAP_REG156
CH_MAP_REG157
CH_MAP_REG158
CH_MAP_REG159
CH_MAP_REG160
CH_MAP_REG161
CH_MAP_REG162
CH_MAP_REG163
CH_MAP_REG164
CH_MAP_REG165
CH_MAP_REG166
CH_MAP_REG167
CH_MAP_REG168
CH_MAP_REG169
CH_MAP_REG170
CH_MAP_REG171
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
HINT_MAP_REG13
HINT_MAP_REG14
HINT_MAP_REG15
HINT_MAP_REG16
HINT_MAP_REG17
HINT_MAP_REG18
HINT_MAP_REG19
ENABLE_HINT_REG0
REGISTER NAME
0x638
0x63C
0x640
0x644
0x648
0x64C
0x650
0x654
0x658
0x65C
0x660
0x664
0x668
0x66C
0x670
0x674
0x678
0x67C
0x680
0x684
0x688
0x68C
0x690
0x694
0x698
0x69C
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x820
0x824
0x828
0x82C
0x830
0x834
0x838
0x83C
0x840
0x844
0x848
0x84C
0x1500
Interrupt Channel Map Register for 584 to 584+3
Interrupt Channel Map Register for 588 to 588+3
Interrupt Channel Map Register for 592 to 592+3
Interrupt Channel Map Register for 596 to 596+3
Interrupt Channel Map Register for 600 to 600+3
Interrupt Channel Map Register for 604 to 604+3
Interrupt Channel Map Register for 608 to 608+3
Interrupt Channel Map Register for 612 to 612+3
Interrupt Channel Map Register for 616 to 616+3
Interrupt Channel Map Register for 620 to 620+3
Interrupt Channel Map Register for 624 to 624+3
Interrupt Channel Map Register for 628 to 628+3
Interrupt Channel Map Register for 632 to 632+3
Interrupt Channel Map Register for 636 to 636+3
Interrupt Channel Map Register for 640 to 640+3
Interrupt Channel Map Register for 644 to 644+3
Interrupt Channel Map Register for 648 to 648+3
Interrupt Channel Map Register for 652 to 652+3
Interrupt Channel Map Register for 656 to 656+3
Interrupt Channel Map Register for 660 to 660+3
Interrupt Channel Map Register for 664 to 664+3
Interrupt Channel Map Register for 668 to 668+3
Interrupt Channel Map Register for 672 to 672+3
Interrupt Channel Map Register for 676 to 676+3
Interrupt Channel Map Register for 680 to 680+3
Interrupt Channel Map Register for 684 to 684+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Interrupt Map Register for 52 to 52+3
Host Interrupt Map Register for 56 to 56+3
Host Interrupt Map Register for 60 to 60+3
Host Interrupt Map Register for 64 to 64+3
Host Interrupt Map Register for 68 to 68+3
Host Interrupt Map Register for 72 to 72+3
Host Interrupt Map Register for 76 to 76+3
Host Int Enable Register 0
124
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-26. CIC0 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
ENABLE_HINT_REG1
ENABLE_HINT_REG2
ENABLE_HINT_REG3
REGISTER NAME
0x1504
0x1508
0x150C
Host Int Enable Register 1
Host Int Enable Register 2
Host Int Enable Register 3
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7.3.2.2 CIC2 Register Map
Table 7-27. CIC2 Registers
ADDRESS
OFFSET
REGISTER MNEMONIC
REVISION_REG
REGISTER NAME
0x0
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
0x20
0x24
0x28
0x2C
0x34
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
RAW_STATUS_REG5
RAW_STATUS_REG6
RAW_STATUS_REG7
RAW_STATUS_REG8
RAW_STATUS_REG9
RAW_STATUS_REG10
RAW_STATUS_REG11
RAW_STATUS_REG12
RAW_STATUS_REG13
RAW_STATUS_REG14
RAW_STATUS_REG15
ENA_STATUS_REG0
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENA_STATUS_REG5
ENA_STATUS_REG6
ENA_STATUS_REG7
ENA_STATUS_REG8
ENA_STATUS_REG9
ENA_STATUS_REG10
ENA_STATUS_REG11
ENA_STATUS_REG12
ENA_STATUS_REG13
ENA_STATUS_REG14
ENA_STATUS_REG15
ENABLE_REG0
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Raw Status Register 5
Raw Status Register 6
Raw Status Register 7
Raw Status Register 8
Raw Status Register 9
Raw Status Register 10
Raw Status Register 11
Raw Status Register 12
Raw Status Register 13
Raw Status Register 14
Raw Status Register 15
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enabled Status Register 5
Enabled Status Register 6
Enabled Status Register 7
Enabled Status Register 8
Enabled Status Register 9
Enabled Status Register10
Enabled Status Register 11
Enabled Status Register 12
Enabled Status Register 13
Enabled Status Register 14
Enabled Status Register 15
Enable Register 0
0x38
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x280
0x284
0x288
0x28C
0x290
0x294
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
0x2B0
0x2B4
0x2B8
0x2BC
0x300
0x304
0x308
0x30C
0x310
ENABLE_REG1
Enable Register 1
ENABLE_REG2
Enable Register 2
ENABLE_REG3
Enable Register 3
ENABLE_REG4
Enable Register 4
126
Memory, Interrupts, and EDMA for 66AK2E0x
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-27. CIC2 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
ENABLE_REG5
REGISTER NAME
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
0x334
0x338
0x33C
0x380
0x384
0x388
0x38C
0x390
0x394
0x398
0x39C
0x3A0
0x3A4
0x3A8
0x3AC
0x3B0
0x3B4
0x3B8
0x38C
0x400
0x404
0x408
0x40C
0x410
0x414
0x418
0x41C
0x420
0x424
0x428
0x42C
0x430
0x434
0x438
0x43C
0x5C0
0x5C4
0x5C8
0x5CC
Enable Register 5
ENABLE_REG6
Enable Register 6
ENABLE_REG7
Enable Register 7
ENABLE_REG8
Enable Register 8
ENABLE_REG9
Enable Register 9
ENABLE_REG10
ENABLE_REG11
ENABLE_REG12
ENABLE_REG13
ENABLE_REG14
ENABLE_REG15
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
ENABLE_CLR_REG5
ENABLE_CLR_REG6
ENABLE_CLR_REG7
ENABLE_CLR_REG8
ENABLE_CLR_REG9
ENABLE_CLR_REG10
ENABLE_CLR_REG11
ENABLE_CLR_REG12
ENABLE_CLR_REG13
ENABLE_CLR_REG14
ENABLE_CLR_REG15
CH_MAP_REG0
Enable Register 10
Enable Register 11
Enable Register 12
Enable Register 13
Enable Register 14
Enable Register 15
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Enable Clear Register 5
Enable Clear Register 6
Enable Clear Register 7
Enable Clear Register 8
Enable Clear Register 9
Enable Clear Register 10
Enable Clear Register 11
Enable Clear Register 12
Enable Clear Register 13
Enable Clear Register 14
Enable Clear Register 15
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
Interrupt Channel Map Register for 20 to 20+3
Interrupt Channel Map Register for 24 to 24+3
Interrupt Channel Map Register for 28 to 28+3
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Interrupt Channel Map Register for 464 to 464+3
Interrupt Channel Map Register for 468 to 468+3
Interrupt Channel Map Register for 472 to 472+3
Interrupt Channel Map Register for 476 to 476+3
CH_MAP_REG1
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
CH_MAP_REG5
CH_MAP_REG6
CH_MAP_REG7
CH_MAP_REG8
CH_MAP_REG9
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
CH_MAP_REG116
CH_MAP_REG117
CH_MAP_REG118
CH_MAP_REG119
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Table 7-27. CIC2 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
CH_MAP_REG120
CH_MAP_REG121
CH_MAP_REG122
CH_MAP_REG123
CH_MAP_REG124
CH_MAP_REG125
CH_MAP_REG126
CH_MAP_REG127
CH_MAP_REG128
CH_MAP_REG129
CH_MAP_REG130
CH_MAP_REG131
CH_MAP_REG132
CH_MAP_REG133
CH_MAP_REG134
CH_MAP_REG135
CH_MAP_REG136
CH_MAP_REG137
CH_MAP_REG138
CH_MAP_REG139
CH_MAP_REG140
CH_MAP_REG141
CH_MAP_REG142
CH_MAP_REG143
CH_MAP_REG144
CH_MAP_REG145
CH_MAP_REG146
CH_MAP_REG147
CH_MAP_REG148
CH_MAP_REG149
CH_MAP_REG150
CH_MAP_REG151
CH_MAP_REG152
CH_MAP_REG153
CH_MAP_REG154
CH_MAP_REG155
CH_MAP_REG156
CH_MAP_REG157
CH_MAP_REG158
CH_MAP_REG159
CH_MAP_REG160
CH_MAP_REG161
CH_MAP_REG162
CH_MAP_REG163
CH_MAP_REG164
CH_MAP_REG165
CH_MAP_REG166
REGISTER NAME
0x5D0
0x5D4
0x5D8
0x5DC
0x5E0
0x5E4
0x5E8
0x5EC
0x5F0
0x5F4
0x5F8
0x5FC
0x600
0x604
0x608
0x60C
0x610
0x614
0x618
0x61C
0x620
0x624
0x628
0x62C
0x630
0x634
0x638
0x63C
0x640
0x644
0x648
0x64C
0x650
0x654
0x658
0x65C
0x660
0x664
0x668
0x66C
0x670
0x674
0x678
0x67C
0x680
0x684
0x688
Interrupt Channel Map Register for 480 to 480+3
Interrupt Channel Map Register for 484 to 484+3
Interrupt Channel Map Register for 488 to 488+3
Interrupt Channel Map Register for 482 to 492+3
Interrupt Channel Map Register for 496 to 496+3
Interrupt Channel Map Register for 500 to 500+3
Interrupt Channel Map Register for 504 to 504+3
Interrupt Channel Map Register for 508 to 508+3
Interrupt Channel Map Register for 512 to 512+3
Interrupt Channel Map Register for 516 to 516+3
Interrupt Channel Map Register for 520 to 520+3
Interrupt Channel Map Register for 524 to 524+3
Interrupt Channel Map Register for 528 to 528+3
Interrupt Channel Map Register for 532 to 532+3
Interrupt Channel Map Register for 536 to 536+3
Interrupt Channel Map Register for 540 to 540+3
Interrupt Channel Map Register for 544 to 544+3
Interrupt Channel Map Register for 548 to 548+3
Interrupt Channel Map Register for 552 to 552+3
Interrupt Channel Map Register for 556 to 556+3
Interrupt Channel Map Register for 560 to 560+3
Interrupt Channel Map Register for 564 to 564+3
Interrupt Channel Map Register for 568 to 568+3
Interrupt Channel Map Register for 572 to 572+3
Interrupt Channel Map Register for 576 to 576+3
Interrupt Channel Map Register for 580 to 580+3
Interrupt Channel Map Register for 584 to 584+3
Interrupt Channel Map Register for 588 to 588+3
Interrupt Channel Map Register for 592 to 592+3
Interrupt Channel Map Register for 596 to 596+3
Interrupt Channel Map Register for 600 to 600+3
Interrupt Channel Map Register for 604 to 604+3
Interrupt Channel Map Register for 608 to 608+3
Interrupt Channel Map Register for 612 to 612+3
Interrupt Channel Map Register for 616 to 616+3
Interrupt Channel Map Register for 620 to 620+3
Interrupt Channel Map Register for 624 to 624+3
Interrupt Channel Map Register for 628 to 628+3
Interrupt Channel Map Register for 632 to 632+3
Interrupt Channel Map Register for 636 to 636+3
Interrupt Channel Map Register for 640 to 640+3
Interrupt Channel Map Register for 644 to 644+3
Interrupt Channel Map Register for 648 to 648+3
Interrupt Channel Map Register for 652 to 652+3
Interrupt Channel Map Register for 656 to 656+3
Interrupt Channel Map Register for 660 to 660+3
Interrupt Channel Map Register for 664 to 664+3
128
Memory, Interrupts, and EDMA for 66AK2E0x
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-27. CIC2 Registers (continued)
ADDRESS
OFFSET
REGISTER MNEMONIC
CH_MAP_REG167
CH_MAP_REG168
CH_MAP_REG169
CH_MAP_REG170
CH_MAP_REG171
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
HINT_MAP_REG13
HINT_MAP_REG14
HINT_MAP_REG15
HINT_MAP_REG16
HINT_MAP_REG17
HINT_MAP_REG18
HINT_MAP_REG19
HINT_MAP_REG20
HINT_MAP_REG21
HINT_MAP_REG22
HINT_MAP_REG23
HINT_MAP_REG24
HINT_MAP_REG25
HINT_MAP_REG26
HINT_MAP_REG27
ENABLE_HINT_REG0
ENABLE_HINT_REG1
ENABLE_HINT_REG2
ENABLE_HINT_REG3
REGISTER NAME
0x68C
0x690
0x694
0x698
0x69C
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x820
0x824
0x828
0x82C
0x830
0x834
0x838
0x83C
0x840
0x844
0x848
0x84C
0x850
0x854
0x858
0x85C
0x860
0x864
0x868
0x86C
0x1500
0x1504
0x1508
0x150C
Interrupt Channel Map Register for 668 to 668+3
Interrupt Channel Map Register for 672 to 672+3
Interrupt Channel Map Register for 676 to 676+3
Interrupt Channel Map Register for 680 to 680+3
Interrupt Channel Map Register for 684 to 684+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Interrupt Map Register for 52 to 52+3
Host Interrupt Map Register for 56 to 56+3
Host Interrupt Map Register for 60 to 60+3
Host Interrupt Map Register for 63 to 63+3
Host Interrupt Map Register for 66 to 66+3
Host Interrupt Map Register for 68 to 68+3
Host Interrupt Map Register for 72 to 72+3
Host Interrupt Map Register for 76 to 76+3
Host Interrupt Map Register for 80 to 80+3
Host Interrupt Map Register for 84 to 84+3
Host Interrupt Map Register for 88 to 88+3
Host Interrupt Map Register for 92 to 92+3
Host Interrupt Map Register for 94 to 94+3
Host Interrupt Map Register for 96 to 96+3
Host Interrupt Map Register for 100 to 100+3
Host Int Enable Register 0
Host Int Enable Register 1
Host Int Enable Register 2
Host Int Enable Register 3
7.4 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-
mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data
movement between external memory and internal memory), performs sorting or subframe extraction of
various data structures, services event driven peripherals, and offloads data transfers from the device
C66x DSP CorePac or the ARM CorePac.
There are 5 EDMA channel controllers on the device:
•
EDMA3CC0 has two transfer controllers: TPTC0 and TPTC1
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•
•
•
•
EDMA3CC1 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
EDMA3CC2 has four transfer controllers: TPTC0, TPTC1, TPTC2, and TPTC3
EDMA3CC3 has two transfer controllers: TPTC0 and TPTC1
EDMA3CC4 has two transfer controllers: TPTC0 and TPTC1
In the context of this document, TPTCx is associated with EDMA3CCy, and is referred to as EDMA3CCy
TPTCx. Each of the transfer controllers has a direct connection to the switch fabric. Section 8.2 lists the
peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR3 subsytems. The
others are used for the remaining traffic.
Each EDMA3 channel controller includes the following features:
•
Fully orthogonal transfer description
–
3 transfer dimensions:
•
•
•
Array (multiple bytes)
Frame (multiple arrays)
Block (multiple frames)
–
–
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
•
Flexible transfer definition:
–
–
Increment or FIFO transfer addressing modes
Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
–
Chaining allows multiple transfers to execute with one event
•
•
512 PaRAM entries for all EDMA3CC
–
–
Used to define transfer context for channels
Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
64 DMA channels for all EDMA3CC
–
–
–
Manually triggered (CPU writes to channel controller register)
External event triggered
Chain triggered (completion of one transfer triggers another)
•
8 Quick DMA (QDMA) channels per EDMA3CCx
–
–
Used for software-driven transfers
Triggered upon writing to a single PaRAM set entry
•
•
Two transfer controllers and two event queues with programmable system-level priority for
EDMA3CC0, EDMA3CC3 and EDMA3CC4
Four transfer controllers and four event queues with programmable system-level priority for each of
EDMA3CC1 and EDMA3CC2
•
•
Interrupt generation for transfer completion and error conditions
Debug visibility
–
–
Queue watermarking/threshold allows detection of maximum usage of event queues
Error and status recording to facilitate debug
7.4.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode.
Constant addressing mode is applicable to a very limited set of use cases. For most applications
increment mode can be used. For more information on these two addressing modes, see the KeyStone
Architecture Enhanced Direct Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
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For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers
and EDMA3 transfer controller (TPTC) control registers, see Section Section 7.1. For memory offsets and
other details on EDMA3CC and TPTC Control Register entries, see the KeyStone Architecture Enhanced
Direct Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
7.4.2 EDMA3 Channel Controller Configuration
Table 7-28 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-28. EDMA3 Channel Controller Configuration
DESCRIPTION
EDMA3 CC0
EDMA3 CC1
EDMA3 CC2
EDMA3 CC3
EDMA3 CC4
Number of DMA channels in channel controller
Number of QDMA channels
64
8
64
8
64
8
64
8
64
8
Number of interrupt channels
Number of PaRAM set entries
Number of event queues
64
512
2
64
512
4
64
512
4
64
512
2
64
512
2
Number of transfer controllers
Memory protection existence
Number of memory protection and shadow regions
2
4
4
2
2
Yes
8
Yes
8
Yes
8
Yes
8
Yes
8
7.4.3 EDMA3 Transfer Controller Configuration
Each transfer controller on the device is designed differently based on considerations like performance
requirements, system topology (like main TeraNet bus width, external memory bus width), etc. The
parameters that determine the transfer controller configurations are:
•
FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.
•
•
•
BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.
DSTREGDEPTH: This determines the number of destination FIFO register sets. The number of
destination FIFO register sets for a transfer controller determines the maximum number of outstanding
transfer requests.
All four parameters listed above are fixed by the design of the device.
Table 7-29 shows the configuration of each of the EDMA3 transfer controllers present on the device.
Table 7-29. EDMA3 Transfer Controller Configuration
EDMA3 CC0/CC4
EDMA3 CC1
EDMA3 CC2
EDMA3CC3
PARAMETER
TC0
TC1
TC0
TC1
TC2
TC3
TC0
TC1
TC2
TC3
TC0
TC1
FIFOSIZE
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
1024
bytes
BUSWIDTH
DSTREGDEPTH
DBS
32
bytes
32
bytes
16
bytes
16
bytes
16
bytes
16
bytes
16
bytes
16
bytes
16
bytes
16
bytes
16
bytes
16
bytes
4
4
4
4
4
4
4
4
4
4
4
4
entries
entries
entries
entries
entries
entries
entries
entries
entries
entries
entries
entries
128
128
128
128
128
128
128
128
128
128
64
64
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
bytes
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7.4.4 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels for all EDMA3CC that can be used to service system
peripherals and to move data between system memories. DMA channels can be triggered by
synchronization events generated by system peripherals. The following tables list the source of the
synchronization event associated with each of the EDMA3CC DMA channels. On the 66AK2E0x, the
association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured,
processed, prioritized, linked, chained, and cleared, etc., see the KeyStone Architecture Enhanced Direct
Memory Access 3 (EDMA3) User's Guide (SPRUGS5).
Table 7-30. EDMA3CC0 Events for 66AK2E0x
EVENT NO.
EVENT NAME
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
CIC_2_OUT66
CIC_2_OUT67
CIC_2_OUT68
CIC_2_OUT69
CIC_2_OUT70
CIC_2_OUT71
CIC_2_OUT72
CIC_2_OUT73
GPIO_INT8
DESCRIPTION
0
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
GPIO interrupt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GPIO_INT9
GPIO interrupt
GPIO_INT10
GPIO interrupt
GPIO_INT11
GPIO interrupt
GPIO_INT12
GPIO interrupt
GPIO_INT13
GPIO interrupt
GPIO_INT14
GPIO interrupt
GPIO_INT15
GPIO interrupt
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
TIMER_18_INTL
TIMER_18_INTH
TIMER_19_INTL
TIMER_19_INTH
GPIO_INT0
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
GPIO interrupt
GPIO_INT1
GPIO interrupt
GPIO_INT2
GPIO interrupt
GPIO_INT3
GPIO interrupt
GPIO_INT4
GPIO interrupt
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Table 7-30. EDMA3CC0 Events for 66AK2E0x (continued)
EVENT NO.
37
EVENT NAME
DESCRIPTION
GPIO_INT5
GPIO interrupt
38
GPIO_INT6
GPIO interrupt
39
GPIO_INT7
GPIO interrupt
40
TIMER_0_INTL
Timer interrupt low
41
TIMER_0_INTH
Timer interrupt high
42
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
SEM_INT0
Timer interrupt low
43
Timer interrupt high
44
Timer interrupt low
45
Timer interrupt high
46
Semaphore interrupt
47
SEM_INT8
Semaphore interrupt
48
SEM_INT9
Semaphore interrupt
49
SEM_INT10
Semaphore interrupt
50
SEM_INT11
Semaphore interrupt
51
SEM_INT12
Semaphore interrupt
52
DBGTBR_DMAINT
ARM_TBR_DMA
QMSS_QUE_PEND_560
QMSS_QUE_PEND_561
QMSS_QUE_PEND_562
QMSS_QUE_PEND_563
QMSS_QUE_PEND_564
QMSS_QUE_PEND_565
QMSS_QUE_PEND_566
QMSS_QUE_PEND_567
QMSS_QUE_PEND_568
QMSS_QUE_PEND_569
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
53
54
55
56
57
58
59
60
61
62
63
Table 7-31. EDMA3CC1 Events for 66AK2E0x
EVENT NO.
EVENT NAME
DESCRIPTION
0
GPIO_INT28
GPIO interrupt
1
GPIO_INT29
GPIO interrupt
2
SPI_0_XEVT
SPI0 transmit event
3
SPI_0_REVT
SPI0 receive event
4
SEM_INT8
Semaphore interrupt
5
SEM_INT9
Semaphore interrupt
6
GPIO_INT0
GPIO interrupt
7
GPIO_INT1
GPIO interrupt
8
GPIO_INT2
GPIO interrupt
9
GPIO_INT3
GPIO interrupt
10
11
12
13
14
15
16
QMSS_QUE_PEND_570
QMSS_QUE_PEND_571
QMSS_QUE_PEND_572
QMSS_QUE_PEND_573
SEM_INT0
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Semaphore interrupt
QMSS_QUE_PEND_574
QMSS_QUE_PEND_575
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
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Table 7-31. EDMA3CC1 Events for 66AK2E0x (continued)
EVENT NO.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
EVENT NAME
DESCRIPTION
QMSS_QUE_PEND_576
QMSS_QUE_PEND_577
QMSS_QUE_PEND_578
QMSS_QUE_PEND_579
QMSS_QUE_PEND_580
TIMER_8_INTL
TIMER_8_INTH
TIMER_9_INTL
TIMER_9_INTH
TIMER_10_INTL
TIMER_10_INTH
TIMER_11_INTL
TIMER_11_INTH
TIMER_12_INTL
TIMER_12_INTH
TIMER_13_INTL
TIMER_13_INTH
TIMER_14_INTL
TIMER_14_INTH
TIMER_15_INTL
TIMER_15_INTH
SEM_INT10
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Semaphore interrupt
SEM_INT11
Semaphore interrupt
SEM_INT12
Semaphore interrupt
SR_0_SR_TEMPSENSOR
TSIP_RCV_FINT0
TSIP_XMT_FINT0
TSIP_RCV_SFINT0
TSIP_XMT_SFINT0
TSIP_RCV_FINT1
TSIP_XMT_FINT1
TSIP_RCV_SFINT1
TSIP_XMT_SFINT1
CIC_2_OUT8
SmartReflex temperature threshold crossing interrupt
TSIP receive frame interrupt for Channel 0
TSIP transmit frame interrupt for Channel 0
TSIP receive super frame interrupt for Channel 0
TSIP transmit super frame interrupt for Channel 0
TSIP receive frame interrupt for Channel 1
TSIP transmit frame interrupt for Channel 1
TSIP receive super frame interrupt for Channel 1
TSIP transmit super frame interrupt for Channel 1
CIC2 Interrupt Controller output
GPIO interrupt
GPIO_INT30
GPIO_INT31
GPIO interrupt
I2C_0_REVT
I2C0 receive
I2C_0_XEVT
I2C0 transmit
CIC_2_OUT13
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
Reserved
CIC_2_OUT14
CIC_2_OUT15
CIC_2_OUT16
CIC_2_OUT17
CIC_2_OUT18
CIC_2_OUT19
Reserved
Reserved
Reserved
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Table 7-32. EDMA3CC2 Events for 66AK2E0x
EVENT NO.
0
EVENT NAME
UART_1_URXEVT
UART_1_UTXEVT
SPI_1_XEVT
SPI_1_REVT
SPI_2_XEVT
SPI_2_REVT
DBGTBR_DMAINT
ARM_TBR_DMA
TIMER_0_INTL
TIMER_0_INTH
I2C_1_REVT
I2C_1_XEVT
DESCRIPTION
UART1 receive event
UART1 transmit event
SPI1 receive event
SPI1 transmit event
SPI2 receive event
SPI2 transmit event
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
Timer interrupt low
Timer interrupt high
I2C1 receive
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I2C1 transmit
I2C_2_REVT
I2C_2_XEVT
I2C2 receive
I2C2 transmit
GPIO_INT16
GPIO interrupt
GPIO_INT17
GPIO interrupt
GPIO_INT18
GPIO interrupt
GPIO_INT19
GPIO interrupt
GPIO_INT20
GPIO interrupt
GPIO_INT21
GPIO interrupt
GPIO_INT22
GPIO interrupt
GPIO_INT23
GPIO interrupt
GPIO_INT24
GPIO interrupt
GPIO_INT25
GPIO interrupt
GPIO_INT26
GPIO interrupt
GPIO_INT27
GPIO interrupt
GPIO_INT0
GPIO interrupt
GPIO_INT1
GPIO interrupt
GPIO_INT2
GPIO interrupt
GPIO_INT3
GPIO interrupt
GPIO_INT4
GPIO interrupt
GPIO_INT5
GPIO interrupt
GPIO_INT6
GPIO interrupt
GPIO_INT7
GPIO interrupt
ARM_NCNTVIRQ3
ARM_NCNTVIRQ2
ARM_NCNTVIRQ1
ARM_NCNTVIRQ0
CIC_2_OUT48
TETB_FULLINT0
UART_0_URXEVT
UART_0_UTXEVT
CIC_2_OUT22
CIC_2_OUT23
CIC_2_OUT24
CIC_2_OUT25
CIC_2_OUT26
ARM virtual timer interrupt for core 3
ARM virtual timer interrupt for core 2
ARM virtual timer interrupt for core 1
ARM virtual timer interrupt for core 0
CIC2 Interrupt Controller output
ETB0 full
UART0 receive event
UART0 transmit event
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
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Table 7-32. EDMA3CC2 Events for 66AK2E0x (continued)
EVENT NO.
EVENT NAME
DESCRIPTION
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
CIC_2_OUT27
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
SPI0 receive event
CIC_2_OUT28
SPI_0_XEVT
SPI_0_REVT
SPI0 transmit event
TETB_HFULLINT0
ETB0 half full
ARM_NCNTPNSIRQ3
ARM_NCNTPNSIRQ2
ARM_NCNTPNSIRQ1
ARM_NCNTPNSIRQ0
QMSS_QUE_PEND_581
QMSS_QUE_PEND_582
QMSS_QUE_PEND_583
QMSS_QUE_PEND_584
QMSS_QUE_PEND_585
QMSS_QUE_PEND_586
QMSS_QUE_PEND_587
QMSS_QUE_PEND_588
ARM non secure timer interrupt for Core 3
ARM non secure timer interrupt for Core 2
ARM non secure timer interrupt for Core 1
ARM non secure timer interrupt for Core 0
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Table 7-33. EDMA3CC3 Events for 66AK2E0x
EVENT NO.
EVENT NAME
Reserved
DESCRIPTION
0
Reserved
1
Reserved
Reserved
2
SPI_2_XEVT
SPI2 transmit event
SPI2 receive event
I2C2 receive
3
SPI_2_REVT
4
I2C_2_REVT
5
I2C_2_XEVT
I2C2 transmit
6
UART_1_URXEVT
UART_1_UTXEVT
TETB_FULLINT0
TETB_HFULLINT0
SPI_1_XEVT
UART1 receive event
UART1 transmit event
ETB0 full
7
8
9
ETB0 half full
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SPI1 transmit event
SPI1 receive event
I2C0 receive
SPI_1_REVT
I2C_0_REVT
I2C_0_XEVT
I2C0 transmit
I2C_1_REVT
I2C1 receive
I2C_1_XEVT
I2C1 transmit
TIMER_16_INTL
TIMER_16_INTH
TIMER_17_INTL
TIMER_17_INTH
ARM_TBR_DMA
DBGTBR_DMAINT
UART_0_URXEVT
UART_0_UTXEVT
GPIO_INT16
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
UART0 receive event
UART0 transmit event
GPIO interrupt
GPIO_INT17
GPIO interrupt
GPIO_INT18
GPIO interrupt
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Table 7-33. EDMA3CC3 Events for 66AK2E0x (continued)
EVENT NO.
27
EVENT NAME
DESCRIPTION
GPIO_INT19
GPIO interrupt
28
GPIO_INT20
GPIO interrupt
29
GPIO_INT21
GPIO interrupt
30
GPIO_INT22
GPIO interrupt
31
GPIO_INT23
GPIO interrupt
32
GPIO_INT24
GPIO interrupt
33
GPIO_INT25
GPIO interrupt
34
GPIO_INT26
GPIO interrupt
35
GPIO_INT27
GPIO interrupt
36
GPIO_INT28
GPIO interrupt
37
GPIO_INT29
GPIO interrupt
38
GPIO_INT30
GPIO interrupt
39
GPIO_INT31
GPIO interrupt
40
QMSS_QUE_PEND_589
QMSS_QUE_PEND_590
QMSS_QUE_PEND_591
QMSS_QUE_PEND_592
QMSS_QUE_PEND_593
QMSS_QUE_PEND_594
QMSS_QUE_PEND_595
QMSS_QUE_PEND_596
QMSS_QUE_PEND_597
QMSS_QUE_PEND_598
QMSS_QUE_PEND_599
QMSS_QUE_PEND_600
QMSS_QUE_PEND_601
QMSS_QUE_PEND_602
QMSS_QUE_PEND_603
QMSS_QUE_PEND_604
CIC_2_OUT57
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
CIC2 Interrupt Controller output
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
CIC_2_OUT50
CIC2 Interrupt Controller output
58
CIC_2_OUT51
CIC2 Interrupt Controller output
59
CIC_2_OUT52
CIC2 Interrupt Controller output
60
CIC_2_OUT53
CIC2 Interrupt Controller output
61
CIC_2_OUT54
CIC2 Interrupt Controller output
62
CIC_2_OUT55
CIC2 Interrupt Controller output
63
CIC_2_OUT56
CIC2 Interrupt Controller output
Table 7-34. EDMA3CC4 Events for 66AK2E0x
EVENT NO.
EVENT NAME
GPIO_INT16
GPIO_INT17
GPIO_INT18
GPIO_INT19
GPIO_INT20
GPIO_INT21
GPIO_INT22
DESCRIPTION
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
0
1
2
3
4
5
6
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Table 7-34. EDMA3CC4 Events for 66AK2E0x (continued)
EVENT NO.
7
EVENT NAME
DESCRIPTION
GPIO_INT23
GPIO interrupt
8
GPIO_INT24
GPIO interrupt
9
GPIO_INT25
GPIO interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
GPIO_INT26
GPIO interrupt
GPIO_INT27
GPIO interrupt
GPIO_INT28
GPIO interrupt
GPIO_INT29
GPIO interrupt
GPIO_INT30
GPIO interrupt
GPIO_INT31
GPIO interrupt
SEM_INT0
Semaphore interrupt
SEM_INT8
Semaphore interrupt
SEM_INT9
Semaphore interrupt
SEM_INT10
Semaphore interrupt
SEM_INT11
Semaphore interrupt
SEM_INT12
Semaphore interrupt
TIMER_12_INTL
Timer interrupt low
TIMER_12_INTH
TIMER_8_INTL
Timer interrupt high
Timer interrupt low
TIMER_8_INTH
Timer interrupt high
TIMER_14_INTL
Timer interrupt low
TIMER_14_INTH
TIMER_15_INTL
Timer interrupt high
Timer interrupt low
TIMER_15_INTH
DBGTBR_DMAINT
ARM_TBR_DMA
QMSS_QUE_PEND_658
QMSS_QUE_PEND_659
QMSS_QUE_PEND_660
QMSS_QUE_PEND_661
QMSS_QUE_PEND_662
QMSS_QUE_PEND_663
QMSS_QUE_PEND_664
QMSS_QUE_PEND_665
QMSS_QUE_PEND_605
QMSS_QUE_PEND_606
QMSS_QUE_PEND_607
QMSS_QUE_PEND_608
QMSS_QUE_PEND_609
QMSS_QUE_PEND_610
QMSS_QUE_PEND_611
QMSS_QUE_PEND_612
ARM_NCNTVIRQ3
ARM_NCNTVIRQ2
ARM_NCNTVIRQ1
ARM_NCNTVIRQ0
ARM_NCNTPNSIRQ3
ARM_NCNTPNSIRQ2
Timer interrupt high
Debug trace buffer (TBR) DMA event
ARM trace buffer (TBR) DMA event
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
Navigator transmit queue pending event for indicated queue
ARM virtual timer interrupt for Core 3
ARM virtual timer interrupt for Core 2
ARM virtual timer interrupt for Core 1
ARM virtual timer interrupt for Core 0
ARM non secure timer interrupt for Core 3
ARM non secure timer interrupt for Core 2
138
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 7-34. EDMA3CC4 Events for 66AK2E0x (continued)
EVENT NO.
EVENT NAME
ARM_NCNTPNSIRQ1
ARM_NCNTPNSIRQ0
CIC_2_OUT82
CIC_2_OUT83
CIC_2_OUT84
CIC_2_OUT85
CIC_2_OUT86
CIC_2_OUT87
CIC_2_OUT88
CIC_2_OUT89
DESCRIPTION
54
55
56
57
58
59
60
61
62
63
ARM non secure timer interrupt for Core 1
ARM non secure timer interrupt for Core 0
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
CIC2 Interrupt Controller output
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Memory, Interrupts, and EDMA for 66AK2E0x
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8 System Interconnect
On the KeyStone II devices, the C66x CorePac, the EDMA3 transfer controllers and the system
peripherals are interconnected through the TeraNets, which are non-blocking switch fabrics enabling fast
and contention-free internal data movement. The TeraNets provide low-latency, concurrent data transfers
between master peripherals and slave peripherals. The TeraNets also allow for seamless arbitration
between the system masters when accessing system slaves.
The ARM CorePac is connected to the MSMC and the debug subsystem directly, and to other masters via
the TeraNets. Through the MSMC, the ARM CorePacs can be interconnected to DDR3 and TeraNet 3_A,
which allows the ARM CorePacs to access to the peripheral buses:
•
•
TeraNet 3P_A for peripheral configuration
TeraNet 6P_A for ARM Boot ROM
8.1 Internal Buses and Switch Fabrics
The C66x CorePacs, the ARM CorePacs, the EDMA3 traffic controllers, and the various system
peripherals can be classified into two categories: masters and slaves.
•
Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3
for their data transfers.
•
Slaves on the other hand rely on the masters to perform transfers to and from them.
Examples of masters include the EDMA3 traffic controllers and network coprocessor packet DMA.
Examples of slaves include the SPI, UART, and I2C.
The masters and slaves in the device communicate through the TeraNet (switch fabric). The device
contains two types of switch fabric:
•
•
Data TeraNet is a high-throughput interconnect mainly used to move data across the system
Configuration TeraNet is mainly used to access peripheral registers
Some peripherals have both a data bus and a configuration bus interface, while others only have one type
of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.
Note that the data TeraNet also connects to the configuration TeraNet.
8.2 Switch Fabric Connections Matrix - Data Space
The figures below show the connections between masters and slaves through various sections of the
TeraNet.
140
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66AK2E
Bridge_11
Bridge_1
Tracer_SPI_
ROM_EMIF16
Bridge_2
Bridge_3
From TeraNet_3_C
MPU_8
MPU_12
MPU_13
MPU_14
EMIF16
SPI_0
S
S
S
S
S
SPI_1
TNet_6P_A
CPU/6
SPI_2
QM
Packet DMA
M
M
Boot_ROM
QM_2
Packet DMA
Boot_ROM
ARM
S
TNet_3_D
CPU/3
Debug_SS
TSIP
M
M
Bridge_5
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
TNet_3_G
CPU/3
USB_0_MST
M
To TeraNet_3_C
Bridge_12
Bridge_13
Bridge_14
To TeraNet_3P_A
Figure 8-1. TeraNet 3_A-1
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System Interconnect
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NETCP_
Global_0
MPU_1
QM_SS
S
M
Tracer_QM_M
Tracer_SPI_
ROM_EMIF16
NETCP_
Global_1
M
PCIe
S
10GbE
M
TC_0
M
TC_1
M
M
M
EDMA
CC1
TC_2
TC_3
TC_0
TC_1
TC_2
TC_3
M
M
M
M
EDMA
CC2
TC_0
TC_1
EDMA
CC3
M
M
TNet_3_L
CPU/3
L2 Cache_0_A
L2 Cache_0_B
To TeraNet C66x SDMA
PCIe_0
PCIe_1
M
M
66AK2E
Figure 8-2. TeraNet 3_A-2
142
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
XMC ´ 8
66AK2E
ARM CorePac
MPU_15
USB_1 MMR CFG
S
USB_1 PHY CFG
S
NetCP
S
NETCP_LOCAL
HyperLink_0
M
M
Tracer_NETCP_
USB_CFG
USB_1
M
S
Tracer_
MSMC0-8
SES
S
S
MSMC
SMS
DDR3
M
M
BR_SES_0
BR_SES_1
BR_SES_2
Bridge_5
TNet_SES
CPU/1
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
From TeraNet_3_A
BR_SMS_0
BR_SMS_1
BR_SMS_2
TNet_SMS
CPU/1
To TeraNet_3_A
To TeraNet_3P_A
TNet_msmc_sys
CPU/1
QM_Second
M
TC_0
TC_1
EDMA
CC0
M
M
TNet_3_U
CPU/3
CPU Port
Sys Port
MPU_7
PCIe_1
TC_0
TC_1
EDMA
CC4
M
M
Tracer_PCIe1
Bridge_1
Bridge_2
Bridge_3
To TeraNet_3_A
Figure 8-3. TeraNet 3_C
66AK2E
L2 Cache_0_A
L2 Cache_0_B
TNet_3_M
CPU/3
CorePac_0
From TeraNet 3_A-2
S
Tracer_L2_0
Figure 8-4. TeraNet C66x to SDMA
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The following table lists the master and slave end-point connections.
Intersecting cells may contain one of the following:
•
•
•
Y — There is a connection between this master and that slave.
- — There is NO connection between this master and that slave.
n — A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 8-1. 66AK2E05/02 Data Space Interconnect
SLAVES
MASTERS
QM
10GbE
-
-
-
Y
-
-
-
-
-
SES_2
SMS_2
Y
-
Y
-
Y
-
-
CorePac0_CFG
CPT_CFG
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
CPT_DDR3
-
-
-
-
-
-
-
-
-
-
-
CPT_INTC
-
-
-
-
-
-
-
-
-
-
CPT_L2_0
-
-
-
-
-
-
-
-
-
-
-
CPT_MSMC(0-7)
CPT_QM_CFG1
CPT_QM_CFG2
CPT_QM_M
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CPT_SPI_ROM_EMIF16
CPT_TPCC(0_4)T
CPT_TPCC(1_2_3)T
DBG_DAP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
-
Y
Y
-
Y
Y
Y
Y
-
Y
Y
-
Y
Y
-
Y
TSIP_DMA
Y
Y
Y
Y
Y
Y
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
-
-
-
-
-
-
2, 11
2, 11
3, 11
3, 11
-
2, 11
2, 11
Y
Y
Y
Y
-
-
Y
Y
Y
Y
-
SES_0
SES_0
SES_1
SES_1
-
SMS_0
SMS_0
SMS_1
SMS_1
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
-
2, 11
2,11
3, 11
3, 11
-
-
-
-
3, 11
3, 11
-
-
-
-
-
-
-
-
-
11
11
11
11
11
11
11
11
-
11
-
11
-
Y
Y
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
Y
Y
Y
Y
-
SES_0
SES_0
SES_1
SES_1
SES_1
SES_1
SES_1
SES_1
-
SMS_0
SMS_0
SMS_1
SMS_1
SMS_1
SMS_1
SMS_1
SMS_1
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
-
11
11
11
11
11
11
11
11
-
Y
-
Y
-
Y
-
-
Y
-
Y
-
-
-
-
Y
-
Y
-
-
-
Y
-
-
-
-
-
11
11
11
11
11
Y
-
Y
-
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
SES_2
SES_2
SES_2
SES_2
SES_0
SMS_2
SMS_2
SMS_2
SMS_2
SMS_0
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
11
11
11
11
11
Y
-
Y
-
Y
-
-
Y
Y
-
144
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SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 8-1. 66AK2E05/02 Data Space Interconnect (continued)
SLAVES
MASTERS
QM
-
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0_Master
MSMC_SYS
11
11
11
-
-
-
Y
Y
Y
-
Y
-
Y
SES_0
SES_0
SES_0
-
SMS_0
SMS_0
SMS_0
-
Y
Y
Y
-
Y
Y
Y
-
11
11
11
-
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
11
11
11
11
-
Y
Y
Y
Y
Y
Y
-
-
Y
Y
Y
Y
-
SES_1
SES_1
SES_1
SES_1
-
SMS_1
SMS_1
SMS_1
SMS_1
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
-
11
11
11
11
-
-
-
Y
-
Y
Y
-
-
-
-
-
-
-
-
2, 11
2, 11
3, 11
3, 11
11
11
-
2, 11
2, 11
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
-
SES_1
SES_1
SES_1
SES_1
Y
SMS_1
SMS_1
SMS_1
SMS_1
Y
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
-
2, 11
2, 11
3, 11
3, 11
Y
-
-
-
3, 11
3, 11
-
-
-
-
-
1, 11
1, 11
-
Y
Y
Y
Y
Y
Y
Y
-
11
-
11
-
Y
-
Y
-
-
-
11
-
NETCP
SES_1
SES_2
SES_2
SES_0
SES_1
SES_2
SES_0
SES_0
SMS_1
SMS_2
SMS_2
SMS_0
SMS_1
SMS_2
SMS_0
SMS_0
PCIE0
11
11
-
-
-
Y
Y
-
10
10
Y
Y
Y
Y
Y
11
11
-
PCIE1
-
-
-
-
QM_Master1
QM_Master2
QM_SEC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
-
-
-
USB0
-
-
-
-
-
Y
Y
-
USB1
-
-
-
-
-
-
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8.3 Switch Fabric Connections Matrix - Configuration Space
The figures below show the connections between masters and slaves through various sections of the
TeraNet.
MPU (´ 15)
S
Bridge_12
From TeraNet_3_A
From TeraNet_3_C
QM_SS_
CFG1
MPU_2
Bridge_13
Bridge_14
M
Tracer_QM_CFG1
QM_SS_
CFG2
MPU_6
M
S
Tracer_QM_CFG2
Tracer_SM
MPU_10
Semaphore
CC0
S
S
TC (´ 2)
Tracer
_EDMA
CC0 & CC4
TNet_3P_M
CPU/3
CC4
S
S
TC (´ 2)
CC1
S
S
TC (´ 4)
CorePac_0
M
Tracer
_EDMA
CC1 - CC3
CC2
S
S
TNet_3P_C
CPU/3
TC (´ 4)
CC3
S
S
TC (´ 2)
ARM INTC
S
S
TNet_3P_L
CPU/3
MPU_9
CP_INTC02
Tracer_INTC
TETB
CorePac
DBG_TBR_SYS
(Debug_SS)
TBR_SYS_
ARM_CorePac
To TeraNet_3P_B
MPU_0
Tracer_CFG
To TeraNet_3P_Tracer
66AK2E
Figure 8-5. TeraNet 3P_A
146
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TNet_3P_N
CPU/3
CP_T0-T8
(MSMC)
From TeraNet_3P_A
S
S
TNet_3P_D
CPU/3
CP_T (´ 12)
NetCP
TSIP
S
S
S
10GbE CFG
66AK2E05 Only
MPU_11
Bridge 20
To TeraNet_6P_B
66AK2E
Figure 8-6. TeraNet 3P_B
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Timer (´ 12)
S
S
S
S
S
S
S
S
S
S
Bridge 20
USIM
From TeraNet_3P_B
OTP
Debug SS
PLL_CTL
GPSC
BOOT_CFG
UART (´ 2)
I2C (´ 3)
GPIO
USB PHY CFG 0-1
S
S
PCIe SerDes CFG 0-1
HyperLink SerDes
CFG 0-1
S
S
XGE SerDes CFG
66AK2E05 Only
NetCP SerDes CFG
DDR3 PHY CFG
USB MMR CFG 0-1
SmartReflex
S
S
S
S
66AK2E
Figure 8-7. TeraNet 6P_B
148
System Interconnect
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66AK2E
Tracer_MSMC_0
Tracer_MSMC_1
Tracer_MSMC_2
Tracer_MSMC_3
Tracer_MSMC_4
Tracer_MSMC_5
Tracer_MSMC_6
Tracer_MSMC_7
Tracer_MSMC_8
M
M
M
M
M
M
M
M
M
From TeraNet_3P_A
Tracer_SM
Tracer_CIC
M
M
M
M
M
M
M
Debug_SS
STM
S
Tracer_QM_CFG1
Tracer_QM_CFG2
Tracer_QM_M
Tracer_L2
Tracer_CFG
Tracer_EDMA3CC0_4
M
M
Tracer_EDMA3CC1_2_3
Tracer_SPI_
ROM_EMIF16
M
Figure 8-8. TeraNet 3P_Tracer
The following tables list the master and slave end point connections.
Intersecting cells may contain one of the following:
•
•
•
Y — There is a connection between this master and that slave.
- — There is NO connection between this master and that slave.
n — A numeric value indicates that the path between this master and that slave goes through bridge n.
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Table 8-2. Configuration Space Interconnect - Section 1
SLAVES
MASTERS
CorePac0_CFG
DBG_DAP
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
-
TSIP_DMA
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
12
Y
MSMC_SYS
150
System Interconnect
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 8-2. Configuration Space Interconnect - Section 1 (continued)
SLAVES
MASTERS
NETCP
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
-
12
12
-
PCIE0
PCIE1
QM_Master1
QM_Master2
QM_SEC
USB0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USB1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 8-3. Configuration Space Interconnect - Section 2
SLAVES
MASTERS
CorePac0_CFG
DBG_DAP
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
-
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
Y
-
Y
Y
-
Y
Y
-
TSIP_DMA
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
-
12
-
-
12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12
-
-
-
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
-
-
-
-
13 13 13 13 13 13 13 13 13 13
13 13 13 13 13 13 13 13 13 13
14 14 14 14 14 14 14 14 14 14
14 14 14 14 14 14 14 14 14 14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Copyright © 2012–2015, Texas Instruments Incorporated
System Interconnect
151
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02
66AK2E05, 66AK2E02
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
www.ti.com
Table 8-3. Configuration Space Interconnect - Section 2 (continued)
SLAVES
MASTERS
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0_Master
MSMC_SYS
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12
-
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
-
-
13 13 13 13 13 13 13 13 13 13
13 13 13 13 13 13 13 13 13 13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
12
-
-
-
-
-
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
-
-
-
14 14 14 14 14 14 14 14 14 14
14 14 14 14 14 14 14 14 14 14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
-
-
14
-
-
-
-
-
-
-
-
14 14 14 14 14 14 14 14 14 14
14 14 14 14 14 14 14 14 14 14
-
-
-
-
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12
-
-
12
-
-
12
Y
-
-
12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
NETCP
PCIE0
12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12
12 12 12 12 12 12 12 12 12 12 12 12
PCIE1
QM_Master1
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
-
-
-
-
-
12
12
-
-
-
-
-
-
12
12
-
-
-
-
-
-
12
12
-
-
-
-
-
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
QM_Master2
QM_SEC
-
12
-
USB0
12
12
-
-
-
-
-
USB1
-
-
-
-
-
-
Table 8-4. Configuration Space Interconnect - Section 3
SLAVES
MASTERS
CorePac0_CFG
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
152
System Interconnect
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: 66AK2E05 66AK2E02
66AK2E05, 66AK2E02
www.ti.com
SPRS865D –NOVEMBER 2012–REVISED MARCH 2015
Table 8-4. Configuration Space Interconnect - Section 3 (continued)
SLAVES
MASTERS
DBG_DAP
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
Y
Y
-
TSIP_DMA
EDMA0_CC_TR
EDMA0_TC0_RD
EDMA0_TC0_WR
EDMA0_TC1_RD
EDMA0_TC1_WR
EDMA1_CC_TR
EDMA1_TC0_RD
EDMA1_TC0_WR
EDMA1_TC1_RD
EDMA1_TC1_WR
EDMA1_TC2_RD
EDMA1_TC2_WR
EDMA1_TC3_RD
EDMA1_TC3_WR
EDMA2_CC_TR
EDMA2_TC0_RD
EDMA2_TC0_WR
EDMA2_TC1_RD
EDMA2_TC1_WR
EDMA2_TC2_RD
EDMA2_TC2_WR
EDMA2_TC3_RD
EDMA2_TC3_WR
EDMA3_CC_TR
EDMA3_TC0_RD
EDMA3_TC0_WR
EDMA3_TC1_RD
EDMA3_TC1_WR
EDMA4_CC_TR
EDMA4_TC0_RD
EDMA4_TC0_WR
EDMA4_TC1_RD
EDMA4_TC1_WR
HyperLink0_Master
MSMC_SYS
-
-
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
-
-
-
-
12
-
12
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
13
-
13
-
-
-
-
-
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
14
-
-
-
-
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
-
-
-
-
12
-
12
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
-
-
-
-
Y
-
Y
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
13
-
13
-
-
-
-
-
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
-
-
-
-
12
-
12
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
14
-
14
-
-
-
-
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
13
13
-
13
13
-
13
13
-
13
-
13
-
13
-
13
-
13
-
13
-
13
-
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
13
13
-
14
-
14
-
14
-
14
-
14
-
14
-
14
-
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
12
12
12
Y
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
Y
-
12
Y
-
-
-
-
-
-
-
-
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
12
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
NETCP
PCIE0
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
PCIE1
QM_Master1
QM_Master2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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Table 8-4. Configuration Space Interconnect - Section 3 (continued)
SLAVES
MASTERS
QM_SEC
USB0
-
-
-
-
-
-
12
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
-
-
-
12
-
-
-
-
-
-
-
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
USB1
-
-
8.4 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User-programmable
priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower
number means higher priority — PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include
the C66x CorePacs, whose priorities are set through software in the UMC control registers. All the Packet
DMA-based peripherals also have internal registers to define the priority level of their initiated
transactions.
The Packet DMA secondary port is one master port that does not have priority allocation register inside
the Multicore Navigator. The priority level for transaction from this master port is described by the
QM_PRIORITY bit field in the CHIP_MISC_CTL0 register shown in Figure 9-33 and Table 9-53.
For all other modules, see the respective User's Guides listed in Section 3.5 for programmable priority
registers.
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9 Device Boot and Configuration
9.1 Device Boot
9.1.1 Boot Sequence
The boot sequence is a process by which the internal memory is loaded with program and data sections.
The boot sequence is started automatically after each power-on reset or warm reset.
The
66AK2E0x supports several boot processes that begins execution at the ROM base address, which
contains the bootloader code necessary to support various device boot modes. The boot processes are
software-driven and use the BOOTMODE[15:0] device configuration inputs to determine the software
configuration that must be completed. For more details on boot sequence see the KeyStone II Architecture
ARM Bootloader User's Guide (SPRUHJ3).
For 66AK2E0x non-secure devices, there is only one type of booting: the ARM CorePac as the boot
master.The C66x CorePac as the boot master is not supported. The ARM CorePac does not support no-
boot mode. The C66x CorePacs and the ARM CorePac needs to read the bootmode register to determine
how to proceed with the boot.
Table 9-1 shows memory space reserved for boot by the C66x CorePac.
Table 9-1. C66x DSP Boot RAM Memory Map
START ADDRESS SIZE
DESCRIPTION
0x80_0000
0x86_bf80
0x86_c000
0x87_3ff0
0x87_4000
0x87_b800
0x87_c000
0x87_e290
0x87_e320
0x87_e410
0x87_f91c
0x87_fd20
0x87_fea0
0x87_ff00
0x87_fff8
0x1_0000
0x80
0x7ff0
4
Reserved
C66x CorePac ROM Version string
Boot Master Table Overlayed With scratch
Host Data Address (boot magic address for secure boot through master peripherals)
0x7800
0x410
0x2290
0x90
0x20
0xf0
Boot Data
Secure Host Data Structure
Boot Stack
Boot Log Data
Boot Status Stack
Boot Stats
0x404
0x180
0x60
0x80
4
Boot Trace Info
DDR3 Configuration Structure
Boot RAM Call Table
Boot Parameter Table
Secure Signal Magic Address
Boot Magic Address
0x87_fffc
4
Table 9-2 shows addresses reserved for boot by the ARM CorePac.
Table 9-2. ARM Boot RAM Memory Map
START ADDRESS SIZE
DESCRIPTION
0xc17_e000
0xc18_6f80
0xc18_7000
0xc18_c000
0xc18_d000
0xc18_e000
0xc18_f000
0xc00
Context RAM not Scrubbed on Secure boot
Global Level 0 Non-secure Translation table
Global Non-secure Page Table for memory Covering ROM
Core 0 Non-secure Level 1 Translation table
Core 1 Non-secure Level 1 Translation table
Core 2 Non-secure Level 1 Translation table
Core 3 Non-secure Level 1 Translation table
0x80
0x5000
0x1000
0x1000
0x1000
0x1000
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Table 9-2. ARM Boot RAM Memory Map (continued)
START ADDRESS SIZE
0x7e80
DESCRIPTION
0xc19_0000
0xc19_7e80
0xc19_7f00
0xc1a_6e00
0xc1a_7000
0xc1a_a000
0xc1a_d000
0xc1a_d004
0xc1a_d008
0xc1a_d00c
0xc1a_e000
0xc1a_e400
0xc1a_e800
0xc1a_ec00
0xc1a_f000
0xc1a_f400
0xc1a_f800
0xc1a_fc00
0xc1b_0000
0xc1b_0180
0xc1b_0200
0xc1b_0300
0xc1b_0400
0xc1b_0500
0xc1b_0600
0xc1b_1fe0
0xc1b_4000
0xc1b_4180
0xc1b_4200
0xc1b_4300
0xc1b_4400
0xc1b_4500
0xc1b_4600
0xc1b_5fe0
0xc1b_6000
0xc1b_6180
0xc1b_6200
0xc1b_6300
0xc1b_6400
0xc1b_6500
0xc1b_6600
0xc1b_7fe0
0xc1b_8000
0xc1b_8180
0xc1b_8200
0xc1b_8300
0xc1b_8400
Packet Memory Buffer
080
PCIE Block
4
Host Data Address (boot magic address for secure boot through master peripherals)
DDR3 Configuration Structure
Boot Data
0x200
0x3000
0x3000
4
Supervisor Stack, Each Core Gets 0xc000 Bytes
ARM Boot Magic Address, Core 0
ARM Boot Magic Address, Core 1
ARM Boot Magic Address, Core 2
ARM Boot Magic Address, Core 3
Abort Stack, Core 0
4
4
4
0x400
0x400
0x400
0x400
0x400
0x400
0x400
0x400
0x180
0x80
Abort Stack, Core 1
Abort Stack, Core 2
Abort Stack, Core 3
Unknown Mode Stack, Core 0
Unknown mOde Stack, Core 1
Unknown Mode Stack, Core 2
Unknown Mode Stack, Core 3
Boot Version String, Core 0
Boot Status Stack, Core 0
Boot Stats, Core 0
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x180
0x80
Boot Log, Core 0
Boot RAM Call Table, Core 0
Boot Parameter Tables, Core 0
Boot Data, Core 0
Boot Trace, Core 0
Boot Version String, Core 1
Boot Status Stack, Core 1
Boot Stats, Core 1
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x180
0x80
Boot Log, Core 1
Boot RAM Call Table, Core 1
Boot Parameter Tables, Core 1
Boot Data, Core 1
Boot Trace, Core 1
Boot Version String, Core 2
Boot Status Stack, Core 2
Boot Stats, Core 2
0x100
0x100
0x100
0x100
0x19e0
0x1010
0x180
0x80
Boot Log, Core 2
Boot RAM Call Table, Core 2
Boot Parameter Tables, Core 2
Boot Data, Core 2
Boot Trace, Core 2
Boot Version String, Core 3
Boot Status Stack, Core 3
Boot Stats, Core 3
0x100
0x100
0x100
Boot Log, Core 3
Boot RAM Call Table, Core 3
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Table 9-2. ARM Boot RAM Memory Map (continued)
START ADDRESS SIZE
DESCRIPTION
0xc1b_8500
0xc1b_8600
0xc1b_9fe0
0xc1c_0000
0x100
Boot Parameter Tables, Core 3
Boot Data, Core 3
Boot Trace, Core 3
Secure MSMC
0x19e0
0x1010
0x4_0000
9.1.2 Boot Modes Supported
The C66x Boot Master modes are not supported only the ARM CorePac Boot Master modes are. The
device supports several boot processes, which leverage the internal boot ROM. Most boot processes are
software-driven, using the BOOTMODE[15:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are two possible boot modes:
•
Public ROM Boot when the ARM CorePac Core0 is the boot master — In this boot mode, the ARM
CorePac performs the boot process while the C66x CorePacs execute idle instructions. When the ARM
CorePac Core0 finishes the boot process, it may send interrupts to the C66x CorePacs and Cortex-
A15 processor cores through IPC registers. The C66x CorePacs complete the boot management
operations and begin executing from the predefined locations.
•
Secure ROM Boot when the ARM CorePac0 is the boot master — The C66x CorePac0 and the
ARM CorePac Core0 are released from reset simultaneously and begin executing from secure ROM.
The ARM CorePac Core0 initiates the boot process. The C66x CorePac0 performs any authentication
and decryption required on the bootloaded image for the C66x CorePacs and ARM CorePac prior to
beginning execution. For more information, refer to the Secure device Addendum.
The boot process performed by the ARM CorePac Core0 in public ROM boot and secure ROM boot are
determined by the BOOTMODE[15:0] value in the DEVSTAT register. The ARM CorePac Core0 read this
value, and then execute the associated boot process in software. The figure below shows the bits
associated with BOOTMODE[15:0] pins (DEVSTAT[16:1] register bits) when the ARM CorePac is the boot
master. Note that Figure 9-1 does not include bit 0 of the DEVSTAT contents. Bit 0 is used to select
overall system endianess that is independent of the boot mode.
The boot ROM will continue attempting to boot in this mode until successful or an unrecoverable error
occurs.
The PLL settings are shown at the end of this section, and the PLL set-up details can be found in
Section 11.5.
NOTE
It is important to keep in mind that BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits of
the DEVSTAT register.
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Figure 9-1. DEVSTAT Boot Mode Pins ROM Mapping
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
0
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
2
0
0
0
1
1
1
1
0
0
1
0
1
1
Mode
X
X
X
PLLEN
SLEEP
I2C SLAVE
I2C MASTER
SPI
SYS PLL
CONFIG
X
SlaveAddr
X
1
Port
Bus Addr
Min
Param ldx
Port
X
Port
Width
Csel
Mode
Width
Clear
Param ldx
0
1
Base Addr
First Block
0
EMIF
Wait
Chip Sel
0 (ARM Boot
Master)
Min
NAND
X
NETC
P clk
Ref clk
Ext Con
Bar Config
Data Rate
Port
Lane Setup
X
1
0
1
Ethernet
SYS PLL
CONFIG
X
Port
0
1
1
1
1
1
1
1
0
0
1
PCIe
HyperLink
UART
Port
Ref clk
X
X
Min
9.1.2.1 Boot Device Field
The Boot Device field DEVSTAT[16-14-4-3-2-1] defines the boot device that is chosen. Table 9-3 shows
the supported boot modes.
Table 9-3. Boot Mode Pins: Boot Device Values
Bit
Field
Description
16, 14, 4, 3, 2, Boot Device
1
Device boot mode - ARM is a boot master when BOOTMODE[8]=0
•
•
•
•
•
•
•
•
•
•
Sleep = X0[Min]000b
I2C Slave = [Slave Addr1]1[Min]000 b
I2C Master = XX[Min]001b
SPI = [Width][Csel0][Min]010b
EMIF = 0X0011b
NAND = 1X[Min]011b
Ethernet (SGMII) = [Pa clk][Ref Clk0][Min]101b
PCI = XBar Config2]0110b
Hyperlink = [Port][Ref Clk0]1110b
UART = XX[Min]111b
9.1.2.2 Device Configuration Field
The device configuration fields DEVSTAT[16:1] are used to configure the boot peripheral and, therefore,
the bit definitions depend on the boot mode.
9.1.2.2.1 Sleep Boot Mode Configuration
Figure 9-2. Sleep Boot Mode Configuration Fields Description
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Boot
Master
X
X
0
X
PLLEN
X
Sys PLL Config
Min
000
Lendian
Table 9-4. Sleep Boot Configuration Field Descriptions
Bit
Field
Description
16-15 Reserved
Reserved
14
Boot Devices
Boot Device- used in conjunction with Boot Devices [Used in conjunction with bits 3-1]
•
•
0 = Sleep (default)
Others = Other boot modes
13
Reserved
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Table 9-4. Sleep Boot Configuration Field Descriptions (continued)
Bit
Field
Description
12
PLLEN
Enable the System PLL
•
•
0 = PLL disabled (default)
1 = PLL enabled
11-9
8
Reserved
Reserved
Boot Master
This pin must be pulled down to GND
7-5
SYS PLL
Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
the device. Table 9-25 shows settings for various input clock frequencies.
4
Min
Minimum boot configuration select bit.
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1] used in conjunction with Boot Device [14]
3-1
0
Boot Devices
Lendian
•
•
000 = Sleep
Others = Other boot modes
Endianess (device)
•
•
0 = Big endian
1 = Little endian
9.1.2.2.2 I2C Boot Device Configuration
9.1.2.2.2.1 I2C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified
address.
Figure 9-3. I2C Passive Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Boot
Master
Slave Addr
1
Port
X
Sys PLL Config
Min
000
Lendian
Table 9-5. I2C Passive Mode Device Configuration Field Descriptions
Bit
Field
Description
16-15 Slave Addr
I2C Slave boot bus address
•
•
•
•
0 = I2C slave boot bus address is 0x00
1 = I2C slave boot bus address is 0x10 (default)
2 = I2C slave boot bus address is 0x20
3 = I2C slave boot bus address is 0x30
14
Boot Devices
Boot Device[14] used in conjunction with Boot Devices [Use din conjunction with bits 3-1]
•
0 = Other boot modes
1= I2C Slave boot mode
•
13-12 Port
I2C port number
•
•
•
•
0 = I2C0
1 = I2C1
2 = I2C2
3 = Reserved
11-9
8
Reserved
Reserved
Boot Master
This pin must be pulled down to GND
7-5
SYS PLL
Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
the device. Table 9-25 shows settings for various input clock frequencies.
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Table 9-5. I2C Passive Mode Device Configuration Field Descriptions (continued)
Bit
Field
Description
Minimum boot configuration select bit.
4
Min
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1] used in conjunction with Boot Device [14]
3-1
0
Boot Devices
Lendian
•
•
000 = I2C Slave
Others = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
9.1.2.2.2.2 I2C Master Mode
In master mode, the I2C device configuration uses ten bits of device configuration instead of seven as
used in other boot modes. In this mode, the device makes the initial read of the I2C EEPROM while the
PLL is in bypass mode. The initial read contains the desired clock multiplier, which must be set up prior to
any subsequent reads.
Figure 9-4. I2C Master Mode Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Bus Addr
Param ldx/Offset
Boot Master
Reserved
Port
Min
001
Lendian
Table 9-6. I2C Master Mode Device Configuration Field Descriptions
Bit
Field
Description
16-14 Reserved
13-12 Bus Addr
Reserved
I2C bus address slave device
•
•
•
•
0 = I2C slave boot bus address is 0x50 (default)
1 = I2C slave boot bus address is 0x51
2 = I2C slave boot bus address is 0x52
3 = I2C slave boot bus address is 0x53
11-9
Param Idx
Parameter Table Index
0-7 = This value specifies the parameter table index (default = 0)
•
8
Boot Master
Reserved
Port
This pin must be pulled down to GND
Reserved
I2C port number
7
6-5
•
•
•
•
0 = I2C0 (default)
1 = I2C1
2 = I2C2
3 = Reserved
4
Min
Minimum boot configuration select bit.
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1]
3-1
Boot Devices
•
•
001 = I2C Master
Others = Other boot modes
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Table 9-6. I2C Master Mode Device Configuration Field Descriptions (continued)
Bit
Field
Lendian
Description
0
Endianess
•
•
0 = Big endian
1 = Little endian
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9.1.2.2.3 SPI Boot Device Configuration
Figure 9-5. SPI Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
Width
15
14
13
12
11
Mode
10
9
8
7
6
5
4
3
2
1
0
Csel
Port
Boot Master
Param Ind
Min
010
Lendian
Table 9-7. SPI Device Configuration Field Descriptions
Bit
Field
Description
16-15
Width
SPI address width configuration
•
•
0 = 16-bit address values are used
1 = 24-bit address values are used (default)
14-13
12-11
Csel
The chip select field value 0-3 (default = 0)
Clk Polarity/ Phase
Mode
•
•
0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling
edges. Input data is latched on the rising edge of SPICLK.
•
•
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge (default).
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising
edges. Input data is latched on the falling edge of SPICLK.
10-9
Port
Specify SPI port
•
•
•
•
0 = SPI0 used (default)
1 = SPI1 used
2 = SPI2 used
3 = Reserved
8
Boot Master
Param Idx
This pin must be pulled down to GND
Parameter Table Index
7-5
•
0-7 = This value specifies the parameter table index (default = 0)
4
Min
Minimum boot configuration select bit.
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1]
3-1
0
Boot Devices
Lendian
•
•
010 = SPI boot mode
Others = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
9.1.2.2.4 EMIF Boot Device Configuration
Figure 9-6. EMIF Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Base Addr
Wait
Width
X
Chip Sel
Boot Master
Sys PLL Cfg
0
011
Lendian
162
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Table 9-8. EMIF Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Boot Devices
Boot Devices[16] used conjunction with Boot Devices[4] and Boot Devices [Used in conjunction with bits
3-1]
•
•
0 = EMIF boot mode
1 = Other boot modes
15-14
13
Base Addr
Wait
Base address (0-3) used to calculate the branch address. Branch address is the chip select plus
Base Address *16MB
Extended Wait
•
•
0 = Extended Wait disabled
1 = Extended Wait enabled
12
Width
EMIF Width
•
•
0 = 8-bit EMIF Width
1 = 16-bit EMIF Width
11
Reserved
Chip Sel
Reserved
10-9
Chip Sel that specifies the chip select region, EMIF16 CS2-EMIF16 CS5.
•
•
•
•
00 = EMIF16 CS2(EMIFCE0)
01 = EMIF16 CS3 (EMIFCE1)
10 = EMIF16 CS4 (EMIFCE2)
11 = EMIF16 CS5 (EMIFCE3)
8
Boot Master
This pin must be pulled down to GND
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Table 9-25 shows settings for various input clock frequencies.
4-1
0
Boot Devices
Lendian
Boot Devices[4] used conjunction with Boot Devices[16]
•
•
0011 = EMIF boot mode
1XXX = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
9.1.2.2.5 NAND Boot Device Configuration
Figure 9-7. NAND Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
First Block
Clear
X
Chip Sel
Boot Master
Sys PLL Cfg
Min
011
Lendian
Table 9-9. NAND Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Boot Devices
Boot Devices[16] used conjunction with Boot Devices [3-1]
•
•
0 = Other boot modes
1 = NAND boot mode
15-13
12
First Block
Clear
First Block. This value is used to calculate the first block read. The first block read is the first block value
*16.
ClearNAND
•
•
0 = Device is not a ClearNAND (default)
1 = Device is a ClearNAND
11-9
Chip Sel
Chip Sel that specifies the chip select region, EMIF16 CS2-EMIF16 CS5.
•
•
•
•
00 = EMIF16 CS2(EMIFCE0)
01 = EMIF16 CS3 (EMIFCE1)
10 = EMIF16 CS4 (EMIFCE2)
11 = EMIF16 CS5 (EMIFCE3)
8
Boot Master
This pin must be pulled down to GND
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Table 9-9. NAND Boot Device Configuration Field Descriptions (continued)
Bit
Field
Description
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Table 9-25 shows settings for various input clock frequencies.
4
Min
Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only
BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that
would normally be set by the other BOOTMODE pins when Min is 0.
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
3-1
0
Boot Devices
Lendian
Boot Devices
•
•
011 = NAND boot mode
Others = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
9.1.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 9-8. Ethernet (SGMII) Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
Lane
Setup
9
8
7
6
5
4
3
2
1
0
NETCP
clk
Ref Clock
Ext Con
X
Boot Master
Sys PLL Cfg
Min
101
Lendian
Table 9-10. Ethernet (SGMII) Boot Device Configuration Field Descriptions
Bit
Field
Description
16
NETCP clk
NETCP clock reference
•
•
0 = NETCP clocked at the same reference as the core reference
1 = NETCP clocked at the same reference as the SerDes reference (default)
15-14
Ref Clock
Reference clock frequency
•
•
•
•
0 = 125MHz
1 = 156.25MHz (default)
2 = Reserved
3 = Reserved
13-12
11-9
Ext Con
External connection mode
•
•
•
•
0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave with auto negotiation (default)
2 = MAC to MAC, forced link, maximum speed
3 = MAC to fiber connection
Lane Setup
Lane Setup.
•
•
•
•
•
0 = All SGMII ports enabled (default)
1 = Only SGMII port 0 enabled
2 = SGMII port 0 and 1 enabled
3 = SGMII port 0, 1 and 2 enabled
4-5 = Reserved
8
Boot Master
This pin must be pulled down to GND
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock
setting for the device. Default system reference clock is 156.25 MHz. Table 9-25 shows settings for
various input clock frequencies. (default = 4)
164
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Table 9-10. Ethernet (SGMII) Boot Device Configuration Field Descriptions (continued)
Bit
Field
Description
4
Min
Minimum boot configuration select bit.
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field
Descriptions table for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices
3-1
0
Boot Devices
Lendian
•
•
101 = Ethernet boot mode
Others = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
9.1.2.3.1 PCIe Boot Device Configuration
Figure 9-9. PCIe Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Ref clk
Bar Config
Port
X
Boot Master
Sys PLL Cfg
0110
Lendian
Table 9-11. PCIe Boot Device Configuration Field Descriptions
Bit
Field
Ref clk
Description
16
PCIe Reference clock frequency
•
•
0 = 100MHz
1 = Reserved
15-12
Bar Config
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 9-12.
PCIe Port number (0-1)
11
Port
10-9
8
Reserved
Boot Master
SYS PLL Setting
This pin must be pulled down to GND
7-5
The PLL default settings are determined by the [7:5] bits.This will set the PLL to the maximum clock
setting for the device. Default system reference clock is 156.25 MHz. Table 9-25 shows settings for
various input clock frequencies.
4-1
0
Boot Devices
Lendian
Boot Devices[4:1]
•
•
0110 = PCIe boot mode
Others = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
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Table 9-12. BAR Config / PCIe Window Sizes
64-BIT ADDRESS
TRANSLATION
32-BIT ADDRESS TRANSLATION
BAR CFG
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
BAR0
BAR1
32
16
16
32
16
16
32
32
64
4
BAR2
32
BAR3
32
BAR4
32
BAR5
BAR2/3
BAR4/5
PCIe MMRs
16
32
64
32
32
64
32
32
64
16
64
64
32
64
64
Clone of
BAR4
32
64
64
32
64
128
256
128
256
256
64
128
128
128
256
128
128
128
4
4
256
256
512
512
1024
2048
1024
2048
9.1.2.3.2 HyperLink Boot Device Configuration
Figure 9-10. HyperLink Boot Device Configuration Fields
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
RefClk
Data Rate
X
Boot Master
Sys PLL Cfg
1110
Lendian
Table 9-13. HyperLink Boot Device Configuration Field Descriptions
Bit
16
Field
Reserve
Description
15-14 Ref Clocks
HyperLink reference clock configuration
•
•
•
0 = 125 MHz
1 = 156.25 MHz
2-3 = Reserved
13-12 Data Rate
HyperLink data rate configuration
•
•
•
•
0 = 1.25 GBs
1 = 3.125 GBs
2 = 6.25 GBs
3 = 12.5GBs
11-9
8
Reserved
Boot Master
This pin must be pulled down to GND
7-5
SYS PLL
Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
the device. Default system reference clock is 156.25 MHz. Table 9-25 shows settings for various input clock
frequencies.
4-1
0
Boot Devices
Boot Devices[4:1]
•
•
1110 = HyperLink boot mode
Others = Other boot modes
Lendian
Endianess
•
•
0 = Big endian
1 = Little endian
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9.1.2.3.3 UART Boot Device Configuration
Figure 9-11. UART Boot Mode Configuration Field Description
DEVSTAT Boot Mode Pins ROM Mapping
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
X
Port
X
X
X
Boot Master
Sys PLL Config
Min
111
Lendian
Table 9-14. UART Boot Configuration Field Descriptions
Bit
Field
Description
16-13 Reserved
Not Used
12
Port
UART Port number
•
•
0 = UART0
1 = UART1
11-9
8
Reserved
Not Used
Boot Master
This pin must be pulled down to GND
7-5
SYS PLL
Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
the device. Table 9-25 shows settings for various input clock frequencies. (default = 4)
4
Min
Minimum boot configuration select bit.
•
•
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1]
3-1
0
Boot Devices
Lendian
•
•
111 = UART boot mode
Others = Other boot modes
Endianess
•
•
0 = Big endian
1 = Little endian
9.1.2.4 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is
the most common format the RBL employs to determine the boot flow. These boot parameter tables have
certain parameters common across all the boot modes, while the rest of the parameters are unique to the
boot modes. The common entries in the boot parameter table are shown in Table 9-15.
Table 9-15. Boot Parameter Table Common Parameters
BYTE OFFSET
NAME
DESCRIPTION
0
2
Length
The length of the table, including the length field, in bytes.
Checksum
The 16 bits ones complement of the ones complement of the entire table. A
value of 0 will disable checksum verification of the table by the boot ROM.
4
Boot Mode
Port Num
Internal values used by RBL for different boot modes.
Identifies the device port number to boot from, if applicable
PLL configuration, MSW
6
8
SW PLL, MSW
SW PLL, LSW
Reserved
10
12
14
16
18
20
PLL configuration, LSW
Reserved
Reserved
Reserved
System Freq
Core Freq
The Frequency of the system clock in MHz
The frequency of the core clock in MHz
Set to TRUE if C66x is the master core.
Boot Master
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9.1.2.4.1 EMIF16 Boot Parameter Table
Table 9-16. EMIF16 Boot Parameter Table
CONFIGURED
THROUGH BOOT
BYTE OFFSET NAME
DESCRIPTION
CONFIGURATION PINS
22
Options
Async Config Parameters are used.
NO
•
0 = Value in the async config paramters are not
used to program async config registers.
•
1 = Value in the async config paramters are used
to program async config registers.
24
26
Type
Set to 0 for EMIF16 (NOR) boot
NO
Branch Address MSW
Most significant bit for Branch address (depends on
chip select)
YES
28
Branch Address LSW
Least significant bit for Branch address (depends on
chip select)
YES
30
32
34
Chip Select
Chip Select for the NOR flash
YES
YES
YES
Memory Width
Wait Enable
Memory width of the EMIF16 bus (16 bits)
Extended wait mode enabled
•
•
0 = Wait enable is disabled
1 = Wait enable is enabled
36
38
Async Config MSW
Async Config LSW
Async Config Register MSW
Async Config Register LSW
NO
NO
9.1.2.4.2 Ethernet Boot Parameter Table
Table 9-17. Ethernet Boot Parameter Table
CONFIGURED
BYTE
OFFSET
THROUGH BOOT
CONFIGURATION PINS
NAME
DESCRIPTION
22
Options
Bits 02 - 00 Interface
NO
•
•
•
•
000 - 100 = Reserved
101 = SGMII
110 = Reserved
111 = Reserved
Bits 03 HD
•
•
0 = Half Duplex
1 = Full Duplex
Bit 4 Skip TX
•
•
0 = Send Ethernet Ready Frame every 3 seconds
1 = Don't send Ethernet Ready Frame
Bits 06 - 05 Initialize Config
•
•
00 = Switch, SerDes, SGMII and NETCP are configured
01 = Initialization is not done for the peripherals that are already
enabled and running.
•
•
10 = Reserved
11 = None of the Ethernet system is configured.
Bits 15 - 07 Reserved
24
26
28
30
32
MAC High
The 16 MSBs of the MAC address to receive during boot
The 16 middle bits of the MAC address to receive during boot
The 16 LSBs of the MAC address to receive during boot
The 16 MSBs of the multi-cast MAC address to receive during boot
NO
NO
NO
NO
NO
MAC Med
MAC Low
Multi MAC High
Multi MAC Med
The 16 middle bits of the multi-cast MAC address to receive during
boot
34
Multi MAC Low
The 16 LSBs of the multi-cast MAC address to receive during boot
NO
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Table 9-17. Ethernet Boot Parameter Table (continued)
CONFIGURED
BYTE
OFFSET
THROUGH BOOT
CONFIGURATION PINS
NAME
DESCRIPTION
36
Source Port
The source UDP port to accept boot packets from. A value of 0 will
accept packets from any UDP port
NO
38
40
Dest Port
The destination port to accept boot packets on.
NO
NO
Device ID 12
The first two bytes of the device ID. This is typically a string value,
and is sent in the Ethernet ready frame
42
44
Device ID 34
The 2nd two bytes of the device ID.
NO
Dest MAC High
The 16 MSBs of the MAC destination address used for the Ethernet NO
ready frame. Default is broadcast.
46
48
50
Dest MAC Med
Dest MAC Low
Lane Enable
The 16 middle bits of the MAC destination address
The 16 LSBs of the MAC destination address
One bit per lane.
NO
NO
•
•
0 - Lane disabled
1 - Lane enabled
52
SGMII Config
Bits 0-3 are the config index, bit 4 set if direct config used, bit 5 set if NO
no configuration done
54
56
58
60
62
64
66
68
70
72
SGMII Control
The SGMII control register value
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
SGMII Adv Ability
SGMII TX Cfg High
SGMII TX Cfg Low
SGMII RX Cfg High
SGMII RX Cfg Low
SGMII Aux Cfg High
SGMII Aux Cfg Low
PKT PLL Cfg MSW
PKT PLL CFG LSW
The SGMII ADV Ability register value
The 16 MSBs of the SGMII Tx config register
The 16 LSBs of the SGMII Tx config register
The 16 MSBs of the SGMII Rx config register
The 16 LSBs of the SGMII Rx config register
The 16 MSBs of the SGMII Aux config register
The 16 LSBs of the SGMII Aux config register
The packet subsystem PLL configuration, MSW
The packet subsystem PLL configuration, LSW
9.1.2.4.3 PCIe Boot Parameter Table
Table 9-18. PCIe Boot Parameter Table
CONFIGURED
BYTE
OFFSET
THROUGH BOOT
CONFIGURATION PINS
NAME
DESCRIPTION
22
Options
Bits 00 Mode
NO
•
0 = Host Mode (Direct boot mode)
•
1 = Boot Table Boot Mode
Bits 01 Configuration of PCIe
•
0 = PCIe is configured by RBL
•
1 = PCIe is not configured by RBL
Bit 03-02 Reserved
Bits 04 Multiplier
•
•
0 = SERDES PLL configuration is done based on SERDES
register values
1 = SERDES PLL configuration based on the reference clock
values
Bits 05-15 Reserved
24
26
Address Width
Link Rate
PCI address width, can be 32 or 64
YES with in conjunction
with BAR sizes
SerDes frequency, in Mbps. Can be 2500 or 5000
NO
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Table 9-18. PCIe Boot Parameter Table (continued)
CONFIGURED
BYTE
THROUGH BOOT
OFFSET
NAME
DESCRIPTION
CONFIGURATION PINS
28
Reference clock
Reference clock frequency, in units of 10 kHz. Value values are 10000 NO
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz)
and 31250 (312.5 MHz). A value of 0 means that value is already in
the SerDes cfg parameters and will not be computed by the boot
ROM.
30
32
34
36
38
40
42
Window 1 Size
Window 2 Size
Window 3 Size
Window 4 Size
Vendor ID
Window 1size.
YES
YES
YES
YES
NO
Window 2 size.
Window 3 size. Valid only if address width is 32.
Window 4 Size. Valid only if the address width is 32.
Vendor ID
Device ID
Device ID
NO
Class code Rev ID
MSW
Class code revision ID MSW
NO
44
Class code Rev ID
LSW
Class code revision ID LSW
NO
46
48
50
52
54
56
58
SerDes cfg msw
SerDes cfg lsw
PCIe SerDes config word, MSW
PCIe SerDes config word, LSW
NO
NO
NO
NO
NO
NO
SerDes lane 0 cfg msw SerDes lane config word, msw lane 0
SerDes lane 0 cfg lsw SerDes lane config word, lsw, lane 0
SerDes lane 1 cfg msw SerDes lane config word, msw, lane 1
SerDes lane 1 cfg lsw SerDes lane config word, lsw, lane 1
Timeout period (Secs) The timeout period. Values 0 disables the time out
9.1.2.4.4 I2C Boot Parameter Table
Table 9-19. I2C Boot Parameter Table
CONFIGURED
THROUGH BOOT
CONFIGURATION PINS
OFFSET
FIELD
VALUE
22
Option
Bits 02 - 00 Mode
NO
•
•
•
•
•
000 = Boot Parameter Table Mode
001 = Boot Table Mode
010 = Boot Config Mode
011 = Load GP header format data
100 = Slave Receive Boot Config
Bits 15 - 03= Reserved
24
26
28
Boot Dev Addr
The I2C device address to boot from
YES
YES
NO
Boot Dev Addr Ext
Broadcast Addr
Extended boot device address
I2C address used to send data in the I2C master
broadcast mode.
30
34
36
Local Address
Bus Frequency
Next Dev Addr
The I2C address of this device
The desired I2C data rate (kHz)
NO
NO
NO
The next device address to boot (Used only if boot
config option is selected)
38
40
Next Dev Addr Ext
Address Delay
The extended next device address to boot (Used only NO
if boot config option is selected)
The number of CPU cycles to delay between writing
the address to an I2C EEPROM and reading data.
NO
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9.1.2.4.5 SPI Boot Parameter Table
Table 9-20. SPI Boot Parameter Table
CONFIGURED
BYTE
OFFSET
THROUGH BOOT
CONFIGURATION PINS
NAME
DESCRIPTION
22
Options
Bits 01 & 00 Modes
NO
•
•
•
•
00 = Load a boot parameter table from the SPI (Default mode)
01 = Load boot records from the SPI (boot tables)
10 = Load boot config records from the SPI (boot config tables)
11 = Load GP header blob
Bits 15- 02= Reserved
24
26
28
30
32
34
36
38
40
42
44
Address Width
NPin
The number of bytes in the SPI device address. Can be 16 or 24 bit
The operational mode, 4 or 5 pin
YES
YES
YES
YES
NO
Chipsel
The chip select used (valid in 4 pin mode only). Can be 0-3.
Standard SPI mode (0-3)
Mode
C2Delay
Setup time between chip assert and transaction
The SPI bus frequency in kHz.
Bus Freq, 100kHz
Read Addr MSW
Read Addr LSW
Next Chip Select
NO
The first address to read from, MSW (valid for 24 bit address width only) YES
The first address to read from, LSW
YES
NO
NO
NO
Next Chip Select to be used (Used only in boot Config mode)
Next Read Addr MSW The Next read address (used in boot config mode only)
Next Read Addr LSW The Next read address (used in boot config mode only)
9.1.2.4.6 HyperLink Boot Parameter Table
Table 9-21. HyperLink Boot Parameter Table
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
BYTE
OFFSET
NAME
DESCRIPTION
12
Options
Bits 00 Reserved
NO
Bits 01 Configuration of Hyperlink
•
•
0 = HyperLink is configured by RBL
1 = HyperLink is not configured by RBL
Bits 15-02 = Reserved
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
Number of Lanes
Number of Lanes to be configured
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
SerDes cfg msw
PCIe SerDes config word, MSW
SerDes cfg lsw
PCIe SerDes config word, LSW
SerDes CFG RX lane 0 cfg msw
SerDes CFG RXlane 0 cfg lsw
SerDes CFG TX lane 0 cfg msw
SerDes CFG TXlane 0 cfg lsw
SerDes CFG RX lane 1 cfg msw
SerDes CFG RXlane 1 cfg lsw
SerDes CFG TX lane 1 cfg msw
SerDes CFG TXlane 1 cfg lsw
SerDes CFG RX lane 2 cfg msw
SerDes CFG RXlane 2 cfg lsw
SerDes CFG TX lane 2 cfg msw
SerDes CFG TXlane 2 cfg lsw
SerDes CFG RX lane 3 cfg msw
SerDes CFG RXlane 3 cfg lsw
SerDes RX lane config word, msw lane 0
SerDes RX lane config word, lsw, lane 0
SerDes TX lane config word, msw lane 0
SerDes TX lane config word, lsw, lane 0
SerDes RX lane config word, msw lane 1
SerDes RX lane config word, lsw, lane 1
SerDes TX lane config word, msw lane 1
SerDes TX lane config word, lsw, lane 1
SerDes RX lane config word, msw lane 2
SerDes RX lane config word, lsw, lane 2
SerDes TX lane config word, msw lane 2
SerDes TX lane config word, lsw, lane 2
SerDes RX lane config word, msw lane 3
SerDes RX lane config word, lsw, lane 3
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Table 9-21. HyperLink Boot Parameter Table (continued)
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
BYTE
OFFSET
NAME
DESCRIPTION
48
50
SerDes CFG TX lane 3 cfg msw
SerDes CFG TXlane 3 cfg lsw
SerDes TX lane config word, msw lane 3
SerDes TX lane config word, lsw, lane 3
NO
NO
9.1.2.4.7 UART Boot Parameter Table
Table 9-22. UART Boot Parameter Table
CONFIGURED THROUGH
BOOT CONFIGURATION
PINS
BYTE
OFFSET
NAME
DESCRIPTION
22
24
Reserved
Data Format
None
NA
NO
Bits 00 Data Format
•
0 = Data Format is BLOB
•
1 = Data Format is Boot Table
Bits 15 - 01 Reserved
26
Protocol
Bits 00 Protocol
NO
•
•
0 = Xmodem Protocol
1 = Reserved
Bits 15 - 01 Reserved
28
30
32
34
36
38
Initial NACK Count Number of NACK pings to be sent before giving up
NO
NO
NO
NO
NO
NO
Max Err Count
NACK Timeout
Maximum number of consecutive receive errors acceptable.
Time (msecs) waiting for NACK/ACK.
Character Timeout Time Period between characters
nDatabits
Parity
Number of bits supported for data. Only 8 bits is supported.
Bits 01 - 00 Parity
•
•
•
00 = No Parity
01 = Odd parity
10 = Even Parity
Bits 15 - 02 Reserved
40
nStopBitsx2
Number of stop bits times two. Valid values are 2 (stop bits = 1), 3 (Stop
Bits = 1.5), 4 (Stop Bits = 2)
NO
42
44
Over sample factor The over sample factor. Only 13 and 16 are valid.
NO
NO
Flow Control
Bits 00 Flow Control
•
0 = No Flow Control
•
1 = RTS_CTS flow control
Bits 15 - 01 Reserved
Baud Rate, MSW
Baud Rate, LSW
46
48
Data Rate MSW
Data Rate LSW
NO
NO
9.1.2.4.8 NAND Boot Parameter Table
Table 9-23. NAND Boot Parameter Table
CONFIGURED THROUGH
BYTE OFFSET NAME
DESCRIPTION
BOOT CONFIGURATION PINS
22
Options
Bits 00 Geometry
NO
•
0 = Geometry is taken from this table
•
1 = Geometry is queried from NAND device.
Bits 01 Clear NAND
•
0 = NAND Device is a non clear NAND and
requires ECC
•
1 = NAND is a clear NAND and doesn.t need
ECC.
Bits 15 - 02 Reserved
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Table 9-23. NAND Boot Parameter Table (continued)
CONFIGURED THROUGH
BYTE OFFSET NAME
DESCRIPTION
BOOT CONFIGURATION PINS
24
26
28
30
32
34
36
38
40
numColumnAddrBytes
Number of bytes used to specify column address
Number of bytes used to specify row address.
Number of data bytes in each page, MSW
Number of data bytes in each page, LSW
Number of Pages per Block
NO
NO
NO
NO
NO
NO
NO
YES
YES
numRowAddrBytes
numofDataBytesperPage_msw
numofDataBytesperPage_lsw
numPagesperBlock
busWidth
EMIF bus width. Only 8 or 16 bits is supported.
Number of spare bytes allocated per page.
Chip Select number (valid chip selects are 2-5)
First block for RBL to try to read.
numSpareBytesperPage
csel
First Block
9.1.2.4.9 DDR3 Configuration Table
The RBL also provides an option to configure the DDR table before loading the image into the external
memory. More information on how to configure the DDR3, refer to the Bootloader User Guide. The
configuration table for DDR3 is shown in Table 9-24
Table 9-24. DDR3 Boot Parameter Table
CONFIGURED
BYTE
THROUGH BOOT
OFFSET
NAME
DESCRIPTION
CONFIGURATION PINS
0
configselect msw
Selecting the configuration register below that to be set. Each
filed below is represented by one bit each.
NO
4
8
configselect slsw
configselect lsw
Selecting the configuration register below that to be set. Each
filed below is represented by one bit each.
NO
NO
Selecting the configuration register below that to be set. Each
filed below is represented by one bit each.
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
pllprediv
PLL pre divider value (Should be the exact value not value -1)
PLL Multiplier value (Should be the exact value not value -1)
PLL post divider value (Should be the exact value not value -1)
SDRAM config register
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
pllMult
pllPostDiv
sdRamConfig
sdRamConfig2
sdRamRefreshctl
sdRamTiming1
sdRamTiming2
sdRamTiming3
IpDfrNvmTiming
powerMngCtl
SDRAM Config register
SDRAM Refresh Control Register
SDRAM Timing 1 Register
SDRAM Timing 2 Register
SDRAM Timing 3 Register
LP DDR2 NVM Timing Register
Power management Control Register
IODFT Test Logic Global Control Register
Performance Counter Config Register
Performance Counter Master Region Select Register
Read IDLE counter Register
iODFTTestLogic
performcountCfg
performCountMstRegSel
readIdleCtl
sysVbusmIntEnSet
sdRamOutImpdedCalcfg
tempAlertCfg
System Interrupt Enable Set Register
SDRAM Output Impedence Calibration Config Register
Temperature Alert Configuration Register
DDR PHY Control Register 1
ddrPhyCtl1
ddrPhyCtl2
DDR PHY Control Register 1
proClassSvceMap
mstId2ClsSvce1Map
mstId2ClsSvce2Map
Priority to Class of Service mapping Register
Master ID to Class of Service Mapping 1 Register
Master ID to Class of Service Mapping 2Register
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Table 9-24. DDR3 Boot Parameter Table (continued)
CONFIGURED
BYTE
THROUGH BOOT
OFFSET
NAME
DESCRIPTION
CONFIGURATION PINS
104
eccCtl
ECC Control Register
NO
NO
NO
NO
NO
108
eccRange1
eccRange2
rdWrtExcThresh
Chip Config
ECC Address Range1 Register
ECC Address Range2 Register
Read Write Execution Threshold Register
Chip Specific PHY configuration
112
116
120 - 376
9.1.2.5 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader
allows for:
•
•
Any level of customization to current boot methods
Definition of a completely customized boot
9.1.3 SoC Security
The TI SoC contains security architecture that allows the ARM CorePac to perform secure accesses
within the device. For more information, contact a TI sales office for additional information available with
the purchase of a secure device.
9.1.4 System PLL Settings
The PLL default settings are determined by the BOOTMODE[7:5] bits. Table 9-25 shows the settings for
various input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
Where OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]
NOTE
Other frequencies are supported, but require a boot in a pre-configured mode.
The configuration for the NETCP PLL is also shown. The NETCP PLL is configured with these values only
if the Ethernet boot mode is selected with the input clock set to match the main PLL clock (not the SGMII
SerDes clock). See Table 9-10 for details on configuring Ethernet boot mode. The output from the NETCP
PLL goes through an on-chip divider to reduce the frequency before reaching the NETCP. The NETCP
PLL generates 1050 MHz, and after the chip divider (/3), applies 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. DDR3 PLL and NETCP PLL are
controlled by chip level MMRs. For details on how to set up the PLL see Section 11.5. For details on the
operation of the PLL controller module, see the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide (SPRUGV2).
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Table 9-25. System PLL Configuration
INPUT
CLOCK
FREQ
(MHz)
800 MHz DEVICE
1000 MHz DEVICE
1200 MHz DEVICE
1400 MHz DEVICE
NETCP = 350 MHz(1)
BOOTMODE
[7:5]
PLLD
PLLM
31
SoC ƒ
PLLD
PLLM
39
SoC ƒ
1000
PLLD
PLLM
47
SoC ƒ
1200
PLLD
PLLM
55
SoC ƒ
1400
PLLD
PLLM
41
SoC ƒ(2)
1050
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
50.00
0
0
0
0
3
4
7
0
800
0
0
0
0
4
0
4
3
0
0
0
0
2
4
2
0
0
0
0
0
0
4
0
0
0
66.67
23
800.04
800
29
1000.05
1000
35
1200.06
1200
41
1400.1
1400
1
62
1050.053
1050
80.00
19
24
29
34
3
104
20
100.00
156.25
250.00
312.50
122.88
15
800
19
1000
23
1200
27
1400
0
1050
40
800.78
800
63
1000
45
1197.92
1200
17
1406.3
1400
24
4
335
41
1050
31
7
1000
47
55
1050
40
800.78
798.72
31
1000
22
1197.92
1228.80
8
1406.3
1413.1
24
11
167
204
1050
12
64
999.989
19
22
1049.6
(1) The NETCP PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
(2) ƒ represents frequency in MHz.
9.2 Device Configuration
Certain device configurations like boot mode and endianess are selected at device power-on reset. The
status of the peripherals (enabled/disabled) is determined after device power-on reset. By default, the
peripherals on the device are disabled and need to be enabled by software before being used.
9.2.1 Device Configuration at Device Reset
The logic level present on each device configuration pin is latched at power-on reset to determine the
device configuration. The logic level on the device configuration pins can be set by using external
pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these
pins. When using a control device, care should be taken to ensure there is no contention on the lines
when the device is out of reset. The device configuration pins are sampled during power-on reset and are
driven after the reset is removed. To avoid contention, the control device must stop driving the device
configuration pins of the SoC. Table 9-26 describes the device configuration pins.
NOTE
If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the
internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use
of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown
resistors and situations in which external pullup/pulldown resistors are required, see
Section 6.4.
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Table 9-26. Device Configuration Pins
CONFIGURATION PIN
PIN NO.
IPD/IPU(1)
DESCRIPTION
LENDIAN(1)(2)
V30
IPU
Device endian mode (LENDIAN)
•
•
0 = Device operates in big endian mode
1 = Device operates in little endian mode
BOOTMODE[15:0](1)(2)
AB33, AB32, AA33, IPD
AA30, Y32, Y30,
AB29, W33, W31,
V31, W32, W30,
V32, V33, Y29,
AA29
Method of boot
•
•
See Section 9.1.2 for more details.
See the KeyStone II Architecture ARM Bootloader User's Guide
(SPRUHJ3) for detailed information on boot configuration.
AVSIFSEL[1:0](1)(2)
K32, K33
IPD
AVS interface selection
•
•
•
•
00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
11 = I2C
MAINPLLODSEL(1)(2)
BOOTMODE_RSVD(1)
Y33
Y31
IPD
IPD
Main PLL Output divider select
•
•
0 = Main PLL output divider needs to be set to 2 by BOOTROM
1 = Reserved
Boot Mode Reserved. Secondary function for GPIO15. Pulldown
resistor required on pin.
(1) Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU.
For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see
Section 6.4.
(2) These signal names are the secondary functions of these pins.
9.2.2 Peripheral Selection After Device Reset
Several of the peripherals on the 66AK2E0x are controlled by the Power Sleep Controller (PSC). By
default, the PCIe and HyperLink are held in reset and clock-gated. The memories in these modules are
also in a low-leakage sleep mode. Software is required to turn these memories on. Then, the software
enables the modules (turns on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code automatically
enables the module.
All other modules come up enabled by default and there is no special software sequence to enable. For
more detailed information on the PSC usage, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide (SPRUGV4).
9.2.3 Device State Control Registers
The 66AK2E0x device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 9-27.
Table 9-27. Device State Control Registers
ADDRESS
START
ADDRESS
END
SIZE ACRONYM
DESCRIPTION
0x02620000
0x02620008
0x02620018
0x0262001C
0x02620020
0x02620024
0x02620038
0x0262003C
0x02620040
0x02620007
0x02620017
0x0262001B
0x0262001F
0x02620023
0x02620037
0x0262003B
0x0262003F
0x02620043
8B
Reserved
Reserved
JTAGID
16B
4B
See Section 9.2.3.3
See Section 9.2.3.1
4B
Reserved
DEVSTAT
Reserved
KICK0
4B
20B
4B
See Section 9.2.3.4
4B
KICK1
4B
Reserved
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Table 9-27. Device State Control Registers (continued)
ADDRESS
START
ADDRESS
END
SIZE ACRONYM
DESCRIPTION
0x02620044
0x02620048
0x0262004C
0x02620050
0x02620054
0x02620058
0x0262005C
0x02620060
0x026200E0
0x02620110
0x02620118
0x02620130
0x02620134
0x02620138
0x0262013C
0x02620140
0x02620144
0x02620148
0x0262014C
0x02620150
0x02620154
0x02620158
0x0262015C
0x02620160
0x02620164
0x02620168
0x0262016C
0x02620180
0x02620184
0x02620190
0x02620194
0x02620198
0x0262019C
0x026201A0
0x026201A4
0x026201A8
0x026201AC
0x026201B0
0x026201B4
0x026201B8
0x026201BC
0x026201C0
0x026201C4
0x026201C8
0x026201CC
0x026201D0
0x02620200
0x02620047
0x0262004B
0x0262004F
0x02620053
0x02620057
0x0262005B
0x0262005F
0x026200DF
0x0262010F
0x02620117
0x0262012F
0x02620133
0x02620137
0x0262013B
0x0262013F
0x02620143
0x02620147
0x0262014B
0x0262014F
0x02620153
0x02620157
0x0262015B
0x0262015F
0x02620160
0x02620167
0x0262016B
0x0262017F
0x02620183
0x0262018F
0x02620193
0x02620197
0x0262019B
0x0262019F
0x026201A3
0x026201A7
0x026201AB
0x026201AF
0x026201B3
0x026201B7
0x026201BB
0x026201BF
0x026201C3
0x026201C7
0x026201CB
0x026201CF
0x026201FF
0x02620203
4B
4B
4B
4B
4B
4B
4B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128B Reserved
48B
8B
24B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
20B
4B
12B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
48B
4B
Reserved
MACID
See Section 11.17
Reserved
LRSTNMIPINSTAT_CLR
RESET_STAT_CLR
Reserved
See Section 9.2.3.6
See Section 9.2.3.8
BOOTCOMPLETE
Reserved
See Section 9.2.3.9
RESET_STAT
LRSTNMIPINSTAT
DEVCFG
See Section 9.2.3.7
See Section 9.2.3.5
See Section 9.2.3.2
See Section 9.2.3.10
PWRSTATECTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SmartReflex Class0
Reserved
See Section 11.2.4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NMIGR0
See Section 9.2.3.11
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Table 9-27. Device State Control Registers (continued)
ADDRESS
START
ADDRESS
END
SIZE ACRONYM
DESCRIPTION
0x02620204
0x02620208
0x0262020C
0x02620210
0x02620214
0x02620218
0x0262021C
0x02620220
0x02620240
0x02620244
0x02620248
0x0262024C
0x02620250
0x02620254
0x02620258
0x0262025C
0x02620260
0x02620264
0x02620268
0x0262026C
0x02620270
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202A4
0x026202A8
0x026202AC
0x026202B0
0x026202BC
0x026202C0
0x02620300
0x02620304
0x02620207
0x0262020B
0x0262020F
0x02620213
0x02620217
0x0262021B
0x0262021F
0x0262023F
0x02620243
0x02620247
0x0262024B
0x0262024F
0x02620253
0x02620257
0x0262025B
0x0262025F
0x02620263
0x02620267
0x0262026B
0x0262026F
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202A3
0x026202A7
0x026202AB
0x026202AF
0x026202BB
0x026202BF
0x026202FF
0x02620303
0x02620307
4B
4B
4B
4B
4B
4B
4B
32B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
12B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
12B
4B
64B
4B
4B
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCGR0
See Section 9.2.3.12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCGR8
IPCGR9
IPCGR10
IPCGR11
Reserved
IPCGRH
IPCAR0
See Section 9.2.3.14
See Section 9.2.3.13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IPCAR8
IPCAR9
IPCAR10
IPCAR11
Reserved
IPCARH
See Section 9.2.3.15
Reserved
TINPSEL
TOUTPSEL
See Section 9.2.3.16
See Section 9.2.3.17
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Table 9-27. Device State Control Registers (continued)
ADDRESS
START
ADDRESS
END
SIZE ACRONYM
DESCRIPTION
0x02620308
0x0262030C
0x02620310
0x02620314
0x02620318
0x0262031C
0x02620320
0x02620324
0x02620328
0x0262032C
0x02620330
0x02620334
0x02620338
0x02620350
0x02620354
0x02620358
0x0262035C
0x02620360
0x02620364
0x02620368
0x0262036C
0x02620370
0x02620374
0x02620378
0x0262039C
0x02620400
0x02620404
0x02620408
0x0262040C
0x02620600
0x02620700
0x02620704
0x02620710
0x02620714
0x02620718
0x0262071C
0x02620720
0x02620730
0x02620734
0x02620738
0x02620750
0x02620800
0x02620C7C
0x02620C80
0x02620C98
0x02620C9C
0x0262030B
0x0262030F
0x02620313
0x02620317
0x0262031B
0x0262031F
0x02620323
0x02620327
0x0262032B
0x0262032F
0x02620333
0x02620337
0x0262034F
0x02620353
0x02620357
0x0262035B
0x0262035F
0x02620363
0x02620367
0x0262036B
0x0262036F
0x02620373
0x02620377
0x0262039B
0x0262039F
0x02620403
0x02620407
0x0262040B
0x026205FF
0x026206FF
0x02620703
0x0262070F
0x02620713
0x02620717
0x0262071B
0x0262071F
0x0262072F
0x02620733
0x02620737
0x0262074F
0x026207FF
0x02620C7B
0x02620C7F
0x02620C97
0x02620C9B
0x02620FFF
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
RSTMUX0
Reserved
See Section 9.2.3.18
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RSTMUX8
RSTMUX9
RSTMUX10
RSTMUX11
Reserved
CorePLLCTL0
CorePLLCTL1
PASSPLLCTL0
PASSPLLCTL1
DDR3PLLCTL0
DDR3PLLCTL1
Reserved
See Section 11.5
See Section 11.7
See Section 11.6
Reserved
Reserved
Reserved
132B Reserved
4B
4B
4B
4B
62B
Reserved
ARMENDIAN_CFG0_0
ARMENDIAN_CFG0_1
ARMENDIAN_CFG0_2
Reserved
See Section 9.2.3.20
256B Reserved
4B
CHIP_MISC_CTL0
See Section 9.2.3.23
See Section 9.2.3.25
12B
4B
Reserved
SYSENDSTAT
Reserved
4B
4B
Reserved
4B
Reserved
16B
4B
Reserved
SYNECLK_PINCTL
Reserved
See Section 9.2.3.26
See Section 9.2.3.27
4B
24B
USB_PHY_CTL
176B Reserved
1148B Reserved
4B
CHIP_MISC_CTL1
See Section 9.2.3.24
See Section 9.2.3.19
24B
4B
Reserved
DEVSPEED
868B Reserved
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9.2.3.1 Device Status (DEVSTAT) Register
The Device Status Register depicts device configuration selected upon a power-on reset by the POR or
RESETFULL pin. Once set, these bits remain set until a power-on reset. The Device Status Register is
shown in the figure below.
Figure 9-12. Device Status Register
31
22
21
Reserved
R/W-00
20
19
18
17
16
1
0
Reserved
R-0
MAINPLLODSEL
R/W-x
AVSIFSEL
R/W-xx
BOOTMODE
LENDIAN
R-x(1)
R/W-x xxxx
xxxx xxxx xxx
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) x indicates the bootstrap value latched via the external pin
Table 9-28. Device Status Register Field Descriptions
Bit
Field
Description
31-22 Reserved
21-20 Reserved
Reserved
Reserved
19
MAINPLLODSEL Main PLL Output divider select
•
•
0 = Main PLL output divider needs to be set to 2 by BOOTROM
1 = Reserved
18-17 AVSIFSEL
AVS interface selection
•
•
•
•
00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
11 = Reserved
16-1
0
BOOTMODE
LENDIAN
Determines the bootmode configured for the device. For more information on bootmode, see Section 9.1.2.
See the KeyStone Architecture DSP Bootloader User Guide (SPRUGY5).
Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or
little endian mode (default).
•
•
0 = System is operating in big endian mode
1 = System is operating in little endian mode (default)
9.2.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard
resets and is locked after the first write. The Device Configuration Register is shown in Figure 9-13 and
described in Table 9-29.
Figure 9-13. Device Configuration Register (DEVCFG)
31
5
4
3
2
1
0
Reserved
R-0
PCIE1SSMODE
R/W-00
PCIE0SSMODE
R/W-00
SYSCLKOUTEN
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-29. Device Configuration Register Field Descriptions
Bit
Field
Description
31-5
4-3
Reserved
PCIE1SSMODE
Reserved. Read only, writes have no effect.
Device Type Input of PCIe1SS
•
•
•
•
00 = Endpoint
01 = Legacy Endpoint
10 = Rootcomplex
11 = Reserved
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Table 9-29. Device Configuration Register Field Descriptions (continued)
Bit
Field
PCIE0SSMODE
Description
2-1
Device Type Input of PCIe0SS
•
•
•
•
00 = Endpoint
01 = Legacy Endpoint
10 = Rootcomplex
11 = Reserved
0
SYSCLKOUTEN SYSCLKOUT enable
•
•
0 = No clock output
1 = Clock output enabled (default)
9.2.3.3 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x02620018. The JTAG ID Register is shown
below.
Figure 9-14. JTAG ID (JTAGID) Register
31
28
27
12
11
1
0
VARIANT
R-xxxx
PART NUMBER
MANUFACTURER
R-0000 0010 111
LSB
R-1
R-1011 1001 1010 0110
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-30. JTAG ID Register Field Descriptions
Bit
Field
Value
Description
31-28 VARIANT
xxxx
Variant value
27-12 PART NUMBER
1011 1001 1010 0110 Part Number for boundary scan
11-1
0
MANUFACTURER
LSB
0000 0010 111
1
Manufacturer
This bit is read as a 1
NOTE
The value of the VARIANT and PART NUMBER fields depends on the silicon revision being
used. See the Silicon Errata for details.
9.2.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent spurious writes from changing any of the
Bootcfg MMR (memory mapped registers) values. When the kicker is locked (which it is initially after
power on reset), none of the Bootcfg MMRs are writable (they are only readable). This mechanism
requires an MMR write to each of the KICK0 and KICK1 registers with exact data values before the kicker
lock mechanism is unlocked. See Table 9-27 for the address location. Once released, all the Bootcfg
MMRs having write permissions are writable (the read only MMRs are still read only). The KICK0 data is
0x83e70b13. The KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs
locks the kicker mechanism and blocks writes to Bootcfg MMRs. To ensure protection to all Bootcfg
MMRs, software must always re-lock the kicker mechanism after completing the MMR writes.
9.2.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register latches the status of LRESET and NMI. The LRESETNMI PIN Status
Register is shown in the figure and table below.
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Figure 9-15. LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
9
8
7
1
0
Reserved
R-0
NMI0
R-0
Reserved
R-0
LR0
R-0
Legend: R = Read only; -n = value after reset
Table 9-31. LRESETNMI PIN Status Register Field Descriptions
Bit
Field
Description
31-16 Reserved
15
14
13
12
11
10
9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NMI0
8
C66x CorePac0 in NMI
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LR0
6
5
4
3
2
1
0
C66x CorePac0 in Local Reset
9.2.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register clears the status of LRESET and NMI. The LRESETNMI PIN
Status Clear Register is shown in the figure and table below.
Figure 9-16. LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
9
8
7
1
0
Reserved
R-0
NMI0
WC-0
Reserved
R-0
LR0
WC-0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
Table 9-32. LRESETNMI PIN Status Clear Register Field Descriptions
Bit
Field
Description
31-16 Reserved
15
14
13
12
11
10
9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NMI0
8
C66x CorePac0 in NMI Clear
7
Reserved
Reserved
6
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Table 9-32. LRESETNMI PIN Status Clear Register Field Descriptions (continued)
Bit
5
Field
Description
Reserved
Reserved
Reserved
Reserved
Reserved
LR0
4
3
2
1
0
C66x CorePac0 in Local Reset Clear
9.2.3.7 Reset Status (RESET_STAT) Register
The Reset Status Register (RESET_STAT) captures the status of local reset (LRx) for each of the cores
and also the global device reset (GR). Software can use this information to take different device
initialization steps.
•
In case of local reset: The LRx bits are written as 1 and the GR bit is written as 0 only when the C66x
CorePac receives a local reset without receiving a global reset.
•
In case of global reset: The LRx bits are written as 0 and the GR bit is written as 1 only when a
global reset is asserted.
The Reset Status Register is shown in the figure and table below.
Figure 9-17. Reset Status Register (RESET_STAT)
31
GR
R-1
30
1
0
Reserved
R- 0
LR0
R-0
Legend: R = Read only; -n = value after reset
Table 9-33. Reset Status Register Field Descriptions
Bit
Field
Description
Global reset status
31
GR
•
•
0 = Device has not received a global reset.
1 = Device received a global reset.
30-1 Reserved
LR0
Reserved.
0
C66x CorePac0 reset status
•
•
0 = C66x CorePac0 has not received a local reset.
1 = C66x CorePac0 received a local reset.
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9.2.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR
register. The Reset Status Clear Register is shown in the figure and table below.
Figure 9-18. Reset Status Clear Register (RESET_STAT_CLR)
31
GR
30
1
0
Reserved
R- 0
LR0
RW-0
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-34. Reset Status Clear Register Field Descriptions
Bit
Field
Description
Global reset clear bit
31
GR
•
•
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
30-1
0
Reserved
LR0
Reserved.
C66x CorePac0 reset clear bit
•
•
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
9.2.3.9 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status to indicate the completion of the
ROM booting process. The Boot Complete register is shown in the figure and table below.
Figure 9-19. Boot Complete Register (BOOTCOMPLETE)
31
Reserved
R-0
12
11
10
9
8
7
1
0
BC11
RW-0
BC10
RW-0
BC9
RW-0
BC8
RW-0
Reserved
R-0
BC0
RW-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-35. Boot Complete Register Field Descriptions
Bit
Field
Description
31-12 Reserved
11
10
9
BC11
BC10
BC9
ARM CorePac 3 boot status (66AK2E05 only)
•
•
0 = ARM CorePac 3 boot NOT complete
1 = ARM CorePac 3 boot complete
ARM CorePac 2 boot status (66AK2E05 only)
•
•
0 = ARM CorePac 2 boot NOT complete
1 = ARM CorePac 2 boot complete
ARM CorePac 1 boot status (66AK2E05 only)
•
•
0 = ARM CorePac 1 boot NOT complete
1 = ARM CorePac 1 boot complete
8
BC8
ARM CorePac 0 boot status
•
•
0 = ARM CorePac 0 boot NOT complete
1 = ARM CorePac 0 boot complete
7-1
0
Reserved
BC0
C66x CorePac0 boot status
•
•
0 = C66x CorePac 0 boot NOT complete
1 = C66x CorePac 0 boot complete
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The BCx bit indicates the boot complete status of the corresponding C66x CorePac and ARM CorePac.
All BCx bits are sticky bits — that is, they can be set only once by the software after device reset and they
will be cleared to 0 on all device resets (warm reset and power-on reset).
Boot ROM code is implemented such that each C66x CorePac or ARM CorePac sets its corresponding
BCx bit immediately before branching to the predefined location in memory.
9.2.3.10 Power State Control (PWRSTATECTL) Register
The Power State Control Register (PWRSTATECTL) is controlled by the software to indicate the power-
saving mode. Under ROM code, the CorePac reads this register to differentiate between the various
power saving modes. This register is cleared only by POR and is not changed by any other device reset.
See the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for more
information. The PWRSTATECTL register is shown in Figure 9-20 and described in Table 9-36.
Figure 9-20. Power State Control Register (PWRSTATECTL)
31
3
2
1
0
Hibernation Recovery Branch Address
RW-0000 0000 0000 0000 0
Hibernation Mode
RW-0
Hibernation
RW-0
Standby
RW-0
Legend: R = Read Only, RW = Read/Write; -n = value after reset
Table 9-36. Power State Control Register Field Descriptions
Bit
Field
Description
31-3
Hibernation
Recovery Branch
Address
Used to provide a start address for execution out of the hibernation modes. See the KeyStone Architecture
DSP Bootloader User's Guide (SPRUGY5).
2
1
0
Hibernation Mode
Hibernation
Standby
Indicates whether the device is in hibernation mode 1 or mode 2.
•
•
0 = Hibernation mode 1
1 = Hibernation mode 2
Indicates whether the device is in hibernation mode or not.
•
•
0 = Not in hibernation mode
1 = Hibernation mode
Indicates whether the device is in standby mode or not.
•
•
0 = Not in standby mode
1 = standby mode
9.2.3.11 NMI Event Generation to C66x CorePac (NMIGRx) Register
NMIGRx registers generate NMI events to the corresponding C66x CorePac. The 66AK2Exx has has one
NMIGRx register. The NMIGR0 register generates an NMI event to C66x CorePac0. Writing a 1 to the
NMIG field generates an NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other
effect. The NMI event generation to the C66x CorePac is shown in Figure 9-21 and described in Table 9-
37.
Figure 9-21. NMI Generation Register (NMIGRx)
31
1
0
Reserved
NMIG
RW-0
R-0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
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Table 9-37. NMI Generation Register Field Descriptions
Bit
31-1
0
Field
Description
Reserved
NMIG
Reserved
Reads return 0
Writes:
•
•
0 = No effect
1 = Creates NMI pulse to the corresponding C66x CorePac — C66x CorePac0 for NMIGR0, etc.
9.2.3.12 IPC Generation (IPCGRx) Registers
The IPCGRx Registers facilitate inter-C66x CorePac interrupts.
The 66AK2E05 device has five IPCGRx registers (IPCGR0, IPCGR8-IPCGR11) and the 66AK2E02 has
two IPCGRx registers (IPCGR0 and IPCGR8). These registers can be used by external hosts or
CorePacs to generate interrupts to other CorePacs. A write of 1 to the IPCG field of the IPCGRx register
generates an interrupt pulse to the:
•
•
C66x CorePac0
ARM CorePac
These registers also provide a Source ID facility identifying up to 28 different sources of interrupts.
Allocation of source bits to source processor and meaning is entirely based on software convention. The
register field descriptions are given in the following tables. There can be numerous sources for these
registers as this is completely controlled by software. Any master that has access to BOOTCFG module
space can write to these registers. The IPC Generation Register is shown in Figure 9-22 and described in
Table 9-38.
Figure 9-22. IPC Generation Registers (IPCGRx)
31
4
3
1
0
SRCS27 - SRCS0
Reserved
R-000
IPCG
RW-0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-38. IPC Generation Registers Field Descriptions
Bit
Field
Description
31-4
SRCSx
Reads return current value of internal register bit.
Writes:
•
•
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
IPCG
Reserved
Reads return 0.
Writes:
•
•
0 = No effect
1 = Creates an inter-DSP/ARM interrupt.
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9.2.3.13 IPC Acknowledgment (IPCARx) Registers
The IPCARx registers facilitate inter-CorePac interrupt acknowledgment.
The 66AK2E05 device has five IPCARx registers and the 66AK2E02 has two IPCARx registers.These
registers also provide a Source ID facility by which up to 28 different sources of interrupts can be
identified. Allocation of source bits to source processor and meaning is entirely based on software
convention. The register field descriptions are given in the following tables. Virtually anything can be a
source for these registers as this is completely controlled by software. Any master that has access to
BOOTCFG module space can write to these registers. The IPC Acknowledgment Register is shown in the
following figure and table.
Figure 9-23. IPC Acknowledgment Registers (IPCARx)
31
4
3
0
SRCC27 - SRCC0
RW +0 (per bit field)
Reserved
R-0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-39. IPC Acknowledgment Registers Field Descriptions
Bit
Field
Description
31-4
SRCCx
Reads return current value of internal register bit.
Writes:
•
•
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
9.2.3.14 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is
the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register
appears on device pin HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock cycles (SYSCLK1/6)
followed by a deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking
window that is eight SYSCLK1/6-cycles long. Back-to-back writes to the IPCRGH register with the IPCG
bit (bit 0) set, generates only one pulse if the back-to-back writes to IPCGRH are less than the eight
SYSCLK1/6 cycle window — the pulse blocking window. To generate back-to-back pulses, the back-to-
back writes to the IPCGRH register must be written after the eight SYSCLK1/6 cycle pulse-blocking
window has elapsed. The IPC Generation Host Register is shown in Figure 9-24 and described in Table 9-
40.
Figure 9-24. IPC Generation Registers (IPCGRH)
31
4
3
1
0
SRCS27 - SRCS0
Reserved
R-000
IPCG
RW +0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-40. IPC Generation Registers Field Descriptions
Bit
Field
Description
31-4
SRCSx
Reads return current value of internal register bit.
Writes:
•
•
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
Reserved
Reserved
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Table 9-40. IPC Generation Registers Field Descriptions (continued)
Bit
Field
Description
0
IPCG
Reads return 0.
Writes:
•
•
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
9.2.3.15 IPC Acknowledgment Host (IPCARH) Register
The IPCARH register facilitates external host interrupts. Operation and use of the IPCARH register is the
same as for other IPCAR registers. The IPC Acknowledgment Host Register is shown in Figure 9-25 and
described in Table 9-41.
Figure 9-25. Acknowledgment Register (IPCARH)
31
4
3
0
SRCC27 - SRCC0
RW +0 (per bit field)
Reserved
R-0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-41. IPC Acknowledgment Register Field Descriptions
Bit
Field
Description
31-4
SRCCx
Reads the return current value of the internal register bit.
Writes:
•
•
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
9.2.3.16 Timer Input Selection Register (TINPSEL)
The Timer Input Selection Register selects timer inputs and is shown in Figure 9-26 and described in
Table 9-42.
Figure 9-26. Timer Input Selection Register (TINPSEL)
31
30
29
28
27
26
25
24
TINPHSEL15
RW-0
TINPLSEL15
RW-0
TINPHSEL14
RW-0
TINPLSEL14
RW-0
TINPHSEL13
RW-0
TINPLSEL13
RW-0
TINPHSEL12
RW-0
TINPLSEL12
RW-0
23
22
21
20
19
18
17
16
TINPHSEL11
RW-0
TINPLSEL11
RW-0
TINPHSEL10
RW-0
TINPLSEL10
RW-0
TINPHSEL9
RW-0
TINPLSEL9
RW-0
TINPHSEL8
RW-0
TINPLSEL8
RW-0
15
2
1
0
Reserved
R-0
LEGEND: R = Read only; RW = Read/Write; -n = value after reset
TINPHSEL0
RW-0
TINPLSEL0
RW-0
Table 9-42. Timer Input Selection Field Description
Bit Field
Description
31 TINPHSEL15 Input select for TIMER15 high.
•
•
0 = TIMI0
1 = TIMI1
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Bit Field
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Table 9-42. Timer Input Selection Field Description (continued)
Description
30 TINPLSEL15 Input select for TIMER15 low.
•
•
0 = TIMI0
1 = TIMI1
29 TINPHSEL14 Input select for TIMER14 high.
•
•
0 = TIMI0
1 = TIMI1
28 TINPLSE14
Input select for TIMER14 low.
•
•
0 = TIMI0
1 = TIMI1
27 TINPHSEL13 Input select for TIMER13 high.
•
•
0 = TIMI0
1 = TIMI1
26 TINPLSEL13 Input select for TIMER13 low.
•
•
0 = TIMI0
1 = TIMI1
25 TINPHSEL12 Input select for TIMER12 high.
•
•
0 = TIMI0
1 = TIMI1
24 TINPLSEL12 Input select for TIMER12low.
•
•
0 = TIMI0
1 = TIMI1
23 TINPHSEL11 Input select for TIMER11 high.
•
•
0 = TIMI0
1 = TIMI1
22 TINPLSEL11 Input select for TIMER11 low.
•
•
0 = TIMI0
1 = TIMI1
21 TINPHSEL10 Input select for TIMER10 high.
•
•
0 = TIMI0
1 = TIMI1
20 TINPLSEL10 Input select for TIMER10 low.
•
•
0 = TIMI0
1 = TIMI1
19 TINPHSEL9 Input select for TIMER9 high.
•
•
0 = TIMI0
1 = TIMI1
18 TINPLSEL9
Input select for TIMER9 low.
•
•
0 = TIMI0
1 = TIMI1
17 TINPHSEL8 Input select for TIMER8 high.
•
•
0 = TIMI0
1 = TIMI1
16 TINPLSEL8
15-2 Reserved
Input select for TIMER8 low.
•
•
0 = TIMI0
1 = TIMI1
1
TINPHSEL0 Input select for TIMER0 high.
•
•
0 = TIMI0
1 = TIMI1
0
TINPLSEL0
Input select for TIMER0 low.
•
•
0 = TIMI0
1 = TIMI1
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9.2.3.17 Timer Output Selection Register (TOUTPSEL)
The control register TOUTSEL handles the timer output selection and is shown in Figure 9-27 and
described in Table 9-43.
Figure 9-27. Timer Output Selection Register (TOUTPSEL)
31
10
9
5
4
0
Reserved
TOUTPSEL1
RW-00001
TOUTPSEL0
RW-00000
R-0000000000000000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-43. Timer Output Selection Field Description
Bit
Field
Description
31-10
9-5
Reserved
TOUTPSEL1
Reserved
Output select for TIMO1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00000: TOUTL0
00001: TOUTH0
00010: Reserved
00011: Reserved
00100: Reserved
00101: Reserved
00110: Reserved
00111: Reserved
01000: Reserved
01001: Reserved
01010: Reserved
01011: Reserved
01100: Reserved
01101: Reserved
01110: Reserved
01111: Reserved
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10000: TOUTL8
10001: TOUTH8
10010: TOUTL9
10011: TOUTH9
10100: TOUTL10
10101: TOUTH10
10110: TOUTL11
10111: TOUTH11
11000: TOUTL12
11001: TOUTH12
11010: TOUTL13
11011: TOUTH13
11100: TOUTL14
11101: TOUTH14
11110: TOUTL15
11111: TOUTH15
4-0
TOUTPSEL0
Output select for TIMO0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00000: TOUTL0
00001: TOUTH0
00010: Reserved
00011: Reserved
00100: Reserved
00101: Reserved
00110: Reserved
00111: Reserved
01000: Reserved
01001: Reserved
01010: Reserved
01011: Reserved
01100: Reserved
01101: Reserved
01110: Reserved
01111: Reserved
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10000: TOUTL8
10001: TOUTH8
10010: TOUTL9
10011: TOUTH9
10100: TOUTL10
10101: TOUTH10
10110: TOUTL11
10111: TOUTH11
11000: TOUTL12
11001: TOUTH12
11010: TOUTL13
11011: TOUTH13
11100: TOUTL14
11101: TOUTH14
11110: TOUTL15
11111: TOUTH15
9.2.3.18 Reset Mux (RSTMUXx) Register
Software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 for the C66x
CorePac and RSTMUX8-RSTMUX11 for the ARM CorePac (66AK2E05) or RSTMUX0 for the C66x
CorePac and RSTMUX8 for the ARM CorePac (66AK2E02) on the device. These registers are located in
Bootcfg memory space. The Reset Mux Register is shown in Figure 9-28 and Table 9-45 below.
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Figure 9-28. Reset Mux Register
31
10
9
8
7
5
4
3
1
0
Reserved
R-0000 0000 0000 0000 0000 00
EVTSTATCLR
RC-0
Reserved
R-0
DELAY
EVTSTAT
R-0
OMODE
RW-000
LOCK
RW-0
RW-100
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
Table 9-44. Reset Mux Register 0 (RSTMUX0) Field Descriptions
Bit
Field
Description
31-10 Reserved
Reserved
9
EVTSTATCLR
Clear event status
•
•
0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
8
Reserved
DELAY
Reserved
7-5
Delay cycles between NMI & local reset
•
•
•
•
•
•
•
•
000b = 256 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
010b = 1024 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
011b = 2048 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
100b = 4096 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b (default)
101b = 8192 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
110b = 16384 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
111b = 32768 SYSCLK1/6 cycles delay between NMI & local reset, when OMODE = 100b
4
EVTSTAT
OMODE
Event status
•
•
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
3-1
Timer event operation mode
•
•
•
•
•
000b = WD timer event input to the Reset Mux block does not cause any output event (default)
001b = Reserved
010b = WD Timer Event input to the Reset Mux block causes local reset input to C66x CorePac.
011b = WD Timer Event input to the Reset Mux block causes NMI input to C66x CorePac.
100b = WD Timer Event input to the Reset Mux block causes NMI input followed by local reset input to
C66x CorePac. Delay between NMI and local reset is set in DELAY bit field.
•
•
110b = Reserved
111b = Reserved
0
LOCK
Lock register fields
•
•
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
Table 9-45. Reset Mux Register 8..11(RSTMUX8-RSTMUX11) Field Descriptions
Bit
Field
Description
31-10 Reserved
9
Reserved
EVTSTATCLR
Clear event status
•
•
0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
8
Reserved
DELAY
Reserved
7-5
Delay cycles between interrupt and device reset
•
•
•
•
•
•
•
•
000b = 256 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
001b = 512 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
010b = 1024 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
011b = 2048 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
100b = 4096 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b (default)
101b = 8192 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
110b = 16384 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
111b = 32768 SYSCLK1/6 cycles delay between interrupt and device reset, when OMODE = 100b
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Table 9-45. Reset Mux Register 8..11(RSTMUX8-RSTMUX11) Field Descriptions (continued)
Bit
Field
Description
4
EVTSTAT
Event status
•
•
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
3-1
OMODE
Timer event operation mode
•
•
•
000b = WD timer event input to the Reset Mux block does not cause any output event (default)
001b = Reserved
010b = Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic
generates reset to PLL Controller.
•
011b = WD Timer Event input to the Reset Mux block causes Local Reset output event of the RSTMUX
logic to generate reset to PLL Controller.
•
•
100b = WD Timer Event input to the Reset Mux block causes an interrupt to be sent to the GIC.
101b = WD timer event input to the Reset Mux block causes device reset to 66AK2E0x. Note that for
Cortex-A15 processor watchdog timers, the Local Reset output event of the RSTMUX logic is connected to
the Device Reset generation to generate reset to PLL Controller.
•
•
110b = Reserved
111b = Reserved
0
LOCK
Lock register fields
•
•
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
9.2.3.19 Device Speed (DEVSPEED) Register
The Device Speed Register shows the device speed grade and is shown below.
Figure 9-29. Device Speed Register (DEVSPEED)
31
28
27
16
15
12
11
0
Reserved
DEVSPEED
R-n
Reserved
ARMSPEED
R-n
Legend: R = Read only; -n = value after reset
Table 9-46. Device Speed Register Field Descriptions
Bit
31-28 Reserved
27-16 DEVSPEED Indicates the speed of the device (read only)
Field
Description
Reserved. Read only
•
•
•
•
•
•
•
•
•
•
•
0b0000 0000 0000 = 800 MHz
0b0000 0000 0001 = 1000 MHz
0b0000 0000 001x = 1200 MHz
0b0000 0000 01xx = 1350 MHz
0b0000 0000 1xxx = 1400 MHz
0b0000 0001 xxxx = 1500 MHz
0b0000 001x xxxx = 1400 MHz
0b0000 01xx xxxx = 1350.8 MHz
0b0000 1xxx xxxx = 1200 MHz
0b0001 xxxx xxxx= 1000 MHz
0b001x xxxx xxxx = 800 MHz
15-12 Reserved
Reserved. Read only
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Table 9-46. Device Speed Register Field Descriptions (continued)
Bit
Field
Description
11-0
ARMSPEED Indicates the speed of the ARM (read only)
•
•
•
•
•
•
•
•
•
•
•
0b0000 0000 0000 = 800 MHz
0b0000 0000 0001 = 1000 MHz
0b0000 0000 001x = 1200 MHz
0b0000 0000 01xx = 1350 MHz
0b0000 0000 1xxx = 1400 MHz
0b0000 0001 xxxx = 1500 MHz
0b0000 001x xxxx = 1400 MHz
0b0000 01xx xxxx = 1350.8 MHz
0b0000 1xxx xxxx = 1200 MHz
0b0001 xxxx xxxx= 1000 MHz
0b001x xxxx xxxx = 800 MHz
9.2.3.20 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
The registers defined in ARM Configuration Register 0 (ARMENDIAN_CFGr_0) and ARM Configuration
Register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral
MMRs shows up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant
view of the peripheral MMRs when performing a 32-bit access. (Only one of the eight register sets is
shown.)
Figure 9-30. ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
31
8
7
0
BASEADDR
RW
Reserved
R-0000 0000
Legend: RW = Read/Write; R = Read only
Table 9-47. ARM Endian Configuration Register 0
Default Values
DEFAULT
ARM ENDIAN CONFIGURATION REGISTER 0
ARMENDIAN_CFG0_0
VALUES
0x0001C000
0x00020000
0x000BC000
0x00210000
0x00023A00
0x00240000
0x01000000
0xFFFFFF00
ARMENDIAN_CFG1_0
ARMENDIAN_CFG2_0
ARMENDIAN_CFG3_0
ARMENDIAN_CFG4_0
ARMENDIAN_CFG5_0
ARMENDIAN_CFG6_0
ARMENDIAN_CFG7_0
Table 9-48. ARM Endian Configuration Register 0 Field Descriptions
Bit
Field
Description
31-8
BASEADDR
24-bit Base Address of Configuration Region R
This base address defines the start of a contiguous block of Memory Mapped Register space for which a
word swap is done by the ARM CorePac bridge.
7-0
Reserved
Reserved
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9.2.3.21 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
Figure 9-31. ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
31
4
3
0
Reserved
SIZE
RW
R-0000 0000 0000 0000 0000 0000 0000
Legend: RW = Read/Write; R = Read only
Table 9-49. ARM Endian Configuration Register 1
Default Values
DEFAULT
ARM ENDIAN CONFIGURATION REGISTER 1
ARMENDIAN_CFG0_1
VALUES
0x00000006
0x00000009
0x00000004
0x00000008
0x00000005
0x00000006
0x00000000
0x00000000
ARMENDIAN_CFG1_1
ARMENDIAN_CFG2_1
ARMENDIAN_CFG3_1
ARMENDIAN_CFG4_1
ARMENDIAN_CFG5_1
ARMENDIAN_CFG6_1
ARMENDIAN_CFG7_1
Table 9-50. ARM Endian Configuration Register 1 Field Descriptions
Bit
Field
Description
31-4
3-0
Reserved
SIZE
Reserved
4-bit encoded size of Configuration Region R
The value in the SIZE field defines the size of the contiguous block of Memory Mapped Register space for
which a word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR).
•
•
•
•
•
•
•
•
•
•
•
•
•
0000 : 64KB
0001 : 128KB
0010 : 256KB
0011 : 512KB
0100 : 1MB
0101 : 2MB
0110 : 4MB
0111 : 8MB
1000 : 16MB
1001 : 32MB
1010 : 64MB
1011 : 128MB
Others : Reserved
9.2.3.22 ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
The registers defined in ARM Configuration Register 2 (ARMENDIAN_CFGr_2) enable the word swapping
of a region.
Figure 9-32. ARM Endian Configuration Register 2 (ARMENDIAN_CFGr_2), r=0..7
31
1
0
DIS
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
RW-0
Legend: RW = Read/Write
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Table 9-51. ARM Endian Configuration Register 2
Default Values
DEFAULT
VALUES
ARM ENDIAN CONFIGURATION REGISTER 2
ARMENDIAN_CFG0_2
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
0x00000001
ARMENDIAN_CFG1_2
ARMENDIAN_CFG2_2
ARMENDIAN_CFG3_2
ARMENDIAN_CFG4_2
ARMENDIAN_CFG5_2
ARMENDIAN_CFG6_2
ARMENDIAN_CFG7_2
Table 9-52. ARM Endian Configuration Register 2 Field Descriptions
Bit
31-1
0
Field
Description
Reserved
DIS
Reserved
Disabling the word swap of a region
•
•
0 : Enable word swap for region
1 : Disable word swap for region
9.2.3.23 Chip Miscellaneous Control (CHIP_MISC_CTL0) Register
Figure 9-33. Chip Miscellaneous Control Register (CHIP_MISC_CTL0)
31
19
18
17
AETMUXSEL1
RW-0
Reserved
R-0
USB_PME_EN
RW-0
16
15
13
12
11
3
2
0
AETMUXSEL0
RW-0
Reserved
RW -0
MSMC_BLOCK_PARITY_RST
RW-0
Reserved
RW-0
QM_PRIORITY
RW-0
Legend: R = Read only; W = Write only; -n = value after reset
Table 9-53. Chip Miscellaneous Control Register (CHIP_MISC_CTL0) Field Descriptions
Bit
Field
Description
31-19 Reserved
Reserved.
18
17
USB_PME_EN
Enables wakeup event generation from USB
•
•
0 = Disable PME event generation
1 = Enable PME event generation
AETMUXSEL1
AETMUXSEL0
Controls the mux that selects whether an AET event from EDMA CC2 or EDMA CC3 is
connected to the C66x Interrupt Controller
•
•
0 = EDMA CC2 (default)
1 = EDMA CC3
16
Controls the mux that selects whether an AET event from EDMA CC2 or EDMA CC4 is
connected to the C66x Interrupt Controller
•
•
0 = EDMA CC2 (default)
1 = EDMA CC4
15-13 Reserved
12
MSMC_BLOCK_PARITY_RST Controls MSMC parity RAM reset. When set to ‘1’ means the MSMC parity RAM will not be reset.
11-3
2-0
Reserved
Reserved
QM_PRIORITY
Control the priority level for the transactions from QM Master port, which access the external
linking RAM.
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9.2.3.24 Chip Miscellaneous Control (CHIP_MISC_CTL1) Register
Figure 9-34. Chip Miscellaneous Control Register (CHIP_MISC_CTL1)
31
15
14
IO_TRACE_SEL
RW-0
13
0
Reserved
Reserved
RW-0
R- 0000 0000 00000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 9-54. Chip Miscellaneous Control Register (CHIP_MISC_CTL1) Field Descriptions
Bit
Field
Description
31-15 Reserved
Reserved.
14
IO_TRACE_SEL
This bit controls the pin muxing of GPIO[31:17] and EMU[33:19] pin
•
•
0 = GPIO[31:17] is selected
1 = EMU[33:19] pins is selected
13-0
Reserved
9.2.3.25 System Endian Status Register (SYSENDSTAT)
This register provides a way for reading the system endianness in an endian-neutral way. A zero value
indicates big endian and a non-zero value indicates little endian. The SYSENDSTAT register captures the
LENDIAN bootmode pin and is used by the BOOTROM to guide the bootflow. The value is latched on the
rising edge of POR or RESETFULL .
Figure 9-35. System Endian Status Register
31
1
0
SYSENDSTAT
R-0
Reserved
R-0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
Table 9-55. System Endian Status Register Descriptions
Bit
31-1
0
Field
Description
Reserved
SYSENDSTAT
Reserved
Reflects the same value as the LENDIAN bit in the DEVSTAT register.
•
•
0 - SoC is in Big Endian
1 - SoC is in Little Endian
9.2.3.26 SYNECLK_PINCTL Register
This register controls the routing of recovered clock signals from any Ethernet port (SGMII/XFI of the
multiport switches) to the clock output TSRXCLKOUT0/TSRXCLKOUT1.
Figure 9-36. SYNECLK_PINCTL Register
31
7
6
4
3
2
0
Reserved
TSRXCLKOUT1SEL
RW-0
Reserved
TSRXCLKOUT0SEL
RW-0
R-0000 0000 0000 0000 0000 0000 0
Legend: RW = Read/Write; - n = value after reset
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Table 9-56. SYNECLK_PINCTL Register Descriptions
Bit
Field
Description
Reserved
31-7
6-4
Reserved
TSRXCLKOUT1SEL
•
•
•
•
•
•
•
•
000 - SGMII Lane 0 rxbclk
001 - SGMII Lane 1 rxbclk
010 - SGMII Lane 2 rxbclk
011 - SGMII Lane 3 rxbclk
100 - XFI Lane 0 rxbclk
101 - XFI Lane 1 rxbclk
110 - XFI Lane 2 rxbclk
111 - XFI Lane 3 rxbclk
3
Reserved
Reserved
2-0
TSRXCLKOUT0SEL
•
•
•
•
•
•
•
•
000 - SGMII Lane 0 rxbclk
001 - SGMII Lane 1 rxbclk
010 - SGMII Lane 2 rxbclk
011 - SGMII Lane 3 rxbclk
100 - XFI Lane 0 rxbclk
101 - XFI Lane 1 rxbclk
110 - XFI Lane 2 rxbclk
111 - XFI Lane 3 rxbclk
9.2.3.27 USB PHY Control (USB_PHY_CTLx) Registers
The following registers control the USB PHY.
Figure 9-37. USB_PHY_CTL0 Register
31
12
11
Reserved
PHY_RTUNE_ACK
R-0
8
R-0
5
10
9
7
6
PHY_RTUNE_REQ
Reserved
PHY_TC_VATESTENB PHY_TC_TEST_POWERDOWN PHY_TC_TEST_POWERDOWN
_SSP
_HSP
R/W-0
4
R-0
R/W-00
R/W-0
R/W-0
3
2
1
0
PHY_TC_LOOPBACKENB
R/W-0
Reserved
R-0
UTMI_VBAUSVLDEXT
R/W-0
UTMI_TXBITSTUFFENH
R/W-0
UTMI_TXBITSTUFFEN
R/W-0
Legend: R = Read only; W = Write only; -n = value after reset
Table 9-57. USB_PHY_CTL0 Register Field Descriptions
Bit
Field
Description
31-12
11
Reserved
Reserved
PHY_RTUNE_ACK
The PHY uses an external resistor to calibrate the termination impedances of the PHY's high-
speed inputs and outputs.
The resistor is shared between the USB2.0 high-speed outputs and the Super-speed I/O. Each
time the PHY is taken out of a reset, a termination calibration is performed. For SS link, the
calibration can also be requested externally by asserting the PHY_RTUNE_REQ. When the
calibration is complete, the PHY_RTUNE_ACK transitions low.
A resistor calibration on the SS link cannot be performed while the link is operational
10
9
PHY_RTUNE_REQ
Reserved
See PHY_RTUNE_ACK.
Reserved
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Table 9-57. USB_PHY_CTL0 Register Field Descriptions (continued)
Bit
Field
Description
8-7
PHY_TC_VATESTENB
Analog Test Pin Select.
Enables analog test voltages to be placed on the ID pin.
•
•
•
•
11 = Invalid setting.
10 = Invalid setting.
01 = Analog test voltages can be viewed or applied on ID.
00 = Analog test voltages cannot be viewed or applied on ID.
6
5
4
PHY_TC_TEST_POWERDOWN SS Function Circuits Power-Down Control.
_SSP
Powers down all SS function circuitry in the PHY for IDDQ testing.
PHY_TC_TEST_POWERDOWN HS Function Circuits Power-Down Control
_HSP
Powers down all HS function circuitry in the PHY for IDDQ testing.
PHY_TC_LOOPBACKENB
Loop-back Test Enable
Places the USB3.0 PHY in HS Loop-back mode, which concurrently enables the HS receive
and transmit logic.
•
•
1 = During HS data transmission, the HS receive logic is enabled.
0 = During HS data transmission, the HS receive logic is disabled.
3
2
Reserved
•
Reserved
UTMI_VBAUSVLDEXT
External VBUS Valid Indicator
Function: Valid in Device mode and only when the VBUSVLDEXTSEL signal is set to 1'b1.
VBUSVLDEXT indicates whether the VBUS signal on the USB cable is valid. In addition,
VBUSVLDEXT enables the pull-up resistor on the D+ line.
•
•
1 = VBUS signal is valid, and the pull-up resistor on D+ is enabled.
0 = VBUS signal is not valid, and the pull-up resistor on D+ is disabled.
1
0
UTMI_TXBITSTUFFENH
UTMI_TXBITSTUFFEN
High-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAINH[7:0] when OPMODE[1:0]=11b.
•
•
1 = Bit stuffing is enabled.
0 = Bit stuffing is disabled.
Low-byte Transmit Bit-Stuffing Enable
Function: controls bit stuffing on DATAIN[7:0] when OPMODE[1:0]=11b.
•
•
1 = Bit stuffing is enabled.
0 = Bit stuffing is disabled.
Figure 9-38. USB_PHY_CTL1 Register
31
6
5
Reserved
R-0
PIPE_REF_CLKREQ_N
R-0
4
3
2
1
PIPE_ALT_CLK_REQ
R-0
0
PIPE_TX2RX_LOOPBK
R/W-0
PIPE_EXT_PCLK_REQ
R/W-0
PIPE_ALT_CLK_SEL
R/W-0
PIPE_ALT_CLK_EN
R/W-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-58. USB_PHY_CTL1 Register Field Descriptions
Bit
31-6
5
Field
Description
Reserved
Reserved
PIPE_REF_CLKREQ_N
Reference Clock Removal Acknowledge.
When the pipeP_power-down control into the PHY turns off the MPLL in the P3 state,
PIPE_REF_CLKREQ_N is asserted after the PLL is stable and the reference clock can be
removed.
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Table 9-58. USB_PHY_CTL1 Register Field Descriptions (continued)
Bit
Field
Description
4
PIPE_TX2RX_LOOPBK
Loop-back.
When this signal is asserted, data from the transmit predriver is looped back to the receiver
slicers. LOS is bypassed and based on the tx_en input so that rx_los=!tx_data_en.
3
2
PIPE_EXT_PCLK_REQ
PIPE_ALT_CLK_SEL
External PIPE Clock Enable Request.
When asserted, this signal enables the pipeP_pclk output regardless of power state (along
with the associated increase in power consumption).
Alternate Clock Source Select.
Selects the alternate clock sources instead of the internal MPLL outputs for the PCS clocks.
•
•
1 = Uses alternate clocks.
0 = Users internal MPLL clocks.
Change only during a reset.
1
0
PIPE_ALT_CLK_REQ
PIPE_ALT_CLK_EN
Alternate Clock Source Request.
Indicates that the alternate clocks are needed by the slave PCS (that is, to boot the master
MPLL). Connect to the alt_clk_en on the master.
Alternate Clock Enable.
Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary, powers up the MPLL).
Figure 9-39. USB_PHY_CTL2 Register
31
20
30
Reserved
29
19
27
26
23
22
PHY_PC_TXRISETUNE
R/W-01
15
21
PHY_PC_LOS_BIAS
PHY_PC_TXVREFTUNE
R-0
R/W-101
18
R/W-1000
17
16
14
PHY_PC_TXRESTUNE
PHY_PC_
PHY_PC_TXPREEMPAMPTUNE
PHY_PC_
TXPREEMPPULSETUNE
TXHSXVTUNE
R/W-01
10
R/W-0
R/W-00
R/W-11
13
9
7
6
4
3
2
0
PHY_PC_TXFSLSTUNE
PHY_PC_SQRXTUNE
R/W-011
PHY_PC_OTGTUNE
Reserved
PHY_PC_
COMPDISTUNE
R/W-0011
R/W-100
R-0
R/W-100
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-59. USB_PHY_CTL2 Register Field Descriptions
Bit
Field
Description
31-30
29-27
Reserved
Reserved
PHY_PC_LOS_BIAS
Loss-of-Signal Detector Threshold Level Control.
Sets the LOS detection threshold level.
•
•
+1 = results in a +15 mVp incremental change in the LOS threshold.
-1 = results in a -15 mVp incremental change in the LOS threshold.
Note: the 000b setting is reserved and must not be used.
HS DC Voltage Level Adjustment.
26-23
22-21
PHY_PC_TXVREFTUNE
PHY_PC_TXRISETUNE
Adjusts the high-speed DC level voltage.
•
•
+1 = results in a +1.25% incremental change in high-speed DC voltage level.
-1 = results in a -1.25% incremental change in high-speed DC voltage level.
HS Transmitter Rise/Fall TIme Adjustment.
Adjusts the rise/fall times of the high-speed waveform.
•
•
+1 = results in a -4% incremental change in the HS rise/fall time.
-1 = results in a +4% incremental change in the HS rise/fall time.
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Table 9-59. USB_PHY_CTL2 Register Field Descriptions (continued)
Bit
Field
Description
20-19
PHY_PC_TXRESTUNE
USB Source Impedance Adjustment.
Some applications require additional devices to be added on the USB, such as a series
switch, which can add significant series resistance. This bus adjusts the driver source
impedance to compensate for added series resistance on the USB.
18
PHY_PC_
HS Transmitter Pre-Emphasis Duration Control.
TXPREEMPPULSETUNE
Controls the duration for which the HS pre-emphasis current is sourced onto DP or DM. It is
defined in terms of unit amounts. One unit of pre-emphasis duration is approximately 580 ps
and is defined as 1x pre-emphasis duration. This signal valid only if either
txpreempamptune[1] or txpreempamptune[0] is set to 1.
•
•
1 = 1x, short pre-emphasis current duration.
0 = 2x, long pre-emphasis current duration.
17-16
PHY_PC_TXPREEMPAMPTUNE HS Transmitter Pre-Emphasis Current Control.
Controls the amount of current sourced to DP and DM after a J-to-K or K-to-J transition.
The HS Transmitter pre-emphasis current is defined in terms of unit amounts. One unit
amount is approximately 600 µ;A and is defined as 1x pre-emphasis current.
•
•
•
•
11 = 3x pre-emphasis current.
10 = 2x pre-emphasis current.
01 = 1x pre-emphasis current.
00 = HS Transmitter pre-emphasis is disabled.
15-14
13-10
PHY_PC_TXHSXVTUNE
PHY_PC_TXFSLSTUNE
Transmitter High-Speed Crossover Adjustment.
Adjusts the voltage at which the DP and DM signals cross while transmitting in HS mode.
•
•
•
•
11 = Default setting.
10 = +15 mV
01 = -15 mV
00 = Reserved
FS/LS Source Impedance Adjustment.
Adjusts the low- and full-speed single-ended source impedance while driving high.
This parameter control is encoded in thermometer code.
•
•
+1 = results in a -2.5% incremental change in threshold voltage level.
-1 = results in a +2.5% incremental change in threshold voltage level.
Any non-thermometer code setting (that is 1001) is not supported and reserved.
Squelch Threshold Adjustment.
9-7
6-4
PHY_PC_SQRXTUNE
PHY_PC_OTGTUNE
Adjusts the voltage level for the threshold used to detect valid high-speed data.
•
•
+1 = results in a -5% incremental change in threshold voltage level.
-1 = results in a +5% incremental change in threshold voltage level.
VBUS Valid Threshold Adjustment.
Adjusts the voltage level for the VBUS valid threshold.
•
•
+1 = results in a +1.5% incremental change in threshold voltage level.
-1 = results in a -1.5% incremental change in threshold voltage level.
3
Reserved
Reserved
2-0
PHY_PC_COMPDISTUNE
Disconnect Threshold Adjustment.
Adjusts the voltage level for the threshold used to detect a disconnect event at the host.
•
•
+1 = results in a +1.5% incremental change in the threshold voltage level.
-1 = results in a -1.5% incremental change in the threshold voltage level.
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Figure 9-40. USB_PHY_CTL3 Register
31
22
30
29
23
Reserved
PHY_PC_PCS_TX_SWING_FULL
R-0
16
R/W-1111000
17
11
10
5
4
0
PHY_PC_PCS_TX_DEEMPH_6DB
R/W-100000
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Reserved
PHY_PC_PCS_TX_DEEMPH_3P5DB
PHY_PC_LOS_LEVEL
R/W-01001
R-0
R/W-010101
Table 9-60. USB_PHY_CTL3 Register Field Descriptions
Bit
Field
Description
31-30
29-23
Reserved
Reserved
PHY_PC_PCS_TX_SWING_
FULL
Tx Amplitude (Full Swing Mode).
Sets the launch amplitude of the transmitter. It can be used to tune Rx eye for compliance.
Tx De-Emphasis at 6 dB.
22-17
PHY_PC_PCS_TX_DEEMPH_
6DB
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to
the PIPE3 specification). This bus is provided for completeness and as a second potential
launch amplitude.
16-11
10-5
Reserved
Reserved
PHY_PC_PCS_TX_DEEMPH_
3P5DB
Tx De-Emphasis at 3.5 dB.
Sets the Tx driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 10b (according to
the PIPE3 specification). Can be used for Rx eye compliance.
4-0
PHY_PC_LOS_LEVEL
Loss-of-Signal Detector Sensitivity Level Control.
Sets the LOS detection threshold level. This signal must be set to 0x9.
Figure 9-41. USB_PHY_CTL4 Register
31
PHY_SSC_EN
R/W-1
30
29
28
PHY_REF_USE_PAD
PHY_REF_SSP_EN
PHY_MPLL_REFSSC_CLK_EN
R/W-0
21
R/W-0
19
R/W-0
17
27
22
20
18
PHY_FSEL
R/W-100111
16
PHY_RETENABLEN
PHY_REFCLKSEL
R/W-10
PHY_COMMONONN
Reserved
R/W-1
15
R/W-0
11
R-0
6
14
12
7
0
PHY_OTG_VBUSVLDEXTSEL
PHY_OTG_
OTGDISABLE
PHY_PC_TX_VBOOST
_LVL
PHY_PC_LANE0_TX_TERM_
OFFSET
Reserved
R/W-0
R/W-1
R/W-100
R/W-00000
R-0
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-61. USB_PHY_CTL4 Register Field Descriptions
Bit
Field
Description
Spread Spectrum Enable.
31
PHY_SSC_EN
Enables spread spectrum clock production (0.5% down-spread at ~31.5 KHz) in the USB3.0
PHY. If the reference clock already has spread spectrum applied, ssc_en must be de-asserted.
30
29
PHY_REF_USE_PAD
PHY_REF_SSP_EN
Select Reference Clock Connected to ref_pad_clk_{p,m}.
When asserted, selects the external ref_pad_clk_{p,m} inputs as the reference clock source.
When de-asserted, ref_alt_clk_{p,m} are selected for an on-chip reference clock source.
Reference Clock Enables for SS function.
Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de asserted
until the reference clock is running at the appropriate frequency, at which point ref_ssp_en can
be asserted. For lower power states, ref_ssp_en can also be de asserted.
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Table 9-61. USB_PHY_CTL4 Register Field Descriptions (continued)
Bit
Field
Description
28
PHY_MPLL_REFSSC_CLK_EN Double-Word Clock Enable.
Enables/disables the mpll_refssc_clk signal. To prevent clock glitch, it must be changed when
the PHY is inactive.
27-22
21
PHY_FSEL
Frequency Selection.
Selects the reference clock frequency used for both SS and HS operations. The value for fsel
combined with the other clock and enable signals will determine the clock frequency used for
SS and HS operations and if a shared or separate reference clock will be used.
PHY_RETENABLEN
Lowered Digital Supply Indicator.
Indicates that the vp digital power supply has been lowered in Suspend mode. This signal
must be de-asserted before the digital power supply is lowered.
•
•
1 = Normal operating mode.
0 = The analog blocks are powered down.
20-19
PHY_REFCLKSEL
Reference Clock Select for PLL Block.
Selects reference clock source for the HS PLL block.
•
•
•
11 = HS PLL uses EXTREFCLK as reference.
10 = HS PLL uses either ref_pad_clk_{p,m} or ref_alt_clk_{p,m} as reference.
x0 = Reserved.
18
PHY_COMMONONN
Common Block Power-Down Control.
Controls the power-down signals in the HS Bias and PLL blocks when the USB3.0 PHY is in
Suspend or Sleep mode.
•
•
1 = In Suspend or Sleep mode, the HS Bias and PLL blocks are powered down.
0 = In Suspend or Sleep mode, the HS Bias and PLL blocks remain powered and continue
to draw current.
17
16
Reserved
Reserved
PHY_OTG_VBUSVLDEXTSEL
External VBUS Valid Select.
Selects the VBUSVLDEXT input or the internal Session Valid comparator to indicate when the
VBUS signal on the USB cable is valid.
•
•
1 = VBUSVLDEXT input is used.
0 = Internal Session Valid comparator is used.
15
PHY_OTG_OTGDISABLE
OTG Block Disable.
Powers down the OTG block, which disables the VBUS Valid and Session End comparators.
The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP
in Device mode) is always on irrespective of the state of otgdisable. If the application does not
use the OTG function, setting this signal to high to save power.
•
•
1 = OTG block is powered down.
0 = OTG block is powered up.
14-12
PHY_PC_TX_VBOOST_LVL
Tx Voltage Boost Level.
Sets the boosted transmit launch amplitude (mVppd).
The default setting is intended to set the launch amplitude to approximately 1,008mVppd
.
•
•
+1 = results in a +156 mVppd change in the Tx launch amplitude.
-1 = results in a -156 mVppd change in the Tx launch amplitude.
11-7
6-0
PHY_PC_LANE0_TX_TERM_
OFFSET
Transmitter Termination Offset.
Enables adjusting the transmitter termination value from the default value of 60 Ω.
Reserved
Reserved
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Figure 9-42. USB_PHY_CTL5 Register
31
12
21
20
19
13
0
Reserved
R-0
PHY_REF_CLKDIV2
PHY_MPLL_MULTIPLIER[6:0]
R/W-0
3
R/W +0011001
2
4
PHY_SSC_REF_CLK_SEL
R/W-000000000
Reserved
R-0
PHY_SSC_RANGE
R/W-000
Legend: R = Read only; R/W = Read/Write, -n = value after reset
Table 9-62. USB_PHY_CTL5 Register Field Descriptions
Bit
Field
Description
31-21
20
Reserved
Reserved
PHY_REF_CLKDIV2
Input Reference Clock Divider Control.
If the input reference clock frequency is greater than 100 MHz, this signal must be asserted.
The reference clock frequency is then divided by 2 to keep it in the range required by the
MPLL.
When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference
clock frequency divided by 4.
19-13
12-4
PHY_MPLL_MULTIPLIER[6:0]
PHY_SSC_REF_CLK_SEL
MPLL Frequency Multiplier Control.
Multiplies the reference clock to a frequency suitable for intended operating speed.
Spread Spectrum Reference Clock Shifting.
Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
corresponds to frequency-synthesis coefficient.
•
•
. ssc_ref_clk_sel[8:6] = modulous - 1
. ssc_ref_clk_sel[5:0] = 2's complement push amount.
3
Reserved
Reserved
2-0
PHY_SSC_RANGE
Spread Spectrum Clock Range.
Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is
spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator.
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10 Device Operating Conditions
10.1 Absolute Maximum Ratings(1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
CVDD
-0.3 V to 1.3 V
-0.3 V to 1.3 V
CVDD1
DVDD15
DVDD18
DDR3VREFSSTL
VDDAHV
VDDALV
-0.3 V to 1.98 V
-0.3 V to 2.45 V
0.49 × DVDD15 to 0.51 × DVDD15
-0.3 V to 1.98 V
-0.3 V to 0.935 V
-0.3V to 3.63 V
USB0DVDD33, USB0DVDD33
VDDUSB0, VDDUSB1
USB0VP, USB1VP
Supply voltage range(2)
:
-0.3V to 0.935 V
-0.3V to 0.935 V
USB0VPH, USB1VPH
USB0VPTX, USB1VPTX
AVDDA1, AVDDA2, AVDDA3
AVDDA6, AVDDA7
-0.3V to 3.63 V
-0.3V to 0.935 V
-0.3 V to 1.98 V
-0.3 V to 1.98 V
AVDDA8, AVDDA9, AVDDA10
VSS Ground
0 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.98 V
LVCMOS (1.8 V)
DDR3
I2C
-0.3 V to 2.45 V
Input voltage (VI) range(3)
:
LVDS
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.3 V
LJCB
SerDes
-0.3 V to VDDAHV1+0.3 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.98 V
LVCMOS (1.8 V)
DDR3
Output voltage (VO) range(3)
:
I2C
-0.3 V to 2.45 V
SerDes
-0.3 V to VDDAHV+0.3 V
0°C to 85°C
Commercial
Operating case temperature range, TC:
Extended
-40°C to 100°C
HBM (human body model)(5)
CDM (charged device model)(6)
±1000 V
(4)
ESD stress voltage, VESD
±250 V
LVCMOS (1.8 V)
20% overshoot/undershoot for 20% of
signal duty cycle
Overshoot/undershoot(7)
DDR3
I2C
Storage temperature range, Tstg
:
-65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS
.
(3) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
(4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(5) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary
precautions are taken. Pins listed as 1000 V may actually have higher performance.
(6) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
(7) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS
signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be VSS - 0.20 × DVDD18
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10.2 Recommended Operating Conditions(1)(2)
MIN
1.0
NOM
1.05
MAX
1.10
UNIT
Initial(3)
V
SRVnom*0.95(4)
SRVnom
SRVnom*1.05
CVDD
SR core supply
1250MHz and
1400MHz Device
V
CVDD1
Core supply
0.95
1.71
1.0
1.05
1.89
V
V
V
DVDD18
1.8-V supply I/O voltage
1.8
DDR3
1.425
1.5
1.575
DVDD15
DDR3 I/O voltage
DDR3L @ 1.5 V
DDR3L @ 1.35 V
1.425
1.5
1.575
1.283
1.35
1.45
DDR3VREFSSTL
VDDAHV
DDR3 reference voltage
SerDes regulator supply
SerDes termination supply
PLL analog, DDR DLL supply
0.85-V USB PHY supply
3.3-V USB
0.49 × DVDD15
1.71
0.5 × DVDD15
0.51 × DVDD15
1.89
V
V
V
V
V
V
1.8
0.85
1.8
VDDALH
AVDDx(5)
0.807
0.892
1.71
1.89
USB0VP, USB1VP
0.807
0.85
3.3
0.892
USB0VPH,
USB1VPH
3.135
3.465
USB0VPTX,
USB1VPTX
USBPHY Transmit supply
USB PHY supply
USB 3.3-V high supply
Ground
0.807
0.807
3.135
0.85
0.85
3.3
0
0.892
0.892
3.465
0
V
V
V
VDDUSB0,
VDDUSB1
USB0DVDD33,
USB1DVDD33
VSS
0
0.65 × DVDD18
0.7 × DVDD18
V
V
LVCMOS (1.8 V)
I2C
(6)
V
VIH
High-level input voltage
DDR3 EMIF
LVCMOS (1.8 V)
DDR3 EMIF
I2C
VREFSSTL + 0.1
V
0.35 × DVDD18
VREFSSTL - 0.1
0.3 × DVDD18
85
V
(6)
-0.3
V
VIL
Low-level input voltage
V
Commercial
Extended
0
°C
°C
TC
Operating case temperature
-40
100
(1) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SerDes I/Os comply with the XAUI
Electrical Specification, IEEE 802.3ae-2002.
(2) All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
(3) Users are required to program their board CVDD supply initial value to 1.0 V on the device. The initial CVDD voltage at power-on will be
1.0V nominal and it must transition to VID set value, immediately after being presented on the VCNTL pins. This is required to maintain
full power functionality and reliability targets guaranteed by TI.
(4) SRVnom refers to the unique SmartReflex core supply voltage that has a potential range of 0.8 V and 1.1 V which preset from the
factory for each individual device. Your device may never be programmed to operate at the upper range but has been designed
accordingly should it be determined to be acceptable or necessary. Power supplies intended to support the variable SRV function shall
be capable of providing a 0.8V-1.1V dynamic range using a 4- or 6-bit binary input value which as provided by the SOC SmartReflex
output.
(5) Where x=1,2,3,4... to indicate all supplies of the same kind.
(6) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
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10.3 Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
TEST
PARAMETER
CONDITIONS(1)
MIN
DVDD18 - 0.45
DVDD15 - 0.4
TYP
MAX
UNIT
LVCMOS (1.8 V)
DDR3
IO = IOH
(2)
VOH
High-level output voltage
V
(3)
I2C(3)
LVCMOS (1.8 V)
DDR3
IO = IOL
0.45
0.4
(2)
VOL
Low-level output voltage
Input current [DC]
V
IO = 3 mA, pulled up
to 1.8 V
I2C
0.4
No IPD/IPU
-10
50
10
170
-50
LVCMOS (1.8 V)
I2C
Internal pullup
Internal pulldown
100
µA
µA
II(4)
-170
-100
0.1 × DVDD18 V < VI
< 0.9 × DVDD18 V
-10
10
LVCMOS (1.8 V)
DDR3
I2C(5)
-6
-8
High-level output current
[DC]
IOH
mA
(5)
LVCMOS (1.8 V)
6
8
IOL
Low-level output current [DC] DDR3
I2C
mA
µA
3
LVCMOS (1.8 V)
-10
-10
-10
10
10
10
(6)
IOZ
Off-state output current [DC] DDR3
I2C
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) For USB High-Speed, Full-Speed, and Low -Speed modes, USB I/Os adhere to Universal Serial Bus, revision 2.0 standard. For USB
Super-Speed mode, USB I/Os adhere to Universal Serial Bus, revision 3.1 specification, revision 1.0 standard.
(3) I2C uses open collector IOs and does not have a VOH Minimum.
(4) II applies to input-only pins and bidirectional pins. For input-only pins, II indicates the input leakage current. For bidirectional pins, II
includes input leakage current and off-state (Hi-Z) output leakage current.
(5) I2C uses open collector IOs and does not have a IOH Maximum.
(6) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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10.4 Power Supply to Peripheral I/O Mapping
Table 10-1. Power Supply to Peripheral I/O Mapping(1)(2)
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
POWER SUPPLY
I/O BUFFER TYPE
ASSOCIATED PERIPHERAL
CORECLK(P|N) PLL input buffer
DDR3CLK(P|N) PLL input buffer
NETCPCLK(P|N) PLL input buffer
USBCLK(P|M) PLL input buffer
CVDD
Supply core AVS voltage
LJCB
SGMII0CLK(P|N) PLL input buffer
SERDES low voltage
VDDALV
VDDAHV
DVDD15
SerDes/CML
PCIECLK(P|N) SerDes Clock Reference
HYPCLK(P|N) SerDes Clock Reference
XFICLK(P|N) SerDes Clock Reference(3)
All DDR3 memory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
SerDes IO voltage
SerDes/CML
DDR3 memory I/O voltage
DDR3 (1.5/1.35 V)
All JTAG and EMU peripheral I/O buffer
All TIMER peripheral I/O buffer
All SPI peripheral I/O buffer
All TSIP peripheral I/O buffer
LVCMOS (1.8 V)
DVDD18
1.8-V supply I/O voltage
All RESETs, NMI, control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All Hyperlink sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
All UART peripheral I/O buffer
Open-drain (1.8 V)
All I2C peripheral I/O buffer
(1) Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to
power peripheral I/O buffers and clock input buffers.
(2) Please see the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for more information about individual
peripheral I/O.
(3) 10 GbE supported in 66AK2E05 only.
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11 66AK2E0x Peripheral Information and Electrical Specifications
This chapter covers the various peripherals on the 66AK2E0x device. Peripheral-specific information,
timing diagrams, electrical specifications, and register memory maps are described in this chapter.
11.1 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
11.2 Power Supplies
The following sections describe the proper power-supply sequencing and timing needed to properly power
on the 66AK2E0x. The various power supply rails and their primary functions are listed in Table 11-1.
Table 11-1. Power Supply Rails on the 66AK2E0x
NAME
PRIMARY FUNCTION
VOLTAGE
1.8 V
NOTES
AVDDAx
Core PLL, DDR3 DLL supply voltage
SmartReflex SoC core supply voltage
SoC core fixed supply voltage
DDR3 I/O power supply voltage
1.8-V I/O power supply voltage
USB 3.3-V IO supply
Core PLL, DDR3 DLL supply
SoC variable core supply
SoC Core fixed supply
DDR3 I/O power supply
1.8-V I/O power supply
USB high voltage supply
SerDes I/O power supply
SerDes analog supply
USB LV PHY supply
CVDD
0.8 V to 1.1 V
0.95 V
CVDD1
DVDD15
1.5/1.35 V
1.8 V
DVDD18
USB0DVDD33, USB1DVDD33
VDDAHV
3.3 V
SerDes I/O power supply voltage
SerDes analog power supply voltage
USB LV PHY power supply voltage
Filtered 0.85-V supply voltage
1.8 V
VDDALV
0.85 V
VDDUSB0, VDDUSB1
0.85 V
USB0VP, USB0VPTX, USB0VP,
USB0VPTX
0.85 V
Filtered 0.85-V USB supply
VSS
Ground
GND
Ground
11.2.1 Power-Up Sequencing
This section defines the requirements for a power-up sequencing from a power-on reset condition. There
are two acceptable power sequences for the device.
The first sequence stipulates the core voltages starting before the IO voltages as shown below.
1. CVDD
2. CVDD1, VDDAHV, AVDDAx, DVDD18
3. DVDD15
4. VDDALV, VDDUSBx, USBxVP, USBxVPTX
5. USBxDVDD33
The second sequence provides compatibility with other TI processors with the IO voltage starting before
the core voltages as shown below.
1. VDDAHV, AVDDAx, DVDD18
2. CVDD
3. CVDD1
4. DVDD15
5. VDDALV, VDDUSBx, USBxVP, USBxVPTX
6. USBxDVDD33
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The clock input buffers for CORECLK, DDRCLK, NETCPCLK, and SGMIICLK use CVDD as a supply
voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a
valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the
device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks may be held in a static
state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid
internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDD
is present.
If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled
to ground through a 1-kΩ resistor. The P leg should be tied to CVDD to ensure it will not have any voltage
present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not
failsafe and should not be driven high before these voltages are active. Driving these IO cells high before
DVDD18 or DVDD15 are valid could cause damage to the device.
The device initialization is divided into two phases. The first phase consists of the time period from the
activation of the first power supply until the point at which all supplies are active and at a valid voltage
level. Either of the sequencing scenarios described above can be implemented during this phase. The
figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence.
POR must be held low for the entire power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of
RESETFULL triggers the end of the initialization phase, but both must be inactive for the initialization to
complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1
in the following section refers to the clock that is used by the CorePacs. See Figure 11-7 for more details.
11.2.1.1 Core-Before-IO Power Sequencing
The details of the Core-before-IO power sequencing are defined in Table 11-2. Figure 11-1 shows power
sequencing and reset control of the 66AK2E0x. POR may be removed after the power has been stable for
the required 100 µsec. RESETFULL must be held low for a period (see item 9 in Figure 11-1) after the
rising edge of POR, but may be held low for longer periods if necessary. The configuration bits shared
with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold
times specified. SYSCLK1 must always be active before POR can be removed.
NOTE
TI recommends a maximum of 80 ms between one power rail being valid and the next power
rail in the sequence starting to ramp.
Table 11-2. Core-Before-IO Power Sequencing
ITEM
SYSTEM STATE
1
Begin Power Stabilization Phase
•
•
CVDD (core AVS) ramps up.
POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous
reset (created from POR) is put into the reset state.
•
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a
CVDD1 (core constant) ramps at the same time or within 80 ms of CVDD. Although ramping CVDD1 simultaneously with
CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
•
The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as
this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit
cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the
order of twice the specified draw of CVDD1.
•
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
The timing for CVDD1 is based on CVDD valid. CVDD1 and DVDD18/ADDAVH/AVDDAx may be enabled at the same time
but do not need to ramp simultaneously. CVDD1 may be valid before or after DVDD18/ADDAVH/AVDDAx are valid, as long
as the timing above is met.
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Table 11-2. Core-Before-IO Power Sequencing (continued)
ITEM
SYSTEM STATE
2b
•
VDDAHV, AVDDAx and DVDD18 ramp at the same time or shortly following CVDD. DVDD18 must be enabled within 80 ms
of CVDD valid and must ramp monotonically and reach a stable level in 20ms or less. This results in no more than 100
ms from the time when CVDD is valid to the time when DVDD18 is valid.
•
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
The timing for DVDD18/ADDAVH/AVDDAx is based on CVDD valid. DVDD18/ADDAVH/AVDDAx and CVDD1 may be
enabled at the same time but do not need to ramp simultaneously. DVDD18/ADDAVH/AVDDAx may be valid before or after
CVDD1 is valid, as long as the timing above is met.
2c
2d
3
•
•
Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should
either be driven with a valid clock or be held in a static state with one leg high and one leg low.
The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 7.
•
•
•
DVDD15 can ramp up within 80ms of when DVDD18 is valid.
RESETSTAT is driven low once the DVDD18 supply is available.
All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or
bidirectional pin before DVDD18 is valid could cause damage to the device.
•
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
4
RESET may be driven high any time after DVDD18 is at a valid level. RESET must be high before POR is driven high.
•
•
VDDALV, VDDUSBx, USBxVP and USBxVPTX ramp up within 80ms of when DVDD15 is valid.
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
•
•
USBxDVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSBx, USBxVP and USBxVPTX are valid.
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
6
7
•
POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
•
Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33
nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire
16 μs.
8
9
•
RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
•
•
The rising edge of the RESETFULL will remove the reset to the eFuse farm allowing the scan to begin.
Once device initialization and the eFuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be
10000 to 50000 clock cycles.
End device initialization phase
10
11
•
•
GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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Power Stabilization Phase
Device Initialization Phase
POR
8
RESETFULL
9
Configuration
Inputs
10
11
RESET
2d
1
1
CVDD
2a
2b
CVDD1
2
VDDAHV
AVDDAx
DVDD18
3a
3
DVDD15
3
4
5
4
VDDALV
USBxVP
USBxVPTX
6
5
USBxDVDD33
SYSCLK1
7
2c
DDRCLKOUT
RESETSTAT
Figure 11-1. Core-Before-IO Power Sequencing
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11.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 11-2 and defined in Table 11-
3.
NOTE
TI recommends a maximum of 100 ms between one power rail being valid, and the next
power rail in the sequence starting to ramp.
Table 11-3. IO-Before-Core Power Sequencing
ITEM
SYSTEM STATE
1
Begin Power Stabilization Phase
•
•
VDDAHV, AVDDAx and DVDD18 ramp up.
POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has asynchronous
reset (created from POR ) is put into the reset state.
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2
•
•
CVDD (core AVS) ramps within 80 ms from the time ADDAHV, AVDDAx and DVDD18 are valid.
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
2a
3
•
•
RESET may be driven high any time after DVDD18 is at a valid level. must be high before POR is driven high.
CVDD1 (core constant) ramp at the same time or within 80 ms following CVDD. Although ramping CVDD1 simultaneously
with CVDD is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
•
The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as
this will ensure that the Word Lines (WLs) in the memories are turned off and there is no current through the memory bit
cells. If, however, CVDD1 (core constant) ramp up before CVDD (core AVS), then the worst-case current could be on the
order of twice the specified draw of CVDD1.
•
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
3a
3b
4
Once CVDD is valid, the clock drivers can be enabled. Although the clock inputs are not necessary at this time, they should
either be driven with a valid clock or held in a static state.
•
The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before
POR goes high specified by item 8.
•
•
•
DVDD15 can ramp up within 80 ms of when CVDD1 is valid.
RESETSTAT is driven low once the DVDD18 supply is available.
All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or
bidirectional pin before DVDD18 is valid could cause damage to the device.
•
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
5
6
•
•
VDDALV, VDDUSBx, USBxVP and USBxVPTX should ramp up within 80 ms of when DVDD15 is valid.
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
•
•
USBxDVDD33 supply is ramped up within 80 ms of when VDDALV, VDDUSBx, USBxVP and USBxVPTX are valid.
Each supply must ramp monotonically and must reach a stable valid level in 20 ms or less.
7
8
•
POR must continue to remain low for at least 100 μs after all power rails have stabilized.
End power stabilization phase
•
Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33
nsec, so a delay of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire
16 μs.
9
•
RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.
The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
10
•
•
Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be
10000 to 50000 clock cycles.
End device initialization phase
11
12
•
•
GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL.
GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL.
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Power Stabilization Phase Device Initialization Phase
POR
9
RESETFULL
10
Configuration
Inputs
2a
11
12
RESET
1
VDDAHV
AVDDAx
DVDD18
1
3b
2
CVDD
2
3
4
3
CVDD1
4
DVDD15
5
VDDALV
USBxVP
USBxVPTX
5
6
7
6
USBxDVDD33
SYSCLK1
8
3a
DDRCLKOUT
RESETSTAT
Figure 11-2. IO-Before-Core Power Sequencing
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11.2.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time may affect the long-term
reliability of the part (due to an elevated voltage condition that can stress the part). The device should not
be held in a reset for times exceeding one hour at a time and no more than 5% of the total lifetime for
which the device is powered-up. Exceeding these limits will cause a gradual reduction in the reliability of
the part. This can be avoided by allowing the device to boot and then configuring it to enter a hibernation
state soon after power is applied. This will satisfy the reset requirement while limiting the power
consumption of the device.
11.2.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of
many of the clocks is contingent on the state of the boot configuration pins. Table 11-4 describes the clock
sequencing and the conditions that affect clock operation. Note that all clock drivers should be in a high-
impedance state until CVDD is at a valid level and that all clock inputs be either active or in a static state
with one leg pulled to ground and the other connected to CVDD.
Table 11-4. Clock Sequencing
CLOCK
CONDITION
None
SEQUENCING
DDRCLK
Must be present 16 µsec before POR transitions high.
None
CORECLK is used to clock the core PLL. It must be present 16 µsec before POR transitions
high.
CORECLK
NETCPCLKSEL = 0
NETCPCLKSEL = 1
NETCPCLK is not used and should be tied to a static state.
NETCPCLK
NETCPCLK is used as a source for the NETCP PLL. It must be present before the NETCP
PLL is removed from reset and programmed.
PCIE will be used as a
boot device.
PCIECLK must be present 16 µsec before POR transitions high.
PCIECLK
PCIE will be used after
boot.
PCIECLK is used as a source to the PCIE SerDes PLL. It must be present before the PCIe is
removed from reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
HyperLink will be used as HYPLNK0CLK must be present 16 µsec before POR transitions high.
a boot device.
HyperLink will be used
after boot.
HYPLNK0CLK is used as a source to the HyperLink SerDes PLL. It must be present before
the HyperLink is removed from reset and programmed.
HYPLNK0CLK
HyperLink will not be
used.
HYPLNK0CLK is not used and should be tied to a static state.
11.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to
prevent an excessive amount of static current and to prevent overstress of the device. A power-good
circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power
supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions
that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails.
Long-term exposure to an environment in which one of the power supply voltages is no longer present will
affect the reliability of the device. Holding the device in reset is not an acceptable solution because
prolonged periods of time with an active reset can affect long term reliability.
11.2.3 Power Supply Decoupling and Bulk Capacitor
To properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors
are required. Bulk capacitors are used to minimize the effects of low-frequency current transients and
decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on
selection of power supply decoupling and bulk capacitors see the Hardware Design Guide for KeyStone II
Devices application report (SPRABV0).
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11.2.4 SmartReflex
Increasing the device complexity increases its power consumption. With higher clock rates and increased
performance comes an inevitable penalty: increasing leakage currents. Leakage currents are present in
any powered circuit, independent of clock rates and usage scenarios. This static power consumption is
mainly determined by transistor type and process technology. Higher clock rates also increase dynamic
power, which is the power used when transistors switch. The dynamic power depends mainly on a specific
usage scenario, clock rates, and I/O activity.
Texas Instruments SmartReflex technology is used to decrease both static and dynamic power
consumption while maintaining the device performance. SmartReflex in the
66AK2E0x device is a feature that allows the core voltage to be optimized based on the process corner of
the device. This requires a voltage regulator for each 66AK2E0x device.
To help maximize performance and minimize power consumption of the device, SmartReflex is required to
be implemented. The voltage selection can be accomplished using 4 VCNTL pins or 6 VCNTL pins
(depending on power supply device being used), which are used to select the output voltage of the core
voltage regulator.
For information on implementation of SmartReflex see the Power Consumption Summary for KeyStone
TCI66x Devices application report (SPRABL4) and the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0).
Table 11-5. SmartReflex 4-Pin 6-bit VID Interface Switching Characteristics
(see Figure 11-3)
NO.
1
PARAMETER
MIN
MAX UNIT
td(VCNTL[4:2]-VCNTL[5])
Delay time - VCNTL[4:2] valid after VCNTL[5] low
300.00
ns
ms
ns
2
toh(VCNTL[5]-VCNTL[4:2]) Output hold time - VCNTL[4:2] valid after VCNTL[5]
0.07 172020C(1)
3
td(VCNTL[4:2]-VCNTL[5])
toh(VCNTL[5]-VCNTL[2:0)
Delay time - VCNTL[4:2] valid after VCNTL[5] high
300.00
4
Output hold time - VCNTL[4:2] valid after VCNTL[5] high
0.07
172020C
ms
(1) C = 1/SYSCLK1 frequency, in ms (see Figure 11-9)
4
VCNTL[5]
1
3
VCNTL[4:2]
LSB VID[2:0]
MSB VID[5:3]
2
Figure 11-3. SmartReflex 4-Pin 6-Bit VID Interface Timing
11.2.5 Monitor Points
Two pairs of monitor points for the CVDD voltage level are provided. Both CVDDCMON and CVDDTMON
are connected directly to the CVDD supply plane on the die itself. VSSCMON and VSSTMON are
connected to the ground plane on the die. These pairs provide the best measurement points for the
voltage at the silicon. They also provide the best point to connect the remote sense lines for the CVDD
power supply. The use of a power supply with a differential remote sense input is highly desirable. The
positive remote sense line should be connected to CVDDCMON and the negative remote sense line
should be connected to VSSCMON. CVDDTMON and VSSTMON can be used as an alternative but
always use either the CMON pair or the TMON pair. If the power supply remote sense is not differential
CVDDCMON or CVDDTMON can be connected to the sense line.
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11.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) includes a Global Power Sleep Controller (GPSC) and a number of
Local Power Sleep Controllers (LPSC) that control overall device power by turning off unused power
domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an
interface to control several important power and clock operations.
For information on the Power Sleep Controller, see the KeyStone Architecture Power Sleep Controller
(PSC) User's Guide (SPRUGV4).
11.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power
dissipation. The Global Power Sleep Controller (GPSC) is used to control the power gating of various
power domains.
The following table shows the 66AK2E0x power domains.
Table 11-6. 66AK2Ex Power Domains
DOMAIN
BLOCK(S)
NOTE
POWER CONNECTION
0
Most peripheral logic (BOOTCFG, EMIF16, Cannot be disabled
I2C, INTC, GPIO, USB, USIM)
Always on
1
2
3
4
5
6
7
Per-core TETB and system TETB
Network Coprocessor
PCIe0
RAMs can be powered down
Software control
Software control
Software control
Logic can be powered down
Logic can be powered down
Reserved
HyperLink
Logic can be powered down
Software control
Software control
Reserved
MSMC RAM
MSMC RAM can be powered
down
8
C66x Core 0, L1/L2 RAMs
L2 RAMs can sleep
Software control via C66x CorePac. For
details, see the C66x CorePac Reference
Guide.
9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EMIF(DDR3)
Reserved
PCIe1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Logic can be powered down
Software control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10GbE
Logic can be powered down
Software control
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Table 11-6. 66AK2Ex Power Domains (continued)
DOMAIN
BLOCK(S)
NOTE
POWER CONNECTION
Software control
30
31
ARM Smart Reflex
ARM CorePac
Logic can be powered down
Logic can be powered down
Software control
11.3.2 Clock Domains
Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each
module. For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL
controller to enable and disable that module's clock(s) at the source. For modules that share a clock with
other modules, the LPSC controls the clock gating logic for each module.
Table 11-7 shows the 66AK2E0x clock domains.
Table 11-7. Clock Domains
LPSC NUMBER
MODULE(S)
NOTES
0
Shared LPSC for all peripherals other than those listed in this table Always on
USB_1
1
2
USB_0
Software control
3
EMIF16 and SPI
TSIP
Software control
Software control
Software control
Always on
4
5
Debug subsystem and tracers
Reserved
6
7
Packet Accelerator
Ethernet SGMIIs
Security Accelerator
PCIe_0
Software control
Software control
Software control
Software control
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Reserved
HyperLink
Software control
Always on
SmartReflex
MSMC RAM
C66x CorePac0
Reserved
Software control
Always on
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DDR3 EMIF
Reserved
Software control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCIe_1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 11-7. Clock Domains (continued)
LPSC NUMBER
MODULE(S)
Reserved
NOTES
35
Reserved
36
Reserved
Reserved
37
Reserved
Reserved
38
Reserved
Reserved
39
Reserved
Reserved
40
Reserved
Reserved
41
Reserved
Reserved
42
Reserved
Reserved
43
Reserved
Reserved
44
Reserved
Reserved
45
Reserved
Reserved
46
Reserved
Reserved
47
Reserved
Reserved
48
Reserved
Reserved
49
Reserved
Reserved
50
10GbE
Software control
Software control
Software control
These modules do not use LPSC
51
ARM Smart Reflex
ARM CorePac
Bootcfg, PSC, and PLL Controller
52
No LPSC
11.3.3 PSC Register Memory Map
Table 11-8 shows the PSC Register memory map.
Table 11-8. PSC Register Memory Map
OFFSET
0x000
REGISTER
PID
DESCRIPTION
Peripheral Identification Register
Reserved
0x004 - 0x010
0x014
Reserved
VCNTLID
Reserved
PTCMD
Reserved
PTSTAT
Voltage Control Identification Register
Reserved
0x018 - 0x11C
0x120
Power Domain Transition Command Register
Reserved
0x124
0x128
Power Domain Transition Status Register
Reserved
0x12C - 0x1FC Reserved
0x200
0x204
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
PDSTAT0
PDSTAT1
PDSTAT2
PDSTAT3
PDSTAT4
PDSTAT5
PDSTAT6
PDSTAT7
PDSTAT8
PDSTAT9
PDSTAT10
PDSTAT11
PDSTAT12
PDSTAT13
Power Domain Status Register 0
Power Domain Status Register 1
Power Domain Status Register 2
Power Domain Status Register 3
Power Domain Status Register 4
Power Domain Status Register 5
Power Domain Status Register 6
Power Domain Status Register 7
Power Domain Status Register 8
Power Domain Status Register 9
Power Domain Status Register 10
Power Domain Status Register 11
Power Domain Status Register 12
Power Domain Status Register 13
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Table 11-8. PSC Register Memory Map (continued)
OFFSET
0x238
0x23C
0x240
0x244
0x248
0x24C
0x250
0x254
0x258
0x25C
0x260
0x264
0x268
0x26C
0x270
0x274
0x278
0x27C
REGISTER
PDSTAT14
PDSTAT15
PDSTAT16
PDSTAT17
PDSTAT18
PDSTAT19
PDSTAT20
PDSTAT21
PDSTAT22
PDSTAT23
PDSTAT24
PDSTAT25
PDSTAT26
PDSTAT27
PDSTAT28
PDSTAT29
PDSTAT30
PDSTAT31
DESCRIPTION
Power Domain Status Register 14
Power Domain Status Register 15
Power Domain Status Register 16
Power Domain Status Register 17
Power Domain Status Register 18
Power Domain Status Register 19
Power Domain Status Register 20
Power Domain Status Register 21
Power Domain Status Register 22
Power Domain Status Register 23
Power Domain Status Register 24
Power Domain Status Register 25
Power Domain Status Register 26
Power Domain Status Register 27
Power Domain Status Register 28
Power Domain Status Register 29
Power Domain Status Register 30
Power Domain Status Register 31
Reserved
0x27C - 0x2FC Reserved
0x300
0x304
0x308
0x30C
0x310
0x314
0x318
0x31C
0x320
0x324
0x328
0x32C
0x330
0x334
0x338
0x33C
0x340
0x344
0x348
0x34C
0x350
0x354
0x358
0x35c
0x360
0x364
0x368
0x36C
PDCTL0
PDCTL1
PDCTL2
PDCTL3
PDCTL4
PDCTL5
PDCTL6
PDCTL7
PDCTL8
PDCTL9
PDCTL10
PDCTL11
PDCTL12
PDCTL13
PDCTL14
PDCTL15
PDCTL16
PDCTL17
PDCTL18
PDCTL19
PDCTL20
PDCTL21
PDCTL22
PDCTL23
PDCTL24
PDCTL25
PDCTL26
PDCTL27
Power Domain Control Register 0
Power Domain Control Register 1
Power Domain Control Register 2
Power Domain Control Register 3
Power Domain Control Register 4
Power Domain Control Register 5
Power Domain Control Register 6
Power Domain Control Register 7
Power Domain Control Register 8
Power Domain Control Register 9
Power Domain Control Register 10
Power Domain Control Register 11
Power Domain Control Register 12
Power Domain Control Register 13
Power Domain Control Register 14
Power Domain Control Register 15
Power Domain Control Register 16
Power Domain Control Register 17
Power Domain Control Register 18
Power Domain Control Register 19
Power Domain Control Register 20
Power Domain Control Register 21
Power Domain Control Register 22
Power Domain Control Register 23
Power Domain Control Register 24
Power Domain Control Register 25
Power Domain Control Register 26
Power Domain Control Register 27
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Table 11-8. PSC Register Memory Map (continued)
OFFSET
0x370
0x374
0x378
0x37C
0x380 - 0x7FC
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x820
0x824
0x828
0x82C
0x830
0x834
0x838
0x83C
0x840
0x844
0x848
0x84C
0x850
0x854
0x858
0x85C
0x860
0x864
0x868
0x86C
0x870
0x874
0x878
0x87C
0x880
0x884
0x888
0x88C
0x890
0x894
0x898
0x89C
0x8A0
0x8A4
REGISTER
PDCTL28
DESCRIPTION
Power Domain Control Register 28
Power Domain Control Register 29
Power Domain Control Register 30
Power Domain Control Register 31
Reserved
PDCTL29
PDCTL30
PDCTL31
Reserved
MDSTAT0
MDSTAT1
MDSTAT2
MDSTAT3
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
MDSTAT8
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
MDSTAT13
MDSTAT14
MDSTAT15
MDSTAT16
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
MDSTAT23
MDSTAT24
MDSTAT25
MDSTAT26
MDSTAT27
MDSTAT28
MDSTAT29
MDSTAT30
MDSTAT31
MDSTAT32
MDSTAT33
MDSTAT34
MDSTAT35
MDSTAT36
MDSTAT37
MDSTAT38
MDSTAT39
MDSTAT40
MDSTAT41
Module Status Register 0 (never gated)
Module Status Register 1
Module Status Register 2
Module Status Register 3
Module Status Register 4
Module Status Register 5
Module Status Register 6
Module Status Register 7
Module Status Register 8
Module Status Register 9
Module Status Register 10
Module Status Register 11
Module Status Register 12
Module Status Register 13
Module Status Register 14
Module Status Register 15
Module Status Register 16
Module Status Register 17
Module Status Register 18
Module Status Register 19
Module Status Register 20
Module Status Register 21
Module Status Register 22
Module Status Register 23
Module Status Register 24
Module Status Register 25
Module Status Register 26
Module Status Register 27
Module Status Register 28
Module Status Register 29
Module Status Register 30
Module Status Register31
Module Status Register 32
Module Status Register 33
Module Status Register 34
Module Status Register 35
Module Status Register 36
Module Status Register 37
Module Status Register 38
Module Status Register 39
Module Status Register 40
Module Status Register 41
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Table 11-8. PSC Register Memory Map (continued)
OFFSET
0x8A8
0x8AC
0x8B0
0x8B4
0x8B8
0x8BC
0x8C0
0x8C4
0x8C8
0x8CC
0x8D0
REGISTER
MDSTAT42
MDSTAT43
MDSTAT44
MDSTAT45
MDSTAT46
MDSTAT47
MDSTAT48
MDSTAT49
MDSTAT50
MDSTAT51
MDSTAT52
DESCRIPTION
Module Status Register 42
Module Status Register 43
Module Status Register 44
Module Status Register 45
Module Status Register 46
Module Status Register 47
Module Status Register 48
Module Status Register 49
Module Status Register 50
Module Status Register 51
Module Status Register 52
Reserved
0x8D4 - 0x9FC Reserved
0xA00
0xA04
0xA08
0xA0C
0xA10
0xA14
0xA18
0xA1C
0xA20
0xA24
0xA28
0xA2C
0xA30
0xA34
0xA38
0xA3C
0xA40
0xA44
0xA48
0xA4C
0xA50
0xA54
0xA58
0xA5C
0xA60
0xA64
0xA68
0xA6C
0xA70
0xA74
0xA78
0xA7C
0xA80
0xA84
0xA88
MDCTL0
MDCTL1
MDCTL2
MDCTL3
MDCTL4
MDCTL5
MDCTL6
MDCTL7
MDCTL8
MDCTL9
MDCTL10
MDCTL11
MDCTL12
MDCTL13
MDCTL14
MDCTL15
MDCTL16
MDCTL17
MDCTL18
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
MDCTL29
MDCTL30
MDCTL31
MDCTL32
MDCTL33
MDCTL34
Module Control Register 0 (never gated)
Module Control Register 1
Module Control Register 2
Module Control Register 3
Module Control Register 4
Module Control Register 5
Module Control Register 6
Module Control Register 7
Module Control Register 8
Module Control Register 9
Module Control Register 10
Module Control Register 11
Module Control Register 12
Module Control Register 13
Module Control Register 14
Module Control Register 15
Module Control Register 16
Module Control Register 17
Module Control Register 18
Module Control Register 19
Module Control Register 20
Module Control Register 21
Module Control Register 22
Module Control Register 23
Module Control Register 24
Module Control Register 25
Module Control Register 26
Module Control Register 27
Module Control Register 28
Module Control Register 29
Module Control Register 30
Module Control Register31
Module Control Register 32
Module Control Register 33
Module Control Register 34
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Table 11-8. PSC Register Memory Map (continued)
OFFSET
0xA8C
0xA90
0xA94
0xA98
0xA9C
0xAA0
0xAA4
0xAA8
0xAAC
0xAB0
0xAB4
0xAB8
0xABC
0xAC0
0xAC4
0xAC8
0xACC
0xAD0
REGISTER
MDCTL35
MDCTL36
MDCTL37
MDCTL38
MDCTL39
MDCTL40
MDCTL41
MDCTL42
MDCTL43
MDCTL44
MDCTL45
MDCTL46
MDCTL47
MDCTL48
MDCTL49
MDCTL50
MDCTL51
MDCTL52
DESCRIPTION
Module Control Register 35
Module Control Register 36
Module Control Register 37
Module Control Register 38
Module Control Register 39
Module Control Register 40
Module Control Register 41
Module Control Register 42
Module Control Register 43
Module Control Register 44
Module Control Register 45
Module Control Register 46
Module Control Register 47
Module Control Register 48
Module Control Register 49
Module Control Register 50
Module Control Register 51
Module Control Register 52
Reserved
0xAD4 - 0xFFC Reserved
11.4 Reset Controller
The reset controller detects the different type of resets supported on the 66AK2E0x device and manages
the distribution of those resets throughout the device. The device has the following types of resets:
•
•
•
•
Power-on reset
Hard reset
Soft reset
Local reset
Table 11-9 explains further the types of reset, the reset initiator, and the effects of each reset on the
device. For more information on the effects of each reset on the PLL controllers and their clocks, see
Section 11.4.8.
Table 11-9. Reset Types
TYPE
INITIATOR
EFFECT(S)
POR pin
RESETFULL pin
Resets the entire chip including the test and emulation logic. The device configuration pins
are latched only during power-on reset.
Power-on reset
Hard reset resets everything except for test, emulation logic, and reset isolation modules.
This reset is different from power-on reset in that the PLL Controller assumes power and
clocks are stable when a hard reset is asserted. The device configurations pins are not
relatched.
RESET pin
PLLCTL Register
(RSCTRL)(1)
Watchdog timers
Emulation
Hard reset
Emulation-initiated reset is always a hard reset.
By default, these initiators are configured as hard reset, but can be configured (except
emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the
DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in self-
refresh mode.
(1) All masters in the device have access to the PLL Control Registers.
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Table 11-9. Reset Types (continued)
TYPE
INITIATOR
EFFECT(S)
Soft reset behaves like hard reset except that PCIe MMRs (memory-mapped registers) and
DDR3 EMIF MMRs contents are retained.
RESET pin
PLLCTL Register
(RSCTRL)
Soft reset
Local reset
By default, these initiators are configured as hard reset, but can be configured as soft reset
in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can
be retained during a soft reset if the SDRAM is placed in self-refresh mode.
Watchdog timers
LRESET pin
Watchdog timer timeout
LPSC MMRs
Resets the C66x CorePac, without disturbing clock alignment or memory contents. The
device configuration pins are not relatched.
11.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following:
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their
normal operating conditions. Also a RESETFULL pin is provided to allow reset of the entire device,
including the reset-isolated logic, when the device is already powered up. For this reason, the
RESETFULL pin, unlike POR, should be driven by the on-board host control other than the power good
circuitry. For power-on reset, the Core PLL Controller comes up in bypass mode and the PLL is not
enabled. Other resets do not affect the state of the PLL or the dividers in the PLL Controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR and
RESETFULL pins asserted (driven low). While POR is asserted, all pins except RESETSTAT will be
set to high-impedance. After the POR pin is deasserted (driven high), all Z group pins, low group pins,
and high group pins are set to their reset state and remain in their reset state until otherwise
configured by their respective peripheral. All peripherals that are power-managed are disabled after a
power-on reset and must be enabled through the Device State Control Registers (for more details, see
Section 9.2.3).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT is driven low, indicating that the device is in
reset.
3. POR and RESETFULL must be held active until all supplies on the board are stable, and then for at
least an additional period of time (as specified in Section 11.2.1) for the chip-level PLLs to lock.
4. The POR pin can now be de-asserted.
5. After the appropriate delay, the RESETFULL pin can now be de-asserted. Reset-sampled pin values
are latched at this point. Then, all chip-level PLLs are taken out of reset, locking sequences begin, and
all power-on device initialization processes begin.
6. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time,
the DDR3 PLL has completed its locking sequences and are supplying a valid clock. The system
clocks of the PLL controllers are allowed to finish their current cycles and then are paused for 10
cycles of their respective system reference clocks. After the pause, the system clocks are restarted at
their default divide-by settings.
7. The device is now out of reset and code execution begins as dictated by the selected boot mode.
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NOTE
To most of the device, reset is de-asserted only when the POR and RESET pins are both
de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is
held low past the low period of the POR pin, most of the device will remain in reset. The
RESET pin should not be tied to the POR pin.
11.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test logic, emulation logic, and reset-
isolated modules. POR should also remain de-asserted during this time.
Hard reset is initiated by the following:
•
•
•
•
RESET pin
RSCTRL Register in the PLL Controller
Watchdog timer
Emulation
By default, all the initiators listed above are configured to generate a hard reset. Except for emulation, all
of the other three initiators can be configured in the RSCFG Register in the PLL Controller to generate soft
resets.
The following sequence must be followed during a hard reset:
1. The RESET pin is asserted (driven low) for a minimum of 24 CLKIN1 cycles. During this time, the
RESET signal propagates to all modules (except those specifically mentioned above). To prevent off-
chip contention during the warm reset, all I/O must be Hi-Z for modules affected by RESET.
2. Once all logic is reset, RESETSTAT is asserted (driven low) to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that
configuration pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
NOTE
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise,
if POR is activated (brought low), the minimum POR pulse width must be met. The RESET
pin should not be tied to the POR pin.
11.4.3 Soft Reset
A soft reset behaves like a hard reset except that the EMIF16 MMRs, DDR3 EMIF MMRs, PCIe MMRs
sticky bits, and external memory content are retained. POR should also remain de-asserted during this
time.
Soft reset is initiated by the following:
•
•
•
RESET pin
RSCTRL Register in the PLL Controller
Watchdog timer
In the case of a soft reset, the clock logic and the power control logic of the peripherals are not affected
and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3
memory controller registers are not reset. If the user places the DDR3 SDRAM in self-refresh mode
before invoking the soft reset, the DDR3 SDRAM memory content is retained.
During a soft reset, the following occurs:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset propagates
through the system. Internal system clocks are not affected. PLLs remain locked.
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2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the
PLL Controller pauses system clocks for approximately 8 cycles. At this point:
–
–
The peripherals remain in the state they were in before the soft reset.
The states of the Boot Mode configuration pins are preserved as controlled by the DEVSTAT
Register.
–
The DDR3 MMRs and PCIe MMRs retain their previous values. Only the DDR3 memory controller
and PCIe state machines are reset by the soft reset.
–
–
The PLL Controller remains in the mode it was in prior to the soft reset.
System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Because the Boot Mode configuration
pins are not latched with a soft reset, the previous values (as shown in the DEVSTAT Register), are used
to select the boot mode.
11.4.4 Local Reset
The local reset can be used to reset a particular C66x CorePac without resetting any other device
components.
Local reset is initiated by the following:
•
•
LRESET pin
Watchdog timer should cause one of the below and RSTCFG registers in the PLL Controller. (See
Section 11.5.2.8 and Section 7.3.2.)
–
–
–
–
Local reset
NMI
NMI followed by a time delay and then a local reset for the C66x CorePac selected
Hard reset by requesting reset via the PLL Controller
•
LPSC MMRs (memory-mapped registers)
For more details see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide
(SPRUGV2).
11.4.5 ARM CorePac Reset
The ARM CorePac uses a combination of power-on-reset and module-reset to reset its components, such
as the Cortex-A15 processor, memory subsystem, debug logic, etc. The ARM CorePac incorporates the
PSC to generate resets for its internal modules. Details of reset generation and distribution inside the
ARM CorePac can be found in the KeyStone II Architecture ARM CorePac User's Guide (SPRUHJ4).
11.4.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLL Controller processes only the highest
priority reset request. The reset request priorities are as follows (high to low):
•
•
Power-on reset
Hard/soft reset
11.4.7 Reset Controller Register
The reset controller registers are part of the PLL Controller MMRs. All 66AK2E0x device-specific MMRs
are covered in Section 11.5.2. For more details on these registers and how to program them, see the
KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2).
11.4.8 Reset Electrical Data/Timing
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Table 11-10. Reset Timing Requirements(1)
(see Figure 11-4 and Figure 11-5)
NO.
MIN
500C
500C
MAX UNIT
RESETFULL Pin Reset
1
2
tw(RESETFULL)
tw(RESET)
Pulse width - pulse width RESETFULL low
Soft/Hard-Reset
ns
ns
Pulse width - pulse width RESET low
(1) C = 1/SYSCLK1 clock frequency in ns
Table 11-11. Reset Switching Characteristics(1)
(see Figure 11-4 and Figure 11-5)
NO.
PARAMETER
RESETFULL Pin Reset
MIN
MAX UNIT
3
td(RESETFULLH-
RESETSTATH)
Delay time - RESETSTAT high after RESETFULL high
50000C
ns
ns
Soft/Hard Reset
4
td(RESETH-RESETSTATH)
Delay time - RESETSTAT high after RESET high
50000C
(1) C = 1/SYSCLK1 clock frequency in ns
POR
1
RESETFULL
RESET
3
RESETSTAT
Figure 11-4. RESETFULL Reset Timing
POR
RESETFULL
2
RESET
4
RESETSTAT
Figure 11-5. Soft/Hard Reset Timing
Table 11-12. Boot Configuration Timing Requirements(1)
(see Figure 11-6)
NO.
MIN
12C
12C
MAX UNIT
1
2
tsu(GPIOn-RESETFULL) Setup time - GPIO valid before RESETFULL asserted
th(RESETFULL-GPIOn) Hold time - GPIO valid after RESETFULL asserted
ns
ns
(1) C = 1/SYSCLK1 clock frequency in ns.
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POR
1
RESETFULL
GPIO[15:0]
2
Figure 11-6. Boot Configuration Timing
11.5 Core PLL (Main PLL), DDR3 PLL, NETCP PLL and the PLL Controllers
This section provides a description of the Core PLL, DDR3 PLL, NETCP PLL, and the PLL Controller. For
details on the operation of the PLL Controller module, see the KeyStone Architecture Phase Locked Loop
(PLL) Controller User's Guide (SPRUGV2).
The Core PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios,
alignment, and gating for the system clocks to the device. By default, the device powers up with the Core
PLL bypassed. Figure 11-7 shows a block diagram of the Core PLL and the PLL Controller.
The DDR3 PLL and NETCP PLL are used to provide dedicated clock to the DDR3 and NETCP
respectively. These chip level PLLs support a wide range of multiplier and divider values, which can be
programmed through the chip level registers located in the Device Control Register block. The Boot ROM
will program the multiplier values for Core PLL and NETCP PLL based on boot mode. (See Section 9 for
more details.)
The DDR3 PLL is used to supply clocks to DDR3 EMIF logic. This PLL can also be used without
programming the PLL Controller. Instead, they can be controlled using the chip-level registers
(DDR3PLLCTL0, DDR3PLLCTL1) located in the Device Control Register block. To write to these
registers, software must go through an unlocking sequence using the KICK0/KICK1 registers.
The multiplier values for all chip-level PLLs can be reprogrammed later based on the input parameter
table. This feature provides flexibility in that these PLLs may be able to reuse other clock sources instead
of having its own clock source.
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PLLM
PLL
CLKOD
PLLD
VCO
0
1
CORECLK(P|N)
PLLOUT
BYPASS
C66x
PLL Controller
CorePacs
/1
To Peripherals,
HyperLink, etc.
PLLDIV1
PLLDIV2
PLLDIV3
PLLDIV4
SYSCLK1
/1
/x
/x
SYSCLK2
SYSCLK3
SYSCLK4
To Switch Fabric,
Accelerators,
SmartReflex, etc.
Figure 11-7. Core PLL and PLL Controller
Note that the Core PLL Controller registers can be accessed by any master in the device. The PLLM[5:0]
bits of the multiplier are controlled by the PLLM Register inside the PLL Controller and the PLLM[12:6] bits
are controlled by the chip-level COREPLLCTL0 Register. The output divide and bypass logic of the PLL
are controlled by fields in the SECCTL Register in the PLL Controller. Only PLLDIV3, and PLLDIV4 are
programmable on the device. See the KeyStone Architecture Phase Locked Loop (PLL) Controller User's
Guide (SPRUGV2) for more details on how to program the PLL controller.
The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks
are determined by a combination of this PLL and the Core PLL Controller. The Core PLL Controller also
controls reset propagation through the chip, clock alignment, and test points. The Core PLL Controller
monitors the PLL status and provides an output signal indicating when the PLL is locked.
Core PLL power is supplied externally via the Core PLL power-supply pin (AVDDA1). An external EMI
filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations. For the best performance, TI recommends
that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching
signal traces and the PLL external components (C1, C2, and the EMI Filter).
The minimum CORECLK rise and fall times should also be observed. For the input clock timing
requirements, see Section 11.5.4.
It should be assumed that any registers not included in these sections are not supported by the device.
Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved
memory location or changing the value of reserved bits.
The PLL Controller module as described in the KeyStone Architecture Phase Locked Loop (PLL)
Controller User's Guide (SPRUGV2) includes a superset of features, some of which are not supported on
the device. The following sections describe the registers that are supported.
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11.5.1 Core PLL Controller Device-Specific Information
11.5.1.1 Internal Clocks and Maximum Operating Frequencies
The Core PLL, used to drive the SoC, the switch fabric, and a majority of the peripheral clocks (all but the
ARM CorePacs, DDR3, and the NETCP modules) requires a PLL Controller to manage the various clock
divisions, gating, and synchronization. PLLM[5:0] input of the Core PLL is controlled by the PLL controller
PLLM register.
The Core PLL Controller has four SYSCLK outputs that are listed below along with the clock descriptions.
Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that
dividers are not programmable unless explicitly mentioned in the description below.
•
SYSCLK1: Full-rate clock for all C66x CorePacs. Using local dividers, SYSCLK1 is used to derive
clocks required for the majority of peripherals that do not need reset isolation.
The system peripherals and modules driven by SYSCLK1 are as follows; however, not all peripherals
are supported in every part. See the Features chapter for the complete list of peripherals supported in
your part.
EMIF16, USB 3.0, XFI, HyperLink, PCIe, SGMII, GPIO, Timer64, I2C, SPI, TSIP, TeraNet, UART,
ROM, CIC, Security Manager, BootCFG, PSC, Queue Manager, Semaphore, MPUs, EDMA, MSMC,
DDR3, EMIF.
•
•
SYSCLK2:Full-rate, reset-isolated clock used to generate various other clocks required by peripherals
that need reset isolation: e.g., SmartReflex.
SYSCLK3: 1/x-rate clock used to clock the C66x CorePac emulation. The default rate for this clock is
1/3. This clock is programmable from /1 to /32, where this clock does not violate the maximum of 350
MHz. SYSCLK3 can be turned off by software.
•
SYSCLK4: 1/z-rate clock for the system trace module only. The default rate for this clock is 1/5. This
clock is configurable: the maximum configurable clock is 210 MHz and the minimum configuration
clock is 32 MHz. SYSCLK4 can be turned off by software.
Only SYSCLK3 and SYSCLK4 are programmable.
11.5.1.2 Local Clock Dividers
The clock signals from the Core PLL Controller are routed to various modules and peripherals on the
device. Some modules and peripherals have one or more internal clock dividers. Other modules and
peripherals have no internal clock dividers, but are grouped together and receive clock signals from a
shared local clock divider. Internal and shared local clock dividers have fixed division ratios. See table
Table 11-13.
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Table 11-13. Core PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers
INTERNAL CLOCK
DIVIDER(S)
SHARED LOCAL CLOCK
DIVIDER
CLOCK
MODULE
SYSCLK1 Internal Clock Dividers
ARM CorePac
/1, /3, /3, /6, /6
--
--
--
--
C66x DSP CorePacs
Chip Interrupt Controllers (CICx)
/1, /2, /3, /4
/6
/2
DDR3 Memory Controller A (also receives clocks from the
DDR3_PLL)
EMIF16
/6
--
--
--
--
--
--
--
--
HyperLink
/2, /3, /6
SYSCLK1
MultiCore Shared Memory Controller (MSMC)
PCI express (PCIe)
/1
/2, /3, /4, /6
ROM
/6
Serial Gigabit Media Independent Interface (SGMII)
Universal Asynchronous Receiver/Transmitter (UART)
Universal Serial Bus 3.0 (USB 3.0)
/2, /3, /6, /8
/6
/3, /6
SYSCLK1 Shared Local Clock Dividers
Power/Sleep Controller (PSC)
EDMA
--
/12, /24
/3
SYSCLK1 Memory Protection Units (MPUx)
--
Semaphore
TeraNet (SYSCLK1/3 domain)
Boot Config
General-Purpose Input/Output (GPIO)
I2C
Security Manager
SYSCLK1
--
/6
Telecom Serial Interface Port (TSIP)
Serial Peripheral Interconnect (SPI)
TeraNet (CPU /6 domain)
Timers
SYSCLK2 Internal Clock Dividers
/12, /128
SYSCLK2 SmartReflex C66x CorePacs
--
11.5.1.3 Module Clock Input
Table 11-7 lists various clock domains in the device and their distribution in each peripheral. The table
also shows the distributed clock division in modules and their mapping with source clocks of the device
PLLs.
11.5.1.4 Core PLL Controller Operating Modes
The Core PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of
operation is determined by the BYPASS bit of the PLL Secondary Control Register (SECCTL).
•
•
In bypass mode, PLL input is fed directly out as SYSCLK1.
In PLL mode, SYSCLK1 is generated from the PLL output using the values set in the PLLM and PLLD
fields in the COREPLLCTL0 Register.
External hosts must avoid access attempts to the SoC while the frequency of its internal clocks is
changing. User software must implement a mechanism that causes the SoC to notify the host when the
PLL configuration has completed.
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11.5.1.5 Core PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device power-up. The device should not be taken out of reset until this stabilization
time has elapsed.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
Core PLL reset time value, see Table 11-14.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the PLL
Controller can be switched to PLL mode. The Core PLL lock time is given in Table 11-14.
Table 11-14. Core PLL Stabilization, Lock, and Reset Times
PARAMETER
MIN
TYP
MAX
UNIT
PLL stabilization time
PLL lock time
100
µs
2000 × C(1)
PLL reset time
1000
ns
(1) C = SYSCLK1(N|P) cycle time in ns.
11.5.2 PLL Controller Memory Map
The memory map of the Core PLL Controller is shown in Table 11-15. 66AK2Exx-specific Core PLL
Controller Register definitions can be found in the sections following Table 11-15. For other registers in
the table, see the KeyStone Architecture Phase Locked Loop (PLL) Controller User's Guide (SPRUGV2).
It is recommended to use read-modify-write sequence to make any changes to the valid bits in the Core
PLL Controller registers.
Note that only registers documented here are accessible on the 66AK2Exx. Other addresses in the Core
PLL Controller memory map including the Reserved registers must not be modified. Furthermore, only the
bits within the registers described here are supported.
Table 11-15. PLL Controller Registers (Including Reset Controller)
HEX ADDRESS RANGE
00 0231 0000 - 00 0231 00E3
00 0231 00E4
ACRONYM
REGISTER NAME
-
Reserved
RSTYPE
Reset Type Status Register (Reset Core PLL Controller)
Software Reset Control Register (Reset Core PLL Controller)
Reset Configuration Register (Reset Core PLL Controller)
Reset Isolation Register (Reset Core PLL Controller)
Reserved
00 0231 00E8
RSTCTRL
00 0231 00EC
RSTCFG
00 0231 00F0
RSISO
00 0231 00F0 - 00 0231 00FF
00 0231 0100
-
PLLCTL
PLL Control Register
00 0231 0104
-
Reserved
00 0231 0108
SECCTL
PLL Secondary Control Register
Reserved
00 0231 010C
-
00 0231 0110
PLLM
PLL Multiplier Control Register
Reserved
00 0231 0114
-
00 0231 0118
PLLDIV1
PLL Controller Divider 1Register
PLL Controller Divider 2 Register
PLL Controller Divider 3Register
Reserved
00 0231 011C
PLLDIV2
00 0231 0120
PLLDIV3
00 0231 0124
-
00 0231 0128
-
Reserved
00 0231 012C - 00 0231 0134
00 0231 0138
-
Reserved
PLLCMD
PLL Controller Command Register
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Table 11-15. PLL Controller Registers (Including Reset Controller) (continued)
HEX ADDRESS RANGE
00 0231 013C
ACRONYM
PLLSTAT
ALNCTL
DCHANGE
CKEN
REGISTER NAME
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
00 0231 0140
00 0231 0144
00 0231 0148
00 0231 014C
CKSTAT
SYSTAT
-
Reserved
00 0231 0150
SYSCLK Status Register
Reserved
00 0231 0154 - 00 0231 015C
00 0231 0160
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
PLLDIV8
PLLDIV9 - PLLDIV16
-
PLL Controller Divider 4Register
Reserved
00 0231 0164
00 0231 0168
Reserved
00 0231 016C
Reserved
00 0231 0170
Reserved
00 0231 0174 - 00 0231 0193
00 0231 0194 - 00 0231 01FF
Reserved
Reserved
11.5.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Core PLL and is shown in
Figure 11-8 and described in Table 11-16.
Figure 11-8. PLL Secondary Control Register (SECCTL)
31
24
23
22
19
18
0
Reserved
BYPASS
RW-1
OUTPUT DIVIDE
RW-0001
Reserved
RW-001 0000 0000 0000 0000
R-0000 0000
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-16. PLL Secondary Control Register Field Descriptions
Bit
Field
Description
31-24
23
Reserved
BYPASS
Reserved
Core PLL bypass enable
•
•
0 - Core PLL bypass disabled
1 - Core PLL bypass enabled
22-19
OUTPUT DIVIDE
Output divider ratio bits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0h - ÷1. Divide frequency by 1
1h - ÷2. Divide frequency by 2
2h - invalid entry
3h - ÷4. Divide frequency by 4
4h - invalid entry
5h - ÷6. Divide frequency by 6
6h - invalid entry
7h - ÷8. Divide frequency by 8
8h - invalid entry
9h - ÷10. Divide frequency by 10
Ah - invalid entry
Bh - ÷12. Divide frequency by 12
Ch - invalid entry
Dh - ÷14. Divide frequency by 14
Eh - invalid entry
Fh - ÷16. Divide frequency by 16
18-0
232
Reserved
Reserved
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11.5.2.2 PLL Controller Divider Register (PLLDIV3, and PLLDIV4)
The PLL Controller Divider Registers (PLLDIV3 and PLLDIV4) are shown in Figure 11-9 and described in
Table 11-17. The default values of the RATIO field on a reset for PLLDIV3, and PLLDIV4 are different as
mentioned in the footnote of Figure 11-9.
Figure 11-9. PLL Controller Divider Register (PLLDIVn)
31
16
15
14
8
7
0
Reserved
R-0
Dn(1)EN
Reserved
R-0
RATIO
R/W-n(2)
R/W-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
(1) D3EN for PLLDIV3; D4EN for PLLDIV4
(2) n=02h for PLLDIV3; n=03h for PLLDIV4
Table 11-17. PLL Controller Divider Register Field Descriptions
Bit
Field
Description
31-16
15
Reserved
DnEN
Reserved
Divider Dn enable bit (See footnote of Figure 11-9)
•
•
0 = Divider n is disabled
1 = No clock output. Divider n is enabled.
14-8
7-0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits (See footnote of Figure 11-9)
•
•
•
•
•
0h = ÷1. Divide frequency by 1
1h = ÷2. Divide frequency by 2
2h = ÷3. Divide frequency by 3
3h = ÷4. Divide frequency by 4
4h - 4Fh = ÷5 to ÷80. Divide frequency range: divide frequency by 5 to divide frequency by 80.
11.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller Clock Align Control Register (ALNCTL) is shown in Figure 11-10 and described in
Table 11-18.
Figure 11-10. PLL Controller Clock Align Control Register (ALNCTL)
31
5
4
3
2
0
Reserved
R-0
ALN4 ALN3
R/W-1 R/W-1
Reserved
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 11-18. PLL Controller Clock Align Control Register Field Descriptions
Bit
Field
Description
31-5
Reserved
Reserved. This location is always read as 0. A value written to this field has no effect.
2-0
4
ALN4
ALN3
SYSCLKn alignment. Do not change the default values of these fields.
•
0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn
3
switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
•
1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn
in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
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11.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLL CTL flags the change in the
DCHANGE Status Register. During the GO operation, the PLL controller changes only the divide ratio of
the SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also
needs to be aligned to other clocks. The PLLDIV Divider Ratio Change Status Register is shown in
Figure 11-11 and described in Table 11-19.
Figure 11-11. PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
5
4
3
2
0
Reserved
R-0
SYS4 SYS3
R/W-1 R/W-1
Reserved
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 11-19. PLLDIV Divider Ratio Change Status Register Field Descriptions
Bit
Field
Description
31-5
Reserved
Reserved. This bit location is always read as 0. A value written to this field has no effect.
2-0
4
SYS4
SYS3
Identifies when the SYSCLKn divide ratio has been modified.
•
•
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
3
11.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[4:1]. SYSTAT is shown in
Figure 11-12 and described in Table 11-20.
Figure 11-12. SYSCLK Status Register (SYSTAT)
31
4
3
2
1
0
Reserved
R-n
SYS4ON SYS3ON SYS2ON SYS1ON
R-1 R-1 R-1 R-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-20. SYSCLK Status Register Field Descriptions
Bit
Field
Description
31-4
3-0
Reserved
SYS[N(1)]ON SYSCLK[N] on status
Reserved. This location is always read as 0. A value written to this field has no effect.
•
•
0 = SYSCLK[N] is gated
1 = SYSCLK[N] is on
(1) Where N = 1, 2, 3, or 4
11.5.2.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources
occur simultaneously, this register latches the highest priority reset source. The Reset Type Status
Register is shown in Figure 11-13 and described in Table 11-21.
Figure 11-13. Reset Type Status Register (RSTYPE)
31
Reserved
R-0
29
28
EMU-RST
R-0
27
Reserved
R-0
12
11
8
7
3
2
1
0
WDRST[N]
R-0
Reserved
R-0
PLLCTRLRST
R-0
RESET
R-0
POR
R-0
LEGEND: R = Read only; -n = value after reset
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Table 11-21. Reset Type Status Register Field Descriptions
Bit
Field
Description
31-29 Reserved
Reserved. Always reads as 0. Writes have no effect.
Reset initiated by emulation
28
EMU-RST
•
•
0 = Not the last reset to occur
1 = The last reset to occur
27-12 Reserved
Reserved. Always reads as 0. Writes have no effect.
Reset initiated by Watchdog Timer[N]
11
10
9
WDRST3
WDRST2
WDRST1
•
•
0 = Not the last reset to occur
1 = The last reset to occur
8
WDRST0
7-3
2
Reserved
Reserved. Always reads as 0. Writes have no effect.
Reset initiated by PLLCTL
PLLCTLRST
•
•
0 = Not the last reset to occur
1 = The last reset to occur
1
0
RESET
POR
RESET reset
•
•
0 = RESET was not the last reset to occur
1 = RESET was the last reset to occur
Power-on reset
•
•
0 = Power-on reset was not the last reset to occur
1 = Power-on reset was the last reset to occur
11.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The
key value is 0x5A69. A valid key will be stored as 0x000C. Any other key value is invalid. When the
RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key.
The Software Reset Control Register (RSTCTRL) is shown in Figure 11-14 and described in Table 11-22.
Figure 11-14. Reset Control Register (RSTCTRL)
31
17
16
15
0
Reserved
R-0x0000
SWRST
R/W-0x(1)
KEY
R/W-0x0003
Legend: R = Read only; -n = value after reset;
(1) Writes are conditional based on valid key.
Table 11-22. Reset Control Register Field Descriptions
Bit
Field
Description
31-17 Reserved
Reserved
16
SWRST
KEY
Software reset
•
•
0 = Reset
1 = Not reset
15-0
Key used to enable writes to RSTCTRL and RSTCFG.
11.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset (a hard reset or a soft reset) initiated by RESET, the
watchdog timer, and the Core PLL Controller’s RSTCTRL Register. By default, these resets are hard
resets. The Reset Configuration Register (RSTCFG) is shown in Figure 11-15 and described in Table 11-
23.
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Figure 11-15. Reset Configuration Register (RSTCFG)
31
14
13
12
11
4
3
0
Reserved
PLLCTLRSTTYPE
R/W-0(2)
RESETTYPE
R/W-0(2)
Reserved
R-0x0
WDTYPE[N(1)
R/W-0x00(2)
]
R-0x000000
Legend: R = Read only; R/W = Read/Write; -n = value after reset
(1) Where N = 1, 2, 3,....N (Not all these outputs may be used on a specific device.)
(2) Writes are conditional based on valid key. For details, see Section 11.5.2.7.
Table 11-23. Reset Configuration Register Field Descriptions
Bit
Field
Description
Reserved
PLLCTLRSTTYPE PLL controller initiates a software-driven reset of type:
31-14 Reserved
13
•
•
0 = Hard reset (default)
1 = Soft reset
12
RESETTYPE
Reserved
RESET initiates a reset of type:
•
•
0 = Hard reset (default)
1 = Soft reset
11-4
Reserved
3
2
1
0
WDTYPE3
WDTYPE2
WDTYPE1
WDTYPE0
Watchdog timer [N] initiates a reset of type:
•
•
0 = Hard reset (default)
1 = Soft reset
11.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through
non-power-on reset. Setting any of these bits effectively blocks reset to all Core PLL Control Registers in
order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting the
module-specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in the PSC to reset-
isolate a particular module. For more information on the MDCTLx Register, see the KeyStone Architecture
Power Sleep Controller (PSC) User's Guide (SPRUGV4). The Reset Isolation Register (RSISO) is shown
in Figure 11-16 and described in Table 11-24.
Figure 11-16. Reset Isolation Register (RSISO)
31
9
8
7
0
Reserved
R-0
SRISO
R/W-0
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 11-24. Reset Isolation Register Field Descriptions
Bit
31-9
8
Field
Description
Reserved
SRISO
Reserved.
Isolate SmartReflex control
•
•
0 = Not reset isolated
1 = Reset isolated
7-0
Reserved
Reserved
11.5.3 Core PLL Control Registers
The Core PLL uses two chip-level registers (COREPLLCTL0 and COREPLLCTL1) along with the Core
PLL Controller for its configuration. These MMRs (memory-mapped registers) exist inside the Bootcfg
space. To write to these registers, software should go through an unlocking sequence using the KICK0
and KICK1 registers. These registers reset only on a POR reset.
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For valid configurable values of the COREPLLCTL registers, see Section 9.1.4. See Section 9.2.3.4 for
the address location of the KICK registers and their locking and unlocking sequences.
See Figure 11-17 and Table 11-25 for COREPLLCTL0 details and Figure 11-18 and Table 11-26 for
COREPLLCTL1 details.
Figure 11-17. Core PLL Control Register 0 (COREPLLCTL0)
31
24
23
19
18
12
11
6
5
0
BWADJ[7:0]
Reserved
PLLM[12:6]
Reserved
PLLD
RW,+000000
RW,+0000 0101
RW - 0000 0
RW,+0000000
RW, +000000
Legend: RW = Read/Write; -n = value after reset
Table 11-25. Core PLL Control Register 0 (COREPLLCTL0) Field Descriptions
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in COREPLLCTL0 and COREPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
23-19 Reserved
Reserved
18-12 PLLM[12:6]
7 bits of a 13-bit field PLLM that selects the values for the multiplication factor. PLLM field is loaded with the
multiply factor minus 1.
The PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL Controller and the
PLLM[12:6] bits are controlled by the above chip-level register. COREPLLCTL0 register PLLM[12:6] bits should
be written just before writing to PLLM register PLLM[5:0] bits in the controller to have the complete 13 bit value
latched when the GO operation is initiated in the PLL controller. See the KeyStone Architecture Phase Locked
Loop (PLL) Controller User's Guide (SPRUGV2) for the recommended programming sequence. Output Divide
ratio and Bypass enable/disable of the Core PLL is also controlled by the SECCTL register in the PLL
Controller. See the Section 11.5.2.1for more details.
11-6
5-0
Reserved
PLLD
Reserved
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value
minus 1.
Figure 11-18. Core PLL Control Register 1 (COREPLLCTL1)
31
7
6
5
4
3
0
Reserved
ENSAT
RW-0
Reserved
R-00
BWADJ[11:8]
RW- 0000
RW - 0000000000000000000000000
Legend: RW = Read/Write; -n = value after reset
Table 11-26. Core PLL Control Register 1 (COREPLLCTL1) Field Descriptions
Bit
31-7
6
Field
Description
Reserved
ENSAT
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in COREPLLCTL0 and COREPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
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11.5.4 Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Electrical
Data/Timing
Table 11-27. Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Timing
Requirements(1)
(see Figure 11-19 through Figure 11-21)
NO.
MIN
MAX UNIT
CORECLK[P:N]
Cycle time CORECLKN cycle time
1
1
3
2
2
3
4
tc(CORECLKN)
tc(CORECLKP)
tw(CORECLKN)
tw(CORECLKN)
tw(CORECLKP)
tw(CORECLKP)
tr(CORECLK_200 mV)
3.2
3.2
25
25
ns
ns
ns
ns
ns
ns
Cycle time CORECLKP cycle time
Pulse width CORECLKN high
Pulse width CORECLKN low
Pulse width CORECLKP high
Pulse width CORECLKP low
0.45*tc
0.45*tc
0.45*tc
0.45*tc
0.55*tc
0.55*tc
0.55*tc
0.55*tc
Transition time CORECLK differential
rise time (200 mV)
50
50
350
350
ps
ps
ps
ps
4
5
5
tf(CORECLK_200 mV)
tj(CORECLKN)
Transition time CORECLK differential
fall time (200 mV)
Jitter, peak_to_peak _ periodic
CORECLKN
0.02*tc(CORECLKN)
0.02*tc(CORECLKP)
tj(CORECLKP)
Jitter, peak_to_peak _ periodic
CORECLKP
SGMII0CLK[P:N]
1
1
3
2
2
3
4
tc(SGMII0CLKN)
tc(SGMII0CLKP)
tw(SGMII0CLKN)
tw(SGMII0CLKN)
tw(SGMII0CLKP)
tw(SGMII0CLKP)
tr(SGMII0CLK_200mV)
Cycle time SGMII0CLKN cycle time
Cycle time SGMII0CLKP cycle time
Pulse width SGMII0CLKN high
Pulse width SGMII0CLKN low
Pulse width SGMII0CLKP high
Pulse width SGMII0CLKP low
3.2 or 6.4 or 8
3.2 or 6.4 or 8
ns
ns
ns
ns
ns
ns
0.45*tc(SGMII0CLKN)
0.55*tc(SGMII0CLKN)
0.55*tc(SGMII0CLKN)
0.55*tc(SGMII0CLKP)
0.55*tc(SGMII0CLKP)
0.45*tc(SGMII0CLKN)
0.45*tc(SGMII0CLKP)
0.45*tc(SGMII0CLKP)
Transition time SGMII0CLK differential
rise time (200 mV)
50
50
350
350
4
ps
ps
4
5
5
tf(SGMII0CLK_200mV)
tj(SGMII0CLKN)
Transition time SGMII0CLK differential
fall time (200 mV)
Jitter, RMS SGMII0CLKN
ps,
RMS
tj(SGMII0CLKP)
Jitter, RMS SGMII0CLKP
ps,
RMS
4
XFICLK[P:N]
1
1
3
2
2
3
4
tc(XFICLKN)
tc(XFICLKP)
Cycle time XFICLKN cycle time
Cycle time XFICLKP cycle time
Pulse width XFICLKN high
Pulse width XFICLKN low
Pulse width XFICLKP high
Pulse width XFICLKP low
3.2 or 6.4
3.2 or 6.4
0.45*tc(XFICLKN)
ns
ns
ns
ns
ns
ns
tw(XFICLKN)
tw(XFICLKN)
tw(XFICLKP)
tw(XFICLKP)
tr(XFICLK_200mV)
0.55*tc(XFICLKN)
0.55*tc(XFICLKN)
0.55*tc(XFICLKP)
0.55*tc(XFICLKP)
0.45*tc(XFICLKN)
0.45*tc(XFICLKP)
0.45*tc(XFICLKP)
Transition time XFICLK differential rise
time (200 mV)
50
50
350
350
4
ps
ps
4
5
5
tf(XFICLK_200mV)
tj(XFICLKN)
Transition time XFICLK differential fall
time (200 mV)
Jitter, RMS XFICLKN
ps,
RMS
tj(XFICLKP)
Jitter, RMS XFICLKP
ps,
RMS
4
HYPLNK0CLK[P:N]
(1) See the Hardware Design Guide for KeyStone II Devices application report (SPRABV0) for detailed recommendations.
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Table 11-27. Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Timing
Requirements(1) (continued)
(see Figure 11-19 through Figure 11-21)
NO.
1
MIN
MAX UNIT
tc(HYPLNK0CLKN)
tc(HYPLNK0CLKP)
tw(HYPLNK0CLKN)
tw(HYPLNK0CLKN)
tw(HYPLNK0CLKP)
tw(HYPLNK0CLKP)
tr(HYPLNK0CLK)
Cycle time HYPLNK0CLKN cycle time
Cycle time HYPLNK0CLKP cycle time
Pulse width HYPLNK0CLKN high
Pulse width HYPLNK0CLKN low
Pulse width HYPLNK0CLKP high
Pulse width HYPLNK0CLKP low
3.2 or 6.4
3.2 or 6.4
ns
ns
1
3
0.45*tc(HYPLNK0CLKN) 0.55*tc(HYPLNK0CLKN)
0.45*tc(HYPLNK0CLKN) 0.55*tc(HYPLNK0CLKN)
0.45*tc(HYPLNK0CLKP) 0.55*tc(HYPLNK0CLKP)
0.45*tc(HYPLNK0CLKP) 0.55*tc(HYPLNK0CLKP)
ns
ns
ns
ns
2
2
3
4
Rise time HYPLNK0CLK differential
rise time (10% to 90%)
0.2*tc(HYPLNK0CLKP)
ps
ps
4
5
5
tf(HYPLNK0CLK)
tj(HYPLNK0CLKN)
tj(HYPLNK0CLKP)
Fall time HYPLNK0CLK differential fall
time (10% to 90%)
0.2*tc(HYPLNK0CLKP)
Jitter, RMS HYPLNK0CLKN
ps,
RMS
4
4
Jitter, RMS HYPLNK0CLKP
ps,
RMS
PCIECLK[P:N]
1
1
3
2
2
3
4
tc(PCIECLKN)
tc(PCIECLKP)
tw(PCIECLKN)
tw(PCIECLKN)
tw(PCIECLKP)
tw(PCIECLKP)
tr(PCIECLK)
Cycle time PCIECLKN cycle time
Cycle time PCIECLKP cycle time
Pulse width PCIECLKN high
Pulse width PCIECLKN low
Pulse width PCIECLKP high
Pulse width PCIECLKP low
10
10
10
10
ns
ns
ns
ns
ns
ns
0.45*tc(PCIECLKN)
0.45*tc(PCIECLKN)
0.45*tc(PCIECLKP)
0.45*tc(PCIECLKP)
0.55*tc(PCIECLKN)
0.55*tc(PCIECLKN)
0.55*tc(PCIECLKP)
0.55*tc(PCIECLKP)
Rise time PCIECLK differential rise
time (10% to 90%)
0.2*tc(PCIECLKP)
ps
ps
4
5
5
tf(PCIECLK)
tj(PCIECLKN)
tj(PCIECLKP)
Fall time PCIECLK differential fall time
(10% to 90%)
0.2*tc(PCIECLKP)
Jitter, RMS PCIECLKN
ps,
RMS
4
4
Jitter, RMS PCIECLKP
ps,
RMS
USBCLK[P:M]
1
1
3
2
2
3
4
tc(USBCLKN)
tc(USBCLKP)
tw(USBCLKN)
tw(USBCLKN)
tw(USBCLKP)
tw(USBCLKP)
tr(USBCLK)
Cycle time USBCLKM cycle time
Cycle time USBCLKP cycle time
Pulse width USBCLKM high
Pulse width USBCLKM low
Pulse width USBCLKP high
Pulse width USBCLKP low
10
10
10
10
ns
ns
ns
ns
ns
ns
0.45*tc(USBCLKN)
0.45*tc(USBCLKN)
0.45*tc(USBCLKP)
0.45*tc(USBCLKP)
0.55*tc(USBCLKN)
0.55*tc(USBCLKN)
0.55*tc(USBCLKP)
0.55*tc(USBCLKP)
Rise time USBCLK differential rise time
(10% to 90%)
50
50
350
350
4
ps
ps
4
5
5
tf(USBCLK)
tj(USBCLKN)
tj(USBCLKP)
Fall time USBCLK differential fall time
(10% to 90%)
Jitter, RMS USBCLKM
ps,
RMS
Jitter, RMS USBCLKP
ps,
RMS
4
TSREFCLK[P:N](2)
1
1
3
tc(TSREFCLKN)
tc(TSREFCLKP)
tw(TSREFCLKN)
Cycle time TSREFCLKN cycle time
Cycle time TSREFCLKP cycle time
Pulse width TSREFCLKN high
3.25
3.25
32.55
32.55
ns
ns
ns
0.45*tc(TSREFCLKN)
0.55*tc(TSREFCLKN)
(2) TSREFCLK clock input is LVDS compliant.
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Table 11-27. Core PLL Controller/SGMII/XFI/TSREF/HyperLink/PCIe/USB Clock Input Timing
Requirements(1) (continued)
(see Figure 11-19 through Figure 11-21)
NO.
2
MIN
0.45*tc(TSREFCLKN)
0.45*tc(TSREFCLKP)
0.45*tc(TSREFCLKP)
MAX UNIT
tw(TSREFCLKN)
tw(TSREFCLKP)
tw(TSREFCLKP)
tr(TSREFCLK_200mV)
Pulse width TSREFCLKN low
Pulse width TSREFCLKP high
Pulse width TSREFCLKP low
0.55*tc(TSREFCLKN)
ns
ns
ns
2
0.55*tc(TSREFCLKP)
0.55*tc(TSREFCLKP)
3
4
Transition time TSREFCLK differential
rise time (200 mV)
50
50
350
350
5.8
ps
ps
4
5
5
tf(TSREFCLK_200mV)
tj(TSREFCLKN)
Transition time TSREFCLK differential
fall time (200 mV)
Jitter, RMS TSREFCLKN
ps,
RMS
tj(TSREFCLKP)
Jitter, RMS TSREFCLKP
ps,
RMS
5.8
1
2
3
<CLK_NAME>CLKN
<CLK_NAME>CLKP
Figure 11-19. Clock Input Timing
peak-to-peak Differential Input
Voltage (250 mV to 2 V)
200 mV Transition Voltage Range
0
TR = 50 ps Min to 350 ps Max
for the 200-mV Transition Voltage Range
Figure 11-20. CORECLK, SGMII0CLK and USBCLK Clock Transition Time
TC Reference Clock Period
peak-to-peak
Differential
Input Voltage
10% to 90%
of peak-to-peak
Voltage
0
(400 mV to 1100 mV)
Max TR = 0.2
T
C from
Max T = 0.2
TC from
×
10% to 90% of the
×
90% to 10% of the
F
peak-to-peak
Differential Voltage
peak-to-peak
Differential Voltage
Figure 11-21. HYPLNK0CLK, XFICLK, and PCIECLK Rise and Fall Times
11.6 DDR3 PLL
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The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on
reset, DDR3 PLL is programmed to a valid frequency during the boot configuration process before being
enabled and used.
DDR3 PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter circuit
must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices application
report (SPRABV0) for detailed recommendations.
PLLM
DDR3 PLL
VCO
0
DDRCLK(N|P)
PLLOUT
DDR3CLKOUT
DDR3
PHY
PLLD
CLKOD
1
´2
BYPASS
Figure 11-22. DDR3 PLL Block Diagram
11.6.1 DDR3 PLL Control Registers
The DDR3 PLL, which is used to drive the DDR3 PHY for the EMIF, does not use a PLL controller. DDR3
PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg
module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these
registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For
suggested configurable values, see Section 9.1.4. See Section 9.2.3.4 for the address location of the
registers and locking and unlocking sequences for accessing the registers. These registers are reset on
POR only.
Figure 11-23. DDR3 PLL Control Register 0 (DDR3PLLCTL0)
31
24
23
22
CLKOD
RW,+0001
19
18
6
5
0
BWADJ[7:0]
BYPASS
RW,+0
PLLM
PLLD
RW,+000000
RW,+0000 1001
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
Table 11-28. DDR3 PLL Control Register 0 Field Descriptions
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
23
BYPASS
Enable bypass mode
•
•
0 = Bypass disabled
1 = Bypass enabled
22-19 CLKOD
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
18-6
5-0
PLLM
PLLD
A 13-bit field that selects the values for the PLL multiplication factor. PLLM field is loaded with the multiply
factor minus 1
A 6-bit field that selects the values for the reference (input) divider. PLLD field is loaded with reference divide
value minus 1
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Figure 11-24. DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31
15
14
13
7
6
5
4
3
0
Reserved
PLLRST
RW-0
Reserved
ENSAT
RW-0
Reserved
R-00
BWADJ[11:8]
RW- 0000
RW - 00000000000000000
RW-0000000
Legend: RW = Read/Write; -n = value after reset
Table 11-29. DDR3 PLL Control Register 1 Field Descriptions
Bit
Field
Description
31-15 Reserved
Reserved
14
PLLRST
PLL Reset bit
•
•
0 = PLL Reset is released
1 = PLL Reset is asserted
13-7
6
Reserved
ENSAT
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in the DDR3PLLCTL0 and the DDR3PLLCTL1 registers.
BWADJ[11:0] should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
11.6.2 DDR3 PLL Device-Specific Information
As shown in Figure 11-22, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3
memory controller. During power-on resets, the internal clocks of the DDR3 PLL are affected as described
in Section Section 11.4. The DDR3 PLL is unlocked only during the power-up sequence and is locked by
the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
11.6.3 DDR3 PLL Input Clock Electrical Data/Timing
Table 11-30 applies to DDR3 memory interface.
Table 11-30. DDR3 PLL DDRCLK(N|P) Timing Requirements
(see Figure 11-25 and Figure 11-20)
No.
Min
Max Unit
DDRCLK[P:N]
1
1
3
2
2
3
4
tc(DDRCLKN)
tc(DDRCLKP)
tw(DDRCLKN)
tw(DDRCLKN)
tw(DDRCLKP)
tw(DDRCLKP)
Cycle time _ DDRCLKN cycle time
Cycle time _ DDRCLKP cycle time
Pulse width _ DDRCLKN high
Pulse width _ DDRCLKN low
Pulse width _ DDRCLKP high
Pulse width _ DDRCLKP low
3.2
3.2
25
25
ns
ns
ns
ns
ns
ns
0.45*tc(DDRCLKN)
0.45*tc(DDRCLKN)
0.45*tc(DDRCLKP)
0.45*tc(DDRCLKP)
0.55*tc(DDRCLKN)
0.55*tc(DDRCLKN)
0.55*tc(DDRCLKP)
0.55*tc(DDRCLKP)
tr(DDRCLK_200
mV)
Transition time _ DDRCLK differential rise time (200 mV)
50
50
350
350
ps
ps
4
tf(DDRCLK_200
mV)
Transition time _ DDRCLK differential fall time (200 mV)
5
5
tj(DDRCLKN)
tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKN
Jitter, peak_to_peak _ periodic DDRCLKP
0.02*tc(DDRCLKN)
0.02*tc(DDRCLKP)
ps
ps
1
2
3
5
DDRCLKN
DDRCLKP
4
Figure 11-25. DDR3 PLL DDRCLK Timing
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11.7 NETCP PLL
The NETCP PLL generates interface clocks for the Network Coprocessor. Using the NETCPCLKSEL pin
the user can select the input source of the NETCP PLL as either the output of the Core PLL mux or the
NETCPCLK clock reference source. When coming out of power-on reset, NETCP PLL comes out in a
bypass mode and needs to be programmed to a valid frequency before being enabled and used.
NETCP PLL power is supplied via the NETCP PLL power-supply pin (AVDDA3). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations.
NETCP
Clock Source
MUX
PLLM
NETCP PLL
SYSCLK0
CLKOD
/3
PLLD
0
1
CORECLK(P|N)
NETCPCLK(P|N)
NETCP
Sub-system
0
1
VCO
0
1
BYPASS
NETCPCLKSEL
NETCPPLLCTL1.PAPLL
(bit13)
Figure 11-26. NETCP PLL Block Diagram
11.7.1 NETCP PLL Local Clock Dividers
The clock signal from the NETCP PLL Controller is routed to the Network Coprocessor. The NETCP
module has two internal dividers with fixed division ratios. See table Table 11-31.
11.7.2 NETCP PLL Control Registers
The NETCP PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. NETCP
PLL can be controlled using the NETCPPLLCTL0 and NETCPPLLCTL1 registers located in the Bootcfg
module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these
registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For
suggested configuration values, see Section 9.1.4. See Section 9.2.3.4 for the address location of the
registers and locking and unlocking sequences for accessing these registers. These registers are reset on
POR only.
Figure 11-27. NETCP PLL Control Register 0 (NETCPPLLCTL0)
31
24
23
22
CLKOD
RW,+0001
19
18
6
5
0
BWADJ[7:0]
BYPASS
RW,+0
PLLM
PLLD
RW,+000000
RW,+0000 1001
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
Table 11-31. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0)
Bit
Field
Description
31-24 BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
23
BYPASS
Enable bypass mode
•
•
0 = Bypass disabled
1 = Bypass enabled
22-19 CLKOD
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
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Table 11-31. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0) (continued)
Bit
Field
Description
18-6
PLLM
A 13-bit field that selects the values for the multiplication factor. PLLM field is loaded with the multiply factor
minus 1.
5-0
PLLD
A 6-bit field that selects the values for the reference divider. PLLD field is loaded with reference divide value
minus 1.
Figure 11-28. NETCP PLL Control Register 1 (NETCPPLLCTL1)
31
15
14
13
12
7
6
5
4
3
0
Reserved
RW - 00000000000000000
PLLRST
RW-0
PAPLL
RW-0
Reserved
ENSAT
RW-0
Reserved
R-00
BWADJ[11:8]
RW-0000
RW-000000
Legend: RW = Read/Write; -n = value after reset
Table 11-32. NETCP PLL Control Register 1 Field Descriptions (NETCPPLLCTL1)
Bit
Field
Description
Reserved
31-15 Reserved
14
13
PLLRST
PAPLL
PLL Reset bit
•
•
0 = PLL Reset is released
1 = PLL Reset is asserted
NETCP Clock Source MUX Control
•
•
0 = SYSCLK0
1 = NETCP PLL
12-7
6
Reserved
ENSAT
Reserved
Needs to be set to 1 for proper PLL operation
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
11.7.3 NETCP PLL Device-Specific Information
As shown in Figure 11-26, the output of NETCP PLL (PLLOUT) is divided by 3 and directly fed to the
Network Coprocessor. During power-on resets, the internal clocks of the NETCP PLL are affected as
described in Section 11.4. The NETCP PLL is unlocked only during the power-up sequence and is locked
by the time the RESETSTAT pin goes high. It does not lose lock during any other resets.
11.7.4 NETCP PLL Input Clock Electrical Data/Timing
Table 11-33. NETCP PLL Timing Requirements
(see Figure 11-29 and Figure 11-20)
NO.
MIN
MAX
UNIT
NETCPCLK[P:N]
Cycle time _ NETCPCLKN cycle time
1
1
3
2
2
3
4
tc(NETCPCLKN)
tc(NETCPCLKP)
tw(NETCPCLKN)
tw(NETCPCLKN)
tw(NETCPCLKP)
tw(NETCPCLKP)
3.2
3.2
25
25
ns
ns
ns
ns
ns
ns
ps
Cycle time _ NETCPCLKP cycle time
Pulse width _ NETCPCLKN high
Pulse width _ NETCPCLKN low
Pulse width _ NETCPCLKP high
Pulse width _ NETCPCLKP low
0.45*tc(NETCPCLKN)
0.45*tc(NETCPCLKN)
0.45*tc(NETCPCLKP)
0.45*tc(NETCPCLKP)
0.55*tc(NETCPCLKN)
0.55*tc(NETCPCLKN)
0.55*tc(NETCPCLKP)
0.55*tc(NETCPCLKP)
Transition time _ NETCPCLK differential rise time
(250 mV)
tr(NETCPCLK_250mV)
tf(NETCPCLK_250mV)
50
50
350
350
4
Transition time _ NETCPCLK differential fall time
(250 mV)
ps
5
5
tj(NETCPCLKN)
tj(NETCPCLKP)
Jitter, peak_to_peak _ periodic NETCPCLKN
Jitter, peak_to_peak _ periodic NETCPCLKP
100
100
ps, pk-pk
ps, pk-pk
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1
2
3
5
NETCPCLKN
NETCPCLKP
4
Figure 11-29. NETCP PLL Timing
11.8 External Interrupts
11.8.1 External Interrupts Electrical Data/Timing
Table 11-34. NMI and LRESET Timing Requirements(1)
(see Figure 11-30)
No.
Min
12*P
Max
Unit
ns
1
1
2
2
3
tsu(LRESET-LRESETNMIEN)
Setup time - LRESET valid before LRESETNMIEN low
Setup time - NMI valid before LRESETNMIEN low
Hold time - LRESET valid after LRESETNMIEN high
Hold time - NMI valid after LRESETNMIEN high
Pulsewidth - LRESETNMIEN low width
tsu(NMI-LRESETNMIEN)
th(LRESETNMIEN-LRESET)
th(LRESETNMIEN-NMI)
tw(LRESETNMIEN)
12*P
12*P
12*P
12*P
ns
ns
ns
ns
(1) P = 1/SYSCLK1 clock frequency in ns.
1
2
LRESET/
NMI
3
LRESETNMIEN
Figure 11-30. NMI and LRESET Timing
11.9 DDR3 Memory Controller
The 72-bit DDR3 Memory Controller bus of the 66AK2E0x is used to interface to JEDEC standard-
compliant DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices and
does not share the bus with any other type of peripheral.
11.9.1 DDR3 Memory Controller Device-Specific Information
The 66AK2E0x includes one 64-bit wide, 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can
operate at 800 mega transfers per second (MTS), 1033 MTS, 1333 MTS, and 1600 MTS.
Due to the complicated nature of the interface, a limited number of topologies are supported to provide a
16-bit, 32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR JEDEC Specification JESD79-3C.
Standard DDR3 SDRAMs are available in 8-bit and 16-bit versions allowing for the following bank
topologies to be supported by the interface:
•
•
•
•
•
72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
36-bit:Five 8-bit SDRAMs (including 4 bits of ECC)
64-bit:Four 16-bit SDRAMs
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•
•
•
•
•
64-bit:Eight 8-bit SDRAMs
32-bit:Two 16-bit SDRAMs
32-bit: Four 8-bit SDRAMs
16-bit:One 16-bit SDRAM
16-bit:Two 8-bit SDRAMs
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces
such as I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual
specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the
approach is to specify compatible DDR3 devices and provide the printed circuit board (PCB) solution and
guidelines directly to the user.
A race condition may exist when certain masters write data to the DDR3 memory controller. For example,
if master A passes a software message via a buffer in external memory and does not wait for an indication
that the write completes before signaling to master B that the message is ready, when master B attempts
to read the software message, the master B read may bypass the master A write. Thus, master B may
read stale data and receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) always wait for the write to
complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do
not have a hardware specification of write-read ordering, it may be necessary to specify data ordering in
the software.
If master A does not wait for an indication that a write is complete, it must perform the following
workaround:
1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
11.9.2 DDR3 Slew Rate Control
The DDR3 slew rate is controlled by use of the PHY registers. See theKeyStone Architecture DDR3
Memory Controller User's Guide SPRUGV8 for details.
11.9.3 DDR3 Memory Controller Electrical Data/Timing
The DDR3 Design Requirements for KeyStone Devices application report SPRABI1 specifies a complete
DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements
are fully specified in the DDR3 JEDEC Specification JESD79-3C. TI has performed the simulation and
system characterization to ensure all DDR3 interface timings in this solution are met. Therefore, no
electrical data/timing information is supplied here for this interface.
NOTE
TI supports only designs that follow the board design guidelines outlined in the application
report.
11.10 I2C Peripheral
The Inter-Integrated Circuit (I2C) module provides an interface between SoC and other devices compliant
with Philips Semiconductors (now NXP Semiconductors) Inter-Integrated Circuit bus specification version
2.1. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from
the device through the I2C module.
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11.10.1 I2C Device-Specific Information
The device includes multiple I2C peripheral modules.
NOTE
When using the I2C module, ensure there are external pullup resistors on the SDA and SCL
pins.
The I2C modules on the 66AK2E0x may be used by the SoC to control local peripheral ICs (DACs, ADCs,
etc.), communicate with other controllers in a system, or to implement a user interface.
The I2C port supports:
•
•
•
•
•
•
•
Compatibility with Philips I2C specification revision 2.1 (January 2000)
Fast mode up to 400 kbps (no fail-safe I/O buffers)
Noise filter to remove noise of 50 ns or less
7-bit and 10-bit device addressing modes
Multi-master (transmit/receive) and slave (transmit/receive) functionality
Events: DMA, interrupt, or polling
Slew-rate limited open-drain output buffers
Figure 11-31 shows a block diagram of the I2C module.
I2C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
I2CPSC
Control
Bit Clock
Generator
Own
Address
I2COAR
I2CSAR
I2CMDR
I2CCNT
I2CEMDR
SCL
Noise
Filter
I2C Clock
I2CCLKH
I2CCLKL
Slave
Address
Mode
Data
Count
Transmit
I2CXSR
Transmit
Shift
Extended
Mode
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIMR
Noise
Filter
I2C Data
Interrupt
Mask/Status
Receive
I2CDRR
Receive
Buffer
Interrupt
Status
I2CSTR
Interrupt
Vector
I2CRSR
I2CIVR
Receive
Shift
Shading denotes control/status registers.
Figure 11-31. I2C Module Block Diagram
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11.10.2 I2C Peripheral Register Description
Table 11-35. I2C Registers
HEX ADDRESS OFFSETS
0x0000
ACRONYM
ICOAR
ICIMR
REGISTER NAME
I2C Own Address Register
0x0004
I2C Interrupt Mask/status Register
I2C Interrupt Status Register
I2C Clock Low-time Divider Register
I2C Clock High-time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
0x0008
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
I2C Mode Register
0x0028
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
I2C Peripheral Identification Register 1 [value: 0x0000 0105]
I2C Peripheral Identification Register 2 [value: 0x0000 0005]
Reserved
0x002C
ICEMDR
ICPSC
ICPID1
ICPID2
-
0x0030
0x0034
0x0038
0x003C -0x007F
11.10.3 I2C Electrical Data/Timing
11.10.3.1 Inter-Integrated Circuits (I2C) Timing
Table 11-36. I2C Timing Requirements(1)
(see Figure 11-32)
STANDARD MODE
FAST MODE
NO.
MIN
MAX
MIN
MAX UNIT
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
µs
µs
3
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
th(SDAL-SCLL)
4
5
6
7
8
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
100(2)
0(3)
µs
µs
ns
tsu(SDAV-SCLH) Setup time, SDA valid before SCL high
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I2C bus devices)
250
0(3)
3.45
0.9(4)
µs
Pulse duration, SDA high between STOP and START
conditions
tw(SDAH)
4.7
1.3
µs
(5)
9
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
(5)
(5)
(5)
10
11
12
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has to be met only if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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Table 11-36. I2C Timing Requirements(1) (continued)
(see Figure 11-32)
STANDARD MODE
FAST MODE
NO.
MIN
MAX
MIN
0.6
0
MAX UNIT
13
14
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
4
µs
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(5)
Cb
400
400
pF
11
9
SDA
8
6
14
13
4
5
10
SCL
1
3
12
7
2
3
Stop
Start
Repeated
Start
Stop
Figure 11-32. I2C Receive Timings
Table 11-37. I2C Switching Characteristics(1)
(see Figure 11-33)
STANDARD
MODE
FAST MODE
NO.
PARAMETER
MIN
MAX
MIN
MAX UNIT
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
Setup time, SCL high to SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
0.6
0.6
µs
µs
18
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
th(SDAL-SCLL)
4
19
20
21
22
23
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
100
0
µs
µs
td(SDAV-SDLH) Delay time, SDA valid to SCL high
tv(SDLL-SDAV)
Valid time, SDA valid after SCL low (for I2C bus devices)
250
0
ns
0.9 µs
Pulse duration, SDA high between STOP and START
conditions
tw(SDAH)
4.7
1.3
µs
(1)
24
25
26
27
28
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300 ns
300 ns
300 ns
300 ns
µs
(1)
(1)
(1)
td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
Cp
Capacitance for each I2C pin
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
4
0.6
10
10 pF
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26
24
SDA
23
21
19
28
20
25
SCL
16
18
17
27
22
18
Stop
Start
Repeated
Start
Stop
Figure 11-33. I2C Transmit Timings
11.11 SPI Peripheral
The Serial Peripheral Interconnect (SPI) module provides an interface between the SoC and other SPI-
compliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot.
The SPI module on 66AK2E0x is supported only in master mode. Additional chip-level components can
also be included, such as temperature sensors or an I/O expander.
11.11.1 SPI Electrical Data/Timing
Table 11-38. SPI Timing Requirements
(see Figure 11-34)
NO.
MIN MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0
tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1
tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0
tsu(SPIDIN-SPC) Input setup time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1
7
7
7
7
8
8
8
8
2
2
2
2
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
th(SPC-SPIDIN)
th(SPC-SPIDIN)
th(SPC-SPIDIN)
th(SPC-SPIDIN)
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0
Input hold time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
Table 11-39. SPI Switching Characteristics
(see Figure 11-34 and Figure 11-35)
NO.
PARAMETER
MIN
MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
2
3
4
tc(SPC)
Cycle time, SPICLK, all master modes
3*P2(1)
ns
ns
ns
tw(SPCH)
tw(SPCL)
Pulse width high, SPICLK, all master modes
Pulse width low, SPICLK, all master modes
0.5*(3*P2) - 1
0.5*(3*P2) - 1
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK. Polarity = 0, Phase = 0.
ns
5
4
4
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK. Polarity = 0, Phase = 1.
ns
5
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
on SPICLK Polarity = 1, Phase = 0
ns
5
(1) P2=1/(SYSCLK1/6)
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Table 11-39. SPI Switching Characteristics (continued)
(see Figure 11-34 and Figure 11-35)
NO.
PARAMETER
MIN
MAX UNIT
4
5
5
5
5
6
6
6
6
td(SPIDOUT-SPC) Setup (Delay), initial data bit valid on SPIDOUT to initial edge
ns
5
on SPICLK Polarity = 1, Phase = 1
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK. Polarity = 0 Phase = 0
ns
2
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK Polarity = 0 Phase = 1
ns
2
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK Polarity = 1 Phase = 0
ns
2
td(SPC-SPIDOUT) Setup (Delay), subsequent data bits valid on SPIDOUT to
initial edge on SPICLK Polarity = 1 Phase = 1
ns
2
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 0 Phase = 0
ns
ns
ns
ns
0.5*tc - 2
0.5*tc - 2
0.5*tc - 2
0.5*tc - 2
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 0 Phase = 1
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 1 Phase = 0
toh(SPC-
SPIDOUT)
Output hold time, SPIDOUT valid after receive edge of
SPICLK except for final bit. Polarity = 1 Phase = 1
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19
19
19
19
20
20
20
20
td(SCS-SPC)
td(SCS-SPC)
td(SCS-SPC)
td(SCS-SPC)
td(SPC-SCS)
td(SPC-SCS)
td(SPC-SCS)
td(SPC-SCS)
tw(SCSH)
Delay from SPISCSx\ active to first SPICLK. Polarity = 0
Phase = 0
ns
2*P2 - 5
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5
2*P2 - 5 2*P2 + 5
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5
1*P2 - 5 1*P2 + 5
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5
1*P2 - 5 1*P2 + 5
2*P2 + 5
Delay from SPISCSx\ active to first SPICLK. Polarity = 0
Phase = 1
ns
ns
ns
ns
ns
ns
ns
ns
Delay from SPISCSx\ active to first SPICLK. Polarity = 1
Phase = 0
Delay from SPISCSx\ active to first SPICLK. Polarity = 1
Phase = 1
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 0 Phase = 0
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 0 Phase = 1
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 1 Phase = 0
Delay from final SPICLK edge to master deasserting
SPISCSx\. Polarity = 1 Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5
2*P2 - 5
Minimum inactive time on SPISCSx\ pin between two transfers
when SPISCSx\ is not held using the CSHOLD feature.
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1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPICLK
5
4
6
SPIDOUT
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
SPIDIN
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPICLK
6
5
5
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
SPIDOUT
8
MI(0)
SPIDIN
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPICLK
6
SPIDOUT
SPIDIN
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPICLK
4
6
SPIDOUT
SPIDIN
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 11-34. SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPICLK
SPIDOUT
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
SPIDIN
MI(0)
SPISCSx
Figure 11-35. SPI Additional Timings for 4-Pin Master Mode with Chip Select Option
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11.12 HyperLink Peripheral
The 66AK2E0x includes HyperLink for companion device interfaces. This is a four-lane SerDes interface
designed to operate at up to 10 Gbps per lane from pin-to-pin. The interface is used to connect with
external accelerators that are manufactured using TI libraries. The HyperLink lines must be connected
with DC coupling.
The interface includes the serial station management interfaces used to send power management and
flow messages between devices. Each HyperLink interface consists of four LVCMOS inputs and four
LVCMOS outputs configured as two 2-wire input buses and two 2-wire output buses. Each 2-wire bus
includes a data signal and a clock signal.
Table 11-40. HyperLink Peripheral Timing Requirements
(see Figure 11-36, Figure 11-37 and Figure 11-38)
NO.
MIN
MAX
UNIT
FL Interface
Clock period - HYPTXFLCLK (C1)
High pulse width - HYPTXFLCLK
Low pulse width - HYPTXFLCLK
1
2
3
6
tc(HYPTXFLCLK)
tw(HYPTXFLCLKH)
tw(HYPTXFLCLKL)
5.75
0.4*C1
0.4*C1
ns
ns
ns
ns
0.6*C1
0.6*C1
Setup time - HYPTXFLDAT valid before HYPTXFLCLK
high
tsu(HYPTXFLDAT-HYPTXFLCLKH)
th(HYPTXFLCLKH-HYPTXFLDAT)
tsu(HYPTXFLDAT-HYPTXFLCLKL)
th(HYPTXFLCLKL-HYPTXFLDAT)
1
1
1
1
7
6
Hold time - HYPTXFLDAT valid after HYPTXFLCLK high
ns
ns
Setup time - HYPTXFLDAT valid before HYPTXFLCLK
low
7
Hold time - HYPTXFLDAT valid after HYPTXFLCLK low
PM Interface
ns
1
2
3
6
tc(HYPRXPMCLK)
tw(HYPRXPMCLK)
tw(HYPRXPMCLK)
Clock period - HYPRXPMCLK (C3)
High pulse width - HYPRXPMCLK
Low pulse width - HYPRXPMCLK
5.75
0.4*C3
0.4*C3
ns
ns
ns
ns
0.6*C3
0.6*C3
tsu(HYPRXPMDAT-
HYPRXPMCLKH)
Setup time - HYPRXPMDAT valid before
HYPRXPMCLK high
1
1
1
1
7
6
7
Hold time - HYPRXPMDAT valid after HYPRXPMCLK
high
ns
ns
ns
th(HYPRXPMCLKH-HYPRXPMDAT)
tsu(HYPRXPMDAT-
HYPRXPMCLKL)
Setup time - HYPRXPMDAT valid before
HYPRXPMCLK low
Hold time - HYPRXPMDAT valid after HYPRXPMCLK
low
th(HYPRXPMCLKL-HYPRXPMDAT)
Table 11-41. HyperLink Peripheral Switching Characteristics
(see Figure 11-36, Figure 11-37 and Figure 11-38)
NO.
PARAMETER
MIN
MAX
UNIT
FL Interface
1
2
3
4
tc(HYPRXFLCLK)
tw(HYPRXFLCLKH)
tw(HYPRXFLCLKL)
Clock period - HYPRXFLCLK (C2)
High pulse width - HYPRXFLCLK
Low pulse width - HYPRXFLCLK
6.4
0.4*C2
0.4*C2
ns
ns
ns
ns
0.6*C2
0.6*C2
tosu(HYPRXFLDAT-
HYPRXFLCLKH)
Setup time - HYPRXFLDAT valid before HYPRXFLCLK
high
0.25*C2-0.4
0.25*C2-0.4
5
4
5
Hold time - HYPRXFLDAT valid after HYPRXFLCLK
high
ns
ns
ns
toh(HYPRXFLCLKH-HYPRXFLDAT)
tosu(HYPRXFLDAT-
HYPRXFLCLKL)
Setup time - HYPRXFLDAT valid before HYPRXFLCLK
low
0.25*C2-0.4
0.25*C2-0.4
toh(HYPRXFLCLKL-HYPRXFLDAT) Hold time - HYPRXFLDAT valid after HYPRXFLCLK low
PM Interface
1
2
3
4
tc(HYPTXPMCLK)
tw(HYPTXPMCLK)
tw(HYPTXPMCLK)
Clock period - HYPTXPMCLK (C4)
High pulse width - HYPTXPMCLK
Low pulse width - HYPTXPMCLK
6.4
0.4*C4
0.4*C4
ns
ns
ns
ns
0.6*C4
0.6*C4
tosu(HYPTXPMDAT-
HYPTXPMCLKH)
Setup time - HYPTXPMDAT valid before HYPTXPMCLK
high
0.25*C2-0.4
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Table 11-41. HyperLink Peripheral Switching Characteristics (continued)
(see Figure 11-36, Figure 11-37 and Figure 11-38)
NO.
PARAMETER
MIN
MAX
UNIT
5
toh(HYPTXPMCLKH-
HYPTXPMDAT)
Hold time - HYPTXPMDAT valid after HYPTXPMCLK
high
ns
0.25*C2-0.4
4
5
tosu(HYPTXPMDAT-
HYPTXPMCLKL)
Setup time - HYPTXPMDAT valid before HYPTXPMCLK
low
ns
ns
0.25*C2-0.4
0.25*C2-0.4
Hold time - HYPTXPMDAT valid after HYPTXPMCLK
low
toh(HYPTXPMCLKL-HYPTXPMDAT)
1
2
3
Figure 11-36. HyperLink Station Management Clock Timing
4
5
4
5
HYPTX<xx>CLK
HYPTX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 11-37. HyperLink Station Management Transmit Timing
6
7
6
7
HYPRX<xx>CLK
HYPRX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 11-38. HyperLink Station Management Receive Timing
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11.13 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the device
and a UART terminal interface or other UART-based peripheral. The UART is based on the industry
standard TL16C550 asynchronous communications element which, in turn, is a functional upgrade of the
TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the
UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the SoC of excessive software
overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to
16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the SoC to be sent to the peripheral device. The SoC can read
the UART status at any time. The UART includes control capability and a processor interrupt system that
can be tailored to minimize software management of the communications link. For more information on
UART, see the KeyStone Architecture Universal Asynchronous Receiver/Transmitter (UART) User's Guide
(SPRUGP1).
Table 11-42. UART Timing Requirements
(see Figure 11-39 and Figure 11-40)
NO.
MIN
MAX UNIT
Receive Timing
4
5
5
6
6
6
tw(RXSTART)
tw(RXH)
Pulse width, receive start bit
0.96U(1)
0.96U
0.96U
0.96U
0.96U
0.96U
1.05U
1.05U
1.05U
1.05U
1.05U
1.05U
ns
ns
ns
ns
ns
ns
Pulse width, receive data/parity bit high
Pulse width, receive data/parity bit low
Pulse width, receive stop bit 1
tw(RXL)
tw(RXSTOP1)
tw(RXSTOP15)
tw(RXSTOP2)
Pulse width, receive stop bit 1.5
Pulse width, receive stop bit 2
Autoflow Timing Requirements
Delay time, CTS asserted to START bit transmit
8
td(CTSL-TX)
P(2)
5P
ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
5
5
6
4
RXD
Start
Bit 0
Bit 1
Bit N-1
Bit N
Parity
Stop
Idle
Start
Stop/Idle
Figure 11-39. UART Receive Timing Waveform
8
TXD
CTS
Bit N-1
Bit N
Stop
Start
Bit 0
Figure 11-40. UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
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Table 11-43. UART Switching Characteristics
(see Figure 11-41 and Figure 11-42)
NO.
PARAMETER
MIN
MAX
UNIT
Transmit Timing
1
2
2
3
3
3
tw(TXSTART)
tw(TXH)
Pulse width, transmit start bit
U(1)- 2
U - 2
U - 2
U - 2
U + 2
U + 2
U + 2
U + 2
ns
ns
ns
ns
ns
ns
Pulse width, transmit data/parity bit high
Pulse width, transmit data/parity bit low
Pulse width, transmit stop bit 1
tw(TXL)
tw(TXSTOP1)
tw(TXSTOP15)
tw(TXSTOP2)
Pulse width, transmit stop bit 1.5
Pulse width, transmit stop bit 2
1.5 * (U - 2) 1.5 * ('U + 2)
2 * (U - 2)
2 * ('U + 2)
Autoflow Timing Requirements
Delay time, STOP bit received to RTS deasserted
7
td(RX-RTSH)
P(2)
5P
ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/(SYSCLK1/6)
2
2
3
1
TXD
Start
Bit 0
Bit 1
Bit N-1
Bit N
Parity
Stop
Idle
Start
Stop/Idle
Figure 11-41. UART Transmit Timing Waveform
7
RXD
CTS
Bit N-1
Bit N
Stop
Start
Figure 11-42. UART RTS (Request-to-Send Output) – Autoflow Timing Waveform
11.14 PCIe Peripheral
The two-lane PCI express (PCIe) module on 66AK2E0x provides an interface between the device and
other PCIe-compliant devices. The PCIe module provides low pin-count, high-reliability, and high-speed
data transfer at rates up to 5.0 Gbps per lane on the serial links. For more information, see the KeyStone
Architecture Peripheral Component Interconnect Express (PCIe) User's Guide (SPRUGS6).
11.15 Packet Accelerator
The Packet Accelerator (PA) provides L2 to L4 classification functionalities and supports classification for
Ethernet, VLAN, MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such
as UDP ports. It maintains 8k multiple-in, multiple-out hardware queues and also provides checksum
capability as well as some QoS capabilities. The PA enables a single IP address to be used for a
multicore device and can process up to 1.5 Mpps. The Packet Accelerator is coupled with the Network
Coprocessor. For more information, see the KeyStone II Architecture Packet Accelerator 2 (PA2) for K2E
and K2L Devices User's Guide (SPRUHZ2).
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11.16 Security Accelerator
The Security Accelerator (SA) provides wire-speed processing on 1 Gbps Ethernet traffic on IPSec, SRTP,
and 3GPP Air interface security protocols. It functions on the packet level with the packet and the
associated security context being one of the above three types. The Security Accelerator is coupled with
the Network Coprocessor, and receives the packet descriptor containing the security context in the buffer
descriptor and the data to be encrypted/decrypted in the linked buffer descriptor. For more information,
see the KeyStone II Architecture Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide
(SPRUHZ1).
11.17 Network Coprocessor Gigabit Ethernet (GbE) Switch Subsystem
The gigabit Ethernet (GbE) switch subsystem provides an efficient interface between the device and the
networked community. The Ethernet Media Access Controller (EMAC) supports 10Base-T
(10 Mbits/second), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps)
in full-duplex mode, with hardware flow control and quality-of-service (QOS) support. The GbE switch
subsystem is coupled with the Network Coprocessor. For more information, see the Gigabit Ethernet
(GbE) Switch Subsystem (1 GB) User's Guide (SPRUGV9).
An address range is assigned to the 66AK2E0x. Each individual device has a 48-bit MAC address and
consumes only one unique MAC address out of the range. There are two registers to hold these values,
MACID1[31:0] (32 bits) and MACID2[15:0] (16 bits) . The bits of these registers are defined as follows:
Figure 11-43. MACID1 Register (MMR Address 0x02620110)
31
0
MACID
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 11-44. MACID1 Register Field Descriptions
Bit
Field
Description
MAC ID. Lower 32 bits.
31-0
MAC ID
Figure 11-44. MACID2 Register (MMR Address 0x02620114)
31
24
23
18
17
16
15
0
CRC
Reserved
R,+rr rrrr
FLOW
R,+z
BCAST
R,+y
MACID
R,+xxxx xxxx xxxx xxxx
R+,cccc cccc
LEGEND: R = Read only; -x = value is indeterminate
Table 11-45. MACID2 Register Field Descriptions
Bit
Field
Description
Variable
31-24
23-18
17
Reserved
Reserved
FLOW
000000
MAC Flow Control
•
•
0 = Off
1 = On
16
BCAST
MAC ID
Default m/b-cast reception
•
•
0 = Broadcast
1 = Disabled
15-0
MAC ID. Upper 16 bits.
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There is a central processor time synchronization (CPTS) submodule in the Ethernet switch module that
can be used for time synchronization. Programming this register selects the clock source for the
CPTS_RCLK. See the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide (SPRUGV9) for the
register address and other details about the time synchronization submodule. The register
CPTS_RFTCLK_SEL for reference clock selection of the time synchronization submodule is shown in
Figure 11-45.
CPTS also allows 8 HW signal inputs for timestamping. Two of these signals are connected to
TSPUSHEVT0 and TSPUSHEVT1. The other 6 are connected to internal SyncE and timer signals. See
Table 11-46 for interconnectivity. Regarding the SyncE signal, see Section 9.2.3.26 for more details on
how to control this input. Furthermore, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's
Guide (SPRUGV9) for details on how to enable HW timestamping on CPTS.
Table 11-46. CPTS Hardware Push Events
EVENT NUMBER
CONNECTION
syncE
1
2
3
4
5
6
7
8
XGE sync
Tspushevt1
Tspushevt0
Timi1
Timi0
Reserved
Reserved
Figure 11-45. RFTCLK Select Register (CPTS_RFTCLK_SEL)
31
4
3
0
Reserved
R - 0
CPTS_RFTCLK_SEL
RW - 0
Legend: R = Read only; -x, value is indeterminate
Table 11-47. RFTCLK Select Register Field Descriptions
Bit
Field
Description
Reserved. Read as 0.
31-4
3-0
Reserved
CPTS_RFTCLK_SE Reference clock select. This signal is used to control an external multiplexer that selects one of 8 clocks for
L
time sync reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN
bit is cleared to 0 in the TS_CTL register.
•
•
•
•
•
•
•
•
0000 = SYSCLK2
0001 = SYSCLK3
0010 = TIMI0
0011 = TIMI1
0100 = TSIPCLKA
1000 = TSREFCLK
1100 = TSIPCLKB
Others = Reserved
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11.18 SGMII/XFI Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY
attached to the EMAC, retrieve the negotiation results, and configure required parameters in the gigabit
Ethernet (GbE) and 10-gigabit Ethernet (10GbE) switch subsystems for correct operation. The module
allows almost transparent operation of the MDIO interface, with very little attention from the SoC. For more
information, see the Gigabit Ethernet (GbE) Switch Subsystem (1 GB) User's Guide (SPRUGV9) and the
KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide (SPRUHJ5).
Table 11-48. MDIO Timing Requirements
(see Figure 11-46)
NO.
1
MIN
400
180
180
10
MAX
UNIT
ns
tc(MDCLK)
Cycle time, MDCLK
2
tw(MDCLKH)
tw(MDCLKL)
Pulse duration, MDCLK high
Pulse duration, MDCLK low
ns
3
ns
4
tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high
ns
5
th(MDCLKH-MDIO)
tt(MDCLK)
Hold time, MDIO data input valid after MDCLK high
Transition time, MDCLK
10
ns
5
ns
1
MDCLK
2
3
4
5
MDIO
(Input)
Figure 11-46. MDIO Input Timing
Table 11-49. MDIO Switching Characteristics
(see Figure 11-47)
NO.
PARAMETER
MIN
10
MAX
UNIT
ns
6
7
8
td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO data output valid
th(MDCLKH-MDIO) Hold time, MDIO data output valid after MDCLK high
300
10
ns
td(MDCLKH-MDIO) Delay time, MDCLK high to MDIO Hi-Z
10
300
ns
1
MDCLK
7
7
6
8
MDIO
(Ouput)
Figure 11-47. MDIO Output Timing
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11.19 Ten-Gigabit Ethernet (10GbE) Switch Subsystem
The 3-port Ten Gigabit Ethernet Switch Subsystem (different from the Network Coprocessor integrated
switch) includes a standalone EMAC switch subsystem and a 2-lane SerDes macro. The 2-lane macro
enables only 2 external ports. It does not include any packet acceleration or security acceleration engine.
11.19.1 10GbE Supported Features
The key features of the 10GbE module are listed below:
•
10 Gbps EMAC switch subsystem
–
–
–
–
MDIO: Media-dependent input/output module
SGMII Interface for 10/100/1000 and 10GBASE-KR for 10G
Ethernet switch with wire-rate switching (only two external ports are supported by the SerDes)
CPTS module that supports time-stamping for IEEE1588v2 with support for eight hardware push
events and generation of compare output pulses
–
Supports XFI electrical interface
•
CPDMA
The CPDMA component provides CPPI 4.2 compatible functionality, and provides a 128-bit wide data path
to the TeraNet, enabling:
•
•
Support for 8 transmit channel and 16 receive channels
Support for reset isolation option
For more information, see the KeyStone II Architecture 10 Gigabit Ethernet Subsystem User's Guide
(SPRUHJ5).
11.20 Timers
The timers can be used to time events, count events, generate pulses, interrupt the C66x CorePacs and
ARM CorePac and send synchronization events to the EDMA3 channel controller.
11.20.1 Timers Device-Specific Information
The 66AK2E0x device has up to twenty 64-bit timers in total, but only 13 timers are used in 66AK2E05
and 12 timers are used in 66AK2E02, of which Timer0 is dedicated to the C66x CorePacs Core 0 as
watchdog timers and can also be used as general-purpose timers. Timer16 and Timer17 (66AK2E02) or
Timer16 through Timer19 (66AK2E05) are dedicated to each of the Cortex-A15 processor cores as a
watchdog timer and can also be used as general-purpose timers. The Timer8 through Timer15 can be
configured as general-purpose timers only, with each timer programmed as a 64-bit timer or as two
separate 32-bit timers.
When operating in 64-bit mode, the timer counts either module clock cycles or input (TINPLx) pulses
(rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a
software-programmable period. When operating in 32-bit mode, the timer is split into two independent 32-
bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins,
TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are
connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a
requirement that software writes to the timer before the count expires, after which the count begins again.
If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be
set by programming the Reset Type Status Register (RSTYPE) (see Section 11.5.2.6) and the type of
reset initiated can set by programming the Reset Configuration Register (RSTCFG) (see
Section 11.5.2.8). For more information, see the KeyStone Architecture Timer 64P User's Guide
SPRUGV5.
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11.20.2 Timers Electrical Timing
The tables and figures below describe the timing requirements and switching characteristics of the timers.
Table 11-50. Timer Input Timing Requirements(1)
(see Figure 11-48)
NO.
1
MIN
12C
12C
MAX UNIT
tw(TINPH)
tw(TINPL)
Pulse duration, high
Pulse duration, low
ns
ns
2
(1) C = 1/SYSCLK1 clock frequency in ns
Table 11-51. Timer Output Switching Characteristics(1)
(see Figure 11-48)
NO.
PARAMETER
MIN
12C - 3
12C - 3
MAX UNIT
3
4
tw(TOUTH)
tw(TOUTL)
Pulse duration, high
Pulse duration, low
ns
ns
(1) C = 1/SYSCLK1 clock frequency in ns.
1
2
TIMIx
4
3
TIMOx
Figure 11-48. Timer Timing
11.21 General-Purpose Input/Output (GPIO)
11.21.1 GPIO Device-Specific Information
The GPIO peripheral pins are used for general purpose input/output for the device. These pins are also
used to configure the device at boot time.
For more detailed information on device/peripheral configuration and the 66AK2E0x device pin muxing,
see Section 9.2.
These GPIO pins can also be used to generate individual core interrupts (no support of bank interrupt)
and EDMA events.
11.21.2 GPIO Peripheral Register Description
Table 11-52. GPIO Registers
Hex Address Offsets
0x0008
Acronym
BINTEN
Register Name
GPIO interrupt per bank enable register
Reserved
0x000C
-
0x0010
DIR
GPIO Direction Register
0x0014
OUT_DATA
SET_DATA
CLR_DATA
IN_DATA
SET_RIS_TRIG
CLR_RIS_TRIG
GPIO Output Data Register
GPIO Set Data Register
0x0018
0x001C
GPIO Clear Data Register
GPIO Input Data Register
GPIO Set Rising Edge Interrupt Register
GPIO Clear Rising Edge Interrupt Register
0x0020
0x0024
0x0028
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Table 11-52. GPIO Registers (continued)
Hex Address Offsets
0x002C
Acronym
Register Name
SET_FAL_TRIG
GPIO Set Falling Edge Interrupt Register
GPIO Clear Falling Edge Interrupt Register
Reserved
0x0030
CLR_FAL_TRIG
0x008C
-
-
0x0090 - 0x03FF
Reserved
11.21.3 GPIO Electrical Data/Timing
Table 11-53. GPIO Input Timing Requirements(1)
(see Figure 11-49)
NO.
MIN
12C
12C
MAX UNIT
1
2
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
ns
ns
(1) C = 1/SYSCLK1 clock frequency in ns
Table 11-54. GPIO Output Switching Characteristics(1)
(see Figure 11-49)
NO.
PARAMETER
Pulse duration, GPOx high
Pulse duration, GPOx low
MIN
36C - 8
36C - 8
MAX UNIT
3
4
tw(GPOH)
tw(GPOL)
ns
ns
(1) C = 1/SYSCLK1 clock frequency in ns
1
2
GPIx
4
3
GPOx
Figure 11-49. GPIO Timing
11.22 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the
SoC. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-
write sequence is not broken. The Semaphore module has unique interrupts to each of the CorePacs to
identify when that CorePac has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software
requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports three masters and contains 64 semaphores that can be shared within
the system.
There are two methods of accessing a semaphore resource:
•
Direct Access: A CorePac directly accesses a semaphore resource. If free, the semaphore is granted.
If not free, the semaphore is not granted.
•
Indirect Access: A CorePac indirectly accesses a semaphore resource by writing to it. Once the
resource is free, an interrupt notifies the CorePac that the resource is available.
11.23 Universal Serial Bus 3.0 (USB 3.0)
The device includes a USB 3.0 controller providing the following capabilities:
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•
Support of USB 3.0 peripheral (or device) mode at the following speeds:
–
–
–
Super Speed (SS) (5 Gbps)
High Speed (HS) (480 Mbps)
Full Speed (FS) (12 Mbps)
•
Support of USB 3.0 host mode at the following speeds:
–
–
–
–
Super Speed (SS) (5 Gbps)
High Speed (HS) (480 Mbps)
Full Speed (FS) (12 Mbps)
Low Speed (LS) (1.5 Mbps)
•
•
Integrated DMA controller with extensible Host Controller Interface (xHCI) support
Support for 14 transmit and 14 receive endpoints plus control EP0
For more information, see the KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) User's Guide
(SPRUHJ7).
11.24 TSIP Peripheral
The Telecom Serial Interface Port (TSIP) module provides a glueless interface to common telecom serial
data streams. For more information, see the KeyStone Architecture Telecom Serial Interface Port (TSIP)
User Guide (SPRUGY4).
11.24.1 TSIP Electrical Data/Timing
Table 11-55. Timing Requirements for TSIP 2x Mode(1)
(see Figure 11-50)
NO.
1
MIN
61(2)
MAX
UNIT
ns
tc(CLK)
Cycle time, CLK rising edge to next CLK rising edge
Pulse duration, CLK low
2
tw(CLKL)
0.4×tc(CLK)
0.4×tc(CLK)
ns
3
tw(CLKH)
Pulse duration, CLK high
ns
4
tt(CLK)
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
2
ns
5
tsu(FS-CLK)
th(CLK-FS)
tsu(TR-CLK)
th(CLK-TR)
td(CLKL-TX)
tdis(CLKH-TXZ)
5
5
5
5
1
2
ns
6
ns
7
ns
8
ns
9
12
10
ns
10
Disable time, CLK low to TX Hi-Z
ns
(1) Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 1b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 0. If the polarity
of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.
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1
2
3
CLKA/B
FSA/B
TR[n]
6
5
8
7
ts127-3
ts127-3
ts127-2
ts127-2
ts127-1
ts127-1
ts127-0
ts000-7
ts000-7
ts000-6
ts000-5
ts000-5
ts000-4
ts000-4
ts000-3
ts000-3
ts000-2
ts000-2
ts000-1
ts000-1
ts000-0
ts000-0
9
TX[n]
ts127-0
ts000-6
A. Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and
frame sync signals would require a RCVDATD=1 and a XMTDATD=1
Figure 11-50. TSIP 2x Timing Diagram(A)
Table 11-56. Timing Requirements for TSIP 1x Mode(1)
(see Figure 11-51)
NO.
11
12
13
14
15
16
17
18
19
20
MIN
122.1(2)
MAX
UNIT
ns
tc(CLK)
Cycle time, CLK rising edge to next CLK rising edge
Pulse duration, CLK low
tw(CLKL)
0.4×tc(CLK)
0.4×tc(CLK)
ns
tw(CLKH)
Pulse duration, CLK high
ns
tt(CLK)
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
2
ns
ns
ns
ns
ns
ns
ns
tsu(FS-CLK)
th(CLK-FS)
tsu(TR-CLK)
th(CLK-TR)
td(CLKL-TX)
tdis(CLKH-TXZ)
5
5
5
5
1
2
12
10
Disable time, CLK low to TX Hi-Z
(1) Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity
of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.
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11
12 13
CLKA/B
16
15
FSA/B
TR[n]
TX[n]
17
18
ts127-3
ts127-3
ts127-2
ts127-2
ts127-1
ts127-1
ts127-0
ts127-0
ts000-7
ts000-6
ts000-5
ts000-5
ts000-4
ts000-4
ts000-3
ts000-3
ts000-2
ts000-2
ts000-1
ts000-1
ts000-0
ts000-0
19
ts000-7
ts000-6
A. Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through
255 and 32.768 Mbps links have timeslots numbered 0 through 511. The data timing shown relative to the clock and
frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.
Figure 11-51. TSIP 1x Timing Diagram(A)
11.25 Universal Subscriber Identity Module (USIM)
The 66AK2E0x is equipped with a Universal Subscriber Identity Module (USIM) for user authentication.
The USIM is compatible with ISO, ETSI/GSM, and 3GPP standards.
The USIM is implemented for support of secure devices only. Contact your local technical sales
representative for further details.
11.26 EMIF16 Peripheral
The EMIF16 module provides an interface between the device and external memories such as NAND and
NOR flash. For more information, see the KeyStone Architecture External Memory Interface (EMIF16)
User's Guide (SPRUGZ3).
11.26.1 EMIF16 Electrical Data/Timing
Table 11-57. EMIF16 Asynchronous Memory Timing Requirements(1)
(see Figure 11-52 through Figure 11-55)
NO.
MIN
MAX
UNIT
General Timing
Pulse duration, WAIT assertion and deassertion minimum time
Setup time, WAIT asserted before WE high
Setup time, WAIT asserted before OE high
Read Timing
2
tw(WAIT)
2E
ns
ns
ns
28
14
td(WAIT-WEH)
td(WAIT-OEH)
4E + 3
4E + 3
3
3
4
5
4
5
6
EMIF read cycle time when ew = 0, meaning not in extended wait
mode
(RS+RST+RH+3) (RS+RST+RH+3)
*E-3 *E+3
ns
ns
ns
ns
ns
ns
ns
tC(CEL)
EMIF read cycle time when ew =1, meaning extended wait mode
enabled
(RS+RST+RH+3) (RS+RST+RH+3)
tC(CEL)
*E-3
*E+3
Output setup time from CE low to OE low. SS = 0, not in select strobe
mode
tosu(CEL-OEL)
toh(OEH-CEH)
tosu(CEL-OEL)
(RS+1) * E - 3
(RS+1) * E + 3
Output hold time from OE high to CE high. SS = 0, not in select strobe
mode
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E + 3
(RS+1) * E + 3
Output setup time from CE low to OE low in select strobe mode, SS =
1
Output hold time from OE high to CE high in select strobe mode, SS =
1
toh(OEH-CEH)
tosu(BAV-OEL)
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E + 3
(RS+1) * E + 3
Output setup time from BA valid to OE low
(1) E = 1/(SYSCLK1/6)
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Table 11-57. EMIF16 Asynchronous Memory Timing Requirements(1) (continued)
(see Figure 11-52 through Figure 11-55)
NO.
MIN
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E - 3
(RST+1) * E - 3
(RST+1) * E - 3
MAX
UNIT
ns
7
toh(OEH-BAIV)
tosu(AV-OEL)
toh(OEH-AIV)
tw(OEL)
Output hold time from OE high to BA invalid
Output setup time from A valid to OE low
Output hold time from OE high to A invalid
OE active time low, when ew = 0. Extended wait mode is disabled.
OE active time low, when ew = 1. Extended wait mode is enabled.
Delay time from WAIT deasserted to OE# high
Input setup time from D valid to OE high
(RH+1) * E + 3
(RS+1) * E + 3
(RH+1) * E + 3
(RST+1) * E + 3
(RST+1) * E + 3
4E + 3
8
ns
9
ns
10
10
11
12
13
ns
tw(OEL)
ns
td(WAITH-OEH)
tsu(D-OEH)
th(OEH-D)
ns
3
ns
Input hold time from OE high to D invalid
Write Timing
0.5
ns
15
15
16
17
16
17
EMIF write cycle time when ew = 0, meaning not in extended wait
mode
(WS+WST+WH+ (WS+WST+WH+
3)*E-3 3)*E+3
ns
ns
ns
ns
ns
ns
tc(CEL)
EMIF write cycle time when ew =1., meaning extended wait mode is
enabled
(WS+WST+WH+ (WS+WST+WH+
tc(CEL)
3)*E-3
3)*E+3
Output setup time from CE low to WE low. SS = 0, not in select strobe
mode
tosuCEL-WEL)
toh(WEH-CEH)
tosuCEL-WEL)
toh(WEH-CEH)
(WS+1) * E - 3
Output hold time from WE high to CE high. SS = 0, not in select strobe
mode
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
Output setup time from CE low to WE low in select strobe mode, SS =
1
Output hold time from WE high to CE high in select strobe mode, SS =
1
18
19
20
21
22
23
24
24
26
27
25
tosu(RNW-WEL)
toh(WEH-RNW)
tosu(BAV-WEL)
toh(WEH-BAIV)
tosu(AV-WEL)
toh(WEH-AIV)
tw(WEL)
Output setup time from RNW valid to WE low
Output hold time from WE high to RNW invalid
Output setup time from BA valid to WE low
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WST+1) * E - 3
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output hold time from WE high to BA invalid
Output setup time from A valid to WE low
Output hold time from WE high to A invalid
WE active time low, when ew = 0. Extended wait mode is disabled.
WE active time low, when ew = 1. Extended wait mode is enabled.
Output setup time from D valid to WE low
tw(WEL)
tosu(DV-WEL)
toh(WEH-DIV)
td(WAITH-WEH)
Output hold time from WE high to D invalid
Delay time from WAIT deasserted to WE# high
4E + 3
3
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
4
5
7
9
6
8
10
EM_OE
12
13
EM_D[15:0]
EM_WE
Figure 11-52. EMIF16 Asynchronous Memory Read Timing Diagram
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EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
16
18
20
22
17
19
21
23
24
EM_WE
26
27
EM_D[15:0]
EM_OE
Figure 11-53. EMIF16 Asynchronous Memory Write Timing Diagram
Setup
Strobe
Extended Due to EM_WAIT
Strobe
Hold
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_OE
14
11
2
2
EM_WAIT
Deasserted
Asserted
Figure 11-54. EMIF16 EM_WAIT Read Timing Diagram
Setup
Strobe
Extended Due to EM_WAIT
Strobe
Hold
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
28
25
2
2
Deasserted
EM_WAIT
Asserted
Figure 11-55. EMIF16 EM_WAIT Write Timing Diagram
11.27 Emulation Features and Capability
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The debug capabilities of KeyStone II devices include the Debug subsystem module (DEBUGSS). The
DEBUGSS module contains the ICEPick module which handles the external JTAG Test Access Port
(TAP) and multiple secondary TAPs for the various processing cores of the device. It also provides Debug
Access Port (DAP) for system wide memory access from debugger, Cross triggering, System trace,
Peripheral suspend generation, Debug port (EMUx) pin management etc. The DEBUGSS module works in
conjunction with the debug capability integrated in the processing cores (ARM and DSP subsystems) to
provide a comprehensive hardware platform for a rich debug and development experience.
11.27.1 Chip Level Features
•
•
Support for 1149.1(JTAG and Boundary scan) and 1149.6 (Boundary scan extensions).
Trace sources to DEBUG SubSystem System Trace Module (DEBUGSS STM)
–
–
–
Provides a way for hardware instrumentation and software messaging to supplement the processor
core trace mechanisms.
Hardware instrumentation support of CPTracers to support logging of bus transactions for critical
endpoints
Software messaging/instrumentation support for SoC and QMSS PDSP cores through DEBUGSS
STM.
•
Trace Sinks
–
Support for trace export (from all processor cores and DEBUGSS STM) through emulation pins.
Concurrent trace of DSP and STM traces or ARM and STM traces via EMU pins is possible.
Concurrent trace export of DSP and ARM is not possible via EMU pins.
–
Support for 32KB DEBUGSS TBR (Trace Buffer and Router) to hold system trace. The data can be
drained using EDMA to on-chip or DDR memory buffers. These intermediate buffers can
subsequently be drained through the device high speed interfaces. The DEBUGSS TBR is
dedicated to the DEBUGSS STM module. The trace draining interface used in KeyStone II for
DEBUGSS and ARMSS are based on the new CT-TBR.
•
•
Cross triggering: Provides
processor/subsystem/module to another
a
way to propagate debug (trigger) events from one
–
–
Cross triggering between multiple devices via EMU0/EMU1 pins
Cross triggering between multiple processing cores within the device like ARM/DSP Cores and
non-processor entities like ARM STM (input only), CPTracers, CT-TBRs and DEBUGSS STM (input
only)
Synchronized starting and stopping of processing cores
–
–
–
Global start of all ARM cores
Global start of all DSP cores
Global stopping of all ARM and DSP cores
•
•
Emulation mode aware peripherals (suspend features and debug access features)
Support system memory access via the DAP port (natively support 32-bit address, and it can support
36-bit address through configuration of MPAX inside MSMC). Debug access to any invalid memory
location (reserved/clock-gated/power-down) does not cause system hang.
•
Scan access to secondary TAPs of DEBUGSS is disabled in Secure devices by default. Security
override sequence is supported (requires software override sequence) to enable debug in secure
devices. In addition, Debug features of the ARM cores are blockable through the ARM debug
authentication interface in secure devices.
•
•
Support WIR (wait-in-reset) debug boot mode for Non-secure devices.
Debug functionality survives all pin resets except power-on resets (POR/RESETFULL) and test reset
(TRST).
•
PDSP Debug features like access/control through DAP, Halt mode debug and software
instrumentation.
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11.27.1.1 ARM Subsystem Features
•
Support for invasive debug like halt mode debugging (breakpoint, watchpoints) and monitor mode
debugging
•
•
•
•
Support for non-invasive debugging (program trace, performance monitoring)
Support for A15 Performance Monitoring Unit (cycle counters)
Support for per core CoreSight™ Program Trace Module (CS-PTM) with timing
Support for an integrated CoreSight System Trace Module (CS-STM) for hardware event and software
instrumentation
•
•
•
A shared timestamp counter for all ARM cores and STM is integrated in ARMSS for trace data
correlation
Support for a 16KB Trace Buffer and Router (TBR) to hold PTM/STM trace. The trace data is copied
by EDMA to external memory for draining by device high speed serial interfaces.
Support for simultaneous draining of trace stream through EMUn pins and TBR (to achieve higher
aggregate trace throughput)
•
•
•
Support for debug authentication interface to disable debug accesses in secure devices
Support for cross triggering between MPU cores, CS-STM and CT-TBR
Support for debug through warm reset
11.27.1.2 DSP Features
•
•
•
•
Support for Halt-mode debug
Support for Real-time debug
Support for Monitor mode debug
Advanced Event Triggering (AET) for data/PC watch-points, event monitoring and visibility into external
events
•
•
Support for PC/Timing/Data/Event trace.
TETB (TI Embedded Trace Buffer) of 4KB to store PC/Timing/Data/Event trace. The trace data is
copied by EDMA to external memory for draining by device high speed serial interfaces or it can be
drained through EMUx pins
•
•
•
Support for Cross triggering source/sink to other C66x CorePacs and device subsystems.
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report
For more information on the AET, see the following documents:
•
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
(SPRA753)
•
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (SPRA387)
11.27.2 ICEPick Module
The debugger is connected to the device through its external JTAG interface. The first level of debug
interface seen by the debugger is connected to the ICEPick module embedded in the DEBUGSS. ICEPick
is the chip-level TAP, responsible for providing access to the IEEE 1149.1 and IEEE1149.6 boundary scan
capabilities of the device.
The device has multiple processors, some with secondary JTAG TAPs (C66x CorePacs) and others with
an APB memory mapped interface (ARM CorePac and Coresight components).ICEPick manages the
TAPs as well as the power/reset/clock controls for the logic associated with the TAPs as well as the logic
associated with the APB ports.
ICEPick provides the following debug capabilities:
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•
•
Debug connect logic for enabling or disabling most ICEPick instructions
Dynamic TAP insertion
–
–
Serially linking up to 32 TAP controllers
Individually selecting one or more of the TAPS for scan without disrupting the instruction register
(IR) state of other TAPs
•
Power, reset and clock management
–
–
Provides the power and clock status of the domain to the debugger
Provides debugger control of the power domain of a processor.
•
•
Force the domain power and clocks on
Prohibit the domain from being clock-gated or powered down
–
–
–
–
Applies system reset
Provides wait-in-reset (WIR) boot mode
Provides global and local WIR release
Provides global and local reset block
The ICEPick module implements a connect register, which must be configured with a predefined key to
enable the full set of JTAG instructions. Once the debug connect key has been properly programmed,
ICEPick signals and subsystems emulation logic should be turned on.
11.27.2.1 ICEPick Dynamic Tap Insertion
To include more or fewer secondary TAPS in the scan chain, the debugger must use the ICEPick TAP
router to program the TAPs. At its root, ICEPick is a scan-path linker that lets the debugger selectively
choose which subsystem TAPs are accessible through the device-level debug interface. Each secondary
TAP can be dynamically included in or excluded from the scan path. From external JTAG interface point of
view, secondary TAPS that are not selected appear not to exist.
There are two types of components connected through ICEPick to the external debug interface:
•
Legacy JTAG Components — C66x implements a JTAG-compatible port and are directly interfaced
with ICEPick and individually attached to an ICEPick secondary TAP.
•
CoreSight Components — The CoreSight components are interfaced with ICEPick through the
CS_DAP module. The CS_DAP is attached to the ICEPick secondary TAP and translates JTAG
transactions into APBv3 transactions.
Table 11-58 shows the ICEPick secondary taps in the system. For more details on the test related P1500
TAPs, see the DFTSS specification.
Table 11-58. ICEPick Debug Secondary TAPs
ACCESS IN
IR SCAN SECURE
TAP #
TYPE NAME
n/a n/a
LENGTH DEVICE
DESCRIPTION
0
n/a
No
Reserved (This is an internal TAP and not exposed at the DEBUGSS
boundary)
1
JTAG C66x CorePac0
38
No
C66x CorePac0
Reserved
2
JTAG
3
JTAG
Reserved
4
JTAG
Reserved
5
JTAG
Reserved
6
JTAG
Reserved
7
JTAG
Reserved
8
JTAG
Reserved
9..13
JTAG Reserved
NA
No
Spare ports for future expansion
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Table 11-58. ICEPick Debug Secondary TAPs (continued)
ACCESS IN
IR SCAN SECURE
LENGTH DEVICE
TAP #
TYPE NAME
DESCRIPTION
14
CS
CS_DAP (APB-AP)
4
No
ARM A15 Cores (This is an internal TAP and not exposed at the
DEBUGSS boundary)
CS_DAP (AHB-AP)
PDSP Cores (This is an internal TAP and not exposed at the
DEBUGSS boundary)
For more information on ICEPick, see the KeyStone II Architecture Debug and Trace User’s Guide
(SPRUHM4).
11.28 Debug Port (EMUx)
The device also supports 34 emulation pins — EMU[33:0], which includes 19 dedicated EMU pins and 15
pins multiplexed with GPIO. These pins are shared by SoC STM trace, cross triggering, and debug boot
modes as shown in Table 11-61. The 34-pin dedicated emulation interface is also defined in the following
table.
NOTE
Note that if EMU[1:0] signals are shared for cross-triggering purposes in the board level, they
SHOULD NOT be used for trace purposes.
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11.28.1 Concurrent Use of Debug Port
The following combinations are possible concurrently:
•
•
•
•
•
•
•
Trigger 0/1
Trigger 0/1 and STM Trace (up to 4 data pins)
Trigger 0/1 and STM Trace (up to 4 data pins) and C66x Trace (up to 20 data pins)
Trigger 0/1 and STM Trace (1-4 data pins) and ARM Trace (27-24 data pins)
STM Trace (1-4 data pins) and ARM Trace (29-26 data pins)
Trigger 0/1 and ARM Trace (up to 29 data pins)
ARM Trace (up to 32 data pins)
ARM and DSP simultaneous trace is not supported.
11.28.2 Master ID for HW and SW Messages
Table 11-59 describes the master ID for the various hardware and software masters of the STM.
Table 11-59. MSTID Mapping for Hardware Instrumentation (CPTRACERS)
CLOCK
CPTRACER NAME
MSTID [7:0] DOMAIN
SID[4:0]
DESCRIPTION
CPT_MSMCx_MST, where x =
0..3
0x94-0x97
SYSCLK1/1
0x0..3
MSMC SRAM Bank 0 to MSMC SRAM Bank 3 monitors
CPT_MSMC4_MST
0xB1
SYSCLK1/1
0x4
MSMC SRAM Bank 4
CPT_MSMCx_MST, where x =
5..7
0xAE - 0xB0 SYSCLK1/1
0x5..7
MSMC SRAM Bank 5to MSMC SRAM Bank 7 monitors
CPT_DDR3_MST
0x98
SYSCLK1/1
0x8
MSMC DDR3 port monitor
CPT_L2_x_MST, where x = 0..7
CPT_TPCC0_4_MST
CPT_TPCC1_2_3_MST
CPT_INTC_MST
0x8C - 0x93 SYSCLK1/3
0x9..0x10 DSP 0 to 7 SDMA port monitors
0xA4
0xA5
0xA6
0x99
0x9A
0xA0
0x9B
0xA7
0x9C
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
SYSCLK1/3
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
EDMA 0 and EDMA 4 CFG port monitor
EDMA 1, EDMA2 and EDMA3 CFG port monitor
INTC port monitor (for INTC 0/1/2 and GIC400)
Semaphore CFG port monitors
CPT_SM_MST
CPT_QM_CFG1_MST
CPT_QM_CFG2_MST
CPT_QM_M_MST
QMSS CFG1 port monitor
QMSS CFG2 port monitor
QM_M CFG/DMA port monitor
CPT_SPI_ROM_EMIF16_MST
CPT_CFG_MST
SPI ROM EMIF16 CFG port monitor
SCR_3P_B and SCR_6P_B CFG peripheral port
monitors
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Reserved
Reserved
Reserved
Reserved
Reserved
DDR 3B port monitor (on SCR 3C)
Table 11-60. MSTID Mapping for Software Messages
CORE NAME
C66x CorePac0
Reserved
MSTID [7:0]
DESCRIPTION
0x0
0x1
0x2
0x3
0x4
0x5
C66x CorePac MDMA Master ID
Reserved
Reserved
Reserved
Reserved
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Table 11-60. MSTID Mapping for Software Messages (continued)
CORE NAME
Reserved
MSTID [7:0]
0x6
DESCRIPTION
Reserved
0x7
A15 Core0
A15 Core1
A15 Core2
A15 Core3
QMSS PDSPs
0x8
ARM Master IDs
0x9
ARM Master ID (66AK2E05 only)
ARM Master ID(66AK2E05 only)
ARM Master ID(66AK2E05 only)
0xA
0xB
0x46
All QMSS PDSPs share the same master ID. Differentiating between the 8 PDSPs is done
through the channel number used
TSIP
0x80
TSIP Master ID
11.28.3 SoC Cross-Triggering Connection
The cross-trigger lines are shared by all the subsystems implementing cross-triggering. An MPU
subsystem trigger event can therefore be propagated to any application subsystem or system trace
component. The remote subsystem or system trace component can be programmed to be sensitive to the
global SOC trigger lines to either:
•
•
•
•
•
•
Generate a processor debug request
Generate an interrupt request
Start/Stop processor trace
Start/Stop CBA transaction tracing through CPTracers
Start external logic analyzer trace
Stop external logic analyzer trace
Table 11-61. Cross-Triggering Connection
SOURCE
SINK
NAME
TRIGGERS
TRIGGERS
COMMENTS
Inside DEBUGSS
Device-to-device trigger via EMU0/1 pins
YES
NO
YES
YES
YES
YES
This is fixed (not affected by configuration)
Trigger input only for MIPI-STM in DebugSS
DEBUGSS CT-TBR
MIPI-STM
CT-TBR
YES
NO
CS-TPIU
DEBUGSS CS-TPIU
Outside DEBUGSS
DSPSS
CP_Tracers
ARM
YES
YES
YES
YES
YES
YES
ARM Cores, ARM CS-STM and ARM CT-
TBR
The following table describes the crosstrigger connection between various cross trigger sources and TI
XTRIG module.
Table 11-62. TI XTRIG Assignment
NAME
ASSIGNED XTRIG CHANNEL NUMBER
C66x CorePac0
XTRIG 0
CPTracer 0..31 (The CPTracer number refers to the SID[4:0] as shown in
Table 11-59
XTRIG 8 .. 39
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11.28.4 Peripherals-Related Debug Requirement
Table 11-63 lists all the peripherals on this device, and the status of whether or not it supports emulation
suspend or emulation request events.
The DEBUGSS supports upto 32 debug suspend sources (processor cores) and 64 debug suspend sinks
(peripherals). The assignment of processor cores is shown in and the assignment of peripherals is shown
in Table 11-63. By default the logical AND of all the processor cores is routed to the peripherals. It is
possible to select an individual core to be routed to the peripheral (For example: used in tightly coupled
peripherals like timers), a logical AND of all cores (Global peripherals) or a logical OR of all cores by
programming the DEBUGSS.DRM module.
The SOFT bit should be programmed based on whether or not an immediate pause of the peripheral
function is required or if the peripheral suspend should occur only after a particular completion point is
reached in the normal peripheral operation. The FREE bit should be programmed to enable or disable the
emulation suspend functionality.
Table 11-63. Peripherals Emulation Support
EMULATION SUSPEND SUPPORT
EMULATION
REQUEST
DEBUG
STOP-
MODE
REAL-TIME
MODE
SUPPORT
(cemudbg/emudbg)
PERIPHERAL
ASSIGNMENT
PERIPHERAL
FREE BIT
STOP BIT
Infrastructure Peripherals
EDMA_x, where
X=0/1/2/3/4
N
N
N
N
Y
Y
N
NA
20
QM_SS
Y (CPDMA
only)
Y (CPDMA
only)
Y (CPDMA
only)
Y (CPDMA
only)
CP_Tracers_X, where X =
0..32
N
N
N
N
NA
MPU_X, where X = 0..11
CP_INTC
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
N
Y
N
N
Y
Y
Y
Y
N
N
N
Y
N
NA
NA
BOOT_CFG
SEC_MGR
PSC
NA
NA
NA
NA
PLL
TIMERx, x=0, 1..7, 8..19
Semaphore
GPIO
0, 1..7, 8..19
NA
NA
Memory Controller Peripherals
DDR3
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
NA
NA
NA
MSMC
EMIF16
N
N
Serial Interfaces
I2C_X, where X = 0/1/2
SPI_X, where X = 0/1/2
UART_X, where X = 0/1
USIM
Y
N
Y
Y
N
N
N
N
Y
N
Y
Y
Y
N
Y
N
Y
Y
Y
N
21/22/23
NA
24/25
28
High Speed Serial Interfaces
Hyperlink
N
N
N
N
N
N
N
N
Y
N
PCIeSS 0..1
Reserved
26
27
NetCP (ethernet switch)
Y
Y
Y
Y
N
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Table 11-63. Peripherals Emulation Support (continued)
EMULATION SUSPEND SUPPORT
EMULATION
REQUEST
DEBUG
STOP-
MODE
REAL-TIME
MODE
SUPPORT
(cemudbg/emudbg)
PERIPHERAL
ASSIGNMENT
PERIPHERAL
FREE BIT
STOP BIT
10GbE (ethernet
switch)(1)
Y
N
Y
Y
N
29
USBSS
N
N
N
N
N
NA
(1) 10 GbE supported by 66AK2E05only.
Based on the above table the number of suspend interfaces in Keystone II devices is listed below.
Table 11-64. EMUSUSP Peripheral Summary (for EMUSUSP handshake from DEBUGSS)
INTERFACES
NUM_SUSPEND_PERIPHERALS
EMUSUSP Interfaces
54
15
EMUSUSP Realtime Interfaces
Table 11-65 summarizes the DEBUG core assignment. Emulation suspend output of all the cores are
synchronized to SYSCLK1/6 which is frequency of the slowest peripheral that uses these signals.
Table 11-65. EMUSUSP Core Summary(for EMUSUSP handshake to DEBUGSS)
Core #
0
Assignment
C66x CorePac0
8..11
12..29
30
ARM CorePac0-3
Reserved
Logical OR of Core #0..11
Logical AND of Core #0..11
31
11.28.5 Advanced Event Triggering (AET)
The device supports advanced event triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
•
Hardware program breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
•
Data watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
•
•
Counters: count the occurrence of an event or cycles for performance monitoring.
State sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
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For more information on the AET, see the following documents:
•
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
(SPRA753)
•
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (SPRA387)
11.28.6 Trace
The device supports trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug
information for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for trace advanced emulation, see the Emulation and
Trace Headers Technical Reference Manual (SPRU655).
11.28.6.1 Trace Electrical Data/Timing
Table 11-66. Trace Switching Characteristics
(see Figure 11-56)
NO.
1
PARAMETER
Pulse duration, DPn/EMUn high
tw(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
tw(DPnL) Pulse duration, DPn/EMUn low
tw(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh
MIN
2.4
1.5
2.4
1.5
MAX
UNIT
ns
tw(DPnH)
1
ns
2
ns
2
ns
3
tsko(DPn)
tskp(DPn)
tsldp_o(DPn)
Output skew time, time delay difference between DPn/EMUn pins
configured as trace
-1
1
ns
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-
high (tplh) propagation delays.
600
ps
Output slew rate DPn/EMUn
3.3
V/ns
A
TPLH
TPLH
Buffer
Inputs
Buffers
DP[n] /
EMU[n] Pins
1
2
B
B
C
A
3
C
Figure 11-56. Trace Timing
11.28.7 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the
device. The boundary scan supported allows for an asynchronous test reset (TRST) and only the five
baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device
follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes (SGMII) support the
AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain
fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant
with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit
Specification (EAI/JESD8-5).
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11.28.7.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the 66AK2E0x device includes an internal pulldown (IPD) on the TRST pin to
ensure that TRST will always be asserted upon power up and the device’s internal emulation logic will
always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments
actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high, but
expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert
TRST to initialize the device after powerup and externally drive TRST high before attempting any
emulation or boundary scan operations.
11.28.7.2 JTAG Electrical Data/Timing
Table 11-67. JTAG Test Port Timing Requirements
(see Figure 11-57)
NO.
MIN
23
9.2
9.2
2
MAX UNIT
1
tc(TCK)
Cycle time, TCK
ns
ns
ns
ns
ns
ns
ns
1a tw(TCKH)
1b tw(TCKL)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
3
3
4
4
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
2
10
10
Table 11-68. JTAG Test Port Switching Characteristics
(see Figure 11-57)
NO.
PARAMETER
MIN
MAX UNIT
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
8.24 ns
1
1a
1b
TCK
TDO
2
4
3
TDI / TMS
Figure 11-57. JTAG Test-Port Timing
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12 Mechanical Data
12.1 Thermal Data
Table 12-1 shows the thermal resistance characteristics for the PBGA - ABD 1089-pin mechanical
package.
Table 12-1. Thermal Resistance Characteristics (PBGA Package) ABD
NO.
1
°C/W
RθJC
RθJB
Junction-to-case
Junction-to-board
0.34
3.14
2
12.2 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
278
Mechanical Data
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
66AK2E02ABDA4
PREVIEW
FCBGA
ABD
1089
40
TBD
Call TI
Call TI
-40 to 100
66AK2E02ABD
@2012 TI
A1.4GHZ
66AK2E05XABD25
66AK2E05XABD4
ACTIVE
ACTIVE
FCBGA
FCBGA
ABD
ABD
1089
1089
1
Green (RoHS
& no Sb/Br)
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
0 to 85
0 to 85
66AK2E05XABD
@2012 TI
40
Green (RoHS
& no Sb/Br)
SNAGCU
66AK2E05XABD
@2012 TI
1.4GHZ
66AK2E05XABDA25
66AK2E05XABDA4
X66AK2E05XABD25
PREVIEW
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
ABD
ABD
ABD
1089
1089
1089
40
40
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 100
-40 to 100
0 to 85
66AK2E05XABD
@2012 TI
A1.25GHZ
66AK2E05XABD
@2012 TI
A1.4GHZ
X66AK2E05XABD
@2012 TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
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PACKAGE OPTION ADDENDUM
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(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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