5962-9754301QSA [TI]
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 八路总线收发器与3态输出
| 型号： | 5962-9754301QSA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总28页 (文件大小：1032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
FEATURES
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
•
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC
)
SN54LVCH245A . . . J OR W PACKAGE
SN74LVCH245A . . . DB, DGV, DW, NS,
OR PW PACKAGE
SN74LVCH245A . . . RGY PACKAGE
(TOP VIEW)
SN54LVCH245A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
20
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
V
CC
3
2
1
20 19
18
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
4
5
6
7
8
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
A1
A2
A3
A4
A5
A6
A7
A8
OE
B1
B2
B3
B4
B5
B6
B7
OE
B1
B2
B3
B4
B5
B6
B7
B8
17
16
15
14
A5
A6
A7
A8
9
10 11 12 13
10
11
GND
DESCRIPTION/ORDERING INFORMATION
The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are designed for asynchronous communication between data buses. These devices transmit data
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
QFN – RGY
SOIC – DW
Reel of 1000
Tube of 25
SN74LVCH245ARGYR
SN74LVCH245ADW
SN74LVCH245ADWR
SN74LVCH245ANSR
SN74LVCH245ADBR
SN74LVCH245APW
SN74LVCH245APWR
SN74LVCH245APWT
SN74LVCH245ADGVR
SN74LVCH245AGQNR
SN74LVCH245AZQNR
SNJ54LVCH245AJ
LCH245A
LVCH245A
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SOP – NS
LVCH245A
LCH245A
SSOP – DB
–40°C to 85°C
TSSOP – PW
Reel of 2000
Reel of 250
Reel of 2000
LCH245A
TVSOP – DGV
VFBGA – GQN
VFBGA – ZQN (Pb-free)
CDIP – J
LCH245A
LCH245A
Reel of 1000
Tube of 20
Tube of 85
Tube of 55
SNJ54LVCH245AJ
SNJ54LVCH245AW
SNJ54LVCH245AFK
–55°C to 125°C
CFP – W
SNJ54LVCH245AW
SNJ54LVCH245AFK
LCCC – FK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
GQN OR ZQN PACKAGE
TERMINAL ASSIGNMENTS
(TOP VIEW)
1
2
3
4
1
2
3
4
A
B
C
D
E
A1
DIR
B2
A4
B6
A8
VCC
A2
B4
A6
B8
OE
B1
B3
B5
B7
A
B
C
D
E
A3
A5
A7
GND
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
L
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
2
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
DIR
A1
19
OE
18
B1
To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DB package(4)
DGV package(4)
DW package(4)
GQN/ZQN package(4)
NS package(4)
PW package(4)
RGY package(5)
92
58
θJA
Package thermal impedance
Storage temperature range
78
°C/W
°C
60
83
37
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
3
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
Recommended Operating Conditions(1)
SN54LVCH245A
SN74LVCH245A
UNIT
MIN
2
MAX
MIN
MAX
Operating
3.6
1.65
3.6
VCC
Supply voltage
V
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
2
0.35 × VCC
0.7
0.8
5.5
VCC
5.5
–4
VIL
Low-level input voltage
V
0.8
5.5
VI
Input voltage
0
0
0
0
0
0
V
V
High or low state
3-state
VCC
5.5
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
10
ns/V
TA
–55
125
–40
85
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVCH245A
MIN TYP(1) MAX
SN74LVCH245A
MIN TYP(1) MAX
PARAMETER
TEST CONDITIONS
VCC
UNIT
VCC
– 0.2
1.65 V to 3.6 V
2.7 V to 3.6 V
IOH = –100 µA
VCC
– 0.2
IOH = –4 mA
IOH = –8 mA
1.65 V
2.3 V
1.2
1.7
2.2
2.4
2.2
0.2
VOH
V
2.7 V
2.2
2.4
2.2
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
0.2
IOL = 4 mA
0.45
VOL
V
IOL = 8 mA
0.7
IOL = 12 mA
IOL = 24 mA
VI = 0 to 5.5 V
VI or VO = 5.5 V
VI = 0.58 V
2.7 V
0.4
0.55
±5
0.4
3 V
0.55
II
Control inputs
3.6 V
±5
µA
µA
Ioff
0
±10
25
–25
45
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
–45
75
µA
VI = 0.8 V
75
–75
±500
±15
10
VI = 2 V
–75
±500
±5
VI = 0 to 3.6 V(2)
VO = 0 V or (VCC to 5.5 V)
VI = VCC or GND
3.6 V
(3)
IOZ
2.3 V to 3.6 V
µA
µA
10
ICC
IO = 0
3.6 V
3.6 V ≤ VI ≤ 5.5 V(4)
10
10
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
2.7 V to 3.6 V
500
500
µA
Ci
Control inputs
A or B port
VI = VCC or GND
VO = VCC or GND
3.3 V
3.3 V
4
12
12
4
pF
pF
Cio
5.5
5.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current required to switch the input from one state to another.
(3) For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the
IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
(4) This applies in the disabled state only.
5
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVCH245A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
UNIT
MIN MAX
MIN MAX
tpd
ten
tdis
A or B
OE
B or A
A or B
A or B
8
9.5
8.5
1
1
1
7
8.5
7.5
ns
ns
ns
OE
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVCH245A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
MIN MAX
UNIT
MIN
MAX
MIN
MAX
MIN
1.5
1.5
1.7
MAX
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
tpd
ten
A or B
OE
B or A
A or B
A or B
7.3
9.5
8.5
6.3
8.5
7.5
1
ns
ns
ns
ns
(1)
(1)
(1)
(1)
tdis
OE
tsk(o)
(1) This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
47
2
(1)
(1)
Outputs enabled
Outputs disabled
Power dissipation capacitance
per transceiver
Cpd
f = 10 MHz
pF
(1)
(1)
(1) This information was not available at the time of publication.
6
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCES008O–JULY 1995–REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with, one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9754301Q2A
5962-9754301QRA
5962-9754301QSA
5962-9754301V2A
5962-9754301VRA
5962-9754301VSA
SN74LVCH245ADBLE
SN74LVCH245ADBR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
FK
J
20
20
20
20
20
20
20
20
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
W
FK
J
Call TI
LCCC
CDIP
CFP
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
Call TI
W
DB
DB
Call TI
Call TI
SSOP
SSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH245ADBRE4
SN74LVCH245ADBRG4
SN74LVCH245ADGVR
SN74LVCH245ADGVRE4
SN74LVCH245ADGVRG4
SN74LVCH245ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
SSOP
SSOP
TVSOP
TVSOP
TVSOP
SOIC
DB
DB
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DGV
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH245ADWE4
SN74LVCH245ADWG4
SN74LVCH245ADWR
SN74LVCH245ADWRE4
SN74LVCH245ADWRG4
SN74LVCH245AGQNR
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQN
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVCH245ANSR
SN74LVCH245ANSRE4
SN74LVCH245ANSRG4
SN74LVCH245APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
1
1
1
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH245APWE4
SN74LVCH245APWG4
SN74LVCH245APWLE
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OBSOLETE TSSOP
TBD
Call TI
Call TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2010
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LVCH245APWR
SN74LVCH245APWRE4
SN74LVCH245APWRG4
SN74LVCH245APWT
TSSOP
PW
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCH245APWTE4
SN74LVCH245APWTG4
SN74LVCH245ARGYR
SN74LVCH245ARGYRG4
SN74LVCH245AZQNR
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
ZQN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74LVCH245AZXYR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZXY
20
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SNJ54LVCH245AFK
SNJ54LVCH245AJ
SNJ54LVCH245AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
W
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2010
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVCH245A, SN54LVCH245A-SP, SN74LVCH245A :
Automotive: SN74LVCH245A-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVCH245ADBR
SSOP
DB
DGV
DW
20
20
20
20
2000
2000
2000
1000
330.0
330.0
330.0
330.0
16.4
12.4
24.4
12.4
8.2
6.9
7.5
5.6
2.5
1.6
2.7
1.6
12.0
8.0
16.0
12.0
24.0
12.0
Q1
Q1
Q1
Q1
SN74LVCH245ADGVR TVSOP
SN74LVCH245ADWR SOIC
10.8
3.3
13.0
4.3
12.0
8.0
SN74LVCH245AGQNR BGA MI
GQN
CROSTA
R JUNI
OR
SN74LVCH245AGQNR BGA MI
GQN
20
1000
330.0
12.4
3.3
4.3
1.5
8.0
12.0
Q1
CROSTA
R JUNI
OR
SN74LVCH245ANSR
SN74LVCH245APWR
SN74LVCH245APWT
SN74LVCH245ARGYR
SO
NS
PW
20
20
20
20
20
2000
2000
250
330.0
330.0
330.0
330.0
330.0
24.4
16.4
16.4
12.4
12.4
8.2
6.95
6.95
3.8
13.0
7.1
7.1
4.8
4.3
2.5
1.6
1.6
1.6
1.5
12.0
8.0
8.0
8.0
8.0
24.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
TSSOP
TSSOP
VQFN
PW
RGY
ZQN
3000
1000
SN74LVCH245AZQNR BGA MI
3.3
CROSTA
R JUNI
OR
SN74LVCH245AZQNR BGA MI
CROSTA
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
R JUNI
OR
SN74LVCH245AZXYR BGA MI
ZXY
20
2500
330.0
12.4
2.8
3.3
1.0
4.0
12.0
Q2
CROSTA
R JUNI
OR
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVCH245ADBR
SN74LVCH245ADGVR
SN74LVCH245ADWR
SSOP
TVSOP
SOIC
DB
DGV
DW
20
20
20
20
2000
2000
2000
1000
346.0
346.0
346.0
340.5
346.0
346.0
346.0
338.1
33.0
29.0
41.0
20.6
SN74LVCH245AGQNR BGA MICROSTAR
JUNIOR
GQN
SN74LVCH245AGQNR BGA MICROSTAR
JUNIOR
GQN
20
1000
346.0
346.0
29.0
SN74LVCH245ANSR
SN74LVCH245APWR
SN74LVCH245APWT
SN74LVCH245ARGYR
SO
NS
PW
20
20
20
20
20
2000
2000
250
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
41.0
33.0
33.0
29.0
29.0
TSSOP
TSSOP
VQFN
PW
RGY
ZQN
3000
1000
SN74LVCH245AZQNR BGA MICROSTAR
JUNIOR
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVCH245AZQNR BGA MICROSTAR
JUNIOR
ZQN
20
1000
340.5
338.1
20.6
SN74LVCH245AZXYR BGA MICROSTAR
JUNIOR
ZXY
20
2500
340.5
338.1
20.6
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
5962-9754302QSX
Bus Transceiver, LVC/LCX/Z Series, 8-Func, 1-Bit, True Output, CMOS, CDFP20, CERPACK-20
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