5962-9689001QXA [TI]
18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS; 18位LVTTL - TO- GTL / GTL通用总线收发器![5962-9689001QXA](http://pdffile.icpdf.com/pdf1/p00019/img/icpdf/5962-9689001_95263_icpdf.jpg)
型号: | 5962-9689001QXA |
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描述: | 18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS |
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SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
FEATURES
SN54GTL16612. . . WD PACKAGE
•
Members of Texas Instruments Widebus™
Family
SN74GTL16612. . . DGG OR DL PACKAGE
(TOP VIEW)
•
UBT™ Transceivers Combine D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enabled Modes
OEAB
LEAB
A1
GND
A2
A3
(3.3 V)
A4
CEAB
CLKAB
1
2
3
4
5
6
7
8
9
56
55
54 B1
GND
53
52
51
50
•
•
•
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
B2
B3
V
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
V
CC
(5 V)
CC
49 B4
48 B5
47 B6
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
A5
A6 10
•
•
Identical to '16601 Function
GND
A7
A8
GND
B7
B8
11
12
13
46
45
44
Ioff Supports Partial-Power-Down Mode
Operation
A9 14
A10 15
A11 16
A12 17
43 B9
•
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
42 B10
41 B11
40 B12
•
•
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
GND
GND
18
39
A13 19
A14 20
38 B13
37 B14
36 B15
Latch-Up Performance Exceeds 500 mA Per
JESD 17
A15 21
V
CC
(3.3 V) 22
A16 23
35
V
REF
34 B16
A17 24
33 B17
GND 25
A18 26
32 GND
31 B18
OEBA 27
LEBA 28
30 CLKBA
29 CEBA
DESCRIPTION/ORDERING INFORMATION
The 'GTL16612 devices are 18-bit UBT™ transceivers that provide LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for
transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The
devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at
GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced
input threshold levels, and OEC™ circuitry.
The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. VREF is the reference input voltage for the B port.
VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A
data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that
for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
–40°C to 85°C
–55°C to 125°C
PACKAGE(1)
ORDERABLE PART NUMBER
SN74GTL16612DL
TOP-SIDE MARKING
GTL16612
Tube
SSOP – DL
Tape and reel
Tape and reel
Tube
SN74GTL16612DLR
TSSOP – DGG
CFP – WD
SN74GTL16612DGGR
SNJ54GTL16612WD
GTL16612
SNJ54GTL16612WD
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE(1)
INPUTS
OUTPUT
B
MODE
Isolation
CEAB
OEAB
LEAB
CLKAB
A
X
X
X
L
X
L
H
L
L
L
L
L
L
L
X
L
X
H
L
Z
(2)
B0
Latched storage of A data
(3)
L
L
B0
X
X
L
H
H
L
X
X
↑
L
H
L
Transparent
H
L
Clocked storage of A data
Clock inhibit
L
L
↑
H
X
H
(3)
H
L
X
B0
(1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA.
(2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low
(3) Output level before the indicated steady-state input conditions were established
2
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
35
V
REF
1
OEAB
CEAB
56
55
CLKAB
2
LEAB
LEBA
28
30
29
27
3
CLKBA
CEBA
OEBA
A1
CE
54
1D
B1
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
3
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
3.3 V
4.6
7
VCC
Supply voltage range
V
V
5 V
A-port and control inputs
7
VI
Input voltage range(2)
B port and VREF
A port
4.6
7
VO
Voltage range applied to any output in the high or power-off state(2)
V
B port
4.6
128
80
A port
IO
IO
Current into any output in the low state
mA
B port
Current into any A-port output in the high state(3)
Continuous current through each VCC or GND
Input clamp current
64
mA
mA
mA
mA
±100
–50
–50
64
IIK
VI < 0
IOK
Output clamp current
VO < 0
DGG package
DL package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
56
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)(2)(3)(4)
SN54GTL16612
MIN NOM
SN74GTL16612
MIN NOM
UNIT
V
MAX
3.45
5.25
1.26
1.65
0.87
1.1
MAX
3.45
5.25
1.26
1.65
0.87
1.1
3.3 V
3.15
4.75
1.14
1.35
0.74
0.87
3.3
5
3.15
4.75
1.14
1.35
0.74
0.87
3.3
5
VCC
VTT
VREF
VI
Supply voltage
5 V
GTL
1.2
1.5
0.8
1
1.2
1.5
0.8
1
Termination
voltage
V
GTL+
GTL
Reference voltage
Input voltage
V
GTL+
B port
VTT
VTT
V
Except B port
B port
5.5
5.5
VREF + 50 mV
2
VREF + 50 mV
2
High-level
input voltage
VIH
VIL
V
Except B port
B port
VREF – 50 mV
VREF – 50 mV
Low-level
input voltage
V
Except B port
0.8
0.8
IIK
Input clamp current
–18
–18
mA
mA
High-level
output current
IOH
A port
–32
–32
A port
B port
64
40
64
40
85
Low-level
output current
IOL
TA
mA
Operating free-air temperature
–55
125
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last.
(3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT
.
4
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54GTL16612
MIN TYP(1) MAX
SN74GTL16612
MIN TYP(1) MAX
PARAMETER
VIK
TEST CONDITIONS
UNIT
VCC (3.3 V) = 3.15 V,
II = –18 mA
–1.2
–1.2
V
VCC (5 V) = 4.75 V
VCC (3.3 V) = 3.15 V to
3.45 V,
VCC (5 V) = 4.75 V to 5.25 V
VCC (3.3 V)
VCC (3.3 V)
IOH = –100 µA
– 0.2
– 0.2
VOH
A port
V
V
IOH = –8 mA
IOH = –32 mA
IOL = 100 µA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
2.4
2
2.4
2
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
0.2
0.4
0.5
0.6
0.2
0.4
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
A port
B port
0.5
VOL
0.55
VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V,
IOL = 40 mA
0.5
10
0.4
10
Control VCC (3.3 V) = 0 or 3.45 V,
inputs
VI = 5.5 V
VCC (5 V) = 0 or 5.25 V
VI = 5.5 V
1000
1
20
1
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V
A port
VI = VCC (3.3 V)
VI = 0
II
µA
–30
5
–30
5
VI = VCC (3.3 V)
VI = 0
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V
B port
–5
–5
100
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
VI = 0.8 V
1000
µA
µA
75
75
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
VI = 2 V
–75
–75
II(hold) A port
VI = 0 to VCC
(3.3 V)(2)
±500
±500
A port
IOZH
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 3 V
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.2 V
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.5 V
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.4 V
1
10
1
10
µA
µA
B port
A port
IOZL
–1
–1
B port
–10
1
–10
1
Outputs high
VCC (3.3 V) = 3.45 V,
ICC
A or B
VCC (5 V) = 5.25 V, IO = 0,
VI = VCC (3.3 V) or GND
Outputs low
5
5
mA
(3.3 V) port
Outputs disabled
Outputs high
1
1
120
120
120
120
120
120
VCC (3.3 V) = 3.45 V,
ICC
A or B
VCC (5 V) = 5.25 V, IO = 0,
VI = VCC (3.3 V) or GND
Outputs low
mA
mA
(5 V)
port
Outputs disabled
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V,
A-port or control inputs at VCC (3.3 V) or GND,
One input at 2.7 V
(3)
∆ICC
1
1
Control
inputs
Ci
VI = 3.15 V or 0
VO = 3.15 V or 0
3.5
12
12
3.5
12
pF
pF
A port
B port
18
10
Cio
5
(1) All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1)
SN54GTL16612
SN74GTL16612
UNIT
MIN
MAX
MIN
MAX
fclock
tw
Clock frequency
Pulse duration
95
95
MHz
ns
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
3.3
5.6
1.3
3.4
1.2
1
3.3
5.6
1.3
2.5
0
tsu
Setup time
ns
ns
B before LEBA↓
1
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
2.1
2.6
2.9
4.1
4.5
4.3
2
2
2.2
1.6
0.3
4
B after CLKBA↑
A after LEAB↓
th
Hold time
B after LEBA↓
3.6
0.8
1.1
CEAB after CLKAB↑
CEBA after CLKBA↑
1.1
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1)
SN54GTL16612
SN74GTL16612
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN TYP(1)
MAX
MIN TYP(1)
MAX
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
95
95
1
1
1
1
1
1
1
1
2.8
2.5
3.6
3.5
3.7
3.4
3.3
3.4
1.3
0.5
4.1
2.9
3.7
3
4.5
4.5
5.5
6
1.5
1.3
2
2.8
2.5
3.6
3.5
3.7
3.4
3.3
3.4
1.3
0.5
4.1
2.9
3.7
3
4.1
4
A
B
B
B
B
5.3
5.4
5.3
5.4
5.5
5.1
LEAB
CLKAB
OEAB
ns
ns
ns
1.9
2.3
1.9
2
5.5
5.5
5.5
5.5
tdis
2
tr
Transition time, B outputs (0.5 V to 1 V)
Transition time, B outputs (1 V to 0.5 V)
ns
ns
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
2
1
2
1
2
2
1
2
6.9
5.1
6.1
5.1
6.4
5.6
7.5
6.9
2.1
1.2
2.3
1.8
2.5
2.3
2.3
2.5
6.3
4.6
5.7
4.8
6.1
5.2
7.4
6.4
B
A
A
A
A
ns
ns
ns
ns
LEBA
CLKBA
OEBA
3.8
3.3
5
3.8
3.3
5
tdis
4.3
4.3
(1) All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
6
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1)
SN54GTL16612
SN74GTL16612
UNIT
MHz
ns
MIN
MAX
MIN
MAX
fclock
tw
Clock frequency
Pulse duration
95
95
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
3.3
5.6
1.3
3.2
1.2
1.3
2.1
2.6
2.9
4.4
4.5
4.3
2
3.3
5.6
1.3
2.3
0
tsu
Setup time
ns
ns
B before LEBA↓
1.3
2
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
2.2
1.6
0.3
4
B after CLKBA↑
A after LEAB↓
th
Hold time
B after LEBA↓
3.6
0.8
1.1
CEAB after CLKAB↑
CEBA after CLKBA↑
1.1
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
SN54GTL16612
SN74GTL16612
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN TYP(1)
MAX
MIN TYP(1)
MAX
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tr
95
95
1
1
1
1
1
1
1
1
2.8
2.5
3.6
3.5
3.7
3.4
3.4
3.3
1.5
0.8
4
4.5
4.6
5.5
6.1
5.5
5.6
5.5
5.6
1.5
1.3
2
2.8
2.5
3.6
3.5
3.7
3.4
3.4
3.3
1.5
0.8
4
4.1
4.1
5.3
5.5
5.3
5.5
5.1
5.6
A
B
B
B
B
LEAB
CLKAB
OEAB
ns
ns
ns
1.9
2.3
1.9
2
2
Transition time, B outputs (0.5 V to 1 V)
Transition time, B outputs (1 V to 0.5 V)
ns
ns
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
1.9
0.9
2
6.9
4.9
6.1
5.1
6.4
5.6
7.5
6.9
2
1.1
2.3
1.8
2.5
2.3
2.3
2.5
6.3
4.4
5.7
4.8
6.1
5.2
7.4
6.4
B
A
A
A
A
ns
ns
ns
ns
2.8
3.7
3
2.8
3.7
3
LEBA
CLKBA
OEBA
1
2
3.8
3.3
5
3.8
3.3
5
2
1
tdis
2
4.3
4.3
(1) All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
7
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K–JUNE 1994–REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V for GTL+
V
6 V
S1
TT
Open
500 Ω
From Output
Under Test
25 Ω
TEST
/t
S1
Open
6 V
GND
From Output
Under Test
Test
Point
t
t
PLH PHL
t
C = 50 pF
(see Note A)
L
/t
500 Ω
PLZ PZL
C = 30 pF
L
(see Note A)
/t
GND
PHZ PZH
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
3 V
t
w
Timing
Input
1.5 V
3 V
0 V
0 V
V
M
V
V V
M
Input
t
t
h
su
3 V
0 V
Data Input
A Port
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
(V = 1.5 V for A port and V
(1)
for B port)
M
REF
V
TT
Data Input
B Port
V
REF
V
REF
3 V
0 V
Input
(see Note B)
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PHL
PLH
V
V
TT
3 V
0 V
Output
Control
(see Note B)
Output
V
V
REF
REF
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
(1)
t
PLZ
PZL
(A port to B port)
Output
Waveform 1
S1 at 6 V
3 V
V
V
TT
Input
(see Note B)
1.5 V
V
REF
V
REF
V
OL
+ 0.3 V
(see Note C)
0 V
OL
t
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.3 V
1.5 V
Output
1.5 V
1.5 V
≈0 V
(see Note C)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
(A port)
(1)
(B port to A port)
(1)
All control inputs are TTL levels.
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9689001QXA
ACTIVE
ACTIVE
CFP
WD
56
56
1
TBD
Call TI
Level-NC-NC-NC
74GTL16612DGGRE4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74GTL16612DGGR
SN74GTL16612DL
SN74GTL16612DLR
SNJ54GTL16612WD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SSOP
SSOP
CFP
DGG
DL
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WD
1
TBD
Call TI
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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