5962-9679101QYC [TI]
DIGITAL SIGNAL PROCESSOR; 数字信号处理器
| 型号： | 5962-9679101QYC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL SIGNAL PROCESSOR |
| 文件： | 总157页 (文件大小：2877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF PACKAGE
D
Single-Chip Parallel Multiple
Instruction/Multiple Data (MIMD) Digital
Signal Processor (DSP)
(BOTTOM VIEW)
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35
D
D
More Than Two Billion RISC-Equivalent
Operations per Second
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
AP
AM
AK
AH
AF
AD
AB
Y
Master Processor (MP)
– 32-Bit Reduced Instruction Set
Computing (RISC) Processor
– IEEE-754 Floating-Point Capability
– 4K-Byte Instruction Cache
– 4K-Byte Data Cache
D
D
Four Parallel Processors (PP)
– 32-Bit Advanced DSPs
– 64-Bit Opcode Provides Many Parallel
Operations per Cycle
– 2K-Byte Instruction Cache and 8K-Byte
Data RAM per PP
V
T
R
P
N
M
L
K
J
H
G
F
E
Transfer Controller (TC)
– 64-Bit Data Transfers
– Up to 400 Megabytes per Second (MBps)
Transfer Rate
D
C
B
A
– 32-Bit Addressing
– Direct DRAM/VRAM Interface With
Dynamic Bus Sizing
HFH PACKAGE
(TOP VIEW)
– Intelligent Queuing and Cycle
Prioritization
320
1
241
240
D
Video Controller (VC)
– Provides Video Timing and Video
Random-Access Memory (VRAM)
Control
– Dual-Frame Timers for Two Simultaneous
Image-Capture and/or Display Systems
D
D
D
D
D
D
Big- or Little-Endian Operation
50K-Byte On-Chip RAM
4G-Byte Address Space
20-ns Cycle Time
161
160
80
81
3.3-V Operation
†
IEEE Standard 1149.1 Test Access Port
(JTAG)
D
Operating Temperature Range
–55°C to 125°C - M-Temperature
–40°C to 85°C - A-Temperature
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
Copyright 2002, Texas Instruments Incorporated
ꢑ ꢕ ꢠ ꢘ ꢗꢣ ꢞꢝ ꢛꢜ ꢝꢗ ꢙꢠ ꢢꢔ ꢚꢕ ꢛ ꢛꢗ ꢁꢉ ꢍꢪ ꢏꢐ ꢫ ꢪꢃꢇꢬ ꢃꢬꢭ ꢚꢢꢢ ꢠꢚ ꢘ ꢚ ꢙꢟ ꢛꢟꢘ ꢜ ꢚ ꢘ ꢟ ꢛꢟ ꢜꢛꢟ ꢣ
ꢏ
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ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ
ꢘ
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ꢞ ꢕꢢ ꢟꢜꢜ ꢗ ꢛꢥꢟ ꢘ ꢧꢔ ꢜꢟ ꢕ ꢗꢛꢟ ꢣꢤ ꢑ ꢕ ꢚꢢ ꢢ ꢗ ꢛꢥꢟ ꢘ ꢠꢘ ꢗ ꢣꢞꢝ ꢛꢜ ꢭ ꢠꢘ ꢗ ꢣꢞꢝ ꢛꢔꢗ ꢕ
ꢛ
ꢠ
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ꢨ
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ꢞ
ꢣ
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ꢛ
ꢟ
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ꢗ
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GF Pin Assignments – Numerical Listing . . . . . . . . . . . . . . . . 3
GF Pin Assignments – Alphabetical Listing . . . . . . . . . . . . . . 5
HFH Pin Assignments – Numerical Listing . . . . . . . . . . . . . . 7
HFH Pin Assignments – Alphabetical Listing . . . . . . . . . . . . 9
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
master processor (MP) architecture . . . . . . . . . . . . . . . . . . . 17
MP control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MP interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PP architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PP data-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PP address-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PP program flow control (PFC) unit registers . . . . . . . . . . . 40
PP cache architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PP-interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PP data-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PP multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PP program-flow-control unit architecture . . . . . . . . . . . . . . 46
PP address-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . 48
PP instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PP opcode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EALU operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
TC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
external memory timing examples . . . . . . . . . . . . . . . . . . . . 73
host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
absolute maximum ratings over specified temperature
ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
recommended operating conditions . . . . . . . . . . . . . . . . . . 129
electrical characteristics over recommended range of
supply voltage and specified temperature . . . . . . . . 129
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
timing parameter symbology . . . . . . . . . . . . . . . . . . . . . . . . 131
general notes on timing parameters . . . . . . . . . . . . . . . . . . 132
CLKIN timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . 132
local-bus switching characteristics over full operating
range: CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
device reset timing requirements . . . . . . . . . . . . . . . . . . . . 133
local bus timing requirements: cycle configuration
inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
local bus timing: cycle completion inputs . . . . . . . . . . . . . . 135
general output signal characteristics over operating
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
local bus timing: 2-cycle/column CAS timing . . . . . . . . . . . 141
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
XPT input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
host-interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
video interface timing: SCLK timing . . . . . . . . . . . . . . . . . . 145
video interface timing: FCLK input and video outputs . . . 146
video interface timing: external sync inputs . . . . . . . . . . . 147
emulator interface connection . . . . . . . . . . . . . . . . . . . . . . . 148
MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
description
The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations
per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations
per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer
controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly
through an on-chip crossbar that provides shared access to on-chip RAM. This performance and
programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications
applications.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Numerical Listing
PIN
PIN
PIN
PIN
NUMBER
A5
NAME
NUMBER
C21
C23
C25
C27
C29
C31
D2
NAME
NUMBER
E33
E35
F2
NAME
HSYNC0
TCK
NUMBER
L5
NAME
CT1
V
DD
V
V
SS
A7
V
W
L31
L33
L35
M2
DD
HACK
SS
A9
DBEN
V
DD
TRST
XPT1
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
B2
V
SS
V
F4
V
SS
CAREA0
SS
DD
CAS/DQM7
CAS/DQM5
F8
V
V
DD
CBLNK0/VBLNK0
RETRY
F10
F12
F14
F16
F18
F20
F22
F24
F26
F28
F32
F34
G1
V
SS
M4
V
SS
SS
DD
DD
V
DD
V
DD
M32
M34
N1
V
V
SS
D4
V
DD
PS0
V
V
RAS
DSF
D6
V
SS
V
SS
CT2
D8
AS0
N3
A8
V
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D30
D32
D34
E1
UTIME
V
DD
N5
V
SS
SS
SCLK1
V
SS
V
N31
N33
N35
P2
V
SS
SS
DD
V
DD
RESET
REQ0
V
TMS
EINT1
NC
V
V
DD
SS
DD
V
SS
V
A4
A9
B4
BS1
CAS/DQM0
FCLK1
V
P4
SS
DD
DD
B6
V
DD
V
V
P32
P34
R1
TDO
XPT0
B8
PS1
V
SS
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
C3
REQ1
CAREA1
SCLK0
G3
A2
A1
V
SS
DD
DD
DD
DD
V
DD
G5
R3
V
V
V
V
CAS/DQM6
CAS/DQM3
V
SS
G31
G33
G35
H2
EINT2
R5
V
DD
CBLNK1/VBLNK1
R31
R33
R35
T2
V
DD
VSYNC0
AS1
V
DD
CAS/DQM1
TRG/CAS
STATUS0
A3
V
SS
E3
FAULT
H4
A5
A13
V
DD
E5
V
SS
H32
H34
J1
CSYNC1/HBLNK1
TDI
T4
DDIN
E7
STATUS2
READY
BS0
T32
T34
U1
D62
FCLK0
E9
STATUS1
EMU0
V
E11
E13
E15
E17
E19
E21
E23
E25
E27
E29
E31
J3
V
V
DD
DD
CSYNC0/HBLNK0
SS
DD
DD
V
SS
J5
V
V
U3
A10
PS3
NC
V
SS
HREQ
CAS/DQM4
RL
J31
J33
J35
K2
U5
C5
STATUS3
AS2
V
SS
U31
U33
U35
V2
C7
EMU1
STATUS4
A6
D61
C9
V
SS
STATUS5
V
V
DD
C11
C13
C15
C17
C19
CT0
PS2
V
SS
K4
DD
CLKOUT
LINT4
K32
K34
L1
VSYNC1
HSYNC1
A0
V4
V
V
SS
SS
DD
V
DD
V32
V34
W1
CLKIN
EINT3
V
CAS/DQM2
V
SS
L3
A7
A11
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Numerical Listing (Continued)
PIN
PIN
PIN
PIN
NUMBER
W3
NAME
NUMBER
AG1
NAME
NUMBER
AL17
AL19
AL21
AL23
AL25
AL27
AL29
AL31
AL33
AL35
AM2
NAME
D20
NUMBER
AN29
AN31
AN33
AP4
NAME
D35
A18
A16
W5
V
V
AG3
V
SS
V
DD
V
DD
V
SS
D21
D45
SS
W31
W33
W35
Y2
AG5
D24
V
DD
A27
SS
D59
D63
A12
A19
XPT2
D56
AG31
AG33
AG35
AH2
V
SS
D29
D32
D38
AP6
V
DD
D57
A20
A30
D44
D54
AP8
D5
D8
Y4
AP10
AP12
AP14
AP16
AP18
AP20
AP22
AP24
AP26
AP28
AP30
AP32
AR5
Y32
AH4
V
SS
V
DD
Y34
AH32
AH34
AJ1
D48
D53
A24
D13
D17
AA1
V
SS
V
DD
V
DD
V
DD
V
DD
V
SS
AA3
V
DD
A31
V
DD
AA5
AJ3
AM4
V
V
D26
D34
DD
AA31
AA33
AA35
AB2
AJ5
V
V
AM6
SS
SS
AJ31
AJ33
AJ35
AK2
AM8
D2
D6
V
DD
SS
D42
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AM32
AM34
AN5
D39
D41
A14
A21
D55
D60
V
DD
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
AB4
D14
D19
V
DD
AB32
AB34
AC1
AC3
AC5
AC31
AC33
AC35
AD2
AD4
AD32
AD34
AE1
AK4
D47
D0
AK8
V
SS
V
DD
A22
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK32
AK34
AL1
D23
D25
AR7
V
DD
D7
AR9
V
V
V
SS
AR11
AR13
AR15
AR17
AR19
AR21
AR23
AR25
AR27
AR29
AR31
V
SS
SS
D31
D33
D11
D15
SS
D52
NC
V
DD
V
DD
V
SS
V
SS
V
DD
V
SS
D27
V
V
V
V
SS
SS
DD
DD
V
DD
V
SS
V
DD
V
SS
V
DD
D50
A29
D1
D30
D36
AN7
V
SS
D40
A15
A26
AN9
V
SS
AE3
AN11
AN13
AN15
AN17
AN19
AN21
AN23
AN25
AN27
D9
V
DD
D43
AE5
V
V
A23
A25
D12
SS
AE31
AE33
AE35
AF2
AL3
V
DD
SS
D51
D58
A17
A28
D46
D49
AL5
V
SS
D18
D22
AL7
D3
AL9
D4
V
DD
AF4
AL11
AL13
AL15
D10
D28
D37
AF32
AF34
V
SS
D16
V
SS
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Alphabetical Listing
PIN
PIN
PIN
PIN
NAME
A0
NUMBER
L1
NAME
NUMBER
B20
NAME
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
NUMBER
AL21
AM22
AP20
AK22
AN23
AL25
AR21
AM26
AL27
AM28
AP22
AN29
AR23
AN25
AL29
AP26
AR27
AP28
AJ33
AR31
AH32
AN31
AF32
AP32
AL33
AF34
AM34
AE33
AC33
AL35
AH34
AB32
Y34
NAME
DBEN
DDIN
NUMBER
C25
B26
A23
A31
G31
E29
T34
J35
E3
CAS/DQM1
CAS/DQM2
CAS/DQM3
CAS/DQM4
CAS/DQM5
CAS/DQM6
CAS/DQM7
A1
G5
C19
A2
G3
B16
DSF
A3
H4
E17
EINT1
EINT2
EINT3
EMU0
EMU1
FAULT
FCLK0
FCLK1
HACK
HREQ
HSYNC0
HSYNC1
LINT4
NC
A4
P2
A15
A5
T2
B14
A6
K4
A13
A7
L3
CBLNK0/VBLNK0
C31
A8
N3
CBLNK1/VBLNK1
G33
A9
P4
CLKIN
C17
B28
D22
A9
A10
A11
U3
CLKOUT
E25
W1
Y2
CSYNC0/HBLNK0
B32
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AS0
AS1
AS2
BS0
BS1
CAREA0
CAREA1
CAS/DQM0
CSYNC1/HBLNK1
H32
E15
E33
K34
E27
B2
T4
CT0
CT1
CT2
D0
C11
AB2
AE1
AG1
AF2
W3
Y4
A5
F18
AR5
D1
AN7
NC
U31
AK18
F14
B8
D2
AM8
AL7
NC
D3
PS0
AH2
AB4
AC3
AL1
AM2
AL3
AE3
AP4
AF4
AN5
AH4
AJ3
D8
D4
AL9
PS1
D5
AP8
PS2
C13
U5
D6
AM10
AR9
PS3
D7
RAS
A21
E9
D8
AP10
AN11
AL11
AR13
AN13
AP14
AM14
AR15
AL15
AP16
AN17
AM16
AL17
AL19
AN19
AM20
READY
REQ0
REQ1
RESET
RETRY
RL
D9
D16
B10
D14
D2
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E19
D28
A27
H2
SCLK0
SCLK1
STATUS0
STATUS1
STATUS2
STATUS3
STATUS4
E1
AG35
AE35
W33
J1
C7
E7
E11
B4
C5
AB34
U33
K2
C29
D26
D20
T32
W35
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
GF Pin Assignments – Alphabetical Listing (Continued)
PIN
PIN
PIN
PIN
NAME
STATUS5
TCK
NUMBER
E21
E35
H34
P32
N33
B22
L33
D10
A7
NAME
NUMBER
R31
NAME
NUMBER
AR29
A11
A19
A25
C3
NAME
NUMBER
AA35
AC5
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
R33
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDI
U1
AC31
AD4
TDO
U35
TMS
V2
AD32
AE5
TRG/CAS
TRST
V34
C9
AA3
C27
D6
AE31
AG3
UTIME
AA5
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
AA31
AA33
AC1
D12
D18
D24
D30
E5
AG33
AJ5
A17
A29
B6
AJ31
AK4
AC35
AD2
B12
B18
B24
B30
C15
C21
D4
AK10
AK14
AK20
AK26
AK32
AL5
AD34
AG5
E13
E23
E31
F4
AG31
AJ1
AJ35
AK2
F10
F16
F22
F26
F32
J3
AL13
AL23
AL31
AM6
D32
F2
AK8
AK12
AK16
AK24
AK28
AK34
AM4
AM32
AN15
AN21
AN33
AP6
F8
F12
F20
F24
F28
F34
G1
AM12
AM18
AM24
AM30
AN9
J33
L5
L31
M4
M32
N5
AN27
AR11
AR17
AR25
D34
G35
J5
N31
R1
J31
M2
AP12
AP18
AP24
AP30
AR7
R35
V4
VSYNC0
VSYNC1
W
M34
N1
K32
V32
W5
C23
N35
R3
XPT0
XPT1
XPT2
P34
W31
AA1
L35
R5
AR19
Y32
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Numerical Listing
PIN
PIN
PIN
PIN
NUMBER
1
NAME
NUMBER
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NAME
NUMBER
81
NAME
LINT4
EINT3
EINT2
EINT1
NUMBER
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
NAME
STATUS3
CAS/DQM6
V
DD
D59
2
V
SS
V
82
SS
CAS/DQM5
3
STATUS2
STATUS1
83
V
SS
D58
4
V
DD
84
5
V
DD
CAS/DQM4
CAS/DQM3
CT2
85
CBLNK1/VBLNK1
CBLNK0/VBLNK0
V
DD
6
STATUS0
AS2
86
D57
7
87
V
XPT2
SS
SS
8
AS1
CAS/DQM2
88
V
V
SS
D56
9
AS0
V
89
CSYNC1/HBLNK1
SS
CAS/DQM1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
FAULT
READY
RETRY
UTIME
BS1
90
V
V
V
V
DD
DD
V
DD
91
DD
DD
CAS/DQM0
RL
92
CSYNC0/HBLNK0
VSYNC1
D55
93
V
SS
D54
RAS
94
VSYNC0
BS0
V
SS
V
SS
V
SS
95
V
V
V
DD
D53
SS
CT1
96
SS
CT0
97
HSYNC1
V
V
SS
PS2
TRG/CAS
98
V
DD
V
DD
V
DD
SS
PS1
V
99
D52
DD
FCLK1
PS0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
DD
V
V
V
HSYNC0
TRST
TCK
D51
D50
D49
DD
RESET
DD
DD
V
SS
W
HREQ
HACK
STATUS5
TMS
V
V
SS
V
DD
DSF
TDI
SS
V
V
TDO
D48
SS
V
EMU1
XPT0
XPT1
V
DD
V
DD
V
DD
SS
SS
DBEN
REQ1
REQ0
V
DD
V
V
DDIN
V
V
D47
D46
D45
DD
SS
CLKOUT
CAREA1
DD
SS
V
SS
EMU0
V
DD
V
V
DD
V
SS
SCLK1
SS
SS
V
V
D63
D62
V
SS
V
D44
SS
DD
FCLK0
CLKIN
V
SS
D61
V
DD
V
DD
V
DD
V
V
SS
CAS/DQM7
SS
SCLK0
V
SS
D60
V
V
V
D43
D42
DD
DD
CAREA0
V
DD
DD
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Numerical Listing (Continued)
PIN
PIN
PIN
NUMBER
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
NAME
NUMBER
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NAME
NUMBER
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
NAME
NUMBER
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
NAME
D41
D20
D0
V
DD
V
DD
V
DD
V
V
V
V
V
V
SS
DD
DD
SS
DD
DD
D40
D19
A31
A15
PS3
A14
V
DD
V
DD
D18
V
SS
D39
D38
D37
A30
A29
V
SS
D17
V
SS
V
V
V
DD
SS
V
SS
D36
V
V
A13
SS
SS
A28
V
V
SS
SS
V
SS
D16
V
DD
DD
DD
SS
V
DD
V
DD
V
V
A12
D35
D34
D33
D15
D14
D13
V
DD
A27
A26
A25
A11
V
SS
A10
V
SS
D32
V
V
SS
V
SS
V
SS
V
SS
V
DD
A9
SS
V
V
D12
DD
V
DD
V
DD
V
DD
V
SS
A8
DD
D31
D30
D29
A24
V
V
DD
A7
DD
DD
DD
D11
D10
D9
V
V
V
SS
V
SS
V
SS
A6
A23
A22
V
SS
V
SS
D8
V
SS
D28
V
DD
A5
V
V
DD
A21
V
SS
A4
DD
DD
V
V
DD
V
V
SS
D27
D26
D25
D7
D6
D5
V
SS
DD
DD
DD
A20
V
V
V
DD
V
SS
D24
V
SS
V
DD
A3
V
SS
A19
V
DD
A2
V
V
D4
V
SS
DD
V
DD
D3
A18
A17
V
SS
A1
DD
D23
D22
D2
V
SS
V
SS
V
SS
A0
V
SS
D21
V
SS
D1
V
DD
STATUS4
V
SS
V
SS
A16
V
SS
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Alphabetical Listing
PIN
PIN
PIN
PIN
NAME
A0
NUMBER
317
316
296
294
292
289
286
284
280
276
275
273
314
270
267
265
264
260
256
255
254
250
247
312
246
244
308
306
303
302
300
298
9
NAME
NUMBER
50
NAME
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D4
NUMBER
181
180
177
175
174
173
170
168
167
166
234
164
161
160
159
155
152
151
150
146
143
231
142
141
139
136
134
132
129
126
124
122
230
119
117
115
114
229
226
224
NAME
DBEN
DDIN
NUMBER
68
CAS/DQM1
A1
CAS/DQM2
48
70
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
CAS/DQM3
46
DSF
66
CAS/DQM4
45
EINT1
EINT2
EINT3
EMU0
EMU1
FAULT
FCLK0
FCLK1
HACK
HREQ
HSYNC0
HSYNC1
LINT4
PS0
84
CAS/DQM5
43
83
CAS/DQM6
41
82
CAS/DQM7
38
112
107
10
CBLNK0/VBLNK0
86
CBLNK1/VBLNK1
85
CLKIN
36
76
CLKOUT
71
60
CSYNC0/HBLNK0
92
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D5
25
CSYNC1/HBLNK1
CT0
CT1
CT2
D0
89
24
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A3
17
101
97
16
47
81
241
239
223
222
218
215
214
213
211
208
206
204
237
201
199
197
196
193
191
190
189
186
182
236
20
D1
PS1
19
D10
D11
PS2
18
PS3
285
54
D12
D13
D14
D15
D16
D17
D18
D19
D2
RAS
READY
REQ0
REQ1
RESET
RETRY
RL
11
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D6
29
28
A30
A31
A4
22
12
53
A5
SCLK0
SCLK1
STATUS0
STATUS1
STATUS2
STATUS3
STATUS4
STATUS5
TCK
78
A6
74
A7
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D3
6
A8
4
A9
3
AS0
AS1
AS2
BS0
BS1
CAREA0
CAREA1
1
8
D60
D61
D62
D63
D7
319
64
7
15
103
105
14
TDI
80
72
D8
CAS/DQM0
52
D9
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
HFH Pin Assignments – Alphabetical Listing (Continued)
PIN
PIN
PIN
PIN
NAME
TDO
NUMBER
106
104
58
NAME
NUMBER
243
251
252
253
261
262
263
266
271
272
281
282
283
288
293
297
30
NAME
NUMBER
110
111
NAME
NUMBER
259
26
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TMS
TRG/CAS
TRST
116
118
123
128
133
137
138
144
145
153
154
162
163
169
171
176
183
184
185
192
198
2
268
269
27
102
13
UTIME
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
100
113
120
121
125
130
131
135
140
147
148
149
156
157
158
165
172
178
179
187
188
194
195
202
203
205
21
274
277
278
279
287
290
291
295
299
304
305
307
315
320
34
301
309
310
311
313
318
39
35
37
42
49
40
200
207
209
216
217
225
23
55
33
56
44
57
5
67
51
73
59
77
61
87
62
232
233
238
240
245
248
249
257
210
258
88
212
219
220
221
227
228
235
31
65
95
69
96
75
VSYNC0
VSYNC1
W
94
79
93
90
63
91
XPT0
XPT1
XPT2
108
109
127
98
99
242
V
SS
32
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions
TERMINAL
NAME
DESCRIPTION
LOCAL MEMORY INTERFACE
†
TYPE
Address bus. A31–A0 output the 32-bit byte address of the external memory cycle. The address can be
multiplexed for DRAM accesses.
A31–A0
O
I
Address-shift selection. AS2–AS0 determine how the column address appears on the address bus. Eight
shift values are supported, including zero.
AS2–AS0
BS1–BS0
Bus size selection. BS1–BS0 indicate the bus size of the memory or other devices being accessed,
allowing dynamic bus sizing for data buses less than 64 bits wide.
I
CT2–CT0
D63–D0
I
Cycle timing selection. CT2–CT0 signals determine the timing of the current memory access.
Data bus. D63–D0 transfer up to 64 bits of data per memory cycle into or out of the ’C80.
I/O
Data-buffer enable. DBEN drives the active-low output enables of bidirectional transceivers that can be
used to buffer input and output data on D63–D0.
DBEN
DDIN
O
O
I
Data direction indicator. DDIN indicates the direction of the data that passes through the transceivers.
When DDIN is low, the transfer is from external memory into the ’C80.
Fault. FAULT is driven low by external circuitry to inform the ’C80 that a fault has occurred on the current
memory row access.
FAULT
PS3–PS0
READY
RL
Page size indication. PS3–PS0 indicate the page size of the memory device(s) being accessed by the
current cycle. The ’C80 uses this information to determine when to begin a new row access.
I
Ready. READY indicates that the external device is ready to complete the memory cycle. READY is driven
low by external circuitry to insert wait states into a memory cycle.
I
Row latch. The high-to-low transition of RL can be used to latch the valid 32-bit byte address that is present
on A31–A0.
O
I
Retry. RETRY is driven low by external circuitry to indicate that the addressed memory is busy. The ’C80
memory cycle is rescheduled.
RETRY
Status code. At row time, STATUS5–STATUS0 indicate the type of cycle being performed. At column time,
they identify the processor and type of request that initiated the cycle.
STATUS5–STATUS0
O
User-timing selection. UTIME causes the timing of RAS and CAS/DQM7–CAS/DQM0 to be modified so
that custom memory timings can be generated. During reset, UTIME selects the endian mode in which the
’C80 operates.
UTIME
I
DRAM, VRAM, AND SDRAM CONTROL
Column-address strobes. CAS/DQM7–CAS/DQM0 drive the CAS inputs of DRAMs and VRAMs, or the
DQM input of synchronous dynamic random-access memories (SDRAMs). The eight strobes provide
byte-write access to memory.
CAS/DQM7–
CAS/DQM0
O
Special function. DSF selects special VRAM functions such as block-write, load color register, split-register
transfer, and synchronous graphics random-access memory (SGRAM) block write.
DSF
O
O
O
RAS
Row-address strobe. RAS drives the RAS inputs of DRAMs, VRAMs, and SDRAMs.
Transfer/output enable or column-address strobe. TRG/CAS is used as an output enable for DRAMs and
VRAMs, and also as a transfer enable for VRAMs. TRG/CAS also drives the CAS inputs of SDRAMs.
TRG/CAS
Write enable. W is driven low before CAS during write cycles. W controls the direction of the transfer during
VRAM transfer cycles.
W
O
†
‡
§
¶
I = input, O = output, Z = high-impedance
This pin has an internal pullup and can be left unconnected during normal operation.
This pin has an internal pulldown and can be left unconnected during normal operation.
For proper operation, all V
DD
and V
SS
pins must be connected externally.
11
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
DESCRIPTION
†
NAME
TYPE
HOST INTERFACE
Host acknowledge. The ’C80 drives HACK output low following an active HREQ to indicate that it has driven
the local memory bus signals to the high-impedance state and is relinquishing the bus. HACK is driven high
asynchronously following HREQ being detected inactive, and then the ’C80 resumes driving the bus.
HACK
HREQ
O
Host request. An external device drives HREQ low to request ownership of the local memory bus. When
HREQ is high, the ’C80 owns and drives the bus. HREQ is synchronized internally to the ’C80’s internal
clock. Also, HREQ is used at reset to determine the power-up state of the MP. If HREQ is low at the rising
edge of RESET, the MP comes up running. If HREQ is high, the MP remains halted until the first interrupt
occurrence on EINT3.
I
Internal cycle request. REQ1 and REQ0 provide a two-bit code indicating the highest-priority memory cycle
request that is being received by the TC. External logic can monitor REQ1 and REQ0 to determine if it is
necessary to relinquish the local memory bus to the ’C80.
REQ1, REQ0
O
SYSTEM CONTROL
Input clock. CLKIN generates the internal ’C80 clocks to which all processor functions (except the frame
timers) are synchronous.
CLKIN
I
Local output clock. CLKOUT provides a way to synchronize external circuitry to internal timings. All ’C80
output signals (except the VC signals) are synchronous to this clock.
CLKOUT
O
Edge-triggered interrupts. EINT1, EINT2 and EINT3 allow external devices to interrupt the master
processor (MP) on one of three interrupt levels (EINT1 is the highest priority). The interrupts are rising-edge
triggered. EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on
EINT3 causes the MP to unhalt and fetch its reset vector (the EINT3 interrupt-pending bit is not set in this
case).
EINT1, EINT2, EINT3
LINT4
I
I
Level-triggered interrupt. LINT4 provides an active-low level-triggered interrupt to the MP. Its priority falls
below that of the edge-triggered interrupts. Any interrupt request should remain low until it is recognized
by the ’C80.
Reset. RESET is driven low to reset the ’C80 (all processors). During reset, all internal registers are set
to their initial state and all outputs are driven to their inactive or high-impedance levels. During the rising
edge of RESET, the MP reset mode and the ’C80’s operating endian mode are determined by the levels
of HREQ and UTIME pins, respectively.
RESET
I
I
External packet transfer. XPT2–XPT0 are used by external devices to request a high-priority XPT by the
TC.
XPT2–XPT0
EMULATION CONTROL
Emulation pins. EMU0 and EMU1 are used to support emulation host interrupts, special functions targeted
at a single processor, and multiprocessor halt-event communications.
‡
EMU0, EMU1
I/O
I
Test clock. TCK provides the clock for the ’C80 IEEE-1149.1 logic, allowing it to be compatible with other
IEEE-1149.1 devices, controllers, and test equipment designed for different clock rates.
‡
TCK
‡
TDI
I
O
I
Test data input. TDI provides input data for all IEEE-1149.1 instructions and data scans of the ’C80.
Test data output. TDO provides output data for all IEEE-1149.1 instructions and data scans of the ’C80.
Test-mode select. TMS controls the IEEE-1149.1 state machine.
TDO
TMS
‡
Test reset. TRST resets the ’C80 IEEE-1149.1 module. When low, all boundary-scan logic is disabled,
allowing normal ’C80 operation.
§
TRST
I
†
‡
§
¶
I = input, O = output, Z = high-impedance
This pin has an internal pullup and can be left unconnected during normal operation.
This pin has an internal pulldown and can be left unconnected during normal operation.
For proper operation, all V
DD
and V
SS
pins must be connected externally.
12
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
†
TYPE
VIDEO INTERFACE
Composite area. CAREA0 and CAREA1 define a special area such as an overscan boundary. This area
represents the logical OR of the internal horizontal and vertical area signals.
CAREA0, CAREA1
O
Composite blanking/vertical blanking. Each of CBLNK0/VBLNK0 and CBLNK1/VBLNK1 provides one of
two blanking functions, depending on the configuration of the CSYNC/HBLNK pin:
Composite blanking disables pixel display/capture during both horizontal and vertical retrace periods
and is enabled when CSYNC is selected for composite-sync video systems.
CBLNK0/VBLNK0,
CBLNK1/VBLNK1
O
Vertical blanking disables pixel display/capture during vertical retrace periods and is enabled when
HBLNK is selected for separate-sync video systems.
Following reset, CBLNK0/VBLNK0 and CBLNK1 / VBLNK1 are configured as CBLNK0 and CBLNK1,
respectively.
Composite sync/horizontal blanking. CSYNC0/HBLNK0 and CSYNC1/HBLNK1 can be programmed for
one of two functions:
Composite sync is for use on composite-sync video systems and can be programmed as an input,
output, or high-impedance signal. As an input, the ’C80 extracts horizontal and vertical sync information
from externally generated active-low sync pulses. As an output, the active-low composite-sync pulses
are generated from either external HSYNC and VSYNC signals or the ’C80’s internal video timers. In
the high-impedance state, the pin is neither driven nor allowed to drive circuitry.
CSYNC0/HBLNK0,
CSYNC1/HBLNK1
I/O/Z
Horizontal blank disables pixel display/capture during horizontal retrace periods in separate-sync
video systems and can be used as an output only.
Immediately following reset, CSYNC0/HBLNK0 and CSYNC1/HBLNK1 are configured as
high-impedance CSYNC0 and CSYNC1, respectively.
Frame clock. FCLK0 and FCLK1 are derived from the external video system’s dotclock and are used to
drive the ’C80 video logic for frame timer 0 and frame timer 1.
FCLK0, FCLK1
I
Horizontal sync. HSYNC0 and HSYNC1 control the video system. They can be programmed as input,
output, or high impedance signals. As an input, HSYNC synchronizes the video timer to externally
generated horizontal sync pulses. As an output, HSYNC is an active-low horizontal sync pulse generated
by the ’C80 on-chip frame timer. In the high-impedance state, the pin is not driven, and no internal
synchronization is allowed to occur. Immediately following reset, HSYNC0 and HSYNC1 are in the
high-impedance state.
HSYNC0,
HSYNC1
I/O/Z
Serial data clock. SCLK0 and SCLK1 are used by the ’C80 shift register transfer (SRT) controller to track
the VRAM tap point when using midline reload. SCLK0 and SCLK1 should be the same signals that clock
the serial register on the VRAMs controlled by frame timer 0 and frame timer 1, respectively.
SCLK0, SCLK1
I
Vertical sync. VSYNC0 and VSYNC1 control the video system. They can be programmed as inputs,
outputs, or high-impedance signals. As inputs, VSYNCx synchronize the frame timer to externally
generated vertical-sync pulses. As outputs, VSYNCx are active-low vertical-sync pulses generated by the
’C80 on-chip frame timer. In the high-impedance state, the pin is not driven and no internal synchronization
is allowed to occur. Immediately following reset, VSYNCx is in the high-impedance state.
VSYNC0,
VSYNC1
I/O/Z
POWER
¶
¶
V
V
I
I
Ground. Electrical ground inputs
SS
Power. Nominal 3.3-V power supply inputs
MISCELLANEOUS
DD
NC
No connect serves as an alignment key or is for factory use and must be left unconnected.
†
‡
§
¶
I = input, O = output, Z = high-impedance
This pin has an internal pullup and can be left unconnected during normal operation.
This pin has an internal pulldown and can be left unconnected during normal operation.
For proper operation, all V
DD
and V
SS
pins must be connected externally.
13
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
architecture
Figure 1 shows the major components of the ’C80: the master processor (MP), the parallel digital signal
processors (PPs), the transfer controller (TC), and the IEEE-1149.1 emulation interface. Shared access to
on-chip RAM is achieved through the crossbar. Crossbar connections are represented by . Each PP can
perform three accesses per cycle through its local (L), global (G), and instruction (I) ports. The MP can access
two RAMs per cycle through its crossbar/data (C/D) and instruction (I) ports, and the TC can access one RAM
through its crossbar interface. Up to nine simultaneous accesses are supported in each cycle. Addresses can
be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention
between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In
addition to the crossbar, a 32-bit data path exists between the MP and the TC and VC. This allows the MP to
access TC control registers that are memory-mapped into the MP memory space.
The ’C80 has a 4G-byte address space as shown in Figure 2. The lower 32M bytes are used to address internal
RAM and memory-mapped registers.
14
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
architecture (continued)
ADSP3
ADSP2
G
ADSP1
G
ADSP0
G
MP
VC
OCR
L
G
I
L
I
L
I
L
I
C/D
I
32
64
32
64
32
64
32
64
32
32
32
32
32
IEEE-
1149.1
(JTAG)
32
64
64
64
TC
L
G
I
Local port
Global port
Instruction port
C/D Crossbar/data port
Figure 1. Block Diagram Showing Data Paths
15
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
architecture (continued)
0xFFFFFFFF
0x010037FF
ADSP3 Parameter RAM
(2K bytes)
0x01003000
0x01002FFF
Reserved
(2K bytes)
0x01002800
0x010027FF
ADSP2 Parameter RAM
(2K bytes)
External Memory
(4064M bytes)
0x01002000
0x01001FFF
Reserved
(2K bytes)
0x01001800
0x010017FF
ADSP1 Parameter RAM
(2K bytes)
0x01001000
0x01000FFF
Reserved
(2K bytes)
0x02000000
0x01FFFFFF
0x01000800
0x010007FF
Reserved
(8063K bytes)
ADSP0 Parameter RAM
(2K bytes)
0x01820400
0x018203FF
0x01000000
0x00FFFFFF
Memory-Mapped VC Registers
(512 bytes)
Reserved
(16338K bytes)
0x01820200
0x018201FF
0x0000B800
0x0000B7FF
Memory-Mapped TC Registers
(512 bytes)
ADSP3 Data RAM2
(2K bytes)
0x01820000
0x0181FFFF
0x0000B000
0x0000AFFF
Reserved
(28K bytes)
Reserved
(2K bytes)
0x01819000
0x01818FFF
0x0000A800
0x0000A7FF
MP Instruction Cache
(4K bytes)
ADSP2 Data RAM2
(2K bytes)
0x01818000
0x01817FFF
0x0000A000
0x00009FFF
Reserved
(28K bytes)
Reserved
(2K bytes)
0x01811000
0x01810FFF
0x00009800
0x000097FF
MP Data Cache
(4K bytes)
ADSP1 Data RAM2
(2K bytes)
0x01810000
0x0180FFFF
0x00009000
0x00008FFF
Reserved
(32K bytes)
Reserved
(2K bytes)
0x01808000
0x01807FFF
0x00008800
0x000087FF
ADSP3 Instruction Cache
(2K bytes)
ADSP0 Data RAM2
(2K bytes)
0x01807800
0x018077FF
0x00008000
0x00007FFF
Reserved
(6K bytes)
Reserved
(16K bytes)
0x01806000
0x01805FFF
ADSP2 Instruction Cache
(2K bytes)
0x00004000
0x00003FFF
0x01805800
0x018057FF
ADSP3 Data RAM1
(2K bytes)
Reserved
(6K bytes)
0x00003800
0x000037FF
0x01804000
0x01803FFF
ADSP3 Data RAM0
(2K bytes)
ADSP1 Instruction Cache
(2K bytes)
0x00003000
0x00002FFF
0x01803800
0x018037FF
ADSP2 Data RAM1
(2K bytes)
Reserved
(6K bytes)
0x00002800
0x000027FF
0x01802000
0x01801FFF
ADSP2 Data RAM0
(2K bytes)
ADSP0 Instruction Cache
(2K bytes)
0x00002000
0x00001FFF
0x01801800
0x018017FF
ADSP1 Data RAM1
(2K bytes)
Registers
(8132K bytes)
0x00001800
0x000017FF
ADSP1 Data RAM0
(2K bytes)
0x01010800
0x010107FF
0x00001000
0x00000FFF
MP Parameter RAM
(2K bytes)
ADSP0 Data RAM1
(2K bytes)
0x01010000
0x0100FFFF
0x00000800
0x000007FF
Registers
(50K bytes)
ADSP0 Data RAM0
(2K bytes)
0x01003800
0x00000000
Figure 2. Memory Map
16
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
master processor (MP) architecture
The master processor (MP) is a 32-bit RISC processor with an integral IEEE-754 floating-point unit. The MP
is designed for effective execution of C code and is capable of performing at well over 130000 dhrystones/s.
Major tasks which the MP typically performs are:
D
D
D
Task control and user interface
Information processing and analysis
IEEE-754 floating point (including graphics transforms)
MP functional block diagram
Figure 3 shows a block diagram of the master processor. Key features of the MP include:
D
D
32-bit RISC processor
–
–
Load/store architecture
Three operand arithmetic and logical instructions
4K-byte instruction cache and 4K-byte data cache
–
–
–
Four-way set associative
Least-recently-used (LRU) information replacement
Data writeback
D
D
D
D
D
D
D
D
4K-byte noncached parameter RAM
Thirty-one 32-bit general-purpose registers
Register and accumulator scoreboard
15-bit or 32-bit immediate constants
32-bit byte addressing
Scalable timer
Leftmost-one and rightmost-one logic
IEEE-754 floating-point hardware
–
–
Four double-precision floating-point vector accumulators
Vector floating-point instructions
Floating-point operation and parallel load or store
Multiply and accumulate
D
High performance
–
–
–
50 million instructions per second (MIPS)
100 million floating-point operations per second (MFLOPS)
Over 130000 dhrystones/s
17
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP functional block diagram (continued)
Register File
(Thirty-One 32-Bit Registers)
Scoreboard
Barrel Rotator
Mask Generator
Zero Comparator
Double-Precision
Floating-Point Multiplier
(Single-Precision Core)
Integer Arithmetic and
Logic Unit (ALU)
Leftmost/Rightmost One
Timer
Double-Precision Floating-Point
Accumulators
Control Registers
Double-Precision
Floating-Point Adder
Instruction Register
Program Counters (PCs)
PC Incrementer
Emulation Logic
Endian Multiplexers
Instruction Cache
Controller
Data-Cache
Controller
Crossbar Interface
Figure 3. MP Block Diagram
MP general-purpose registers
The MP contains 31 32-bit general-purpose registers, R1–R31. Register R0 always reads as zero and writes
to it are discarded. Double-precision values are always stored in an even-odd register pair with the
higher-numbered register always holding the sign bit and exponent. The R0/R1 pair is not available for this use.
A scoreboard keeps track of which registers are awaiting loads or the result of a previous instruction and stalls
the instruction pipeline until the register contains valid data. As a recommended software convention, R1 is
typically used as a stack pointer and R31 as a return-address link register.
Figure 4 shows the MP general-purpose registers.
18
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP general-purpose registers (continued)
Zero/Discard
Not Available
R2, R3
R1
R2
R3
R4
R5
R4, R5
•
•
•
•
•
•
R30
R31
R30, R31
32-Bit Registers
64-Bit Register Pairs
Figure 4. MP General-Purpose Registers
The 32-bit registers can contain signed-integer, unsigned-integer, or single-precision floating-point values.
Signed and unsigned bytes and halfwords are sign-extended or zero-filled. Doublewords can be stored in a
64-bit even/odd register pair. Double-precision floating-point values are referenced using the even register
number or the register pair. Figure 5 through Figure 7 show the register data formats.
31
S
22
M
0
M
Single-Precision
Floating Point
E
E
E
E
E
E
E
E
M M M M M M M M M M M M M M M M M M M M M
MS
LS
31
S
0
I
Signed 32-bit
Integer
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MS
LS
31
U
0
U
Unsigned 32-Bit
Integer
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
MS
LS
S
E
M
I
Sign bit
Exponent
Value
Signed integer value
Unsigned integer value
U
MS Most significant
LS Least signficant
Figure 5. MP Register 32-Bit Data Formats
19
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP general-purpose registers (continued)
31
7
0
I
S
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
I
S
0
I
S
0
I
S
0
I
S
0
I
S
0
I
S
0
I
S
I
I
I
I
I
I
Signed Byte
Unsigned Byte
Signed Halfword
MS
LS
31
0
7
0
U
U
U
I
U
I
U
I
U
I
U
I
U
I
MS
LS
31
S
15
S
0
I
I
MS
LS
31
0
15
U
0
U
Unsigned
Halfword
U
U
U
U
U
U
U
U
U
U
U
U
U
U
MS
LS
S
I
U
Sign bit(s)
Signed byte/halfword value
Unsigned byte/halfword value
MS Most significant
LS Least signficant
Figure 6. MP Register 8-Bit and 16-Bit Data Formats
31
0
Odd Register
Most Significant 32-Bit Word
MS
31
0
Even Register
Least Significant 32-Bit Word
19
LS
31
0
S
E
E
E
E
E
E
E
E
E
E
E
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Odd Register
MS
31
M
0
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Even Register
LS
S
E
I
Sign bit(s)
Exponent
Signed byte/halfword value
Unsigned byte/halfword value
U
MS Most significant
LS Least signficant
Figure 7. MP Register 64-Bit Data Formats
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP double-precision floating-point accumulators
There are four double-precision floating-point registers (see Figure 8) to accumulate intermediate floating-point
results.
63
0
a0
a1
a2
a3
Accumulator 0
Accumulator 1
Accumulator 2
Accumulator 3
MSB
LSB
S
E
M
Sign bit
Exponent
Value
MS Most significant
LS Least signficant
Figure 8. Double-Precision Floating-Point Accumulators
MP control registers
In addition to the general-purpose registers, there are a number of control registers that are used to represent
the state of the processor. Table 1 shows the control register numbers of the accessible registers.
Table 1. Control Register Numbers
NUMBER
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
NAME
EPC
EIP
DESCRIPTION
Exception Program Counter
Exception Instruction Pointer
Configuration
NUMBER
0x0015–0x001F
0x0020
NAME
—
DESCRIPTION
Reserved
SYSSTK
SYSTMP
—
System Stack Pointer
CONFIG
—
0x0021
System Temporary Register
Reserved
Reserved
0x0022–0x002F
0x0030
INTPEN
—
Interrupt Pending Register
Reserved
MPC
Emulator Exception Program Counter
Emulator Exception Instruction Pointer
Reserved
0x0031
MIP
IE
Interrupt Enable Register
Reserved
0x0032
—
—
0x0033
ECOMCNTL
ANASTAT
—
Emulator Communication Control
Emulation Analysis Status Register
Reserved
FPST
—
Floating-Point Status
Reserved
0x0034
0x0035–0x0038
0x0039
PPERROR PP Error Register
BRK1
BRK2
—
Emulation Breakpoint 1 Register
Emulation Breakpoint 2 Register
Reserved
—
—
Reserved
Reserved
0x003A
0x003B–0x01FF
Packet-Transfer Request
Register
0x000D
PKTREQ
0x0200 – 0x020F
iCACHET
Instruction Cache Tags 0 to 15
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
TCOUNT
TSCALE
FLTOP
Current Counter Value
Counter Reload Value
Faulting Operation
Faulting Address
0x0300
0x0400–0x040F
0x0500
iCACHEL
dCACHET
dCACHEL
IN0P
Instruction Cache LRU Register
Data Cache Tags 0 to 15
Data Cache LRU Register
Vector Load Pointer 0
FLTADR
FLTTAG
FLTDTL
FLTDTH
0x4000
Faulting Tag
0x4001
IN1P
Vector Load Pointer 1
Faulting Data (low)
Faulting Data (high)
0x4002
OUTP
Vector Store Pointer
21
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP pipeline registers
The MP uses a three-stage fetch, execute, access (FEA) pipeline. The primary pipeline registers are
manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and
emulation pipeline registers are user-accessible as control registers. All pipeline registers are 32 bits.
Program Execution Mode
Normal
PC
Exception
EPC
Emulation
MPC
Program Counter
Instruction Pointer
Instruction Register
IP
EIP
MIP
IR
•
•
•
Instruction register (IR) contains the instruction being
executed.
Instruction pointer (IP) points to the instruction being
executed.
Program counter (PC) points to the instruction being
fetched.
•
•
Exception/emulator instruction pointer (EIP/MIP) points to the
instruction that would have been executed had the exception /
emulation trap not occurred.
Exception/emulator program counter (EPC/MPC) points to the
instruction to be fetched on returning from the exception/emulation
trap.
Figure 9. MP FEA Pipeline Registers
configuration (CONFIG) register (0x0002)
The CONFIG register controls or reflects the state of certain options as shown in Figure 10.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
E
R
T
H
X
Reserved
Type
Reserved
Release
Reserved
E
R
T
H
X
Endian mode; 0 = big-endian, 1 = little-endian, read only
PPData RAM round robin; 0 = fixed, 1 = variable, read/write
TC packet transfer (PT) round robin; 0 = variable, 1 = fixed, read/write
High priority MP events; 0 = disabled, 1 = enabled, read/write
Externally initiated packet transfers; 0 = disabled, 1 = enabled, read/write
Type Number of PPs in device, read only
Release SMJ320C80 version number
Figure 10. CONFIG Register
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
interrupt-enable (IE) register (0x0006)
The IE register contains enable bits for each of the interrupts/traps as shown in Figure 11. The
global-interrupt-enable (ie) bit and the appropriate individual interrupt-enable bit must be set in order for an
interrupt to occur.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
p
e
x
4
x
3
b
p
p
b
p
c
m
i
p
3
p
2
p
1
p
0
i
o
m
f
x
2
x
1
f
1
f
0
f
x
f
u
f
o
ti
fz fi
ie
pe PP error
p2 PP2 message interrupt
p1 PP1 message interrupt
p0 PP0 message interrupt
io Integer overflow
f1 Frame-timer 1 interrupt
f0 Frame-timer 0 interrupt
fx Floating-point inexact
fu Floating-point underflow
fo Floating-point overflow
x4 External interrupt 4 (LINT4)
x3 External interrupt 3 (EINT3)
bp Bad packet transfer
pb Packet transfer busy
mf Memory fault
pc Packet transfer complete
mi MP message interrupt
p3 PP3 message interrupt
x2 External interrupt 2 (EINT2)
x1 External interrupt 1 (EINT1)
ti MP timer interrupt
fz Floating-point divide-by-zero
fi Floating-point invalid
ie Global-interrupt enable
Figure 11. IE Register
interrupt-pending (INTPEN) register (0x0004)
The bits in INTPEN register show the current state of each interrupt/trap. Pending interrupts do not occur unless
the ie bit and corresponding interrupt-enable bit are set. Software must write a 1 to the appropriate INTPEN bit
to clear an interrupt. Figure 12 shows the INTPEN register locations.
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
p
e
x
4
x
3
b
p
p
b
p
c
m
i
p
3
p
2
p
1
p
0
i
o
m
f
x
2
x
1
f
1
f
0
f
x
f
u
f
o
ti
fz fi
pe PP error
p2 PP2 message interrupt
p1 PP1 message interrupt
p0 PP0 message interrupt
io Integer overflow
f1 Frame-timer 1 interrupt
f0 Frame-timer 0 interrupt
fx Floating-point inexact
fu Floating-point underflow
fo Floating-point overflow
x4 External interrupt 4 (LINT4)
x3 External interrupt 3 (EINT3)
bp Bad packet transfer
pb Packet transfer busy
mf Memory fault
pc Packet transfer complete
mi MP message interrupt
p3 PP3 message interrupt
x2 External interrupt 2 (EINT2)
x1 External interrupt 1 (EINT1)
ti MP timer interrupt
fz Floating-point divide-by-zero
fi Floating-point invalid
ie Global-interrupt enable
Figure 12. INTPEN Register
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
floating-point status (FPST) register (0x0008)
FPST contains status and control information for the floating-point unit (FPU) as shown in Figure 13. Bits 17–21
are read/write FPU control bits. Bits 22–26 are read/write accumulated status bits. All other bits show the status
of the last FPU instruction to complete and are read only.
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
a
z
a
o
a
u
a
x
ꢜ
ꢙ
f
s
ꢳ
ꢙ
e
1
e
0
dest
ai
drm
opcode
pd
rm
ꢙꢗ
i
z
o
u
x
dest Destination register value
ai Accumulated value invalid
e0 The ninth MSB of exponent
pd Destination precision
00 – single float
01 – double float 11 – unsigned int
rm Rounding mode
00 – nearest
az Accumulated divide-by-zero
ao Accumulated overflow
au Accumulated underflow
ax Accumulated inexact
sm Sequential mode select
fs Floating-point stall
vm Vector fast mode
drm Rounding mode
00 – nearest
10 – signed int
10 – positive ∞
11 – negative ∞
01 – zero
mo Int multiply overflow
i
z
o
u
x
Invalid
Divide-by-zero
Overflow
Underflow
Inexact
10 – positive ∞
11 – negative ∞
01 – zero
opcode Last opcode
e1 The tenth MSB of exponent
Figure 13. FPST Register
PP error (PPERROR) register (0x000A)
The bits in the PPERROR register reflect parallel processor errors (see Figure 14). The MP can use these when
a PP error interrupt occurs to determine the cause of the error.
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
Reserved
h
3
h
2
h
1
h
0
Reserved
PP#
i
i
i
i
Reserved
PP#
f
f
f
f
PP#
3
2
1
0
3
2
1
0
h
I
f
0
1
PPhalted
PP illegal instruction
PP fault type
icache
Direct external access (DEA)
Figure 14. PPERROR Register
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
packet-transfer request (PKTREQ) register (0x000D)
PKTREQ controls the submission and priority of packet-transfer requests as shown in Figure 15. It also
indicates that a packet transfer is currently active.
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
Reserved
I
F
S
Q
P
I
F
S
Q
P
Immediate (urgent) priority selected
High (foreground) priority selected
Suspend packet transfer
Packet transfer queued; read only
Submit packet-transfer request
Figure 15. PKTREQ Register
memory-fault registers
The five read-only memory-fault registers contain information about memory address exceptions, as shown in
Figure 16.
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
FLTOP
(0x0010)
Dest
Reserved
K
SZ
i
d
x
r
Reserved
Block
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
FLTTAG
(0x0011)
22-Bit Cache Tag Address
P
D
P
D
P
D
P
D
3
2
1
0
Sub-Block
31
0
FLTADR
(0x0012)
Faulting Address Accessed by the Instruction
Faulting Write Most-Significant-Data Word
Faulting Write Least-Significant-Data Word
FLTDTH
(0x0013)
FLTDTL
(0x0014)
Dest Destination Register Number
i
d
x
r
MP icache fault
MP dcache fault
DEA Fault
K
Kind of Operation:
00 – load
01 – unsigned load
10 – store
Modified return sequence
Block Faulting block number
11 – cache flush/clean
SZ Size of Data:
00 – 8-bit
P
D
Sub-block is present.
Dirty bit set
01 – 16-bit
10 – 32-bit
11 – 64-bit
Figure 16. Memory-Fault Registers
25
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP cache registers
The ILRU and DLRU registers track least-recently-used (LRU) information for the sixteen instruction-cache and
sixteen data-cache blocks. The ITAGxx registers contain block addresses and the present flags for each
sub-block. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each sub-block. Figure 17
shows the cache registers.
ILRU (0x0300)
DLRU (0x0500)
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
MRU NMRU NLRU LRU MRU NMRU NLRU LRU MRU NMRU NLRU LRU MRU NMRU NLRU LRU
Set 3
Set 2
Set 1
Set 0
ITAG0–ITAG15 (0x0200–0x020F)
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
22-Bit Cache Tag Address
P
P
P
P
3
2
1
0
Sub-Block
DTAG0–DTAG15 (0x0400–0x040F)
ꢃ
ꢮ
ꢃ
ꢅ
ꢄ
ꢯ
ꢄ
ꢇ
ꢄ
ꢰ
ꢄ
ꢱ
ꢄ
ꢬ
ꢄ
ꢲ
ꢄ
ꢃ
ꢄ
ꢄ
ꢄ
ꢮ
ꢄ
ꢅ
ꢮ
ꢯ
ꢮ
ꢇ
ꢮ
ꢰ
ꢮ
ꢱ
ꢮ
ꢬ
ꢮ
ꢲ
ꢮ
ꢃ
ꢮ
ꢄ
ꢮ
ꢮ
ꢮ
ꢅ
ꢯ
ꢇ
ꢰ
ꢱ
ꢬ
ꢲ
ꢃ
ꢄ
ꢮ
ꢅ
22-Bit Cache Tag Address
P
D
P
D
P
D
P
D
3
2
1
0
Sub-Block
MRU Most-recently-used
LRU Least-recently-used
NMRU Next most-recently-used
NLRU Next least-recently-used
P
D
Sub-block present
Sub-block dirty
mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set.
Figure 17. Cache Registers
26
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP cache architecture
The MP contains two four-way set-associative, 4K caches for instructions and data. Each cache is divided into
four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and
is aligned to a 256-byte address boundary. Each block is partitioned into four sub-blocks that each contain
sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one sub-block
to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19
shows how addresses map into the cache using the cache tags and address bits.
LRU in SET 0
Block 0
Block 1
Block 2
Block 3
Tag Reg 0 (Block 0)
Tag Reg 1 (Block 1)
Tag Reg 2 (Block 2)
Tag Reg 3 (Block 3)
NLRU in SET 0
NMRU in SET 0
MRU in SET 0
Set 0
LRU Stack for SET 0
LRU Least-recently-used
NLRU Next least-recently-used
NMRU Next most-recently-used
MRU Most-recently-used
Figure 18. MP Cache Architecture (x4 Sets)
32-Bit Logical Address
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
s
6
s
5
4
3
2
1
0
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
S
S
W
W
W
W
B
B
On-Chip MP 4K Cache RAMS
Bank 0
Bank 1
Set 0
Set 1
Set 2
Set 3
11 10 9
8
7
6
5
4
3
2
1 0
S
S
A A
s
s W W W W B B
Address in On-Chip
Cache Bank
T – Tag Address Bits
s – Sub-Block (within block) Select (0–3)
W – Word (within sub-block) Select (0–15)
B – Byte (within word) Select (0–3)
A – Block Select (which tag matched) (0–3)
S – Set Select Bits (0–3)
Figure 19. MP Cache Addressing
27
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP parameter RAM
The parameter RAM is a noncachable, 2K-byte, on-chip RAM that contains MP interrupt vectors, MP-requested
TC task buffers, and a general-purpose area. Figure 20 shows the parameter RAM address map.
Suspended PT Parameters
(128 Bytes)
XPTf Linked List Start Add.
XPTe Linked List Start Add.
XPTd Linked List Start Add.
XPTc Linked List Start Add.
XPTb Linked List Start Add.
XPTa Linked List Start Add.
XPT9 Linked List Start Add.
XPT8 Linked List Start Add.
XPT7 Linked List Start Add.
XPT6 Linked List Start Add.
XPT5 Linked List Start Add.
XPT4 Linked List Start Add.
XPT3 Linked List Start Add.
XPT2 Linked List Start Add.
XPT1 Linked List Start Add.
0x001010000–0x0101007F
0x001010800–0x010100DF
0x0010100E0–0x010100FB
0x0010100FC–0x010100FF
0x001010100–0x0101017F
0x001010180–0x0101021F
0x001010220–0x0101029F
0x0010102A0–0x010107FF
Reserved
(64 Bytes)
XPT Linked List Start Addresses
(60 Bytes)
MP Linked List Start Address
Off-Chip to Off-Chip PT Buffer
(128 Bytes)
0x010100E0
0x010100E4
0x010100E8
0x010100EC
0x010100F0
0x010100F4
0x010100F8
Interrupt and Trap Vectors
(160 Bytes)
XPT Off-Chip to Off-Chip PT Buffer
(128 Bytes)
General-Purpose RAM
(3472 Bytes)
Figure 20. MP Parameter RAM
28
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP interrupt vectors
Table 2 and Table 3 show the MP interrupts and traps and their vector addresses.
Table 2. Maskable Interrupts
IE BIT
(TRAP#)
VECTOR
ADDRESS
NAME
MASKABLE INTERRUPT
0
ie
fi
0x01010180
0x01010188
0x0101018C
0x01010194
0x01010198
0x0101019C
0x010101A0
0x010101A4
0x010101A8
0x010101AC
0x010101B0
0x010101B8
0x010101BC
0x010101C0
0x010101C4
0x010101C8
0x010101CC
0x010101E4
0x010101E8
0x010101EC
0x010101F0
0x010101F4
0x010101F8
0x010101FC
2
Floating-point invalid
3
fz
Floating-point divide-by-zero
Floating-point overflow
Floating-point underflow
Floating-point inexact
Reserved
5
fo
6
fu
7
fx
8
f0
9
f1
Reserved
10
11
12
14
15
16
17
18
19
25
26
27
28
29
30
31
ti
MP timer interrupt
x1
x2
mf
io
External interrupt 1 (EINT1)
External interrupt 2 (EINT2)
Memory fault
Integer overflow
p0
p1
p2
p3
mi
pc
pb
bp
x3
x4
pe
PP0 message interrupt
PP1 message interrupt
Reserved
Reserved
MP message interrupt
Packet-transfer complete
Packet-transfer busy
Bad packet transfer
External interrupt 3 (EINT3)
External interrupt 4 (LINT4)
PP error
Table 3. Nonmaskable Traps
TRAP
NUMBER
VECTOR
NAME
NONMASKABLE TRAP
ADDRESS
0x01010200
0x01010204
0x01010208
0x0101020C
0x01010210
0x01010214
0x01010218
0x0101021C
32
33
34
35
36
37
38
39
e1
e2
e3
e4
fe
Emulator trap1 (reserved)
Emulator trap2 (reserved)
Emulator trap3 (reserved)
Emulator trap4 (reserved)
Floating-point error
Reserved
er
Illegal MP instruction
Reserved
72
to
415
0x010102A0 to
0x010107FC
System- or user-defined
29
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode formats
The three basic classes of MP instruction opcodes are: short immediate, three register, and long immediate.
Figure 21 shows the opcode structure for each class of instruction.
31
31
31
27 26
27 26
27 26
22 21
15 14
0
0
0
Short
Immediate
Dest
Dest
Dest
Source 2
Source 2
Source 2
Opcode
15-Bit Immediate
22 21 20 19
13 12 11
0
5
4
4
Three
Register
1
1
Opcode
Options
Source 1
Source 1
22 21 20 19
13 12 11
1
5
Long
Immediate
1
1
Opcode
Options
32-Bit Long Immediate
Figure 21. MP Opcode Formats
MP opcode summary
Table 4 through Table 6 show the opcode formats for the MP. Table 7 summarizes the master processor
instruction set.
30
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 4. Short-Immediate Opcodes
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
illop0
trap
Dest
–
Source
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
M
M
M
M
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
Unsigned Immediate
–
–
–
–
–
–
E
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Unsigned Trap Number
Unsigned Immediate
cmnd
rdcr
–
–
Dest
Dest
–
Unsigned Control Register Number
Unsigned Control Register Number
Unsigned Control Register Number
swcr
brcr
Source
–
–
–
–
–
–
–
–
–
shift.dz
shift.dm
shift.ds
shift.ez
shift.em
shift.es
shift.iz
shift.im
and.tt
and.tf
and.ft
xor
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Source
Source
Source
Source
Source
Source
Source
Source
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Base
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
i
i
i
i
i
i
i
i
n
n
n
n
n
n
n
n
Endmask
Endmask
Rotate
Rotate
Rotate
Rotate
Rotate
Rotate
Rotate
Rotate
Endmask
Endmask
Endmask
Endmask
Endmask
Endmask
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Unsigned Immediate
Signed Offset
or.tt
and.ff
xnor
or.tf
or.ft
or.ff
ld
SZ
ld.u
Base
SZ
SZ
Signed Offset
st
Source
Base
Signed Offset
dcache
bsr
–
–
–
–
F
Source2
0
0
0
0
1
0
0
0
1
0
Signed Offset
Link
–
–
–
–
–
A
A
A
A
A
0
Signed Offset
jsr
Link
Base
Signed Offset
bbz
BITNUM
BITNUM
Cond
Dest
Source
Source
Source
Source2
Source2
Source2
Signed Offset
bbo
Signed Offset
bcnd
cmp
Signed Offset
Signed Immediate
Signed Immediate
Signed Immediate
add
Dest
U
U
sub
Dest
–
A
E
F
i
Reserved bit (code as 0)
Annul delay slot instruction if branch taken
Emulation trap bit
Clear present flags
Invert endmask
M
n
SZ
U
Modify, write modified address back to register
Rotate sense for shifting
Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword)
Unsigned form
31
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 5. Long-Immediate and Three-Register Opcodes
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
trap
cmnd
rdcr
–
–
–
–
–
–
–
E
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
M
M
M
M
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
–
–
–
–
–
i
–
–
–
–
–
n
n
n
n
n
n
n
n
–
–
–
–
–
–
–
–
–
–
D
D
D
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
IND TR
Source1
IND CR
IND CR
IND CR
Rotate
–
–
Dest
Dest
–
swcr
brcr
Source
–
–
–
–
–
–
–
–
–
shift.dz
shift.dm
shift.ds
shift.ez
shift.em
shift.es
shift.iz
shift.im
and.tt
and.tf
and.ft
xor
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Dest
Source
Source
Source
Source
Source
Source
Source
Source
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Source2
Base
Endmask
Endmask
Endmask
Endmask
Endmask
Endmask
Endmask
Endmask
i
Rotate
i
Rotate
i
Rotate
i
Rotate
i
Rotate
i
Rotate
i
Rotate
–
–
–
–
–
–
–
–
–
–
S
S
S
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Offset
or.tt
and.ff
xnor
or.tf
or.ft
or.ff
ld
SZ
ld.u
Base
SZ
SZ
Offset
st
Source
Base
Offset
dcache
bsr
–
–
–
–
F
Source2
0
0
0
0
1
0
0
0
1
0
Source
Offset
Link
–
–
–
–
–
A
A
A
A
A
0
jsr
Link
Base
Offset
bbz
BITNUM
BITNUM
Cond
Dest
Source
Source
Source
Source2
Source2
Source2
Target
bbo
Target
bcnd
cmp
Target
Source1
Source1
Source1
add
Dest
U
U
sub
Dest
–
D
E
F
i
Reserved bit (code as 0)
Direct external access bit
Emulation trap bit
Clear present flags
Invert endmask
l
M
n
S
Long immediate
Modify, write modified address back to register
Rotate sense for shifting
Scale offset by data size
Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword
SZ
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 6. Miscellaneous Instruction Opcodes
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
vadd
vsub
Mem Src/Dst
Mem Src/Dst
Mem Src/Dst
Mem Src/Dst
Mem Src/Dst
Mem Src/Dst
Mem Src/Dst
Mem Src/Dst
Dest
Source2/Dest
Source2/Dest
Source2/Dest
Dest
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
–
–
–
a
a
–
a
a
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
I
I
–
–
–
a
a
–
a
a
–
–
–
–
–
–
–
–
–
–
–
m
m
m
m
m
m
m
m
P
P
P
P
P
P
P
P
–
–
–
Z
d
d
d
–
m
m
m
m
m
m
m
m
s
s
s
–
s
s
–
–
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
Source1
vmpy
vmsub
vrnd(FP)
vrnd(Int)
vmac
vmac
fadd
I
I
Dest
I
PD
Dest
I
–
Z
Z
d
–
–
Source2
Source2
Source2
Source2
Source2
Source2
I
I
I
PD
P2
P2
P2
P2
P1
fsub
Dest
I
PD
PD
PD
PD
–
P1
P1
P1
P1
P1
P1
fmpy
Dest
I
fdiv
Dest
I
frndx
fcmp
Dest
–
–
–
–
–
–
–
I
RM
P2
Dest
Source2
I
fsqrt
Dest
–
–
–
I
PD
–
–
–
–
–
–
lmo
Dest
Source
Source
–
–
–
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
rmo
Dest
–
–
–
–
–
–
–
–
–
estop
illopF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
a
C
d
Reserved bit (code as 0)
Floating-point accumulator select
Constant operands rather than register
Destination precision for vector (0 = sp, 1 = dp)
Long immediate 32-bit data
P
Destination precision for parallel load/store (0 = single, 1 = double)
P1 Precision of source1 operand
P2 Precision of source2 operand
PD Precision of destination result
RM Rounding Mode (0 = N, 1 = Z, 2 = P, 3 = M)
l
m
Parallel memory operation specifier
S
Z
Scale offset by data size
Use 0 rather than accumulator
Mem Src/Dst Vector store or load source/dst register
Dest Destination register
33
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
MP opcode summary (continued)
Table 7. Summary of MP Opcodes
INSTRUCTION
add
DESCRIPTION
INSTRUCTION
or.ff
DESCRIPTION
Bitwise OR with 1s complement
Bitwise OR with 1s complement
Bitwise OR with 1s complement
Read control register
Signed integer add
and.tt
and.ff
and.ft
and.tf
bbo
Bitwise AND
or.ft
Bitwise AND with 1s complement
Bitwise AND with 1s complement
Bitwise AND with 1s complement
Branch bit one
or.tf
rdcr
rmo
Rightmost one
shift.dz
shift.dm
shift.ds
shift.ez
shift.em
shift.es
shift.iz
shift.im
st
Shift, disable mask, zero extend
Shift, disable mask, merge
Shift, disable mask, sign extend
Shift, enable mask, zero extend
Shift, enable mask, merge
Shift, enable mask, sign extend
Shift, invert mask, zero extend
Shift, invert mask, merge
Store register into memory
Signed integer subtract
bbz
Branch bit zero
bcnd
br
Branch conditional
Branch always
brcr
Branch control register
Branch and save return
Send command
bsr
cmnd
cmp
Integer compare
dcache
estop
fadd
Flush data cache sub-block
Emulation stop
sub
Floating-point add
swcr
Swap control register
fcmp
fdiv
Floating-point compare
Floating-point divide
trap
Trap
vadd
Vector floating-point add
Vector floating-point multiply and add to
accumulator
fmpy
frndx
fsqrt
Floating-point multiply
vmac
vmpy
vmsc
Floating-point convert/round
Floating-point square root
Vector floating-point multiply
Vector floating-point multiply and subtract
from accumulator
Vector floating-point subtract accumulator
from source
fsub
Floating-point subtract
vmsub
illop
jsr
Illegal operation
vrnd(FP)
vrnd(Int)
vsub
Vector round with floating-point input
Vector round with integer input
Vector floating-point subtract
Bitwise exclusive NOR
Jump and save return
Load signed into register
Load unsigned into register
Leftmost one
ld
ld.u
lmo
or.tt
xnor
xor
Bitwise exclusive OR
Bitwise OR
34
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP architecture
The parallel processor (PP) is a 32-bit integer DSP optimized for imaging and graphics applications. Each PP
can execute in parallel: a multiply, ALU operation, and two memory accesses within a single instruction. This
internal parallelism allows a single PP to achieve over 500 million operations per second for certain algorithms.
The PP has a three-input ALU that supports all 256 three input Boolean combinations and many combinations
of arithmetic and Boolean functions. Data-merging and bit-to-byte, bit-to-word, and bit-to-halfword translations
are supported by hardware in the input data path to the ALU. Typical tasks performed by a PP include:
D
Pixel-intensive processing
–
–
–
–
–
–
Motion estimation
Convolution
PixBLTs
Warp
Histogram
Mean square error
D
D
Domain transforms
–
–
–
Discrete Cosine Transform (DCT)
Fast Fourier Transform (FFT)
Hough
Core graphics functions
–
–
–
–
Line
Circle
Shaded fills
Fonts
D
D
Image analysis
–
–
Segmentation
Feature extraction
Bit-stream encoding/decoding
–
–
Data merging
Table look-ups
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP functional block diagram
Figure 22 shows a block diagram of a parallel processor. Key features of the PP include:
D
D
D
64-bit instruction word (supports multiple parallel operations)
Three-stage pipeline for fast instruction cycle
Numerous registers
–
–
8 data, 10 address, 6 index registers
20 other user-visible registers
D
D
Data Unit
–
–
–
–
–
–
–
–
16 x 16 integer multiplier (optional dual 8 x 8)
Splittable 3-input ALU
32-bit barrel rotator
Mask generator
Multiple status flag expander for translations to/from 1 bit-per-pixel space.
Conditional assignment of data unit results
Conditional source selection
Special processing hardware
Leftmost one/rightmost one
Leftmost bit change/rightmost bit change
Memory addressing
–
Two address units (global and local) provide up to two 32-bit accesses in parallel with data unit
operation.
–
–
–
–
–
12 addressing modes (immediate and indexed)
Byte, halfword, and word addressability
Scaled indexed addressing
Conditional assignment for loads
Conditional source selection for stores
D
D
Program flow
–
Three hardware loop controllers
Zero overhead looping/branching
Nested loops
Multiple loop endpoints
–
–
–
Instruction cache management
PC mapped to register file
Interrupts for messages and context switching
Algebraic assembly language
36
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP functional block diagram (continued)
Data Unit
ALU Data Path
Multiplier
Data Path
d0–d7
Expander
Mask Generator
Barrel Rotator
Three-Input ALU
mf and sr
Registers
Figure 22. PP Block Diagram
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP registers
The PP contains many general-purpose registers, status registers, and configuration registers. All PP registers
are 32-bit registers. Figure 23 shows the accessible registers of the PP blocks.
Data-Unit Registers
Data Registers
Multiple Flags
mf
Status
sr
d0/EALU Operation
d1
d2
d3
d4
d5
d6
d7
Address-Unit Registers
Global-Address Unit
Address Registers
Local-Address Unit
Index Flags
Address Registers
Index Flags
a8
a9
x8
x9
a0
a1
x0
x1
x2
a10
x10
a2
a11
a3
a12
a4
Stack Pointer
Same Physical
Register
a14/sp
a15 = 0
a6/sp
a7 = 0
Program Flow Control (PFC) Unit Registers
PC-Related Registers
Loop Addresses
Loop Counts
Communications
comm
pc (br, call)
ls0
ls1
ls2
le0
le1
le2
lr0
lr1
lr2
lc0
lc1
lc2
iprs
Interrupts
lntflg
ipa (read only)
ipe (read only)
inten
Cache Tags
tag0 (read only)
tag1 (read only)
tag2 (read only)
tag3 (read only)
Loop Control
lctl
Figure 23. PP Registers
38
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit registers
The data unit contains eight 32-bit general-purpose data registers (d0–d7) referred to as the D registers. The
d0 register also acts as the control register for extended ALU (EALU) operations.
d0 register
Figure 24 shows the format when d0 is used as the EALU control register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FMOD
A
EALU Function Code
C
I
S
N
E
F
T
–
–
DMS
M
R
U
DBR
FMOD Function modifiers
E
F
Explicit multiple carry-in
Expanded multiple flags
A
C
I
S
N
Arithmetic enable
EALU carry-In
Invert-carry-In
Sign extend
DMS Default multiply shift amount
M
R
Split multiply
Rounded multiply
Nonmultiple mask
DBR Default barrel rotate amount
Figure 24. d0 Format for EALU Operations
multiple flags (mf) register
The mf register records status information from each split ALU segment for multiple arithmetic operations. The
mf register can be expanded to generate a mask for the ALU. Figure 25 shows the mf register format.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Figure 25. mf Register Format
status register (sr)
The sr contains status and control bits for the PP ALU. See Figure 26.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
N
C
V
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MSS
R
Msize
Asize
N
C
V
Z
Negative status bit
Carry status bit
Overflow status bit
Zero status bit
Rotation bit
MSS mf status selection
00 – set by zero 10 – set by extended result
01 – set by sign 11 – reserved
Msize Expander data size
Asize Split ALU data size
R
Figure 26. sr Format
PP address-unit registers
address registers
The address unit contains ten 32-bit address registers which contain the base address for address
computations or which can be used for general-purpose data. The registers a0 – a4 are used for local-address
computations and registers a8–a12 are used for global-address computations.
39
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
index registers
The six 32-bit index registers contain index values for use with the address registers in address computations
or they can be used for general-purpose data. Registers x0–x3 are used by the local-address unit and registers
x8–x9 are used by the global-address unit.
stack pointer (sp)
The sp contains the address of the top of the PP’s system stack. The stack pointer is addressed as a6 by the
local-address unit and as a14 by the global-address unit. Figure 27 shows the sp register format.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Word-Aligned Address
0
0
Figure 27. sp Register Format
zero registers
The zero registers are read-as-zero address registers for the local address unit (a7) and global-address unit
(a15). Writes to the registers are ignored and can be specified when operational results are to be discarded.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28. Zero Registers
PP program flow control (PFC) unit registers
loop registers
The loop registers control three levels of zero-overhead loops. The 32-bit loop-start registers (ls0 – ls2) and
loop-end registers (le0 – le2) contain the starting and ending addresses for the loops. The loop-counter registers
(lc0 – lc2) contain the number of repetitions remaining in their associated loops. The lr0 – lr2 registers are loop
reload registers used to support nested loops. The format for the loop-control (lctl) register is shown in Figure 29.
There are also six special write-only mappings of the loop-reload registers. The lrs0 – lrs2 codes are used for
fast initialization of lsn, lrn, and lcn registers for multi-instruction loops while the lrse0 – lrse2 codes are used
for single instruction-loop fast initialization.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E
LCD2
E
LCD1
E
LCD0
E
Loop-end enable
LCDn Loop-counter designator
le2
le1
le0
000 – None
001 – lc0
010 – lc1
011 – lc2
1xx – reserved
Figure 29. lctl Register
pipeline registers
The PFC unit contains a pointer to each stage of the PP pipeline. The pc contains the program counter which
points to the instruction being fetched. The ipa points to the instruction in the address stage of the pipeline and
the ipe points to the instruction in the execute stage of the pipeline. The instruction pointer
return-from-subroutine (iprs) register contains the return address for a subroutine call.
40
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
pipeline registers (continued)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PC (29-Bit Doubleword Address)
9
8
7
6
5
4
4
4
4
3
3
3
3
2
1
0
pc
ipa
ipe
iprs
–
G
L
G – Global Interrupt Enable
L – Loop Inhibit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
9
9
8
8
8
7
7
7
6
6
6
5
5
5
2
2
1
1
0
0
32-Bit Copy of the Previous pc Register Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
32-Bit Copy of the Previous ipa Register Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
2
1
0
29-Bit Doubleword Return Address
–
–
–
Figure 30. Pipeline Registers
interrupt registers
The interrupt-enable (inten) register allows individual interrupts to be enabled and configures the interrupt flag
(intflg) register operation. The intflg register contains the interrupt flag bits. Interrupt priority increases moving
from left to right on intflg.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
inten
r
r
r
r
E
E
E
E
–
–
–
E
E
E
E
–
–
E
–
–
–
–
–
–
–
–
–
–
–
–
–
W
P
P
3
M
S
G
P
P
2
M
S
G
P
P
1
M
S
G
P
P
0
M
S
G
M
P
M
S
P
T
E
N
D
P
T
E
R
R
P
T
Q
T
A
S
K
G
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
intflg
r
r
r
r
I
I
I
I
–
–
–
I
I
I
I
–
–
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MPMSG
PTEND
PTERR
PTQ
MP message interrupt
r
E
W
Reserved (write as 0)
Enable interrupt
Write mode
0 – writing 1 clears intflg
1 – writing 1 sets intflg
Packet transfer complete
Packet-transfer error
Packet transfer queued
MP task interrupt
TASK
PPnMSG PPn message interrupt
Figure 31. PP-Interrupt Registers
41
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
communication (comm) register
The comm register contains the packet-transfer handshake bits and PP indicator bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
H
S
Q
P
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PP#
H
S
Q
P
High-priority packet transfer
Packet-transfer suspend
Packet transfer queued
PP# PP Number (read only)
000 – PP0 010 – PP2
001 – PP1 011 – PP3
1xx – Not implemented
Submit packet transfer request
Figure 32. comm Register
cache-tag registers
The tag0 – tag3 registers contain the tag address and sub-block present bits for each cache block.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
23-Bit Tag Address
P
P
P
P
–
–
–
LRU
P
Present bit
Sub-Block #
3
2
1
0
LRU Least-recently-used code
00 – Most-recently-used (MRU)
10 – next LRU
01 – next MRU (NMRU)
11 – LRU
Figure 33. Cache-Tag Registers
PP cache architecture
Each PP has its own 2K-byte instruction cache. Each cache is divided into four blocks and each block is divided
into four sub-blocks containing 16 64-bit instructions each. Cache misses cause one sub-block to be loaded
into cache. Figure 34 shows the cache architecture for one of the four sets in each cache. Figure 35 shows how
addresses map into the cache using the cache tags and address bits.
LRU
Block 0
Block 1
Block 2
Block 3
Tag 0 (Block 0)
Tag 1 (Block 1)
Tag 2 (Block 2)
Tag 3 (Block 3)
NLRU
NMRU
MRU
LRU Stack
Figure 34. PP Cache Architecture
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
23-Bit Tag Value
sub
instruction
ignored
sub – sub-block
Figure 35. PP Register Cache-Address Mapping
42
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP parameter RAM
The parameter RAM is a 2K-byte, on-chip RAM which contains PP-interrupt vectors, PP-requested TC task
buffers, and a general-purpose area. The parameter RAM does not use the cache memory. Figure 35 shows
the parameter RAM address map.
Suspended PT Parameters
0x0100#000–0x0100#07F
(128 Bytes)
Reserved
(120 Bytes)
0x0100#080–0x0100#0F7
DEA / Cache Fault Address
PP Linked-List Start Address
0x0100#0F8–0x0100#0FB
0x0100#0FC–0x0100#0FF
Off-Chip to Off-Chip PT Buffer
(128 Bytes)
0x0100#100–0x0100#17F
0x0100#180–0x0100#1FF
Interrupt Vectors
(128 Bytes)
0x0100#200
General-Purpose RAM
(3572 Bytes Less Stack Size)
Application-Dependent Boundary
Stack
0x0100#FF7
Stack Pointer After Reset
Stack State Information After Reset
(12 Bytes)
0x0100#FF4–0x0100#FFF
# – PP Number
Figure 36. PP Parameter RAM Address Map
PP-interrupt vectors
The PP interrupts and their vector addresses are shown in Table 8.
Table 8. PP-Interrupt Vectors
VECTOR
NAME
TASK
INTERRUPT
ADDRESS
0x0100#1B8
0x0100#1C4
0x0100#1C8
0x0100#1CC
0x0100#1D0
0x0100#1E0
0x0101#1E4
Task Interrupt
PTQ
Packet Transfer Queued
Packet-Transfer Error
Packet Transfer End
MP Message
PTERR
PTEND
MPMSG
PP0MSG
PP1MSG
PP0 Message
PP1 Message
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit architecture
The data unit has independent data paths for the ALU and the multiplier, each with its own set of hardware
functions. The multiplier data path includes a 16 × 16 multiplier, a halfword swapper, and rounding hardware.
The ALU data path includes a 32-bit three-input ALU, a barrel rotator, mask generator, multiple flag (mf)
expander, left/rightmost one and left/rightmost bit-change logic, and several multiplexers. Figure 37 shows the
data-unit block diagram.
src1/src2/dstc/0
dst2
src3
src4
src4/src2
0
src1/0x1
d0
mf
dst/dst1
Rotate Amount
Multiplexer
Mask Generator
Multiplexer
LMO, RMO,
Expander
LMBC, RMBC
Barrel Rotator
Mask
Generator
Barrel
Rotator Input
Sign Bit
C Port
Multiplexer
Multiplier
(Splittable)
Scale
ALU
Function
Code Logic
A
C
B
Round
Three-Input ALU (Splittable)
Swap/Merge
N, C, V, Z, LV mf
Any register, D reg only for left/right most one (LMO/RMO), left/right most bit change (LMBC/RMBC) hardware
src1
scr2
scr3
scr4
D reg or sometimes 5/32-bit immediate
D reg only
D reg only
dst2 D reg only
dstc D reg only (destination companion reg source)
0x1 Constant
dst/dst1 Any register
0
Constant
d0
5 LSBs of d0
Figure 37. Data-Unit Block Diagram
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP data-unit architecture (continued)
The PP’s ALU can be split into one 32-bit ALU, two 16-bit ALUs, or four 8-bit ALUs. Figure 38 shows the multiple
arithmetic data flow for the case of a four 8-bit split of the ALU (called multiple-byte arithmetic). The ALU
operates as independent parallel ALUs where each ALU receives the same function code.
32
Rotate
Clear
mf Register
4
Expander (Replicate)
8
8
8
8
sr(C)
A
B
C
A
B
C
A
B
C
A
B
C
C-IN
Logic
C-IN
Logic
C-IN
Logic
C-IN
Logic
C-Out
C-IN
C-Out
C-IN
C-Out
C-IN
C-Out
C-IN
8
8
8
8
C, Z,
S, or
E
C, Z,
S, or
E
C, Z,
S, or
E
C, Z,
S, or
E
Figure 38. Multiple-Byte Arithmetic Data Flow
PP multiplier
The PP’s hardware multiplier can perform one 16x16 multiply with a 32-bit result or two 8x8 multiplies with two
16-bit results in a single cycle. A 16x16 multiply can use signed or unsigned operands as shown in Figure 39.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
9
9
8
7
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S
Signed Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
8
8
7
7
6
6
S
S
Signed × Signed Result
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Unsigned Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
Unsigned × Unsigned Result
Figure 39. 16 x 16 Multiplier Data Formats
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP multiplier (continued)
When performing two simultaneous 8x8 split multiplies, the first input word contains unsigned byte operands
and the second input word contains signed or unsigned byte operands. These formats are shown in Figure 40
and Figure 41.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
8
8
7
6
6
6
5
4
3
2
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Unsigned Input 1b
Unsigned Input 1a
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
7
5
4
3
2
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S
Signed Input 2b
S
Signed Input 2a
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
7
5
4
3
2
1
S
1b × 2b Signed Result
S
1a × 2a Signed Result
Figure 40. Signed Split Multiply Data Formats
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
9
9
8
8
8
7
7
7
6
6
6
5
4
3
2
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Unsigned Input 1b
Unsigned Input 1a
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
5
4
3
2
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Unsigned Input 2b
Unsigned Input 2a
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
5
4
3
2
1
1b × 2b Unsigned Result
1a × 2a Unsigned Result
Figure 41. Unsigned Split Multiply Data Formats
PP program-flow-control unit architecture
The program-flow-control (pfc) unit performs instruction fetching and decoding, loop control, and handshaking
with the transfer controller. The pfc unit architecture is shown in Figure 43.
The PP has a three-stage fetch, address, execute (FAE) pipeline as shown in Figure 42. The pc, ipa, and ipe
registers point to the address of the instruction in each stage of the pipeline. On each cycle in which the pipeline
advances, ipa is copied into ipe, pc is copied into ipa, and the pc is incremented by one instruction (8 bytes).
pc
Instruction
One
T1
T2
T3
T4
T5
Fetch
Address
Execute
ipa
ipe
Two
Fetch
Address
Fetch
Execute
Address
Three
Execute
Figure 42. FAE-Instruction Pipeline
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP program-flow-control unit architecture (continued)
pc
lprs
incrementer
Cache Controller
ipa
ipe
Tag Comparators
Tag Registers
Present Bits
LRU Stack
Loop Controller 0
ls0
le0
Figure 43. Program-Flow-Control Unit Block Diagram
Instruction Decode
Comparator
lr0
lctl
FAE Pipeline Control
decr.
zero
Control Signal Generation
lc0
Loop Control
Loop Controller 1
Loop Controller 2
Instruction
Control
Signal
Instruction
Address
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP address-unit architecture
The PP has both a local- and global-address unit which operate independently of each other. The address units
support twelve different addressing modes. In place of performing a memory access, either or both of the
address units can perform an address computation that is written directly to a PP register instead of being used
for a memory access. This address unit arithmetic provides additional arithmetic operation to supplement the
data unit during compute-intensive algorithms.
From Global
To Global
From Global
To Global
Destination Bus
Offset
Source Bus
Destination Bus
Offset
Source Bus
sp = a6 (local)
sp = a14 (global)
a0–a4
(a7 = 0)
a8–a12
(a15 = 0)
x0–x2
x8–x10
pba, dba
pba dba
Index Multiplexer
Index Scaler
Index Multiplexer
Index Scaler
PP-Relative
Multiplexer
PP-Relative
Multiplexer
Scale
Data Size
Scale
Data Size
32-Bit Adder/Subtracter Unit
32-Bit Adder/Subtracter Unit
Preindex/Postindex
Multiplexer
Preindex/Postindex
Multiplexer
Preindex/Postindex
Preindex/Postindex
Local-Address Port
Global-Address Port
Figure 44. Address-Unit Architecture
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP instruction set
PP instructions are represented by algebraic expressions for the operations performed in parallel by the
multiplier, ALU, global-address unit, and local-address unit. The expressions use the || symbol to indicate
operations that are to be performed in parallel. The PP ALU operator syntax is shown in Table 9. The data unit
operations (multiplier and ALU) are summarized in Table 10 and the parallel transfers (global and local) are
summarized in Table 11.
Table 9. PP Operators by Precedence
OPERATOR
FUNCTION
Select odd (n=true) or even (n=false) register of D register pair
based on negative condition code
src1 [n] src1–1
( )
Subexpression delimiters
@mf
Expander operator
%
Mask generator
%%
Nonmultiple mask generator (EALU only)
%!
Modified mask generator (0xFFFFFFFF output for 0 input)
%%!
Nonmultiple shift right mask generator (EALU only)
\\
Rotate left
<<
Shift left (pseudo-op for rotate and mask)
Unsigned shift right
Signed shift right
>>u
>> or >>s
&
Bitwise AND
^
Bitwise XOR
|
Bitwise OR
+
Addition
–
Subtraction
=[cond]
=[cond.pro]
=
Conditional assignment
Conditional assignment with status protection
Equate
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP instruction set (continued)
Table 10. Summary of Data-Unit Operations
Operation
Base set ALUs
Description
Perform an ALU operation specifying ALU function, 2 src and 1 dest operand, and operand routing. ALU function is one of
256 three-input Boolean operations or one of 16 arithmetic operations combined with one of 16 function modifiers.
Syntax
dst = [fmod] [ [[cond [.pro] ]] ] ALU_EXPRESSION
Examples
d6 = (d6 ^ d4) & d2
d3 = [nn.nv] d1 –1
Operation
EALU || ROTATE
Description
Perform an extended ALU (EALU) operation (specified in d0) with one of two data routings to the ALU and optionally write
the barrel rotator output to a second dest register. ALU function is one of 256 Boolean or 256 arithmetic.
Syntax
dst1 = [ [[cond [.pro] ]] ] ealu (src2, [dst2 = ] [ [[cond]] src1 [[[n]] src1–1] \\ src3, [%] src4)
dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label:EALU_EXPRESSION [ || dst2 = [[cond]] src1 [ [[n]] src1–1] \\ src3])
Examples
d7 = [nn] ealu(d2, d6 = [nn] d3\\d1, %d4)
d3 = mzc ealu(mylabel: d4 + (d5\\d6 & %d7) || d1 = d5\\d6)
Operation
Description
Syntax
MPY || ADD
Perform a 16x16 multiply with optional parallel add or subtract. Condition code applies to both multiply and add.
dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 + src1 [ [[n]] src1 –1] ]
dst2 = [sign] [ [[cond]] ] src3 * src4 [ || dst = [ [[cond[.pro] ]] ] src2 – src1 [ [[n]] src1 –1] ]
Example
Operation
Description
Syntax
d7 = u d6 * d5 || d5 = d4 – d1
MPY || SADD
Perform a 16x16 multiply with a parallel right-shift and add or subtract. Condition code applies to multiply, shift, and add.
dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 + src1 [ [[n]] src1 –1] >> –d0
dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[ cond [.pro] ]] ] src2 – src1 [ [[n]] src1 –1] >> –d0
Examples
Operation
Description
Syntax
d7 = u d6 * d5 || d5 = d4 – d1 >> –d0
MPY || EALU
Perform a multiply and an optional parallel EALU. Multiply can use rounding, scaling, or splitting features.
Generic Form:
dst2 = [sign] [ [[cond]] ] src3 * src4 || dst = [ [[cond [.pro] ]] ] ealu[f] (src2, src1 [ [[n]] src1 –1] \\ d0, %d0)
dst2 = [sign] [ [[cond]] ] src3 * src4 || ealu()
Explicit Form:
dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || dst1 = [fmod] [ [[cond [.pro] ]] ] ealu (label: EALU_EXPRESSION)
dst2 = [sign] [opt] [ [[cond]] ] src3 * src4 [<<dms] || ealu (label)
Examples
d7 = [p] d5 * d3 || d2 = [p] ealu(d1, d6\\d0, %d0)
d2 = m d4 * d7 || d3 = ealu (mylabel: d3 + d2 >> 9)
; generic form
; explicit form
Operation
Description
Syntax
divi
Perform one iteration of unsigned divide algorithm. Generates one quotient bit per execution using iterative subtraction.
dst1 = [ [[cond [.pro] ]] ] divi (src2, dst2 = [[cond]] src1 [ [[n]] src1 –1])
Examples
d3 = divi (d1, d2 = d2)
d3 = divi (d1, d2 = d3[n]d2)
Misc. Operations dint; eint; nop
Description
Syntax
Globally disable interrupts; globally enable interrupts; do nothing in the data unit
dint
eint
nop
Legend:
[ ]
Optional parameter extension
Square brackets ([ ]) must be used
Protect status bits
cond
fmod
dms
sign
Condition code
Function modifier
Default multiply shift amount
u = unsigned, s = signed
[[ ]]
pro
f
Use 1s complement of d0
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP instruction set (continued)
Table 11. Summary of Parallel Transfers
Operation
Description
Syntax
Load
Transfer from memory into PP register
dst = [sign] [size] [ [[cond]] ]* addrexp
dst = [sign] [size] [ [[cond]] ]* an.element
Examples
d3 = uh[n]* (a9++=[2])
d1 = * a2.sMY_ELEMENT
Operation
Description
Syntax
Store
Transfer from PP register into memory
* addrexp = [size] src [ [[n]] src–1]
* an.element = [size] src [ [[n]] src–1]
Examples
*––a2 = d3
*a9.sMY_ELEMENT = a3
Operation
Description
Syntax
Address unit arithmetic
Compute address and store in PP register
dst = [size] [ [[cond]] ] & * addrexp
dst = [size] [ [[cond]] ] & * an.element
Examples
d2 = &*(a3 + x0)
a1 = &*a9.sMY_ELEMENT
Operation
Description
Syntax
Move
Transfer from PP register to PP register
dst = [g] [ [[cond]] ] src
Examples
x2 = mf
d1 = g d3
Operation
Description
Syntax
Field extract move
Transfer from PP register to PP register extracting and right-aligning one byte or halfword
dst = [sign] [size item]
Example
Operation
Description
Syntax
d3 = ub2 d1
Field replicate move
Transfer from PP register to PP register replicating the least significant byte or least significant halfword to 32 bits
dst = r [size] [[cond]] src
Example
d7 = rh d3
Legend:
[ ]
[[ ]]
g
Optional parameter extension
Square brackets ([ ]) must be used
Use global unit
cond
sign
size
Condition code
u = unsigned, s = signed
b = byte, h = halfword, w = word (default)
item
0 = byte0/halfword0, 1 = byte1/halfword1, 2 = byte2, 3 = byte3
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats
A PP instruction uses a 64-bit opcode. The opcode is divided essentially into a data unit portion and a parallel
transfer portion. There are five data unit opcode formats comprising bits 38–63 of the opcode. Bits 0–38 of the
opcode specify one of 10 parallel transfer formats. An alphabetical list of the mnemonics used in Figure 45 for
the data unit and parallel transfer portions of the opcode are shown in Table 12 and Table 13, respectively.
Data Unit Formats
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
3
2 1 0
0
1
1
1
1
0
0
1
1
oper
A
src3
dst2
dst1
dst
src1
src1
src1
src1
src4
imm. src2
src2
dstbank s1bnk
Operation
src2
Parallel Transfers
Parallel Transfers
Parallel Transfers
A. Six-Operand (MPYIIADD, etc.)
B. Base Set ALU (5-Bit Immediate)
C. Base Set ALU (Register src2)
D. Base Set ALU (32-Bit Immediate)
E. Miscellaneous
class
class
class
ALU Operation
ALU Operation
ALU Operation
0
1
1
0
A
dst
0
1
–
A
dst
cond
32-Bit Immediate
0
0
0
1
–
0
–
0
–
0
–
0
–
–
–
–
–
–
Parallel Transfers
0
1
Reserved
Reserved
0
Transfer Formats
3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2
8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1
2
0
1
9
1
8
1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2
1
0
Lmode
Lmode
Lmode
Lmode
0 0
d
d
e size
e size
e size
e size
s
s
s
s
La
La
La
La
Gim/X
L
0bank
L
Gmode
reg
e size
srcbank
e size
s
Ga
dst
dst
Lim/X
Lim/X
Lim/X
1. Double Parallel
2. Move II Local
0
0
1
Lrm
Lrm
Lrm
dstbank
dstbank
bank
L 0 0 0 0 src
L 0 0 0 1 src
L 0 0
d
D
3. Field Move II Local
4. Local (Long Offset)
reg
Local Long Offset / X
e size Ga
Global Long Offset /X
e size La
bank
L
Gmode
reg
s
0 Grm 5. Global (Long Offset)
Lmode
d
s
0
Lrm Adstbank L 0 0 1 – – – – As1bank – – – Lim/X
6. Non-D DU II Local
0 0 – cond
0 0 – cond
0 0 – cond
0 0 – cond
c
c
c
c
r
r
r
r
g N C V Z 0 –
g N C V Z 0 itm
g N C V Z Gim/X
– N C V Z 0 –
–
dstbank
dstbank
bank
– 0 0 0 0 src
– 0 0 0 1 src
srcbank
e size
e size
dst
dst
Ga
–
–
1
–
–
– 7. Conditional DU II Conditional Mode
– 8. Conditional DU II Conditional Field Move
D
s
L
Gmode
reg
Grm 9. Conditional DU II Conditional Global
– 10. Conditional Non-D DU
–
Adstbank – 0 0 1 – – – – As1bank – – – –
–
Figure 45. PP Opcode Formats
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats (continued)
Table 12. Data Unit Mnemonics
MNEMONIC
FUNCTION
A
A = 1 selects arithmetic operations, A = 0 selects Boolean operations
ALU Operation
For Boolean operation (A = 0), select the eight ALU function signals. For arithmetic operation (A = 1), odd bits specify the
ALU function and even bits define the ALU function modifiers.
class
Operation class: determines routing of ALU operands
cond
condition code
dst
D register destination or lower 3 bits of non-D register code
ALU dest. for MPY||ADD, MPY||EALU, or EALU||ROTATE operation. D register or lower 3 bits of non-D register code
Multiply dest. for MPY||ADD or MPY||EALU operation, or rotate dest. for EALU||ROTATE operation. D register
ALU register bank
dst1
dst2
dstbank
imm.src2
32-Bit Immediate
oper
5-bit immediate for src2 of ALU operation
32-bit immediate for src2 of ALU operation
Six-operand data unit operation (MPY||ADD, MPY||SADD, MPY||EALU, EALU||ROTATE, divi)
Miscellaneous operation
Operation
src1
ALU source 1 register code (D register unless srcbank or s1bnk is used)
D register used as ALU source 2
src2
src3
D register for multiplier source (MPY||ADD or MPY||EALU) or rotate amount (EALU||ROTATE)
D reg. for ALU C port operand or EALU||ROTATE mask generator input or multiplier source 2 for MPY||ADD, MPY||EALU
Bits 5-3 of src1 register code (bit 6 assumed to be 0)
src4
s1bnk
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats (continued)
Table 13. Parallel Transfer Mnemonics
MNEMONIC
FUNCTION
0bank
Bits 5–3 of global transfer source/destination register code (bit 6 assumed to be 0)
Bits 6–3 of ALU destination register code
Adstbank
As1bank
Bits 6–3 of ALU source 1 register code
bank
Bits 6–3 of global (or local) store source or load destination
Conditional choice of D register for src1 operand of the ALU
Protect status register’s carry bit
c
C
cond
Condition code
d
D register or lower 3 bits of register code for local transfer source/destination
Duplicate least significant data during moves
D
dst
The three lowest bits of the register code for move or field-move destination
Bits 6–3 of move destination register code
dstbank
e
Sign-extend local (bit 31), sign-extend global (bit 9)
Conditional global transfer
g
Ga
Global address register for load, store, or address unit arithmetic
Global address unit immediate offset or index register
Global unit addressing mode
Gim / X
Gmode
Grm
Global PP-relative addressing mode
itm
Number of items selected for field-extract move
L = 1 selects load operation, L = 0 selects store/address unit arithmetic operation
Local address register for load, store, or address unit arithmetic
Local address unit immediate offset or index register
Local unit addressing mode
L
La
Lim / X
Lmode
Lrm
Local PP-relative addressing mode
N
Protect status register’s negative bit
r
Conditional write of ALU result
reg
Register number used with bank or 0bank for global load, store, or address unit arithmetic
Enable index scaling. Additional index bit for byte accesses or arithmetic operations (bit 28, local; bit 6, global)
Size of data transfer (bits 30–29, local; bits 8–7, global)
Three lowest bits of register code for register-register move source or non-field moves. D register source for field move
Bits 6–3 of register code for register-register move source
Protect status register’s overflow bit
s
size
src
srcbank
V
Z
–
Protect status register’s zero bit
Unused bit (fill with 0)
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats (continued)
Table 14 summarizes the supported parallel-transfer formats and indicates whether the transfers are local or
global. It also lists the allowed ALU operations and states whether conditions and status protection are
supported.
Table 14. Parallel-Transfer Format Summary
GLOBAL TRANSFER
Move Load/Store/AUA
LOCAL TRANSFER
Load/Store/AUA
ALU
OPERANDS
Status
Protection
FORMAT
Cond
dst1
D
src1
D
src → dst
s/d
Index
Rel
s/d
D
Index
Rel
Port
Local
Local
Local
—
Double parallel
No
No
No
No
—
Any³Any
D³Any
—
Lower X/short
No
—
X/short
No
Move || Local
D
D
—
—
—
—
D
X/short Yes
Field move || Local
Global (long offset)
Local (long offset)
Non-D DU || Local
Conditional move
Conditional field move
Conditional global
Conditional non-D DU
D
D
No
No
—
D
X/short
—
No
D
D
No
No
Any
—
X/long
—
Yes
—
—
Any
D
—
D
D
No
No
—
X/long
Yes Global
Any
D
Any
D
No
No
—
—
—
—
X/short Yes Global
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Any³Any
D³Any
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
D
—
—
—
D
D
Any
—
X/short Yes
Any
Any
—
—
—
—
32-bit imm. base ALU
Legend:
Any
Lower
Yes
No
DU
AUA Address unit arithmetic
s/d Source/destination register
Rel Relative addressing support
Data unit
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PP opcode formats (continued)
Table 15 shows the encoding used in the opcodes to specify particular PP registers. A 3-bit register field
contains the three least significant bits (LSBs). The register codes are used for the src, src1, src2, src3, src4,
dst, dst1, dst2, d, reg, Ga, La, Gim/X, and Lim/X opcode fields. The four most significant bits (MSBs) specify
the register bank which is concatenated to the register field for the full 7-bit code. The register bank codes are
used for the dstbank, s1bnk, srcbank, 0bank, bank, Adstbank, and As1bank opcode fields. When no associated
bank is specified for a register field in the opcode, the D register bank is assumed. When the MSB of the bank
code is not specified in the opcode (as in 0bank and s1bnk), it is assumed to be 0, indicating a lower register.
Table 15. PP Register Codes
LOWER REGISTERS (MSB OF BANK = 0)
UPPER REGISTERS (MSB OF BANK = 1)
CODING
BANK REG
CODING
CODING
BANK REG
CODING
REGISTER
REGISTER
REGISTER
REGISTER
BANK REG
BANK REG
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0011
0011
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
a0
a1
0100
0100
0100
0100
0100
0100
0100
0100
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111
0111
0111
0111
0111
0111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
d0
1000
1000
1000
1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1010
1010
1010
1010
1010
1010
1010
1010
1011
1011
1011
1011
1011
1011
1011
1011
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1100
1100
1100
1100
1100
1100
1100
1100
1101
1101
1101
1101
1101
1101
1101
1101
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
lc0
lc1
d1
a2
d2
lc2
a3
d3
reserved
lr0
a4
d4
reserved
a6 (sp)
a7 (zero)
a8
d5
lr1
d6
lr2
d7
reserved
lrse0
lrse1
lrse2
reserved
lrs0
reserved
sr
a9
a10
mf
a11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
pc/call
ipa/br
a12
reserved
a14 (sp)
a15 (zero)
x0
lrs1
lrs2
reserved
ls0
x1
ls1
x2
ls2
reserved
reserved
reserved
reserved
reserved
x8
reserved
le0
le1
le2
reserved
reserved
reserved
reserved
reserved
x9
†
ipe
x10
reserved
reserved
reserved
reserved
reserved
iprs
inten
intflg
comm
lctl
†
†
†
†
tag0
tag1
tag2
tag3
†
Read only
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
data unit operation code
For data unit opcode format A, a 4-bit operation code specifies one of 16 six-operand operations and an
associated data path. See Figure 45.
Table 16. Six-Operand Format Operation Codes
oper FIELD BIT
OPERATION TYPE
60
0
59
u
58
0
1
f
57
s
MPY || ADD
MPYU || EALU
EALU || ROTATE
divi
0
u
f
1
0
k
1
0
1
u
0
s
1
1
SPY || SADD
Legend:
u
f
s
k
Unsigned
1s complement EALU function code
Subtract
Use mask or mf expander
operation class code
The base set ALU opcodes (formats B, C, D) use an operation-class code to specify one of eight different
routings to the A, B, and C ports of the ALU. See Figure 45.
Table 17. Base Set ALU Class Summary
CLASS DESTINATION
A PORT
src2
dstc
B PORT
C PORT
@mf
000
001
010
011
100
101
110
111
dst
dst
dst
dst
dst
dst
dst
dst
src1
src1
src1
src1
src1
src1
src1
1
\ \
d0
src2
dstc
\ \
\ \
\ \
\ \
%src2
%src2
%d0
dstc
src2
d0
src2
src2
dstc
d0
@mf
src2
src1
\ \
src2
src2
Legend:
\ \
Rotate left
@mf
%
Expand function
Mask generation
dstc
dst
src2
srd1
Companion D register
Destination D register or any register if dstbank or Adstbank is used with destination.
Source D register or immediate
Source D register or any register if As1bank is used or any lower register if s1bnk is used
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
ALU operation code
For base set ALU Boolean opcodes (A=0), the ALU function is formed by a sum of Boolean products selected
by the ALU operation opcode bits as shown in Table 18. For base set arithmetic opcodes (A=1), the four odd
ALU operation bits specify an arithmetic operation as described in Table 19 while the four even bits specify one
of the ALU function modifiers as shown in Table 20. See Table 9 for a list of PP operators and Figure 45 for PP
opcode formats.
Table 18. Base-Set ALU Boolean Function Codes
OPCODE BIT
PRODUCT TERM
A & B & C
58
57
56
55
54
53
52
51
~A & B & C
A & ~B & C
~A & ~B & C
A & B & ~C
~A & B & ~C
A & ~B & ~C
~A & ~B & ~C
Table 19. Base Set Arithmetics
MODIFIED FUNCTION
(IF DIFFERENT FROM
NATURAL FUNCTION)
OPCODE BITS
CARRY
IN
NATURAL
FUNCTION
ALGEBRAIC DESCRIPTION
57 55 53 51
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
x
1
A – (B | C)
A – B <1<
A + B <0<
A – C
0
A + (B & ~C)
A – C
1
1
A – (B | ~C)
A – B
A – B >1>
A – B
(A – (B & C)) if sign=0
1
C(n)
1/0
1
A – (B & @mf | –B & ~@mf)
A + |B|
A + B / A – B
A + B / A – B
A – B>0>
A + B>0>
A – B / A + B
A – B / A + B
A + B
if class 0 or 5
if class 1–4 or 6–7, A–B if sign=1
0
1
1
1
0
0
1
0
0
1
0
1
A – (B & C)
A + (B & C)
A + (B & @mf | –B & ~@mf)
A – |B|
0
~C(n)
0/1
0
if class 0 or 5
if class 1–4 or 6–7, A+B if sign=1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
A + B
0
A + (B | ~C)
A + C
A + B >1>
A + C
(A + (B & C)) if sign=0
0
1
A – (B & ~C)
A + (B | C)
A – B <0<
A + B <1<
field A + B
0
0
(A & C) + (B & C)
Legend:
C(n)
>0>
LSB of each part of C port register
Zero-extend shift right
Zero-extend shift left
<0<
>1>
<1<
One-extend shift right
One-extend shift left
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
ALU-operation code (continued)
Table 20. Function Modifier Codes
FUNCTION
MODIFIER BITS
MODIFICATION PERFORMED
58 56 54 52
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal operation
cin
%! if maskgen instruction, lmo if not maskgen
%! and cin if maskgen instruction, rmo if not maskgen
A port = 0
A port = 0 and cin
A port = 0 and %! if maskgen, lmbc if not maskgen
A port = 0, %! and cin if maskgen, rmbc if not maskgen
mf bit(s) set by carry out(s). (mc)
mf bit(s) set based on status register MSS field. (me)
Rotate mf by Asize, mf bit(s) set by carry out(s). (mrc)
Rotate mf by Asize, mf bit(s) set based on status register MSS field. (mre)
Clear mf, mf bit(s) set by carry out(s). (mzc)
Clear mf, mf bit(s) set based on status register MSS field. (mze)
No setting of bits in mf register. (mx)
Reserved
Legend:
cin
Carry in from sr(C)
Leftmost-bit change
Leftmost one
%!
rmbc
rmo
Modified mask generator
Rightmost-bit change
Rightmost one
lmbc
lmo
miscellaneous operation code
For data-unit opcode format E, the operation field selects one of the miscellaneous operations.
Table 21. Miscellaneous Operation Codes
OPCODE BITS
MNEMONIC
OPERATION
43 42 41 40 39
0
0
0
0
0
0
1
0
0
0
0
0
1
x
0
0
0
0
1
x
x
0
0
1
1
x
x
x
0
1
0
1
x
x
x
nop
No data-unit operation. Status not modified
reserved
eint
Global-interrupt enable
Global-interrupt disable
dint
reserved
reserved
reserved
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
addressing mode codes
The Lmode (bits 35–38) and Gmode (bits 13–16) of the opcode specify the local and global transfer for various
parallel transfer opcode formats (Lmode in formats 1, 2, 3, 4, and 6 and Gmode in formats 1, 5, and 9). See
Figure 45 for PP opcode formats. Table 22 shows the coding for the addressing mode fields.
Table 22. Addressing Mode Codes
CODING
00xx
0100
0101
0110
0111
EXPRESSION
DESCRIPTION
Nop (nonaddressing mode operation)
Postaddition of index register, with modify
Postsubtraction of index register, with modify
Postaddition of immediate, with modify
Postsubtraction of immediate, with modify
Preaddition of index register
*(an ++= xm)
*(an – –= xm)
*(an ++= imm)
*(an – –= imm)
*(an + xm)
1000
1001
1010
1011
1100
1101
1110
*(an – xm)
Presubtraction of index register
*(an + imm)
*(an – imm)
*(an += xm)
*(an –= xm)
*(an += imm)
*(an –= imm)
Preaddition of immediate
Presubtraction of immediate
Preaddition of index register, with modify
Presubtraction of index register, with modify
Preaddition of immediate, with modify
Presubtraction of immediate, with modify
1111
Legend:
an
imm
xm
Address register in local/global (l/g) address unit
Immediate offset
Index register in same unit as an register
L, e codes
The L and e bits combine to specify the type of parallel transfer performed. For the local transfer, L and e are
bits 21 and 31, respectively. For the global transfer, L and e are bits 17 and 9, respectively. See Figure 45 for
PP opcode formats.
Table 23. Parallel Transfer Type
L
0
0
1
1
e
0
1
0
1
PARALLEL TRANSFER
Store
Address unit arithmetic
Zero-extend load
Sign-extend load
size codes
The size code specifies the data transfer size. For field moves (parallel transfer format 3), only byte and halfword
data sizes are valid.
Table 24. Transfer Data Size
CODING
DATA SIZE
Byte (8 bits)
00
01
10
11
Halfword (16 bits)
Word (32 bits)
Reserved
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
relative-addressing mode codes
The Lrm and Grm opcode fields allow the local-address or global-address units, respectively, to select
PP-relative addressing as shown in Table 25.
Table 25. Relative-Addressing Mode Codes
RELATIVE-ADDRESSING
CODING
MODE
00
01
Normal (absolute addressing)
Reserved
10
PP-relative dba
11
PP-relative pba
Legend:
dba – Data RAM 0 base is base address
pba – Paramater RAM base is base address
condition codes
In the four conditional parallel transfer opcodes (formats 7–10), the condition code field specifies one of
16 condition codes to be applied to the data unit operation source, data unit result, or global transfer based on
the settings of the c, r, and g bits, respectively. Table 26 shows the condition codes. For the 32-bit immediate
data unit opcode (format D), the condition applies to the data unit result only. See Figure 45 for PP opcode
formats.
Table 26. Condition Codes
CONDITION
BITS
MNEMONIC
DESCRIPTION
STATUS BIT COMBINATION
35 34 33 32
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
u
p
Unconditional (default)
Positive
None
~N & ~Z
ls
Lower than or same
Higher than
~C | Z
hi
C & ~Z
lt
Less than
(N & ~V) | (~N & V)
le
Less than or equal
Greater than or equal
Greater than
(N & ~V) | (~N & V) | Z
ge
gt
(N & V) | (~N & ~V)
(N & V & ~Z) | (~N & ~V & ~Z)
hs, c
lo, nc
eq, z
ne, nz
v
Higher than or same, carry
Lower than, no carry
Equal, zero
C
~C
Z
Not equal, not zero
Overflow
~Z
V
nv
No overflow
~V
N
n
Negative
nn
Nonnegative
~N
EALU operations
Extended ALU (EALU) operations allow the execution of more advanced ALU functions than those specified
in the base set ALU opcodes. The opcode for EALU instructions contains the operands for the operation while
the d0 register extends the opcode by specifying the EALU operation to be performed. The format of d0 for EALU
operations is shown in Figure 24.
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
EALU Boolean functions
EALU operations support all 256 Boolean ALU functions plus the flexibility to add 1 or a carry-in to Boolean sum.
The Boolean function performed by the ALU is:
(F0 & (~A & ~B & ~C)) | (F1 & (A & ~B & ~C)) | (F2 & (~A & B & ~C)) | (F3 & (A & B &
~C)) | (F4 & (~A & ~B & C)) | (F5 & (A & ~B & C)) | (F6 & (~A & B & C)) | (F7 & (A & B
& C)) [+1 | +cin]
Table 27. EALU Boolean Function Codes
d0 BIT
26
ALU FUNCTION SIGNAL
PRODUCT TERM
A & B & C
F7
F6
F5
F4
F3
F2
F1
F0
25
~A & B & C
24
A & ~B & C
23
~A & ~B & C
A & B & ~C
22
21
~A & B & ~C
A & ~B & ~C
~A & ~B & ~C
20
19
EALU arithmetic functions
EALU operations support all 256 arithmetic functions provided by the three-input ALU plus the flexibility to add
1 or a carry-in to the result. The arithmetic function performed by the ALU is:
f(A,B,C) = A & f1(B,C) + f2(B,C) [+1 | cin]
f1(B,C) and f2(B,C) are independent Boolean combinations of the B and C ALU inputs. The ALU function is
specified by selecting the desired f1 and f2 subfunction and then XORing the f1 and f2 code from Table 28 to
create the ALU function code for bits 19–26 of d0. Additional operations such as absolute values and signed
shifts can be performed using d0 bits which control the ALU function based on the sign of one of the inputs.
Table 28. ALU f1(B,C) and f2(B,C) Subfunctions
f1
CODE
f2
CODE
SUBFUNCTION
COMMON USAGE
00
AA
88
22
A0
0A
80
2A
A8
02
08
A2
8A
20
28
82
00
FF
CC
33
0
Zero the term
–1 (All 1s)
B
–1
B
–B –1
C
Negate B
C
F0
0F
C0
3F
FC
03
–C –1
B & C
Negate C
Force bits in B to 0 where bits in C are 0
–(B & C) – 1
B | C
Force bits in B to 0 where bits in C are 0 and negate
Force bits in B to 1 where bits in C are 1
–(B | C) – 1
Force bits in B to 1 where bits in C are 1 and negate
Force bits in B to 0 where bits in C are 1
0C
F3
CF
30
B & ~C
–(B & ~C) –1
B | ~C
Force bits in B to 0 where bits in C are 1 and negate
Force bits in B to 1 where bits in C are 0
–(B | ~C) –1
(B & ~C) | ((–B – 1) & C)
(B & C) | ((–B – 1) & ~C)
Force bits in B to 1 where bits in C are 0 and negate
Choose B if C = all 0s and –B if C = all 1s
Choose B if C = all 1s and –B if C = all 0s
3C
C3
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
TC architecture
The transfer controller (TC) is a combined memory controller and DMA (direct memory access) machine. It
handles the movement of data within the ’C80 system as requested by the master processor, parallel
processors, and external devices. The transfer controller performs the following data movement and memory
control functions:
D
D
D
D
D
D
D
D
MP and PP instruction cache fills
MP data-cache fills and dirty block write-back
MP and PP direct external accesses (DEAs)
MP and PP packet transfers
Externally initiated packet transfers (XPTs)
Shift register transfer (SRT) packet transfers for updating VRAM-based frame buffers
DRAM refresh
Host bus request
TC functional block diagram
Figure 46 shows a functional block diagram of the transfer controller. Key features of the TC include:
D
D
Crossbar interface
–
–
64-bit data path
Single-cycle access
External memory interface
–
–
4G-Byte address range
Programmable:
bus size: 8-, 16-, 32-, or 64-bits
page size
bank size
address multiplexing
cycle timing
block-write mode
bank priority
–
Big- or little-endian operation
D
D
Cache, VRAM, refresh controller
–
–
Programmable refresh rate
VRAM block-write support
Independent Src and Dst addressing
–
–
–
Autonomous addressing based on packet-transfer parameters
Data read and write at different rates
Numerous data merging and alignment functions performed during transfer
D
Intelligent request prioritization
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
TC functional block diagram (continued)
Packet Transfer
FIFO
Src MUX and
Alignment
Dst MUX and
Alignment
Cache Buffer
External
Memory
Interface
64
64
Crossbar
Interface
64
64
Src
Dst
Controller
Controller
Memory
Configuration
Cache
Cache, VRAM, and
Refresh Controller
Src Control
Registers
Dst Control
Registers
Request Queuing and Prioritization
Figure 46. TC Block Diagram
TC registers
The TC contains four on-chip memory-mapped registers accessible by the MP.
refresh control (REFCNTL) register (0x01820000)
The REFCNTL register controls refresh cycles.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RPARLD
REFRATE
REFRATE Refresh Interval (in clock cycles)
RPARLD Refresh Pseudo-Address Reload Value
Figure 47. REFCNTL Register
packet-transfer minimum (PTMIN) register (0x01820004)
The PTMIN register determines the minimum number of cycles that a packet transfer executes before being
suspended by a higher priority packet transfer.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PTMIN
Figure 48. PTMIN Register
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PT maximum (PTMAX) register (0x01820008)
The PTMAX register determines the maximum number of cycles after PTMIN has elapsed that a packet transfer
executes before timing out.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PTMAX
Figure 49. PTMAX Register
fault status (FLTSTS) register (0x0182000C)
The FLTSTS register indicates the cause of a memory access fault. Fault status bits are cleared by writing a
1 to the appropriate bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
P
C
P
C
P
C
P
C
P
P
P
P
P
P
P
P
XPT
M
PP #
3
2
1
0
PP#
3
2
1
0
PC PPx Cache / DEA Fault
PP PPx Packet-Transfer Fault
XPT Faulting XPT
MP Packet-Transfer Fault
M
Figure 50. FLTSTS Register
packet-transfer parameters
The most efficient method for data movement in a SMJ320C80 system is through the use of packet transfers
(PTs). Packet transfers allow the TC to move blocks of data autonomously between a specified src and dst
memory region. Requests for the TC to execute a packet transfer may be made by the MP, PPs, or external
devices. A packet-transfer parameter table describing the data packet and how it is to be transferred must be
programmed in on-chip memory before the transfer is requested. The TC on the SMJ320C80 supports short-
and long-form packet transfers. The PT parameter table format is shown in Figure 51.
31
0
31
0
Next Entry Address
PT Options
PT
Src B Pitch
Dst B Pitch
PT + 32
PT + 36
PT + 40
PT + 44
PT + 48
PT + 52
PT + 56
PT + 60
PT + 4
PT + 8
PT + 12
PT + 16
PT + 20
PT + 24
PT + 28
Src Start/Base Address
Dst Start/Base Address
Src C Pitch/Guide Table Pointer
Dst C Pitch/Guide Table Pointer
Transparency/Color Word 0
Transparency/Color Word 1
Reserved
†
†
Src B Count
Dst B Count
Src A Count
Dst A Count
Src C Count/# of Entries
Dst C Count/# of Entries
Reserved
PT – 64-byte aligned on-chip starting address of
†
Words are swapped in big-endian mode
parameter table
Figure 51. Packet-Transfer Parameter Table
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
PT-options field
The PT-options field of the parameter table controls the type of src and dst transfer that the TC performs. The
format of the options field is shown in Figure 52.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
C
D
R
D
B
R
S
C
R
S
B
R
A
S
PTS
I
X
PAM
STM
SUM
DTM
DUM
S
Stop bit
PTS PT status
00 – Active
01 – Suspended
Interrupt when complete
PAM PT Access Mode
000 – Normal
100 – 8 Bit Transfer
101 – 16 Bit Transfer
110 – 32 bit Transfer
111 – 64 Bit Transfer
10 – Fault on src
11 – Fault on dst
001 – PDT
010 – Block Write
011 – SRT
I
RDC Reverse dst C addressing
RDB Reverse dst B addressing
RA Reverse A addressing
RSC Reverse src C addressing
RSB Reverse src B addressing
STM/DTM src/dst Transfer Mode
000 – Dimensioned 100 – Var Delta-Guided
†
001 – Fill
010 – Reserved
101 – Var Offset-Guided
110 – Fixed Delta-Guided
111 – Fixed Offset-Guided
†
011 – LUT
X
Exchange src and dst parameters
SUM/DUM src/dst update mode
00 – None
01 – Add C Pitch
01 – Add B Pitch
11 – Add C Pitch/Reverse
†
Valid for src only.
Figure 52. PT-Options Field
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
local memory interface
status codes
Status codes are output on STATUS[5:0] to describe the cycle being performed. During row time, STATUS[5:0]
pins indicate the type of cycle being performed. The cycle type can be latched using RL or RAS and used by
external logic to perform memory bank decoding or to enable special hardware features. During column time,
the STATUS[5:0] pins indicate the requesting processor or special column information.
Table 29. Row-Time Status Codes
STATUS[5:0]
CYCLE TYPE
Normal Read
STATUS[5:0]
CYCLE TYPE
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal Write
Reserved
Refresh
Reserved
SDRAM DCAB
Peripheral Device PT Read
Peripheral Device PT Write
Reserved
Reserved
XPT1 Read
XPT1 Write
XPT1 PDPT Read
XPT1 PDPT Write
XPT2 Read
Reserved
Reserved
Block-Write PT
Reserved
XPT2 Write
XPT2 PDPT Read
XPT2 PDPT Write
XPT3 Read
Reserved
SDRAM MRS
Load Color Register
Reserved
XPT3 Write
XPT3 PDPT Read
XPT3 PDPT Write
XPT4/SAM1 Read
XPT4/SAM1 Write
XPT4/SAM1 PDPT Read
XPT4/SAM1 PDPT Write
XPT5/SOF1 Read
XPT5/SOF1 Write
XPT5/SOF1 PDPT Read
XPT5/SOF1 PDPT Write
XPT6/SAM0 Read
XPT6/SAM0 Write
XPT6/SAM0 PDPT Read
XPT6/SAM0 PDPT Write
XPT7/SOF0 Read
XPT7/SOF0 Write
XPT7/SOF0 PDPT Read
XPT7/SOF0 PDPT Write
Reserved
Frame 0 Read Transfer
Frame 0 Write Transfer
Frame 0 Split-Read Transfer
Frame 0 Split-Write Transfer
Frame 1 Read Transfer
Frame 1 Write Transfer
Frame 1 Split-Read Transfer
Frame 1 Split-Write Transfer
Reserved
Reserved
Reserved
Reserved
PT Read Transfer
PT Write Transfer
Reserved
Idle
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
local memory interface (continued)
Table 30. Column-Time Status Codes
STATUS[5:0]
CYCLE TYPE
STATUS[5:0]
CYCLE TYPE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Write Drain / SDRAM DCAB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PP0 Low-Priority Packet Transfer
PP0 High-Priority Packet Transfer
PP0 Instruction Cache
PP0 DEA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PP1 Low-Priority Packet Transfer
PP1 High-Priority Packet Transfer
PP1 Instruction Cache
PP1 DEA
PP2 Low-Priority Packet Transfer
PP2 High-Priority Packet Transfer
PP2 Instruction Cache
PP2 DEA
PP3 Low-Priority Packet Transfer
PP3 High-Priority Packet Transfer
PP3 Instruction Cache
PP3 DEA
MP Low-Priority Packet Transfer
MP High-Priority Packet Transfer
MP Urgent Packet Transfer (Low)
MP Urgent Packet Transfer (High)
XPT/VCPT in Progress
XPT/VCPT Complete
MP Instruction Cache (Low)
MP Instruction Cache (High)
MP DEA (Low)
MP DEA (High)
MP Data Cache (Low)
MP Data Cache (High)
Frame 0
Frame 1
Refresh
Idle
Low – MP operating in low-(normal) priority mode
High – MP operating in high-priority mode
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
address multiplexing
To support various RAM devices, the SMJ320C80 can provide multiplexed row and column addresses on its
address bus. A full 32-bit address is always output at row time. The alignment of column addresses is configured
by the value input on the AS[2:0] pins at row time.
A Pins
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
31 30 29 28 27 26 25 24 23 22 21 20 19
14 13 12 11 10
18 17 16 15
Row Time
A Pins
AS [2:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
9
1
0
x
x
x
x
x
8
8
0
x
x
x
x
x
x
7
7
x
x
x
x
x
x
x
6
6
x
x
x
x
x
x
x
5
5
x
x
x
x
x
x
x
4
4
x
x
x
x
x
x
x
3
3
x
x
x
x
x
x
x
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
000
001
010
100
011
100
110
111
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
8
7
6
5
4
3
2
7
6
5
4
3
2
1
6
5
4
3
2
1
0
5
4
3
2
1
0
x
4
3
2
1
0
x
x
3
2
1
0
x
x
x
2
1
0
x
x
x
x
22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
19 18 17 16 15 14 13 12 11 10
9
8
7
18 17 16 15 14 13 12 11 10
17 16 15 14 13 12 11 10
9
8
9
Column Time
Figure 53. Address Multiplexing
dynamic bus sizing
The ’C80 supports data bus sizes of 8, 16, 32, or 64 bits. The value input on the BS[1:0] pins at row time
indicates the bus size of the addressed memory. This determines the maximum number of bytes which the ’C80
can transfer during each column access. If the number of bytes to be transferred exceeds the bus size, multiple
accesses are performed automatically to complete the transfer.
Table 31. Bus Size Selection
BS[1:0]
0 0
BUS SIZE
8 bits
0 1
16 bits
32 bits
64 bits
1 0
1 1
The selected bus size also determines which portion of the data bus is used for the transfer. For 64-bit memory,
the entire data bus is used. For 32-bit memory, D[31:0] are used in little-endian mode and D[63:32] are used
in big-endian mode. 16-bit buses use D[15:0] and D[63:48] and 8-bit buses use D[7:0] and D[63:56] for little-
and big-endian modes, respectively. The ’C80 always aligns data to the proper portion of the bus and activates
the appropriate CAS strobes to ensure that only valid bytes are transferred.
69
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
cycle time selection
The ’C80 supports eight basic sets of memory timings to support various memory types directly. The cycle timing
is selected by the value input on the CT[2:0] pins at row time. The selected timing remains in effect until the next
row access.
Table 32. Cycle-Timing Selection
CT[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
MEMORY TIMING
Pipelined (Burst Length 1) SDRAM, CAS Latency of 2
Pipelined (Burst Length 1) SDRAM, CAS Latency of 3
Interleaved (Burst Length 2) SDRAM, CAS Latency of 2
Interleaved (Burst Length 2) SDRAM, CAS Latency of 3
Pipelined 1 Cycle/Column
Nonpipelined 1 Cycle/Column
2 Cycle/Column
3 Cycle/Column
page sizing
Whenever an external memory access occurs, the TC records the 22 most significant bits of the address in its
internal LASTPAGE register. The address of each subsequent (column) access is compared to this value. The
page size value input on the PS[3:0] pins determines which bits of LASTPAGE are used for this comparison.
If a difference exists between the enabled LASTPAGE bits and the corresponding bits of the next access, then
the page has changed and the next memory access begins with a new row-address cycle.
Table 33. Page-Size Selection
PS[3:0]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
ADDRESS BITS COMPARED
A[31:6]
PAGE SIZE (BYTES)
64
128
256
512
1K
A[31:7]
A[31:8]
A[31:9]
A[31:10]
A[31:18]
256K
512K
1M
A[31:19]
A[31:20]
†
1–8
A[31:0]
A[31:11]
2K
4K
A[31:12]
A[31:13]
8K
A[31:14]
16K
32K
64K
128K
A[31:15]
A[31:16]
A[31:17]
†
PS[3:0] = 1000 disables page-mode cycles so that the effective page size is the same
as the bus size
70
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write support
The SMJ320C80 supports three modes of VRAM block-write. The block-write mode is dynamically selectable
so that software can specify block-writes regardless of the type of block-write the addressed memory supports.
Block-writes are supported only for 64-bit buses. During block-write and load-color-register cycles, the BS[1:0]
inputs determine which block mode will be used.
Table 34. Block-Write Selection
BS[1:0]
0 0
BLOCK-WRITE MODE
Simulated
Reserved
4x
0 1
1 0
1 1
8x
SDRAM support
The SMJ320C80 provides direct support for synchronous DRAM (SDRAM), synchronous VRAM (SVRAM), and
synchronous graphics RAM (SGRAM). During ’C80 power-up refresh cycles, the external system must signal
the presence of these memories by inputting a CT2 value of 0. This causes the ’C80 to perform special
deactivate (DCAB) and mode register set (MRS) commands to initialize the synchronous RAMs. Figure 54
shows the MRS value generated by the ’C80.
SDRAM Mode
Register Bit
11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
CT0
0
0
0
CT1
CT0, CT1 as input at the start of the MRS cycle
Figure 54. MRS Value
Because the MRS register is programmed through the SDRAM address inputs, the alignment of the MRS data
to the ’C80 logical-address bits is adjusted for the bus size (see Figure 55). The appearance of the MRS bits
on the ’C80 physical-address bus is dependent on the address multiplexing as selected by the AS[2:0] inputs.
’C80 LOGICAL ADDRESS BITS
BS[1:0] A15 A14 A13 A12 A11 A10 A9
A8
8
A7
7
A6
6
A5
5
A4
4
A3
3
A2
2
A1
1
A0
0
0 0
0 1
1 0
1 1
X
X
X
X
X
X
X
X
X
11
10
9
11
10
9
10
9
9
8
7
6
7
6
5
4
3
2
1
0
X
X
11
10
8
6
5
4
3
2
1
0
X
X
11
8
7
5
4
3
2
1
0
X
X
X
Figure 55. MRS Value Alignment
memory cycles
SMJ320C80 external memory cycles are generated by the TC’s external memory controller. The controller’s
state machine generates a sequence of states which define the transition of the memory interface signals. The
state sequence is dependent on the cycle timing selected for the memory access being performed as shown
in Figure 56. Memory cycles consist of row states and the column pipeline.
71
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
memory cycles (continued)
rhiz
bus release
idle or abort
bus request
always
r1
r2
r3
r4
r5
r9
always
any cycle
r8
always
wait
drn
r7
always
MRS or DCAB
!MRS & !DCAB
spin
spin
r6
rspin
col access
wait
col access
Column Pipeline
Figure 56. Memory Cycle State Diagram
72
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
row states
The row states make up the row time of each memory access. They occur when each new page access begins.
The transition indicators determine the conditions that cause transitions to another state.
Table 35. Row States
STATE
DESCRIPTION
Beginning state for all memory accesses. Outputs row address (A[31:0]) and cycle type (STATUS[5:0]) and drives control
signals to their inactive state
r1
r2
Common to all memory accesses. Asserts RL and drives DDIN according to the data transfer direction. AS[2:0], BS[1:0],
CT[2:0], PS[3:0], and UTIME inputs are sampled
Common to all memory accesses. DBEN is driven to its active level. For non-SDRAM, W, TRG/CAS, and DSF are driven to their
active levels, and for non-SDRAM refreshes, all CAS/DQM strobes are activated. FAULT, READY, and RETRY inputs are
sampled.
r3
r4
r5
Inserted for 3 cycle/column accesses (CT=111) only. No signal transitions occur. RETRY input is sampled.
Common to SDRAM and 2 or 3 cycle/column accesses (CT=0xx or 11x). RAS is driven low. W is driven low for DCAB and MRS
cycles and TRG/CAS is driven low for MRS and SDRAM refresh cycles.
Common to all memory accesses. For SDRAM cycles, RAS, TRG/CAS, and W are driven high. For non-SDRAM, RAS is driven
low (if not already) and W, TRG/CAS, and DSF are driven to their appropriate levels. DBEN is driven low and READY and
RETRY are sampled.
r6
Additional state to allow TC column time pipeline to load. No signal transitions occur. RETRY is sampled. The rspin state can, on
occasion, repeat multiple times.
rspin
r7
Common to 2 and 3 cycle/column refreshes (CT=11x). Processor activity code is output on STATUS[5:0]. RETRY input is
sampled.
r8
r9
For 3 cycle/column refreshes only (CT=111). No signal transitions occur. RETRY input is sampled.
Common to all refresh cycles. Processor activity code is output on STATUS[5:0] and RETRY input is sampled.
Occurs for SDRAM cycles (CT = 0xx) and pipelined 1 cycle/column writes only. For SDRAM cycles, RAS, and W are activated
to perform a DCAB command. For pipelined writes, all CAS/DQM strobes are activated.
drn
rhiz
High-impedance state. Occurs during host requests and repeats until bus is released by the host
Table 36. State Transition Indicators
INDICATOR
any cycle
CT=xxx
abort
DESCRIPTION
Continuation of current cycle
State change occurs for indicated CT[2:0] value (as latched in r2 state)
Current cycle aborted by TC in favor of higher-priority cycle
FAULT input sampled low (in r3 state), memory access faulted
RETRY input sampled low (in r3 state), row-time retry
fault
retry
wait
READY input sampled low (in r3, r6, or last column state) repeat current state
Internally generated wait state to allow TC pipeline to load
The next access requires a page change (new row access)
spin
new page
external memory timing examples
The following sections contain descriptions of the ’C80 memory cycles and illustrate the signal transitions for
those cycles. Memory cycles can be separated into two basic categories: DRAM-type cycles for use with
DRAM-like devices, SRAM, and peripherals, and SDRAM-type cycles for use with SDRAM-like devices.
73
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ꢌ ꢅꢆꢅ ꢃ ꢃ ꢅ ꢆ
ꢎ
ꢅ ꢆꢅ ꢂ ꢂ
ꢆꢅ ꢌ
ꢀ
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ꢁ
ꢔ ꢁ ꢕꢓ ꢋ ꢁꢖ ꢓ ꢒ ꢍꢗ ꢀ ꢘꢀꢋ ꢓ
ꢩ ꢢ ꢁ ꢦꢓ ꢤꢥ ꢋ ꢊꢣꢒ ꢀ ꢊꢋ ꢊꢢ ꢢ ꢓ ꢮꢁ ꢤ ꢦꢓ ꢢ ꢝꢪꢂ ꢫ ꢡꢥ ꢬ ꢋꢊ ꢀꢭ ꢩ ꢢ ꢁ ꢦꢓ ꢤ
ꢆ
ꢀ ꢊ ꢋꢙ ꢚ ꢖ ꢝꢂ ꢞ ꢟ ꢠꢠꢠꢠꢡ
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ꢢꢓꢣ ꢒꢤ ꢥ ꢢꢓꢣ ꢒ ꢦ ꢢꢣ ꢖ ꢤ ꢧꢓꢢ ꢤ ꢥ ꢤ ꢕꢋꢁ ꢦ ꢢ ꢓꢣ ꢒ ꢦ ꢢ ꢣꢖ ꢤ ꢧꢓꢢ ꢤ
ꢨ ꢊ ꢖꢕ ꢁ ꢕꢓ ꢋ ꢁ ꢖ ꢓꢒ ꢍꢗ ꢀ ꢘꢀꢋ ꢓ ꢆ ꢀ ꢊ ꢋꢙ ꢚ ꢖ ꢝꢂ ꢞ ꢟ ꢠꢠꢠꢍꢡ
ꢩ ꢢ ꢁ ꢦꢓ ꢤꢥ ꢪꢂ ꢫꢤ ꢥ ꢬ ꢋꢊ ꢀꢭ ꢩ ꢢ ꢁ ꢦꢓ ꢤ
ꢅ
ꢃ
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ꢏꢗ ꢀꢘꢀ ꢋ ꢅ ꢅ ꢀꢊꢋꢙ ꢚꢖ ꢛꢇ ꢜ ꢝ ꢂꢞ ꢟ ꢠꢠꢍꢠ ꢡ
ꢢꢓꢣ ꢒꢤ ꢥ ꢢ ꢓꢣꢒ ꢦ ꢢ ꢣꢖ ꢤ ꢧꢓꢢ ꢤ ꢥ ꢤ ꢕꢋꢁ ꢦ ꢢ ꢓꢣ ꢒ ꢦ ꢢ ꢣꢖ ꢤ ꢧꢓꢢ ꢤ
ꢏꢗ ꢀ ꢘꢀꢋ ꢓ ꢆ ꢀ ꢊ ꢋꢙ ꢚ ꢖ ꢝꢂ ꢞ ꢟ ꢠꢠꢍꢠꢡ
ꢩ ꢢ ꢁ ꢦꢓ ꢤꢥ ꢪꢂ ꢫꢤ ꢥ ꢬ ꢋꢊ ꢀꢭ ꢩ ꢢ ꢁ ꢦꢓ ꢤ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢅ
ꢇ
ꢈ
ꢉ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢅ
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ꢉ
ꢀ
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ꢏ
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ꢯ
ꢀ
ꢰ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ
ꢐꢗ ꢀꢘꢀ ꢋ ꢅ ꢅ ꢀꢊꢋꢙ ꢚꢖ ꢛꢇ ꢜ ꢝ ꢂꢞ ꢟ ꢠꢠꢍꢍ ꢡ
ꢢꢓꢣ ꢒꢤ ꢥ ꢢ ꢓꢣ ꢒ ꢦ ꢢ ꢣꢖ ꢤ ꢧꢓꢢ ꢤ ꢥ ꢤ ꢕꢋꢁ ꢦ ꢢ ꢓꢣ ꢒ ꢦ ꢢ ꢣꢖ ꢤ ꢧꢓꢢ ꢤ
ꢐꢗ ꢀ ꢘꢀꢋ ꢓ ꢆ ꢀ ꢊ ꢋꢙ ꢚ ꢖ ꢝꢂ ꢞ ꢟ ꢠꢠꢍꢍꢡ
ꢩ ꢢ ꢁ ꢦꢓ ꢤꢥ ꢪꢂ ꢫꢤ ꢥ ꢣꢖ ꢒ ꢬ ꢋꢊ ꢀꢭ ꢩ ꢢ ꢁ ꢦꢓ ꢤ
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
DRAM-type cycles
The DRAM-type cycles are page-mode accesses consisting of a row access followed by one or more column
accesses. Column accesses may be one, two, or three clock cycles in length with two and three cycle accesses
allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column
accesses have completed or between column accesses due to “bubbles” in the TC data-flow pipeline. The
pipeline diagrams in Figure 57 show the pipeline stages for each access type and when the CAS/DQM signal
corresponding to the column access is activated.
ꢃ
ꢅꢎ
ꢂ
ꢂꢃꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢃ ꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢊꢋ ꢃ ꢀ ꢍ
ꢂ ꢊꢋ ꢎ
ꢂ ꢊꢋ ꢃ ꢀꢍ ꢀꢏ ꢀꢐ
ꢀ ꢍ
ꢂ ꢊꢋ ꢎ
ꢂ ꢊꢋ ꢂ
ꢑꢒꢋꢓ
ꢀꢍ ꢀꢏ ꢀꢐ
ꢂ ꢊꢋ ꢂ
ꢀ ꢍ
ꢀꢍ ꢀꢏ ꢀꢐ
ꢑꢒ ꢋꢓ
ꢀꢁ
ꢀꢁ
ꢔ ꢁ ꢕꢓꢋꢁ ꢖ ꢓꢒ ꢍꢗ ꢀꢘ ꢀꢋꢓ ꢅꢆ ꢅꢀ ꢊꢋꢙ ꢚꢖ ꢛꢇ ꢜ ꢝ ꢂꢞ ꢟ ꢠꢠꢠꢠ ꢡ
ꢢꢓꢣ ꢒꢤ ꢥ ꢢꢓꢣ ꢒ ꢦ ꢢꢣ ꢖ ꢤ ꢧꢓꢢ ꢤ ꢥ ꢤ ꢕꢋꢁ ꢦ ꢢ ꢓꢣ ꢒ ꢦ ꢢ ꢣꢖ ꢤ ꢧꢓꢢ ꢤ
ꢃ
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ꢂ
ꢂꢃ ꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢊꢋ ꢃ ꢀ ꢍ
ꢂ ꢊꢋ ꢎ
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ꢂ ꢊꢋ ꢂ
ꢑꢒꢋꢓ
ꢀ ꢍ
ꢀꢍ ꢀꢏ
ꢀꢁ
ꢂ ꢊꢋ ꢂ
ꢎ
ꢎ
ꢂ ꢃ ꢄ ꢅ ꢆꢅ ꢇꢈ ꢉ
ꢂ ꢊꢋ ꢃ ꢀ ꢍ ꢀ ꢏ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢂ ꢊꢋ ꢎ
ꢂ ꢊꢋ ꢂ
ꢑꢒꢋꢓ
ꢀꢍ ꢀꢏ ꢀꢐ
ꢂ ꢊꢋ ꢎ
ꢀ ꢍ ꢀ ꢏ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢀꢍ ꢀꢏ ꢀꢐ
ꢂ ꢊꢋ ꢂ
ꢑꢒ ꢋꢓ
ꢀ ꢍ ꢀ ꢏ
ꢌ
ꢌ
ꢌ
ꢀꢁ
ꢌ
ꢀ ꢁ
ꢌ
ꢀ ꢁ
ꢀ ꢁ
ꢀ ꢁ
ꢃ
ꢂ ꢊꢋ ꢃ ꢀꢍ ꢀꢏ ꢀꢐ ꢀꢯ ꢀꢰ
ꢃ
ꢎ
ꢎ
ꢂ
ꢂ
ꢃ
ꢃ
ꢂ ꢊꢋ ꢃ ꢀ ꢍ ꢀ ꢏ ꢀ ꢐ
ꢎ
ꢎ
ꢂ
ꢌ
ꢂ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢂ ꢊꢋ ꢎ
ꢂ ꢊꢋ ꢂ
ꢑꢒꢋꢓ
ꢀꢍ ꢀꢏ ꢀꢐ ꢀꢯ ꢀꢰ
ꢂ ꢊꢋ ꢎ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢂ ꢊꢋ ꢂ
ꢌ
ꢀ ꢍ ꢀ ꢏ ꢀ ꢐ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
ꢌ
Figure 57. DRAM Cycle Column Pipelines
74
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ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles
Read cycles transfer data or instructions from external memory to the ’C80. The cycles can occur as a result
of a packet transfer, cache request, or DEA request. During the cycle, W is held high, TRG/CAS is driven low
after RAS to enable memory output drivers and DBEN and DDIN are low so that data transceivers can drive
into the ’C80. During column time, the TC places D[63:0] into the high-impedance state, allowing it to be driven
by the memory and latches input data during the appropriate column state. The TC always reads 64 bits and
extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. During
peripheral device packet transfers, DBEN and DDIN remain high.
75
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
Col A
Col B
Col C
Col D
r1
r2
r3
r6
col
c1
col
c2
c1
col
c3
c2
c1
col
col
col
c3
r1
c3
c2
c1
c3
c2
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
4
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
PAC
PAC
PAC
Idle
RL
A[31:0]
Col A
Col B
Col C
Col D
RAS
CAS/DQM[7:0]
DSF
–/A
A/B
B/C
C/D
D/–
TRG/CAS
W
D[63:0]
A
B
C
D
DBEN
DDIN
0 For Normal Reads, 1 For PDPT Reads
For user-modified timing:
UTIME
RAS
–/A
A/B
B/C
C/D
D/–
CAS/DQM[7:0]
Figure 58. Pipelined 1-Cycle/Column Read-Cycle Timing
76
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
State
Col A
Col B
Col C
r1
r2
r3
r6
col
c1
col
c2
c1
col
col
c2
r1
c2
c1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
5
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
PAC
PAC
Idle
RL
A[31:0]
Col A
Col B
Col C
RAS
CAS/DQM[7:0]
DSF
A
B
C
TRG/CAS
W
D[63:0]
A
B
C
0 For Normal Reads, 1 For PDPT Reads
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
Figure 59. Nonpipelined 1-Cycle/Column Read-Cycle Timing
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
†
‡
r1
r2
r3
r5
r6
col
c1
col
c2
col
c1
col
col
c2
ci
col
c1
col
c2
r1
State
Col A
Col B
Col C
c2
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
6
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
PAC
Idle
PAC
STATUS[5:0]
RL
A[31:0]
Col A
A
Col B
B
Col C
C
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
A
B
C
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
C
A
B
CAS/DQM[7:0]
†
‡
Wait state inserted by external logic (example)
Internally generated pipeline bubble (example)
Figure 60. 2-Cycle/Column Read-Cycle Timing
78
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
read cycles (continued)
†
‡
col
c1
col col
r1
r2
r3
r4
r5
r6
col col col col col
col ci
col
c3
r1
State
Col A
Col B
Col C
c2
c3
c1
c2
c3
c3
c1
c2
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
7
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
Row
PAC
PAC
Idle
PAC
Column A
Column B
Column C
A[31:0]
RAS
A
B
C
CAS/DQM[7:0]
DSF
TRG/CAS
W
A
B
C
D[63:0]
DBEN
0 For Normal Reads, 1 For PDPT Reads
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
‡
Wait state inserted by external logic (example)
Internally generated pipeline bubble (example)
Figure 61. 3-Cycle/Column Read-Cycle Timing
write cycles
Write cycles transfer data from the ’C80 to external memory. These cycles can occur as a result of a packet
transfer, a DEA request, or an MP data cache write-back. During the cycle TRG/CAS is held high, W is driven
low after the fall of RAS to enable early-write cycles, and DDIN is high so that data transceivers drive toward
memory. The TC drives data out on D[63:0] and indicates valid bytes by activating the appropriate CAS/DQM
strobes. During peripheral device packet transfers, DBEN remains high and D[63:0] is placed in high impedance
so that the peripheral device can drive data into the memory.
79
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
†
ci
col
c1
col
c1
col
c1
r1
r2
r3
r6
rspin rspin
drn
r1
State
Col A
Col B
Col C
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
4
FAULT
READY
RETRY
STATUS[5:0]
PAC
PAC
Idle
PAC
Drain
Cycle Type
Row
RL
Col A
Col B
Col C
A[31:0]
RAS
CAS/DQM[7:0]
DSF
A
B
C
TRG/CAS
W
A
B
C
D[63:0]
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
C
A
B
CAS/DQM[7:0]
†
Internally generated pipeline bubble (example)
Figure 62. Pipelined 1-Cycle/Column Write-Cycle Timing
80
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
†
State
r1
r2
r3
r6
rspin
rspin
col
c1
col
c1
col
c1
r1
ci
Col A
Col B
Col C
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
5
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
Col A
A
PAC
Col B
B
Idle
PAC
Col C
C
RL
A[31:0]
Row
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
A
B
C
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
Internally generated pipeline bubble (example)
Figure 63. Nonpipelined 1-Cycle/Column Write-Cycle Timing
81
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
†
‡
ci
r1
r2
r3
r5
r6
rspin col
c1
col
c2
col
c1
col
col
c2
col
c1
col
c2
r1
State
Col A
Col B
Col C
c2
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
6
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
Row
PAC
PAC
Idle
PAC
Col A
Col B
Col C
A[31:0]
RAS
A
B
C
CAS/DQM[7:0]
DSF
TRG/CAS
W
A
B
C
D[63:0]
DBEN
0 For Normal Write, 1 For PDPT Write
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
‡
Wait state inserted by external logic (example)
Internally generated pipeline bubble (example)
Figure 64. 2-Cycle/Column Write-Cycle Timing
82
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
write cycles (continued)
†
‡
State
Col A
Col B
Col C
r1
r2
r3
r4
r5
r6
col col col
col col col
col ci
col col col
r1
c1
c2
c3
c1
c2 c3
c3
c1
c2 c3
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
7
UTIME
FAULT
READY
RETRY
PAC
Cycle Type
PAC
Idle
PAC
STATUS[5:0]
RL
Row
Col A
Col B
Col C
A[31:0]
RAS
CAS/DQM[7:0]
DSF
A
B
C
TRG/CAS
W
A
B
C
D[63:0]
0 For Normal Write, 1 For PDPT Write
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
‡
Wait state inserted by external logic (example)
Internally generated pipeline bubble (example)
Figure 65. 3-Cycle/Column Write-Cycle Timing
83
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles
Load-color-register (LCR) cycles are used to load a VRAM’s color register prior to performing a block-write. LCR
cycles are supported only on 64-bit data buses. An LCR cycle closely resembles a normal write cycle because
it writes into a VRAM. The difference is that the DSF output is high at both the fall of RAS and the fall of
CAS/DQM. Also, because the VRAM color register is a single location, only one column access occurs.
The row address that is output by the TC is used for bank-decode only. Normally, all VRAM banks should be
selected during an LCR cycle because another LCR cycle cannot occur when a block-write memory-page
change occurs. The column address that is output during an LCR is likewise irrelevant because the VRAM color
register is the only location written. All CAS/DQM strobes are active during an LCR cycle.
If exception support for a given bank is enabled, the EXCEPT [1:0] inputs are sampled during LCR column states
and must be at valid levels. A retry code (EXCEPT [1:0] = 10) at column time has no effect, however, because
only one column access is performed.
If the BW field of the configuration cache entry for the given bank indicates that the addressed memory supports
only simulated block-writes, the LCR cycle will be changed into a normal write cycle at the start of the simulated
block-write.
84
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
c1
r1
r2
4
r3
r6
rspin rspin
drn
r1
State
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
Drain
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 66. Pipelined 1-Cycle/Column Load-Color-Register-Cycle Timing
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
State
r1
r2
5
r3
r6
rspin
rspin
c1
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
STATUS[5:0]
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 67. Nonpipelined 1-Cycle/Column Load-Color-Register-Cycle Timing
86
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
r1
r2
6
r3
r5
r6
rspin
c1
c2
r1
State
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color Value
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 68. 2-Cycle/Column Load-Color-Register-Cycle Timing
87
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
load-color-register cycles (continued)
r1
r2
r3
r4
r5
r6
c1
c2
c3
r1
State
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
7
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
RL
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color Value
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 69. 3-Cycle/Column Load-Color-Register-Cycle Timing
88
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles
Block-write cycles cause the data stored in the VRAM color registers to be written to the memory locations
enabled by the appropriate data bits output on the D[63:0] bus. This allows up to a total of 64 bytes (depending
on the type of block-write being used) to be written in a single-column access. This cycle is identical to a standard
write cycle with the following exceptions:
D
D
DSF is active (high) at the fall of CAS, enabling the block-write function within the VRAMs.
Only 64-bit bus sizes are supported during block-write; therefore, BS[1:0] inputs are used to indicate the
type of block-write that is supported by the addressed VRAMs, rather than the bus size.
D
D
The two or three LSBs (depending on the type of block-write) of the column address are ignored by the
VRAMs because these column locations are specified by the data inputs.
The values output by the TC on D[63:0] represent the column locations to be written to, using the color
register value. Depending on the type of block-write supported by the VRAM, all of the data bits are not
necessarily used by the VRAMs.
D
Block-writes always begin with a row access. Upon completion of a block-write, the memory interface
returns to state r1 to await the next access.
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
†
ci
State
r1
r2
r3
r6
rspin rspin col
c1
col
c1
col
c1
drn
r1
Col A
Col B
Col C
CLKOUT
CT[2:0]
4
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
PAC
Idle
PAC Drain
RL
A[31:0]
Col A Col B
Col C
C
RAS
CAS/DQM[7:0]
DSF
A
B
TRG/CAS
W
D[63:0]
Sel A Sel B
Sel C
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
Internally generated pipeline bubble (example)
Figure 70. Pipelined 1-Cycle/Column Block-Write-Cycle Timing
90
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
†
State
Col A
Col B
Col C
r1
r2
r3
r6
rspin rspin
col
c1
col
c1
ci
col
c1
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
5
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
PAC
Idle
PAC
Col C
C
RL
A[31:0]
RAS
Col A Col B
A
B
CAS/DQM[7:0]
DSF
TRG/CAS
W
Sel A Sel B
Sel C
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
Internally generated pipeline bubble (example)
Figure 71. Nonpipelined 1-Cycle/Column Block-Write-Cycle Timing
91
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
†
‡
ci
r1
r2
r3
r5
r6
rspin col
c1
col
c2
col
col
col
c2
col
c1
col
c2
r1
State
Col A
Col B
Col C
c1
c2
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
6
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
PAC
PAC
Idle
PAC
Row
Col A
Col B
Col C
A[31:0]
RAS
A
B
C
CAS/DQM[7:0]
DSF
TRG/CAS
W
Col Sel A
Col Sel B
Col Sel C
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
A
B
C
CAS/DQM[7:0]
†
‡
Wait state inserted by external logic (example)
Internally generated pipeline bubble (example)
Figure 72. 2-Cycle/Column Block-Write-Cycle Timing
92
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
block-write cycles (continued)
†
‡
col
r1
r2
r3
r4
r5
r6
col
c1
col
c2
col
c3
col
c1
col
c2
col
c3
ci
col
c1
col
c2
col
c3
r1
State
Col A
Col B
Col C
c3
CLKOUT
CT[2:0]
7
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
PAC
PAC
Idle
PAC
STATUS[5:0]
RL
†
‡
Wait state inserted by external logic (example)
Internally generated pipeline bubble (example)
Figure 73. 3-Cycle/Column Block-Write-Cycle Timing
93
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles
Read-transfer (memory-to-register) cycles transfer a row from the VRAM memory array into the VRAM shift
register (sequential-access memory, or SAM). This causes the entire SAM (both halves of the split SAM) to be
loaded with the array data.
Split-register read-transfer (memory-to-split-register) cycles also transfer data from a row in the memory array
to the SAM. However, these transfers cause only half of the SAM to be written. Split-register read transfers allow
the inactive half of the SAM to be loaded with the new data while the other active half continues to shift data
in or out.
Write-transfer (register-to-memory) cycles transfer data from the SAM into a row of the VRAM array. This
transfer causes the entire SAM (both halves of the split SAM) to be written into the array.
Split-register write-transfer (split-register-to-memory) cycles also transfer data from the SAM to a row in the
memory array. However, these transfers write only half of the SAM into the array. Split-register write transfers
allow the inactive half of the SAM to be transferred into memory while the other (active) half continues to shift
serial data in or out.
Read and split-read transfers resemble a standard read cycle. Write and split-write transfers resemble a
standard write cycle. The TRG/CAS output is driven low prior to the fall of RAS to indicate a transfer cycle. Only
a single column access is performed so RETRY, while required to be at a valid level, has no effect if asserted
at column time. The value output on A[31:0] at column time represents the SAM tap point.
94
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
4
r3
r6
c1
c2
c3
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
Idle
RL
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
DSF
0 for Full Transfer, 1 for Split Transfer
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 74. Pipelined 1-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
95
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
c1
State
r1
r2
5
r3
r6
c2
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
Idle
RL
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
0 for Full Transfer, 1 for Split Transfer
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 75. Nonpipelined 1-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
96
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
6
r3
r5
r6
c1
c2
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
RL
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 76. 2-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
97
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
7
r3
r4
r5
r6
c1
c2
c3
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
RL
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
0 for Full Transfer, 1 for Split Transfer
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 77. 3-Cycle/Column Read-Transfer and Split-Register Read-Transfer-Cycle Timing
98
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
4
r3
r6
c1
drn
r1
rspin rspin
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Drain
Cycle Type
PAC
STATUS[5:0]
RL
Row
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 78. Pipelined 1-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
99
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
rspin
rspin
State
r1
r2
5
r3
r6
c1
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
PAC
STATUS[5:0]
RL
A[31:0]
Row
Tap Point
RAS
CAS/DQM[7:0]
DSF
0 for Full Transfer, 1 for Split Transfer
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 79. Nonpipelined 1-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
100
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
rspin
State
r1
r2
6
r3
r5
r6
c1
c2
rl
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
RL
A[31:0]
Tap Point
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 80. 2-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
101
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
transfer cycles (continued)
State
r1
r2
7
r3
r4
r5
r6
c1
c2
c3
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
RL
A[31:0]
Column
RAS
CAS/DQM[7:0]
0 for Full Transfer, 1 for Split Transfer
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
For user-modified timing:
UTIME
RAS
CAS/DQM[7:0]
Figure 81. 3-Cycle/Column Write-Transfer and Split-Register Write-Transfer-Cycle Timing
102
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles
Refresh cycles are generated by the TC at the programmed refresh interval. They are characterized by the
following signal activity:
D
D
D
D
D
D
CAS falls prior to RAS.
All CAS pins (CAS[7:0]) are active.
TRG, W, and DBEN all remain inactive (high) because no data transfer occurs.
DSF is active (high) at the fall of CAS and is driven inactive prior to the fall of RAS.
The data bus is driven to the high-impedance state.
The upper half of the address bus (A[31:16]) contains the refresh pseudo-address and the lower half
(A[15:0]) is driven to all zeros.
D
If RETRY is asserted at any sample point during the cycle, the cycle timing is not modified. Instead, the
pseudo-address and backlog counters are simply not decremented.
D
D
Selecting user-modified timing has no effect on the cycles.
Upon completion of the refresh cycle, the memory interface returns to state r1 to await the next access.
103
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ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles (continued)
State
r1
r2
r3
r6
r9
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
4/5
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
PAC
Refresh Pseudo Address
A[31:16]
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Figure 82. 1-Cycle/Column Refresh-Cycle Timing
104
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles (continued)
State
r1
r2
6
r3
r5
r6
r7
r9
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
PAC
Refresh Pseudo Address
A[31:16]
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Figure 83. 2-Cycle/Column Refresh-Cycle Timing
105
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
refresh cycles (continued)
State
r2
7
r3
r4
r5
r6
r7
r8
r9
r1
r1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
PAC
Refresh Pseudo Address
A[31:16]
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Figure 84. 3-Cycle/Column Refresh-Cycle Timing
106
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ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM-type cycles
The SDRAM-type cycles support the use of SDRAM, SGRAM, or SVRAM devices for single-cycle memory
accesses. While SDRAM cycles use the same state sequences as DRAM cycles, the memory-control signal
transitions are modified to perform SDRAM command cycles. The supported SDRAM commands are:
DCAB
ACTV
READ
WRT
MRS
Deactivate (precharge) all banks
Activate the selected bank and select the row
Input starting column address and start read operation
Input starting column address and start write operation
Set SDRAM mode register
REFR
SRS
Auto-refresh cycle with internal address
Set special register (color register)
Block write
BLW
SDRAM cycles begin with an activate (ACTV) command followed by the requested column accesses. When
a memory-page change occurs, the selected bank is deactivated with a DCAB command.
The SMJ320C80 supports CAS latencies of 2 or 3 cycles and burst lengths of 1 or 2. These are selected by the
CT code input at the start of the access.
The column pipelines for SDRAM accesses are shown in Figure 85. Idle cycles can occur after necessary
column accesses have completed or between column accesses due to “bubbles” in the TC data flow pipeline.
The pipeline diagrams show the pipeline stages for each access type and when the CAS/DQM signal
corresponding to the column access is activated.
107
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM type cycles (continued)
ꢅꢃ
ꢎ
ꢂ
ꢃ
ꢎ
ꢂ
ꢂ ꢃꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢊꢋ ꢃ ꢀ ꢍ
ꢂ ꢃ ꢄ ꢅ ꢆꢅ ꢇꢈ ꢉ
ꢀ ꢏ
ꢀ ꢍ
ꢀ ꢐ
ꢀ ꢏ
ꢀ ꢍ
ꢀ ꢯ
ꢀ ꢐ
ꢀ ꢏ
ꢀ ꢁ
ꢂ ꢊꢋ ꢃ ꢀꢍ
ꢂ ꢊꢋ ꢎ
ꢀꢏ
ꢀꢍ
ꢀꢐ
ꢀꢏ
ꢀꢍ
ꢂ ꢊꢋ ꢎ
ꢂ ꢊꢋ ꢂ
ꢑꢒ ꢋꢓ
ꢀ ꢯ
ꢀ ꢐ
ꢀ ꢁ
ꢀꢐ
ꢀꢏ
ꢀꢁ
ꢀ ꢯ
ꢀ ꢁ
ꢂ ꢊꢋ ꢂ
ꢀꢐ
ꢀꢁ
ꢀ ꢁ
ꢑꢒꢋꢓ
ꢀꢁ
Burst-length 1, 3-cycle latency reads, read
transfers, split-read transfers
Burst-length 1, 2-cycle latency reads, read
transfers, split-read transfers
ꢃ
ꢅꢝ ꢎꢡ
ꢂ
ꢝꢇ ꢡ
ꢛ
ꢅꢝ ꢱꢡ
ꢂ ꢃꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢊꢋ ꢃ ꢥ ꢎ ꢀ ꢍ
ꢂ ꢊꢋ ꢂ ꢥ ꢇ
ꢂ ꢊꢋ ꢛ ꢥ ꢱ
ꢑꢒ ꢋꢓ
ꢀ ꢏ
ꢌ
ꢀ ꢐ
ꢌ
ꢌ
ꢀ ꢏ
ꢌ
ꢃ
ꢅ ꢎ
ꢂ
ꢂꢃ ꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢀ ꢍ
ꢀ ꢐ
ꢌ
ꢂ ꢊꢋ ꢃ ꢀꢍ
ꢂ ꢊꢋ ꢎ
ꢌ
ꢀ ꢏ
ꢌ
ꢀꢍ
ꢀ ꢍ
ꢀ ꢐ
ꢌ
ꢀ ꢁ
ꢂ ꢊꢋ ꢂ
ꢀꢍ
ꢌ
ꢀ ꢁ
ꢑꢒꢋꢓ
ꢀꢁ
ꢀ ꢁ
Burst-length 1 writes, block writes, SRSs, write transfers,
split-write transfers
Burst-length 2, 2-cycle latency reads, read transfers,
split-read transfers
ꢃ
ꢅ ꢝ ꢎꢡ
ꢂ
ꢝ ꢇꢡ
ꢛ
ꢅ ꢝ ꢱꢡ
ꢃ
ꢅꢝ ꢎꢡ
ꢂ
ꢝꢇ ꢡ
ꢛ
ꢅꢝ ꢱꢡ
ꢂ ꢃ ꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢃꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢊꢋ ꢃ ꢥ ꢎ ꢀꢍ
ꢂ ꢊꢋ ꢂ ꢥ ꢇ
ꢂ ꢊꢋ ꢛ ꢥ ꢱ
ꢑꢒꢋꢓ
ꢀꢏ
ꢌ
ꢀꢐ
ꢌ
ꢀꢯ
ꢌ
ꢂ ꢊꢋ ꢃ ꢥ ꢎ ꢀ ꢍ
ꢂ ꢊꢋ ꢂ ꢥ ꢇ
ꢂ ꢊꢋ ꢛ ꢥ ꢱ
ꢑꢒ ꢋꢓ
ꢀ ꢏ
ꢌ
ꢌ
ꢀꢐ
ꢌ
ꢌ
ꢀꢍ
ꢀꢏ
ꢌ
ꢀꢯ
ꢌ
ꢀ ꢍ
ꢀ ꢏ
ꢌ
ꢌ
ꢀꢐ
ꢌ
ꢀꢁ
ꢌ
ꢀꢍ
ꢀꢏ
ꢌ
ꢀ ꢯ
ꢌ
ꢀ ꢁ
ꢀ ꢍ
ꢀ ꢏ
ꢌ
ꢌ
ꢀ ꢁ
ꢌ
ꢀ ꢁ
ꢀ ꢁ
ꢀ ꢁ
Burst-length 2, 3-cycle latency reads, read transfers,
split-read transfers
Burst-length 2, 3-cycle latency writes
ꢃ
ꢅ
ꢎ
ꢂ
ꢅ
ꢂ ꢃ ꢄ ꢅ ꢆꢅ ꢇ ꢈꢉ
ꢂ ꢊꢋ ꢃ ꢀꢍ
ꢌ
ꢂ ꢊꢋ ꢎ
ꢀꢍ
ꢌ
ꢂ
ꢊ
ꢋ
ꢂ
ꢀꢍ
ꢌ
ꢑꢒꢋꢓ
ꢀ
ꢁ
Burst-length 2, 3-cycle latency block-writes, write
transfers, split-write transfers
Figure 85. SDRAM Column Pipelines
special SDRAM cycles
To initialize the SDRAM properly, the SMJ320C80 performs two special SDRAM cycles after reset. The ’C80
first performs a deactivate cycle on all banks (DCAB) and then initializes the SDRAM mode register with a mode
register set (MRS) cycle. The CT code input at the start of the MRS cycle determines the burst length and latency
that is programmed into the SDRAM mode register.
108
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢅ
ꢈꢉ ꢊꢉ ꢋꢌꢍ ꢀꢉ ꢊ ꢎꢌꢍ ꢏꢐ ꢑ ꢆꢒ ꢀ ꢀꢑ ꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
special SDRAM cycles (continued)
r1
r2
r3
r5
r1
State
CLKOUT
0xx
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Figure 86. SDRAM Power-Up Deactivate Cycle Timing
109
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ
ꢈ ꢉꢊ ꢉꢋꢌ ꢍ ꢀꢉ ꢊꢎ ꢌ ꢍ ꢏ ꢐꢑ ꢆꢒ ꢀꢀ ꢑꢐ
SGUS025B – AUGUST 1998 – REVISED JUNE 2002
special SDRAM cycles (continued)
r1
r2
r3
r5
r1
State
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
0xx
FAULT
READY
RETRY
Figure 87. SDRAM Mode-Register-Set Cycle Timing
SDRAM read cycles
Read cycles begin with an activate (ACTV) command to activate the bank and to select the row. The TC outputs
the column address and activates the TRG/CAS strobe for each read command. For burst-length 1 accesses,
a read command can occur on each cycle. For burst-length 2 accesses, a read command can occur every two
cycles. The TC places D[63:0] into the high-impedance state, allowing it to be driven by the memory, and latches
input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the
appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. The CAS/DQM strobes are
activated two cycles before input data is latched. If the second column in a burst is not required, then CAS/DQM
is not activated. During peripheral device packet transfers, DBEN remains high.
110
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
r6
col
c1
col
col
col
col
r1
Col Pipe
Col A
Col B
Col C
Col D
c2
c1
c3
c2
c1
c3
c2
c1
c3
c2
c3
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
0
FAULT
READY
RETRY
Cycle Type
PAC
PAC
PAC
PAC
DCAB
STATUS[5:0]
RL
Row
Col A
Col B
Col C
Col D
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
A
B
C
D
0 For Normal Read, 1 For PDPT read
DBEN
DDIN
ACTV
READ
READ
READ
READ
DCAB
Command
Figure 88. SDRAM Burst-Length 1, 2-Cycle Latency Read-Cycle Timing
111
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
r6
col
c1
col
col
col
col
col
r1
Col Pipe
Col A
Col B
Col C
Col D
c2
c1
c3
c2
c1
c4
c3
c2
c1
c4
c3
c2
c4
c3
c4
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
1
FAULT
READY
RETRY
Cycle Type
PAC
PAC
PAC
PAC
Idle
DCAB
STATUS[5:0]
RL
Row
Col A
Col B
Col C
Col D
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
A
B
C
D
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
ACTV
READ
READ
READ
READ
DCAB
Command
Figure 89. SDRAM Burst-Length 1, 3-Cycle Latency Read-Cycle Timing
112
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
r6
col
c1
col
col
col
col
r1
Col Pipe
Col A
Col B
Col C
Col D
c2
c1
c3
c2
c1
c3
c2
c1
c3
c2
c3
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
2
FAULT
READY
RETRY
Cycle Type
PAC
DCAB
PAC
STATUS[5:0]
RL
Row
Col A
(Col B)
Col C
(Col D)
A[31:0]
RAS
A
B
C
C, D
A
D
CAS/DQM[7:0]
DSF
A, B
TRG/CAS
W
D[63:0]
B
C
D
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
ACTV
READ
READ
DCAB
Command
Figure 90. SDRAM Burst-Length 2, 2-Cycle Latency Read-Cycle Timing
113
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM read cycles (continued)
State
r1
r2
r3
r5
r6
col
c1
col
col
col
col
col
r1
Col Pipe
Col A
Col B
Col C
Col D
c2
c1
c3
c2
c1
c4
c3
c2
c1
c4
c3
c2
c4
c3
c4
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
3
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
PAC
PAC
Idle
DCAB
RL
A[31:0]
Row
Col A
(Col B)
Col C
(Col D)
RAS
A
B
C
D
CAS/DQM[7:0]
DSF
A, B
C, D
TRG/CAS
W
D[63:0]
A
B
C
D
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
ACTV
READ
READ
DCAB
Command
Figure 91. SDRAM Burst-Length 2, 3-Cycle Latency Read-Cycle Timing
114
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM write cycles
Write cycles begin with an activate (ACTV) command to activate the bank and select the row. The TC outputs
the column address and activates the TRG/CAS and W strobes for each write command. For burst-length 1
accesses, a write command can occur on each cycle. For burst-length 2 accesses, a write command can occur
every two cycles. The TC drives data out on D[63:0] during each cycle of an active-write command and indicates
valid bytes by driving the appropriate CAS/DQM strobes low. During peripheral device packet transfers, DBEN
remains high and D[63:0] are placed in the high-impedance state so that the peripheral can drive data into the
memories.
115
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM write cycles (continued)
State
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
Col D
col
c1
col
c1
col
c1
col
c1
col
col
r1
Col Pipe
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
0,1
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
Col A
A
PAC
Col B
B
PAC
Col C
C
PAC
Idle
DCAB
RL
A[31:0]
Col D
RAS
D
D
D
CAS/DQM[7:0]
DSF
A
B
C
TRG/CAS
W
D[63:0]
A
B
C
0 For Normal Read, 1 For PDPT Read
DBEN
DDIN
ACTV
WRT
WRT
WRT
WRT
DCAB
Command
Figure 92. SDRAM Burst-Length 1 Write-Cycle Timing
116
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM write cycles (continued)
State
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
Col D
col
c1
col
c1
col
c1
col
c1
col
col
r1
Col Pipe
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
2, 3
FAULT
READY
RETRY
PAC
PAC
STATUS[5:0]
Cycle Type
Row
Idle
DCAB
RL
A[31:0]
Col A (Col B) Col C
(Col D)
RAS
A
A, B
A
B
C
C, D
C
D
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
B
D
DBEN
DDIN
ACTV
WRT
WRT
DCAB
Command
Figure 93. SDRAM Burst-Length 2 Write-Cycle Timing
117
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
special register set cycles
Special register set (SRS) cycles are used to program control registers within an SVRAM or SGRAM. The ’C80
only supports programming of the color register for use with block-writes. The cycle is similar to a single
burst length 1 write cycle but DSF is driven high. The values output on the ’C80 address bits cause the color
register to be selected as shown in Figure 94.
SDRAM Address Pin
SDRAM Function
BS
0
A8
0
A7
0
A6
LC
1
A5
LM
0
A4
LS
0
A3
A2
A1
A0
Stop Register
SMJ320C80 Output Value
0
0
0
0
0
0
0
Figure 94. Special-Register-Set Value
r1
r2
r3
r6
rspin
rspin
col
c1
r1
State
Col Pipe
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
0xx
FAULT
READY
RETRY
STATUS[5:0]
RL
Cycle Type
PAC
SRS
Row
A[31:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
Color
D[63:0]
DBEN
DDIN
SRS
Command
Figure 95. SDRAM SRS-Cycle Timing
118
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM block-write cycles
Block-write cycles allow SVRAMs and SGRAMs to write a stored color value to multiple column locations in a
single access. Block-write cycles are similar to write cycles except that DSF is driven high to indicate a
block-write command. Because burst is not supported for block-write, burst-length 2 accesses generate a single
block-write every other clock cycle.
State
r1
r2
r3
r5
r6
rspin
Col A
Col B
Col C
Col D
col
col
col
col
col
col
r1
Col Pipe
c1
c1
c1
c1
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
0,1
FAULT
READY
RETRY
STATUS[5:0]
Cycle Type
Row
PAC
PAC
PAC
PAC
Idle
DCAB
RL
A[31:0]
Col A
Col B
Col C
Col D
RAS
A
A
B
B
C
C
D
D
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
Sel A
Sel B
Sel C
Sel D
DBEN
DDIN
ACTV
BLKW BLKW BLKW BLKW
DCAB
Command
Figure 96. SDRAM Burst-Length 1 Block-Write Cycle Timing
119
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM block-write cycles (continued)
State
r1
r2
r3
r5
r6
rspin
Col A
Col B
col
c1
col
col
c1
col
col
col
r1
Col Pipe
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
2, 3
FAULT
READY
RETRY
PAC
PAC
STATUS[5:0]
Cycle Type
Row
Idle
DCAB
RL
A[31:0]
Col A
Col B
RAS
A
B
CAS/DQM[7:0]
DSF
A
B
TRG/CAS
W
D[63:0]
Sel A
Sel B
DBEN
DDIN
ACTV
BLKW
BLKW
DCAB
Command
Figure 97. SDRAM Burst-Length 2 Block-Write Cycle Timing
120
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles
The SVRAM read- and write-transfer cycles transfer data between the SVRAM memory-array and the serial
register (SAM). The SMJ320C80 supports both normal and split transfers for SVRAMs. Read- and split-read
transfers resemble a standard read cycle. Write- and split-write transfers resemble a standard write cycle.
Because the ’C80’s TRG output is used as CAS, external logic must generate a TRG signal (by decoding
STATUS) to enable the SVRAM transfer cycle. The value output on A[31:0] at column time represents the SAM
tap point.
r1
r2
r3
r5
r6
col
c1
col
c2
r1
State
c3
Col Pipe
CLKOUT
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
000
FAULT
READY
RETRY
Cycle Type
Row
STATUS[5:0]
PAC
DCAB
RL
A[31:0]
RAS
Tap Pt.
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
RTR
DCAB
Command
Figure 98. SVRAM Burst-Length 1, 2-Cycle Latency Read-Transfer Cycle Timing
121
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
r1
r2
r3
r5
r6
col
c1
col
c2
col
c3
r1
State
Col Pipe
CLKOUT
CT[2:0]
001
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
Idle
DCAB
STATUS[5:0]
RL
A[31:0]
RAS
Tap Pt.
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
RTR
DCAB
Command
Figure 99. SVRAM Burst-Length 1, 3-Cycle Latency Read-Transfer Cycle Timing
122
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
r1
r2
r3
r5
r6
col
c1
col
c2
col
c3
r1
State
Col Pipe
CLKOUT
CT[2:0]
010
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
Idle
DCAB
STATUS[5:0]
RL
A[31:0]
RAS
Tap Pt.
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
RTR
DCAB
Command
Figure 100. SVRAM Burst-Length 2, 2-Cycle Latency Read-Transfer Cycle Timing
123
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
r1
r2
r3
r5
r6
col
col
c1
col
c2
col
c3
r1
State
Col Pipe
CLKOUT
CT[2:0]
011
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
Idle
DCAB
STATUS[5:0]
RL
A[31:0]
RAS
Tap Pt.
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
RTR
DCAB
Command
Figure 101. SVRAM Burst-Length 2, 3-Cycle Latency Read-Transfer Cycle Timing
124
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
r1
r2
r3
r5
r6
col
c1
col
col
r1
State
Col Pipe
CLKOUT
CT[2:0]
00x
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
Idle
DCAB
STATUS[5:0]
RL
A[31:0]
RAS
Tap Pt.
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
WTR
DCAB
Command
Figure 102. SVRAM Burst-Length 1, Write-Transfer Cycle Timing
125
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SVRAM transfer cycles (continued)
r1
r2
r3
r5
r6
col
c1
col
col
col
r1
State
Col Pipe
CLKOUT
CT[2:0]
01x
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
Row
PAC
Idle
DCAB
STATUS[5:0]
RL
A[31:0]
RAS
Tap Pt.
CAS/DQM[7:0]
DSF
0 For Full, 1 For Split
TRG/CAS
W
D[63:0]
DBEN
DDIN
ACTV
WTR
DCAB
Command
Figure 103. SVRAM Burst-Length 2, Write-Transfer Cycle Timing
SDRAM refresh cycle
The SDRAM refresh cycle is performed when the TC receives an SDRAM cycle timing input (CT=0xx) at the
start of a refresh cycle. The RAS and TRG/CAS outputs are driven low for one cycle to strobe a refresh
command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The ’C80 outputs
a 16-bit pseudo-address (used for refresh bank decode) on A[31:16] and drives A[15:0] low.
126
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
SDRAM refresh cycle (continued)
r1
r2
r3
r5
r6
r9
r1
State
CLKOUT
0xx
CT[2:0]
AS[2:0]
BS[1:0]
PS[3:0]
UTIME
FAULT
READY
RETRY
Cycle Type
PAC
STATUS[5:0]
RL
Refresh Pseudo-Address
A[31:16]
A[15:0]
RAS
CAS/DQM[7:0]
DSF
TRG/CAS
W
D[63:0]
DBEN
DDIN
Command
REFR
Figure 104. SDRAM Refresh Cycle Timing
127
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SGUS025B – AUGUST 1998 – REVISED JUNE 2002
host interface
The ’C80 contains a simple four-pin mechanism by which a host or another device can gain control of the ’C80
local memory bus. The HREQ input can be driven low by the host to request the ’C80’s bus. Once the TC has
completed the current memory access, it places the local bus (except CLKOUT) into a high-impedance state.
It then drives the HACK output low to indicate that the host device owns the bus and can drive it. The REQ[1:0]
outputs reflect the highest-priority cycle request being received internally by the TC. The host can monitor these
outputs to determine if it needs to relinquish the local bus back to the ’C80.
Table 37. TC Priority Cycles
REQ[1:0]
ASSOCIATED INTERNAL TC REQUEST
SRT, urgent refresh, XPT, or VCPT
11
10
01
00
Cache/DEA request, urgent packet transfer
High-priority packet transfer
Low-priority packet transfer, trickle refresh, idle
device reset
The SMJ320C80 is reset when the RESET input is driven low. The ’C80 outputs immediately go into a
high-impedance state with the exception of CLKOUT, HACK, and REQ[1:0]. While RESET is low, all internal
registers are set to their default values and internal logic is reset.
On the rising edge of RESET, the state of UTIME is sampled to determine if big-endian (UTIME = 0) or
little-endian (UTIME = 1) operation is selected. Also, on the rising edge of RESET, the state of HREQ is sampled
to determine if the master processor comes up running (HREQ = 0) or halted (HREQ = 1).
Once RESET is high, the ’C80 drives the high-impedance signals to their inactive values. The TC then performs
32 refresh cycles to initialize system memory. If, during initialization refresh, the TC receives an SDRAM cycle
timing code (CT = 0xx), it performs an SDRAM DCAB cycle and a MRS cycle to initialize the SDRAM, and then
continues the refresh cycles.
After completing initialization refresh, if the MP is running, the TC performs its instruction-cache-fill request to
fetch the cache block beginning at 0xFFFFFFC0. This block contains the starting MP instruction located at
0xFFFFFFF8. If the MP comes up halted, the instruction cache fill does not take place until the first occurrence
of an EINT3 interrupt to unhalt the MP.
128
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
†
absolute maximum ratings over specified temperature ranges (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
I
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Case temperature, T (M-temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
C
(A-temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
3.135
0
3.3 3.465
DD
Supply voltage (see Note 2)
High-level output current
Low-level output current
0
0
–400
2
V
SS
I
I
µA
mA
OH
OL
M-temperature
A-temperature
–55
–40
125
85
T
C
Case temperature
°C
NOTE 2: To minimize noise on V , care should be taken to provide a minimum inductance path between the V
SS
pins and system ground.
SS
electrical characteristics over recommended range of supply voltage and specified temperature
(unless otherwise noted)
§
‡
PARAMETER
High-level input voltage
MIN
2
TYP
MAX
+ 0.3
UNIT
TEST CONDITIONS
V
V
V
V
V
V
V
V
V
IH
DD
0.8
Low-level input voltage
High-level output voltage
Low-level output voltage
–0.3
2.2
IL
V
V
V
V
= MIN,
= MAX
= MAX,
= MAX,
I = MAX
OH
OH
OL
DD
DD
DD
DD
0.8
20
V
V
= 2.8 V
= 0.6 V
Output current, leakage (high impedance)
(except EMU0 and EMU1)
O
I
O
µA
–20
±20
2.5
O
I
I
Input current (except TCK, TDI, and TMS), TRST
Supply current (see Note 3)
Input capacitance
V = V
SS
to V
DD
µA
A
I
I
§
1
§
10
§
10
V
DD
= MAX,
50 MHz
DD
C
C
pF
pF
i
Output capacitance
o
‡
§
¶
For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
All typical values are at V = 3.3 V, T = 25°C
DD
A
Typical steady-state V
will not exceed V
OH
DD
NOTE 3: Maximum supply current is derived from a test case that generates the theoretical maximum data flow using a worst case checkerboard
data pattern on a sustained cycle by cycle basis. Actual maximum I varies in real applications based on internal and external data
DD
flow and transitions. Typical supply current is derived from a test case which attempts to emulate typical use conditions of the on-chip
processors with random data. Typical I
utilization.
varies from application to application based on data flow and transitions and on-chip processor
DD
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
LOAD
C
T
I
OH
Where:
I
I
V
=
=
=
=
2.0 mA (all outputs)
400 µA (all outputs)
1.5 V
OL
OH
LOAD
T
C
60 pF typical load circuit capacitance
Figure 105. Test Load Circuit
signal transition levels
TTL-output levels are driven to a minimum logic-high level of 2.2 V and to a maximum logic-low level of
0.8 V. Figure 106 shows the TTL-level outputs.
2.2 V
1.75 V
1.0 V
0.8 V
Figure 106. TTL-Level Outputs
TTL-output transition times are specified as follows:
D
D
For a high-to-low transition, the level at which the output is said to be no longer high is 1.75 V, and the level
at which the output is said to be low is 1.0 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1.0 V, and the level
at which the output is said to be high is 1.75 V.
Figure 107 shows the TTL-level inputs.
2 V
0.8 V
Figure 107. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
D
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2 V, and the level at which the input is said to be low is 0.8 V.
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V, and the level at which the input is said to be high is 2 V.
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
A[31:0]
RDY
RST
RTY
REQ
RL
READY
RESET
RETRY
REQ[1:0]
RL
CAS
CFG
CKI
CKO
CMP
D
CAS/DQM[7:0]
AS[2:0], BS[1:0], CT[2:0], PS[3:0], UTIME
CLKIN
CLKOUT
RETRY, READY, FAULT
D[63:0]
RR
READY, RETRY
SCLK0, SCLK1
TCK
SCK
TCK
TDI
EIN
EMU
FCK
HAK
HRQ
LIN
EINT1, EINT2, EINT3, or EINTx
EMU0, EMU1
FCLK0, FCLK1
HACK
TDI
TDO
TMS
TRS
UTM
SI
TDO
TMS
HREQ
TRST
LINT4
UTIME
MID
A[31:0], STATUS[5:0]
HSYNC0, VSYNC0, CSYNC0, HSYNC1, VSYNC1,
or CSYNC1
OUT
RAS
A[31:0], CAS/DQM[7:0], D[63:0], DBEN, DDIN,
DSF, RAS, RL, STATUS[5:0], TRG/CAS, W
SY
HSYNC0, VSYNC0, CSYNC0/HBLNK0,
CBLNK0/VBLNK0, HSYNC1, VSYNC1,
CSYNC1/HBLNK1, CBLNK1/VBLNK1, CAREA0, or
CAREA1
RAS
XPT
XPT[2:0] OR XPTx
Lowercase subscripts and their meanings are:
The following letters and symbols and their meanings are:
a
c
access time
H
L
High
cycle time (period)
delay time
Low
d
h
su
t
V
Z
X
Valid
hold time
High impedance
setup time
Unknown, changing, or don’t care level
transition time
pulse duration (width)
w
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
general notes on timing parameters
The period of the output clock (CLKOUT) is twice the period of the input clock (CLKIN), or 2 × t
. The half
c(CKI)
cycle time (t ) that appears in the following tables is one-half of the output clock period, or equal to the input
H
clock period, t
.
c(CKI)
All output signals from the ’C80 (including CLKOUT) are derived from an internal clock such that all output
transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
CLKIN timing requirements (see Figure 108)
NO
1
MIN
10
MAX
UNIT
ns
t
t
t
t
Period of CLKIN (t )
H
c(CKI)
2
Pulse duration of CLKIN high
Pulse duration of CLKIN low
Transition time of CLKIN
4.2
4.2
ns
w(CKIH)
w(CKIL)
t(CKI)
3
ns
4
1.5*
ns
* This parameter is not production tested.
1
4
2
4
CLKIN
3
Figure 108. CLKIN Timing
local-bus switching characteristics over full operating range: CLKOUT† (see Figure 109)
NO
5
PARAMETER
MIN
MAX
UNIT
ns
‡*
t
t
t
t
Period of CLKOUT
2t
c(CKI)
c(CKO)
6
Pulse duration of CLKOUT high
Pulse duration of CLKOUT low
Transition time of CLKOUT
t –4.5
H
ns
w(CKOH)
w(CKOL)
t(CKO)
7
t –4.5
H
ns
8
2.5*
ns
†
‡
The CLKOUT output has twice the period of CLKIN. No propagation delay or phase relationship to CLKIN is ensured. Each state of a memory
access begins on the falling edge of CLKOUT.
This parameter can also be specified as 2t .
H
* This parameter is not production tested.
t
t
t
t
H
H
6
H
H
5
8
8
CLKOUT
7
Figure 109. CLKOUT Timing
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
device reset timing requirements (see Figure 110)
NO
MIN
MAX
UNIT
ns
Initial reset during power-up
Reset during active operation
6t
6t
4t
h
9
t
Pulse duration, RESET low
w(RSTL)
ns
h
10
11
12
13
t
t
t
t
Setup time of HREQ low to RESET high to configure self-bootstrap mode
Hold time, HREQ low after RESET high to configure self-bootstrap mode
Setup time of UTIME low to RESET high to configure big-endian operation
Hold time, UTIME low after RESET high to configure big-endian operation
ns
su(HRQL-RSTH)
h(RSTH-HRQL)
su(UTML-RSTH)
h(RSTH-UTML)
h
0
ns
4t
h
0
ns
ns
9
RESET
10
11
13
HREQ
UTIME
12
Figure 110. Device-Reset Timing
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing requirements: cycle configuration inputs (see Figure 111)
The cycle configuration inputs are sampled at the beginning of each row access during the r2 state. The inputs
typically are generated by a static decode of the A[31:0] and STATUS[5:0] outputs.
NO
14
MIN
8
MAX
UNIT
ns
t
t
Setup time, AS, BS, CT, PS, and UTIME valid to CLKOUT no longer low
Hold time, AS, BS, CT, PS, and UTIME valid after CLKOUT high
su(CFGV-CKOH)
15
2
ns
h(CKOH-CFGV)
Access time, AS, BS, CT, PS, and UTIME valid after memory identification
(A, STATUS) valid
16
t
3t – 10
H
ns
a(MIDV-CFGV)
t
t
t
t
t
t
H
H
H
H
H
H
CLKOUT
Cycle Type
STATUS[5:0]
A[31:0]
RL
Row Address
15
16
14
Valid
Valid
Valid
Valid
Valid
AS[2:0]
BS[1:0]
CT[2:0]
PS[3:0]
UTIME
Figure 111. Local Bus Timing: Cycle Configuration Inputs
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (see Figure 112 and Figure 113)
The cycle completion inputs are sampled at the beginning of each row access at the start of the r3 state. The
READY input is sampled also at the start of the r6 state and during each column access (2 and 3 cyc/col
accesses only). The RETRY input is sampled on each CLKOUT falling edge following r3. The value n as used
in the parameters represents the integral number of half cycles between the transitions of the two signals in
question.
NO
MIN
MAX
nt –8
UNIT
Access time, RETRY, READY, FAULT valid after memory identification
(A, STATUS) valid
17
t
ns
a(MIDV-CMPV)
H
18
19
20
21
t
t
t
t
Setup time, RETRY, READY, FAULT valid to CLKOUT no longer high
Hold time, RETRY, READY, FAULT valid after CLKOUT low
Access time RETRY, READY valid from RAS low
7.5
1.2
ns
ns
ns
ns
su(CMPV-CKOL)
h(CKOL-CMPV)
a(RASL-RRV)
a(RLL-RRV)
nt –7.5
H
Access time, RETRY, READY valid from RL low
nt –7.5
H
2 cyc/col accesses
3 cyc/col accesses
t –12
H
22
t
ns
Access time, READY valid from CAS low
a(CASL-RRV)
2t –8
H
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (continued)
t
t
t
t
t
t
t
t
t
t
H
H
H
H
H
H
H
H
H
H
CLKOUT
STATUS[5:0]
A[31:0]
RL
RAS
17
18
21
20
19
RETRY
READY
FAULT
Figure 112. Local Bus Timing: Row-Time Cycle Completion Inputs
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: cycle completion inputs (continued)
t
t
t
t
t
t
t
t
t
t
H
H
H
H
H
H
H
H
H
H
CLKOUT
STATUS[5:0]
A[31:0]
CAS/DQM[7:0]
18
22
19
17
READY
RETRY
Figure 113. Local Bus Timing: Column-Time Cycle Completion Inputs
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
general output signal characteristics over operating conditions
The following general timing parameters apply to all SMJ320C80 output signals unless otherwise specifically
given. The value n as used in the parameters represents the integral number of half cycles between the
transitions of the two outputs in question. For timing purposes, outputs fall into one of three groups – the data
bus (D[63:0]); the other output buses (A[31:0], STATUS[5:0], CAS/DQM[7:0]; and non-bus outputs (DBEN, RL,
DDIN, DSF, RAS, TRG/CAS, W). When measuring output to output, the named group refers to the second
output to transition (output B), and the first output (output A) refers to any output group.
NO
PARAMETER
MIN
nt –5.6
MAX
UNIT
Hold time, CLKOUT high after output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
H
†
23
t
t
nt –5.0
ns
h(OUTV-CKOL)
H
nt –4.3
H
Hold time, CLKOUT low after output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
nt –5.6
H
†
24
nt –5.0
ns
h(OUTV-CKOH)
H
nt –4.3
H
25
26
t
t
Hold time, output valid after CLKOUT low
Hold time, output valid after CLKOUT high
nt –5.5
ns
ns
h(CKOL-OUTV)
H
nt –5
H
h(CKOH-OUTV)
Hold time, output valid after output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
nt –6.5
H
H
nt –5
H
†
27
28
29
t
t
t
nt –6.0
ns
ns
ns
h(OUTV-OUTV)
d(CKOH-OUTV)
d(CKOL-OUTV)
Delay time, CLKOUT no longer low to output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS,TRG/CAS, W, RL
nt +6.5
H
H
nt +5
H
†
nt +5.5
Delay time, CLKOUT no longer high to output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS,TRG/CAS, W, RL
nt +6.5
H
†
nt +5.5
nt +5
H
H
30
31
t
t
Delay time, output no longer valid to CLKOUT high
Delay time, output no longer valid to CLKOUT low
nt +5
ns
ns
d(OUTV-CKOH)
H
nt +5.5
H
d(OUTV-CKOL)
Delay time, output no longer valid to output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
nt +6.5
H
H
nt +5
H
†
32
33
t
nt +6.0
ns
ns
d(OUTV-OUTV)
Pulse duration, output valid D[63:0]
A[31:0], STATUS[5:0], CAS/DQM[7:0]
DBEN, DDIN, DSF, RAS, TRG/CAS, W, RL
nt –6.5
H
†
nt –6.0
H
t
w(OUTV)
nt –5.0
H
†
Except for CAS/DQM[7:0] during nonuser-timed 2-cycle/column accesses
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
general output signal characteristics over operating conditions (continued)
t
t
t
t
t
t
t
t
t
t
t
t
H
H
H
H
H
H
H
H
H
H
H
H
CLKOUT
30
26
28
24
Output A
25
31
32
23
27
29
Output B
33
Figure 114. General Output-Signal Timing
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
data input timing (see Figure 115)
The following general timing parameters apply to the D[63:0] inputs unless otherwise specifically given. The
value n as used in the parameters represents the integral number of half cycles between the transitions of the
output and input in question.
NO
34
35
36
37
38
39
PARAMETER
MIN
MAX
nt –5.3
UNIT
ns
t
t
t
t
t
t
Access time, CLKOUT high to D[63:0] valid
Access time, CLKOUT low to D[63:0] valid
Setup time, D[63:0] valid to CLKOUT no longer low
Setup time, D[63:0] valid to CLKOUT no longer high
Hold time, D[63:0] valid after CLKOUT low
Hold time, D[63:0] valid after CLKOUT high
a(CKOH-DV)
a(CKOL-DV)
su(DV-CKOH)
su(DV-CKOL)
h(CKOL-DV)
h(CKOH-DV)
H
nt –6.5
H
ns
6.1
6.1
2
ns
ns
ns
2
ns
†
Access time, output valid to D[63:0] inputs valid A[31:0], CAS/DQM[7:0] ,
STATUS[5:0], RL
DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W
nt –7
H
40
t
ns
ns
a(OUTV-DV)
nt –6.5
H
‡
41
t
Hold time, D[63:0] valid after output valid RAS, CAS/DQM[7:0], A[31:0]
3
h(OUTV-DV)
†
‡
Except CAS/DQM[7:0] during nonuser-timed 2-cycle/column accesses
Applies to RAS, CAS/DQM[7:0], and A[31:0] transitions that occur on CLKOUT edge coincident with input data sampling
t
t
t
t
t
t
t
t
t
t
t
t
H
H
H
H
H
H
H
H
H
H
H
H
CLKOUT
38
39
37
36
34
35
D[63:0]
41
40
Output
Figure 115. Data-Input Timing
140
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
local bus timing: 2-cycle/column CAS timing
These timing parameters apply to the CAS/DQM[7:0] signals during 2-cycle-per-column memory accesses
only. They should be used in place of the general output and data input timing parameters when the
2-cycle/column (nonuser-timed) cycle timing is selected (CT[2:0] inputs = 0b110). The value n as used in the
parameters represents the integral number of half cycles between the transitions of the signals in question.
NO
42
MIN
t –2
MAX
UNIT
ns
t
t
Pulse duration, CAS/DQM high
Pulse duration, CAS/DQM low
w(CASH)
H
43
3t –9.5
H
ns
w(CASL)
Hold time, CAS/DQM high after output valid
D[63:0]
A[31:0], STATUS[5:0]
nt –4.5
H
44
t
ns
h(OUTV-CASL)
nt –4.0
H
DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W
nt –3
H
45
46
47
t
t
t
Hold time, output valid after CAS/DQM low
Access time, data valid from CAS/DQM low
Hold time, data valid after CAS/DQM high
nt –9.5
ns
ns
ns
h(CASL-OUTV)
a(CASL-DV)
h(CASH-DV)
H
3t –12
H
2
t
t
t
t
t
t
t
t
t
t
H
H
H
H
H
H
H
H
H
H
CLKOUT
42
43
CAS/DQM[7:0]
44
45
Output
47
46
D[63:0]
Figure 116. 2-Cycle/Column CAS Timing
141
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
external interrupt timing (see Figure 117)
The following description defines the timing of the edge-triggered interrupts EINT1 – EINT3 and the
level-triggered interrupt LINT4 (see Note 4).
NO
48
49
50
51
MIN
MAX UNIT
t
t
t
t
Pulse duration, EINTx low
6*
ns
ns
ns
ns
w(EINL)
†
9.5
Setup time, EINTx high before CLKOUT no longer low
Pulse duration, EINTx high
su(EINH-CKOH)
w(EINH)
6*
†
9.5
Setup time, LINT4 low before CLKOUT no longer high
su(LINL-CKOL)
†
This parameter must only be met to ensure that the interrupt is recognized on the indicated cycle.
* This parameter is not production tested.
NOTE 4: In order to ensure recognition, LINT4 must remain low until cleared by the interrupt service routine.
Interrupt Recognized
CLKOUT
49
50
EINTx
LINT4
51
48
Figure 117. External Interrupt Timing
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
XPT input timing (see Figure 118 and Figure 119)
The following description defines the sampling of the XPT[2:0] inputs. The value encoded on the XPT[2:0]inputs
is synchronized over multiple cycles to ensure that a stable value is present.
NO
52
53
54
55
MIN
12t
MAX
UNIT
ns
t
t
t
t
Pulse duration, XPTx valid
w(XPTV)
H*
†
12
Setup time, XPT[2:0] valid before CLKOUT no longer low
Hold time, XPT[2:0] valid after CLKOUT high
Hold time, XPT[2:0] valid after RL low
ns
su(XPTV-CKOH)
h(CKOH-XPTV)
h(RLL-XPTV)
5
ns
‡
6t
H *
ns
†
‡
This parameter must only be met to ensure that the XPT input is recognized on the indicated cycle.
This parameter must be met to ensure that a second XPT request does nor occur.
* This parameter is not production tested.
XPT Inputs Sampled
XPT Inputs Recognized
CLKOUT
53
54
52
XPT[2:0]
Figure 118. XPT Input Timing – XPT Recognition
CLKOUT
STATUS[5:0]
XPTn Row Status
RL
55
XPT[2:0]
XPTn
XPTz
Figure 119. XPT Input Timing – XPT Service
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
host-interface timing (see Figure 120)
’C80-40
MIN
NO
UNIT
MAX
56
57
58
t
t
t
Setup time, REQ1–REQ0 valid to CLKOUT no longer low
Hold time, REQ1–REQ0 valid after CLKOUT high
Hold time for HACK high after HREQ goes low*
t
t
– 7
– 7
ns
ns
ns
su(REQV-CKOH)
h(CKOH-REQV)
h(HRQL-HAKL)
H
H
4t – 12*
H
All signals except D[63:0]
D[63:0]
1*
1*
59
t
Delay time, HACK low to output hi-Z
ns
ns
d(HAKL-OUTZ)
60
61
62
t
t
t
Delay time, HREQ high to HACK no longer low
10
d(HRQH-HAKH)
d(HAKH-OUTD)
su(HRQL-CKOH)
†
Delay time, HACK high to outputs driven
Setup time, HREQ low to CLKOUT no longer low (see Note 5)
6t
H
8.5
ns
* This parameter is not production tested.
NOTE 5: Parameter must be met only to ensure HREQ recognition during the indicated clock cycle.
HREQ Sampled
CLKOUT
56
57
REQ[1:0]
62
HREQ
58
60
HACK
61
59
A[31:0]
RL, TRG,
WE, DSF,
DSF2, DBEN
RAS
CAS[7:0]
D[63:0]
DDIN
Figure 120. Host-Interface Timing
144
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: SCLK timing (see Figure 121)
NO
MIN
13
5
MAX
UNIT
ns
63
64
65
66
t
t
t
t
SCLK period
c(SCK)
Pulse duration, SCLK high
Pulse duration, SCLK low
Transition time, SCLK (rise and fall)
ns
w(SCKH)
w(SCKL)
t(SCK)
5
ns
2*
ns
* This parameter is not production tested.
63
66
64
66
SCLK0
SCLK1
65
Figure 121. Video Interface Timing: SCLK Timing
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: FCLK input and video outputs (see Note 6 and Figure 122)
NO
67
68
69
70
MIN
MAX
UNIT
ns
t
t
t
t
FCLK period
25
8
c(FCK)
Pulse duration, FCLK high
Pulse duration, FCLK low
Transition time, FCLK (rise and fall)
ns
w(FCKH)
w(FCKL)
t(FCK)
8
ns
2*
ns
Hold time, HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK, or CAREA high after FCLK
low
71
72
73
74
t
t
t
t
0
0
ns
ns
ns
ns
h(FCKL-SYL)
h(FCKL-SYH)
d(FCKL-SYL)
d(FCKL-SYH)
Hold time, HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK, or CAREA low after FCLK
low
Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK,
or CAREA low
20
20
Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC/HBLNK, CBLNK/VBLNK,
or CAREA high
* This parameter is not production tested.
NOTE 6: Under certain circumstances, these outputs also can transition asynchronously. These transitions occur when controller timing register
values are modified by user programming. If the new register value forces the output to change states, then this transition occurs without
regard to FCLK inputs.
70
68
70
67
69
FCLK0
FCLK1
74
72
73
71
HSYNCn, VSYNCn,
CSYNCn/HBLNKn
CBLNKn/VBLNKn
CAREAn
Figure 122. Video Interface Timing: FCLK Input and Video Outputs
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
video interface timing: external sync inputs (see Figure 123)
When configured as inputs, the HSYNCn, VSYNCn, and CSYNCn signals may be driven asynchronously. The
following parameters apply only when the inputs are being generated synchronous to FCLKn in order to ensure
recognition on a particular FLCKn edge.
NO
75
76
77
78
MIN
5
MAX
UNIT
ns
†
Setup time, HSYNC, VSYNC, or CSYNC low to FCLK no longer low
t
t
t
t
su(SIL-FCKH)
h(FCKH-SIL)
su(SIH-FCKH)
h(FCKH-SIH)
‡
Hold time, HSYNC, VSYNC, or CSYNC high after FCLK high
Setup time, HSYNC, VSYNC, or CSYNC high to FCLK no longer low
7
ns
§
5
ns
¶
Hold time, HSYNC, VSYNC, or CSYNC low after FCLK high
7
ns
†
‡
§
¶
This parameter must be met only to ensure the input is recognized as low at FLCK edge B.
This parameter must be met only to ensure the input is recognized as high at FLCK edge A.
This parameter must be met only to ensure the input is recognized as high at FLCK edge D.
This parameter must be met only to ensure the input is recognized as low at FLCK edge C.
A
B
C
D
FCLK0
FCLK1
76
77
78
HSYNC0, HSYNC1
VSYNC0, VSYNC1
CSYNC0, CSYNC1
(Inputs)
75
Figure 123. Video Interface Timing: External Sync Inputs
147
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator interface connection
The ’C80 supports emulation through a dedicated emulation port that is a superset of the IEEE Standard 1149.1
(JTAG) Standard. To support the ’C80 emulator, a target system must include a 14-pin header (2 rows of 7 pins)
with the connections shown in Figure 124. Table 38 describes the emulation signal.
TMS
TDI
TRST
GND
1
2
4
Pin Spacing: 0.100 in. (X,Y)
Pin Width: 0.025 in, square post
Pin Length: 0.235 in. nominal
(see Table 38)
3
PD(+3.3V)
TDO
No pin (key)
GND
5
6
7
8
TCKRET
TCK
GND
9
10
12
14
GND
11
13
EMU0
EMU1
Figure 124. Target System Header
Table 38. Target Connectors
XDS510
SIGNAL
XDS510
STATE
TARGET
STATE
DESCRIPTION
†
Test-mode select
TMS
O
O
I
I
I
†
Test-data input
TDI
†
TDO
TCK
O
I
Test-data output
Test clock – 10-MHz clock source from emulator. Can be used to drive system-test clock.
†
O
O
I
†
Test reset
TRST
EMU0
EMU1
I
I/O
I/O
Emulation pin 0
Emulation pin 1
I
Presence detect. Indicates that the target is connected and powered up. Should be tied to
+ 3.3 V on target system.
PD (3.3 V)
TCKRET
I
I
O
O
Test clock return. Test clock input to the XDS510 emulator. Can be buffered or unbuffered
†
version of TCK.
†
IEEE Standard 1149.1
For best results, the emulation header should be located as close as possible to the ’C80. If the distance exceeds
six inches, the emulation signals should be buffered. See Figure 125.
XDS510 is a trademark of Texas Instruments Incorporated.
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator-interface connection (continued)
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
T34
J35
L33
N33
H34
P32
E35
13
14
2
5
T34
J35
L33
N33
H34
P32
E35
13
14
2
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
6
1
6
3
8
3
8
TDI
TDI
7
10
12
7
10
12
TDO
TCK
TDO
TDO
TCK
TDO
11
9
11
9
TCK
TCK
TCKRET
TCKRET
’C80
’C80
6 in. or less
More than 6 in.
Emulator
Header
Emulator
Header
Figure 125. Emulation Header Connections – Emulator-Driven Test Clock
The target system also can generate the test clock. This allows the user to:
D
D
Set the test clock frequency to match the system requirements. (The emulator provides only a 10-MHz
test clock.)
Have other devices in the system that require a test clock when the emulator is not connected
3.3 V
3.3 V
3.3 V
5
T34
J35
L33
N33
H34
P32
E35
13
14
2
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
GND
GND
GND
GND
GND
1
6
3
8
TDI
7
10
12
TDO
TCK
TDO
11
9
TCK
TCKRET
’C80
Emulator
Header
System
Test
Clock
More than 6 in.
Figure 126. Emulation Header Connections – System-Driven Test Clock
149
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
emulator-interface connection (continued)
For multiprocessor applications, the following conditions are recommended:
D
D
To reduce timing skew, buffer TMS, TDI, TDO, and TCK through the same physical package.
If buffering is used, 4.7-kΩ resistors are recommended for TMS, TDI, and TCK, which should be pulled
high (3.3 V).
D
Buffering EMU0 and EMU1 is recommended highly to provide isolation. The buffers need not be in the
same physical package as TMS, TCK, TDI, or TDO. Pullups to 3.3 V are required and should provide
a signal rise time of less than 10 µs. A 4.7-kΩ resistor is suggested for most applications.
D
To ensure high-quality signals, special printed wire board (PWB) routing and use of termination resistors
may be required. The emulator provides fixed series termination (33 Ω) on TMS and TDI, and optional
parallel terminators (180-Ω pullup and 270-Ω pulldown) on TCKRET and TDO.
3.3 V
3.3 V
3.3 V
5
T34
J35
L33
N33
H34
P32
E35
13
14
2
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
GND
GND
GND
GND
GND
1
6
3
8
TDI
7
10
12
TDO
TCK
TDO
11
9
TCK
TCKRET
’C80
Emulator
Header
T34
J35
L33
N33
H34
P32
E35
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
’C80
Figure 127. Emulation Header Connections – Multiprocessor Applications
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
MECHANICAL DATA
GF (S-CPGA-P305)
CERAMIC PIN GRID ARRAY PACKAGE
1.717 (43,61)
1.683 (42,75)
1.879 (47,73)
TYP
SQ
1.841 (46,76)
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
R
N
L
J
G
E
C
A
1 3
5 7 9 11 13 15 17 19 2123 25 27 29 3133 35
Heatsink
0.050 (1,27)
0.045 (1,14) DIA 4 Places
0.060 (1,52)
0.040 (1,02)
0.019 (0,48)
0.014 (0,36)
0.190 (4,83)
0.170 (4,32)
0.026 (0,660)
0.006 (0,152)
0.150 (3,81)
0.110 (2,79)
0.180 (4,57)
0.140 (3,56)
0.040 (1,02)
4040035-3/E 03/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Package thickness of 0.150 (3,81) / 0.110 (2,79) includes package body and lid, but does not include integral heatsink or attached
features.
151
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SGUS025A – AUGUST 1998 – REVISED JUNE 2002
MECHANICAL DATA
HFH (R-CQFP-F320)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
5,50
4,50
44,44
43,56
1,55
Dia
39,50
BSC
1,45
(4 Places)
320
1
241
240
DETAIL “C”
Heatsink
70,00
3,60
3,50
80
161
160
81
DETAIL “B”
2,60
2,50
2,60
Dia (2 Places)
2,50
DETAIL ”A”
0,50 MAX
0,25
0,18
320 ꢀ
0,51
4,55 MAX
4,00 MAX
1,05
0,75
0,20
0,10
0,35
0,05
0,50
DETAIL “C”
DETAIL “A”
DETAIL “B”
4040232-6/E 09/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals will be gold plated.
E. Falls within JEDEC MO-134 AD
152
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CPGA
CFP
Drawing
5962-9679101QXA
5962-9679101QYC
SM320C80GFA50
SM320C80GFM50
SM320C80HFHM50
SMJ320C80GFM50
SMJ320C80HFHM50
ACTIVE
ACTIVE
NRND
GF
305
320
305
305
320
305
320
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
HFH
GF
CPGA
CPGA
CFP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
GF
HFH
GF
CPGA
CFP
HFH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP028B – JANUARY 1995 – REVISED JUNE 1999
HFH (R-CQFP-F320)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
44,44
5,50
SQ
Tie Bar Width
4,50
43,56
1,55
1,45
4 Places
Dia
39,50
BSC
320
1
241
240
DETAIL ”C”
70,00 BSC
3,60
3,50
161
160
80
81
DETAIL ”B”
2,60
2,50
2,60
Dia 2 Places
2,50
DETAIL ”A”
0,50 MAX
0,25
320 X
0,18
3,21 MAX
2,66 MAX
1,05
0,75
0,20
0,10
0,35
0,05
0,50
DETAIL ”C”
DETAIL ”B”
DETAIL ”A”
4040232-4/F 12/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Leads not shown for clarity purposes
F. Falls within JEDEC MO-134AD
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCPG021B – FEBRUARY 1996 – REVISED DECEMBER 2001
GF (S-CPGA-P305)
CERAMIC PIN GRID ARRAY
1.717 (43,61)
1.683 (42,75)
1.879 (47,73)
TYP
SQ
1.841 (46,76)
0.100 (2,54)
AR
AN
AL
AJ
AG
AE
AC
AA
W
U
R
A1 Corner
N
L
J
G
E
C
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35
Bottom View
Heatslug
0.050 (1,27)
0.045 (1,14) DIA 4 Places
0.060 (1,52)
0.040 (1,02)
0.019 (0,48)
0.014 (0,36)
0.190 (4,83)
0.170 (4,32)
0.026 (0,660)
0.006 (0,152)
0.150 (3,81)
0.110 (2,79)
0.180 (4,57)
0.140 (3,56)
0.040 (1,02)
4040035-3/F 11/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark can appear on top or bottom, depending on package vendor.
D. Pins are located within 0.010 (0,25) diameter of true position relative to
each other at maximum material condition and within 0.030 (0,76) diameter
relative to the edge of the ceramic.
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.
F. The pins can be gold-plated or solder-dipped.
G. Package thickness of 0.150 (3,81) / 0.110 (2,79) includes package body and lid,
but does not include integral heatslug or attached features.
H. Falls within JEDEC MO-128AK
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCQF008B – FEBRUARY 1996 – REVISED JUNE 1999
HFH (R-CQFP-F320)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
44,44
43,56
5,50
Tie Bar Width
4,50
1,55
Dia
39,50
BSC
1,45
4 Places
320
1
241
240
DETAIL ”C”
Heat Sink
70,00 BSC
3,60
3,50
161
160
80
81
DETAIL ”B”
2,60
2,50
2,60
Dia 2 Places
DETAIL ”A”
2,50
0,50 MAX
0,64
0,38
0,25
0,18
320 X
3,85 MAX
2,66 MAX
1,05
0,20
0,10
0,75
0,35
0,05
0,50
DETAIL ”C”
DETAIL ”B”
DETAIL ”A”
4040232-6/F 12/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a metal lid.
D. The terminals are gold-plated.
E. Leads not shown for clarity purposes
F. Falls within JEDEC MO-134AD
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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