5962-9677701QXA [TI]
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 3.3 -V ABT 18位通用总线和三态输出收发器
| 型号： | 5962-9677701QXA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
SN54LVTH16501 . . . WD PACKAGE
SN74LVTH16501 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
OEAB
LEAB
A1
GND
A2
GND
CLKAB
B1
GND
B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
A3
B3
V
V
CC
CC
A4
A5
B4
B5
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
)
CC
A6 10
47 B6
Support Unregulated Battery Operation
Down to 2.7 V
GND
A7
GND
B7
11
12
46
45
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
A8 13
A9 14
44 B8
= 3.3 V, T = 25°C
A
43 B9
I
and Power-Up 3-State Support Hot
off
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
V
22
35
V
Flow-Through Architecture Optimizes PCB
Layout
CC
CC
A16 23
34 B16
33 B17
32 GND
31 B18
30 CLKBA
29 GND
A17 24
Latch-Up Performance Exceeds 500 mA Per
JESD 17
GND 25
A18 26
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
OEBA 27
LEBA 28
description/ordering information
The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V operation,
CC
but with the capability to provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LVTH16501DL
SN74LVTH16501DLR
SN74LVTH16501DGGR
SNJ54LVTH16501WD
SSOP – DL
LVTH16501
–40°C to 85°C
–55°C to 125°C
Tape and reel
Tape and reel
Tube
TSSOP – DGG
CFP – WD
LVTH16501
SNJ54LVTH16501WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
description/ordering information (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the
outputs are active. When OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors
with the bus-hold circuitry is not recommended.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor
CC
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
LEAB
CLKAB
A
X
L
L
X
H
H
L
X
X
X
↑
Z
L
H
H
H
H
H
H
H
L
H
L
L
↑
H
X
X
H
‡
B
0
§
B
0
L
H
L
L
†
‡
A-to-B data flow is shown; B-to-A flow is similar, but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§
Output level before the indicated steady-state input
conditions were established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
logic diagram (positive logic)
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
A1
1D
C1
54
B1
CLK
1D
C1
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH16501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH16501 . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH16501 . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
recommended operating conditions (see Note 4)
SN54LVTH16501 SN74LVTH16501
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
200
CC
T
A
Operating free-air temperature
–55
125
–40
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH16501
SN74LVTH16501
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
–1.2
–1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
CC
2.4
V
–0.2
CC
2.4
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
20
1
CC
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
‡
V
CC
= 3.6 V
V = V
I CC
1
A or B ports
A or B ports
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
CC
V = 2 V
I
–75
–75
I(hold)
§
V
V
= 3.6 V ,
V = 0 to 3.6 V
±500
±100
CC
I
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE/OE = don’t care
CC
O
±100*
±100*
µA
µA
I
I
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE/OE = don’t care
O
±100
OZPD
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
¶
0.2
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
4
pF
pF
i
I
V
O
= 3 V or 0
10
10
io
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
CC
or GND
A
Unused pins at V
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH16501
= 3.3 V
SN74LVTH16501
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
150
150
150
150
MHz
ns
clock
LE high
3.3
3.3
2.5
2.5
3.4
2.2
2.2
2.1
3.3
3.3
2.8
2.8
2.8
1.3
1.5
1.9
3.3
3.3
2.1
2.1
2.4
1.4
1
3.3
3.3
2.4
2.4
1.6
0.5
0
w
CLK high or low
A before CLKAB↑
B before CLKBA↑
t
t
Setup time
Hold time
ns
ns
su
CLK high
CLK low
A or B before LE↓
A or B after CLK↑
A or B after LE↓
h
1.7
1.7
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH16501
= 3.3 V
SN74LVTH16501
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
MAX
PARAMETER
UNIT
CC
± 0.3 V
± 0.3 V
†
MIN
150
1.2
1.2
1.4
1.4
1.2
1.2
1.2
1.2
1.6
1.6
MAX
MIN
MAX
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
t
t
t
150
150
150
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
4.3
4.3
6.2
5.9
6
4.7
4.6
6.6
6.5
6.7
6.6
5.9
5.9
6.7
6.6
1.3
1.3
1.5
1.5
1.3
1.3
1.3
1.3
1.7
1.7
2.7
2.4
3.4
3.5
3.5
3.4
3.4
3.4
4.2
3.8
3.7
3.7
5.1
5.1
5.1
5.1
4.8
4.8
5.8
5.8
4
4
A or B
A or B
A or B
A or B
A or B
B or A
5.7
5.7
5.7
5.7
5.5
5.5
6.3
6.3
ns
ns
ns
ns
LEBA or LEAB
CLKBA or
CLKAB
5.9
5.5
5.5
6.3
6.1
OEBA or OEAB
OEBA or OEAB
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH16501, SN74LVTH16501
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS700E – JULY 1997 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
su
h
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
PHL
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
S1 at 6 V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
+ 0.3 V
OL
V
OL
(see Note B)
V
OL
t
t
t
PZH
PHZ
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
– 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9677701QXA
ACTIVE
ACTIVE
CFP
WD
56
56
1
TBD
Call TI
Level-NC-NC-NC
74LVTH16501DGGRE4
TSSOP
DGG
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
74LVTH16501DLRG4
SN74LVTH16501DGGR
SN74LVTH16501DL
SN74LVTH16501DLR
SNJ54LVTH16501WD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
TSSOP
SSOP
SSOP
CFP
DL
DGG
DL
56
56
56
56
56
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WD
1
TBD
Call TI
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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