5962-9560401QPA [TI]
双路高速、低功耗、低失真电压反馈放大器 | NAB | 8 | -55 to 125;
| 型号： | 5962-9560401QPA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路高速、低功耗、低失真电压反馈放大器 | NAB | 8 | -55 to 125 放大器 商用集成电路 |
| 文件： | 总22页 (文件大小：1284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM6172QML
LM6172QML Dual High Speed, Low Power, Low Distortion, Voltage Feedback
Amplifiers
Literature Number: SNOSAR4A
October 5, 2011
LM6172QML
Dual High Speed, Low Power, Low Distortion, Voltage
Feedback Amplifiers
General Description
Features
The LM6172 is a dual high speed voltage feedback amplifier.
It is unity-gain stable and provides excellent DC and AC per-
formance. With 100MHz unity-gain bandwidth, 3000V/μs slew
rate and 50mA of output current per channel, the LM6172 of-
fers high performance in dual amplifiers; yet it only consumes
2.3mA of supply current each channel.
Available with Radiation Guarantee
■
High Dose Rate
ELDRS Free
300 krad(Si)
100 krad(Si)
—
—
Easy to Use Voltage Feedback Topology
■
■
■
■
■
■
High Slew Rate 3000V/μs
Wide Unity-Gain Bandwidth 100MHz
Low Supply Current 2.3mA / Amplifier
High Output Current 50mA / Amplifier
Specified for ±15V and ±5V operation
The LM6172 operates on ±15V power supply for systems re-
quiring large voltage swings, such as ADSL, scanners and
ultrasound equipment. It is also specified at ±5V power supply
for low voltage applications such as portable video systems.
The LM6172 is built with National's advanced VIP® III (Verti-
cally Integrated PNP) complementary bipolar process.
Applications
Scanner I- to -V Converters
■
■
■
■
■
■
■
ADSL/HDSL Drivers
Multimedia Broadcast Systems
Video Amplifiers
NTSC, PAL® and SECAM Systems
ADC/DAC Buffers
Pulse Amplifiers and Peak Detectors
Ordering Information
NS Part Number
LM6172AMJ-QML
SMD Part Number
NS Package Number
Package Description
8LD Ceramic Dip
5962-9560401QPA
J08A
5962F9560401QPA
300 krad(Si)
LM6172AMJFQML
J08A
8LD Ceramic Dip
5962F9560401VPA
300 krad(Si)
LM6172AMJFQMLV
LM6172AMWG-QML
LM6172AMWGFQMLV
LM6172AMGW-QML
LM6172AMGWFQMLV
J08A
8LD Ceramic Dip
10LD Ceramic SOIC
10LD Ceramic SOIC
10LD Ceramic SOIC
10LD Ceramic SOIC
5962-9560401QXA
WG16A
WG16A
WG16A
WG16A
5962F9560401VXA
300 krad(Si)
5962-9560402QXA
5962F9560402VXA
300 krad(Si)
LM6172AMGWRLQV
ELDRS FREE(Note 15)
5962R9560403VXA
100 krad(Si)
WG16A
(Note 1)
(Note 1)
10LD Ceramic SOIC
Bare Die
5962F9560401V9A
300 krad(Si)
LM6172 MDR
LM6172–MDE
ELDRS FREE(Note 15)
5962R9560403V9A
100 krad(Si)
Bare Die
Note 1: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die
VIP® is a registered trademark of National Semiconductor Corporation.
PAL® is a registered trademark of and used under lisence from Advanced Micro Devices, Inc.
© 2011 National Semiconductor Corporation
201594
www.national.com
Connection Diagrams
8-Pin DIP
16LD Ceramic SOIC
20159401
Top View
20159459
Top View
LM6172 Driving Capacitive Load
20159444
20159450
LM6172 Simplified Schematic (Each Amplifier)
20159455
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2
Absolute Maximum Ratings (Note 2)
Supply Voltage (V+ − V−)
36V
±10V
150°C
1.03W
Continuous
Differential Input Voltage (Note 7)
Maximum Junction Temperature
Power Dissipation (Note 3), (Note 4)
Output Short Circuit to Ground (Note 6)
Storage Temperature Range
−65°C ≤ TA ≤ +150°C
V+ +0.3V to V− −0.3V
±10mA
Common Mode Voltage Range
Input Current
Thermal Resistance (Note 8)
ꢀꢀꢀθJA
8LD Ceramic Dip (Still Air)
8LD Ceramic Dip (500LF/Min Air Flow)
16LD Ceramic SOIC (Still Air) “WG”
16LD Ceramic SOIC (500LF/Min Air Flow) “WG”
16LD Ceramic SOIC (Still Air) “GW”
16LD Ceramic SOIC (500LF/Min Air Flow) “GW”
ꢀꢀꢀθJC
100°C/W
46°C/W
124°C/W
74°C/W
135°C/W
85°C/W
8LD Ceramic Dip (Note 4)
16LD Ceramic SOIC “WG”(Note 4)
16LD Ceramic SOIC “GW”
Package Weight
2°C/W
6°C/W
7°C/W
8LD Ceramic Dip
980mg
365mg
410mg
4KV
16LD Ceramic SOIC “WG”
16LD Ceramic SOIC “GW”
ESD Tolerance (Note 5)
Recommended Operating Conditions (Note 2)
Supply Voltage
5.5V ≤ VS ≤ 36V
−55°C ≤ TA ≤ +125°C
Operating Temperature Range
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Static tests at
Temp (°C)
1
2
+25
+125
-55
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
+25
+125
-55
5
6
7
+25
+125
-55
8A
8B
9
+25
+125
-55
10
11
12
13
14
+25
+125
-55
3
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LM6172 (±5V) Electrical Characteristics (Note 14)
DC Parameters
The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V & RL > 1MΩ
Sub-
groups
Symbol
VIO
Parameter
Input Offset Voltage
Conditions
Notes
Min Max
Units
1.0
3.0
2.5
3.5
1.5
2.2
70
mV
mV
µA
µA
µA
µA
dB
dB
dB
dB
dB
dB
dB
dB
V
1
2, 3
1
IIB
Input Bias Current
2, 3
1
IIO
Input Offset Current
2, 3
1
VCM = ±2.5V
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
65
2, 3
1
75
VS = ±15V to ±5V
RL = 1KΩ
70
2, 3
1
(Note 9)
(Note 9)
(Note 9)
(Note 9)
70
65
2, 3
1
AV
Large Signal Voltage Gain
Output Swing
65
RL = 100Ω
60
2, 3
1
3.1
3.0
2.5
2.4
25
-3.1
-3.0
-2.4
-2.3
RL = 1KΩ
V
2, 3
1
VO
V
RL = 100Ω
V
2, 3
1
(Note 13)
(Note 13)
(Note 13)
(Note 13)
mA
mA
mA
mA
mA
mA
Sourcing RL = 100Ω
Sinking RL = 100Ω
Both Amplifiers
24
2, 3
1
IL
Output Current (Open Loop)
Supply Current
-24
-23
6.0
7.0
2, 3
1
IS
2, 3
DC Drift Parameters (Note 14)
The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +5V, V− = −5V, VCM = 0V & RL > 1MΩ
Delta calculations performed on QMLV devices at group B , subgroup 5.
Sub-
groups
Symbol
VIO
Parameter
Conditions
Notes
Min Max
Units
Input Offset Voltage
Input Bias Current
Input Ofset Current
-0.25 0.25
-0.50 0.50
-0.25 0.25
mV
µA
µA
1
1
1
IIB
IIO
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4
LM6172 (±15V) Electrical Characteristics
DC Parameters (Note 14)
The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V, & RL = 1MΩ
Sub-
groups
Symbol
VIO
Parameter
Input Offset Voltage
Conditions
Notes
Min Max
Units
1.5
mV
mV
µA
µA
µA
µA
dB
dB
dB
dB
dB
dB
dB
dB
V
1
2, 3
1
3.5
3.0
IIB
Input Bias Current
4.0
2, 3
1
2.0
IIO
Input Offset Current
3.0
2, 3
1
70
VCM = ±10V
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
65
2, 3
1
75
VS = ±15V to ±5V
RL = 1KΩ
70
2, 3
1
(Note 9)
(Note 9)
(Note 9)
(Note 9)
75
70
2, 3
1
AV
Large Signal Voltage Gain
Output Swing
65
RL = 100Ω
60
2, 3
1
12.5 -12.5
RL = 1KΩ
12
6.0
5.0
60
-12
-6.0
-5.0
V
2, 3
1
VO
V
RL = 100Ω
V
2, 3
1
(Note 13)
(Note 13)
(Note 13)
(Note 13)
mA
mA
mA
mA
mA
mA
Sourcing RL = 100Ω
Sinking RL = 100Ω
Both Amplifiers
50
2, 3
1
IL
Output Current (Open Loop)
Supply Current
-60
-50
8.0
9.0
2, 3
1
IS
2, 3
AC Parameters (Note 14)
The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V
Sub-
groups
Symbol
SR
GBW
Parameter
Conditions
Notes
Min Max
Units
AV = 2, VI = ±2.5V
3nS Rise & Fall time
(Note 10),
(Note 11)
Slew Rate
Unity-Gain Bandwidth
1700
80
V/µS
MHz
4
4
(Note 12)
DC Drift Parameters (Note 14)
The following conditions apply, unless otherwise specified. TJ = 25°C, V+ = +15V, V− = −15V, VCM = 0V
Delta calculations performed on QMLV devices at group B , subgroup 5.
Sub-
groups
Symbol
VIO
Parameter
Conditions
Notes
Min Max
Units
Input Offset Voltage
Input Bias Current
Input Offset Current
-0.25 0.25
-0.50 0.50
-0.25 0.25
mV
µA
µA
1
1
1
IIB
IIO
5
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Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θ
JA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 4: The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this
improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through,
the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using θJA, rather than θJC, thermal resistance. It must
not be assumed that the device leads will provide substantial heat transfer out the package, since the thermal resistance of the leadframe material is very poor,
relative to the material of the package base. The stated θJC thermal resistance is for the package material only, and does not account for the additional thermal
resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must combine
this with the stated value for the package, to calculate the total allowed power dissipation for the device.
Note 5: Human body model, 1.5 kΩ in series with 100 pF.
Note 6: Continuous short circuit operation can result in exceeding the maximum allowed junction temperature of 150°C
Note 7: Differential Input Voltage is measured at VS = ±15V.
Note 8: All numbers apply for packages soldered directly into a PC board.
Note 9: Large signal voltage gain is the total output swing divided by the input signal required to produce that swing. For VS = ±15V, VOUT = ±5V. For VS = ±5V,
VOUT = ±1V.
Note 10: See AN0009 for SR test circuit.
Note 11: Slew Rate measured between ±4V.
Note 12: See AN0009 for GBW test circuit.
Note 13: The open loop output current is guaranteed by measurement of the open loop output voltage swing using 100Ω output load.
Note 14: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. These parts may be dose rate sensitive in a space
environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters are guaranteed only for the conditions as
specified in Mil-Std-883, Method 1019.5, Condition A.
Note 15: Low dose rate testing has been performed per test method 1019, condition D, MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics. Radiation end point limits for the noted parameters are
guaranteed for only the conditions as specified in MIL-STD-883, Method 1019, condition D. The “03” device has been characterized to only 100k.
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6
Typical Performance Characteristics Unless otherwise noted, TA = 25°C
Supply Voltage vs. Supply Current
Supply Current vs. Temperature
20159414
20159415
Input Offset Voltage vs. Temperature
Input Bias Current vs. Temperature
20159416
20159417
Short Circuit Current vs. Temperature (Sourcing)
Short Circuit Current vs. Temperature (Sinking)
20159418
20159435
7
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Output Voltage vs. Output Current
(VS = ±15V)
Output Voltage vs. Output Current
(VS = ±5V)
20159436
20159437
CMRR vs. Frequency
PSRR vs. Frequency
20159419
20159420
PSRR vs. Frequency
Open-Loop Frequency Response
20159433
20159421
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8
Open-Loop Frequency Response
Gain-Bandwidth Product vs. Supply Voltage at Different
Temperature
20159422
20159423
Large Signal Voltage Gain vs. Load
Large Signal Voltage Gain vs. Load
20159438
20159439
Input Voltage Noise vs. Frequency
Input Voltage Noise vs. Frequency
20159440
20159441
9
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Input Current Noise vs. Frequency
Input Current Noise vs. Frequency
20159442
20159443
Slew Rate vs. Supply Voltage
Slew Rate vs. Input Voltage
20159425
20159426
Large Signal Pulse Response
AV = +1, VS = ±15V
Small Signal Pulse Response
AV = +1, VS = ±15V
20159402
20159403
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Large Signal Pulse Response
AV = +1, VS = ±5V
Small Signal Pulse Response
AV = +1, VS = ±5V
20159404
20159405
Large Signal Pulse Response
AV = +2, VS = ±15V
Small Signal Pulse Response
AV = +2, VS = ±15V
20159406
20159407
Large Signal Pulse Response
AV = +2, VS = ±5V
Small Signal Pulse Response
AV = +2, VS = ±5V
20159408
20159409
11
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Large Signal Pulse Response
AV = −1, VS = ±15V
Small Signal Pulse Response
AV = −1, VS = ±15V
20159410
20159411
Large Signal Pulse Response
AV = −1, VS = ±5V
Small Signal Pulse Response
AV = −1, VS = ±5V
20159412
20159413
Closed Loop Frequency Response vs. Supply Voltage
(AV = +1)
Closed Loop Frequency Response vs. Supply Voltage
(AV = +2)
20159428
20159429
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12
Harmonic Distortion vs. Frequency
(VS = ±15V)
Harmonic Distortion vs. Frequency
(VS = ±5V)
20159430
20159434
Crosstalk Rejection vs. Frequency
Maximum Power Dissipation vs. Ambient Temperature
20159432
20159431
divided by the total degeneration resistor RE. Therefore, the
slew rate is proportional to the input voltage level, and the
higher slew rates are achievable in the lower gain configura-
tions.
Application Notes
LM6172 PERFORMANCE DISCUSSION
The LM6172 is a dual high-speed, low power, voltage feed-
back amplifier. It is unity-gain stable and offers outstanding
performance with only 2.3mA of supply current per channel.
The combination of 100MHz unity-gain bandwidth, 3000V/μs
slew rate, 50mA per channel output current and other attrac-
tive features makes it easy to implement the LM6172 in
various applications. Quiescent power of the LM6172 is
138mW operating at ±15V supply and 46mW at ±5V supply.
When a very fast large signal pulse is applied to the input of
an amplifier, some overshoot or undershoot occurs. By plac-
ing an external series resistor such as 1kΩ to the input of
LM6172, the slew rate is reduced to help lower the overshoot,
which reduces settling time.
REDUCING SETTLING TIME
The LM6172 has a very fast slew rate that causes overshoot
and undershoot. To reduce settling time on LM6172, a 1kΩ
resistor can be placed in series with the input signal to de-
crease slew rate. A feedback capacitor can also be used to
reduce overshoot and undershoot. This feedback capacitor
serves as a zero to increase the stability of the amplifier cir-
cuit. A 2pF feedback capacitor is recommended for initial
evaluation. When the LM6172 is configured as a buffer, a
feedback resistor of 1kΩ must be added in parallel to the
feedback capacitor.
LM6172 CIRCUIT OPERATION
The class AB input stage in LM6172 is fully symmetrical and
has a similar slewing characteristic to the current feedback
amplifiers. In the LM6172 Simplified Schematic (Page 2), Q1
through Q4 form the equivalent of the current feedback input
buffer, RE the equivalent of the feedback resistor, and stage
A buffers the inverting input. The triple-buffered output stage
isolates the gain stage from the load to provide low output
impedance.
Another possible source of overshoot and undershoot comes
from capacitive load at the output. Please see the section
“Driving Capacitive Loads” for more detail.
LM6172 SLEW RATE CHARACTERISTIC
The slew rate of LM6172 is determined by the current avail-
able to charge and discharge an internal high impedance
node capacitor. This current is the differential input voltage
13
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DRIVING CAPACITIVE LOADS
LAYOUT CONSIDERATION
Amplifiers driving capacitive loads can oscillate or have ring-
ing at the output. To eliminate oscillation or reduce ringing, an
isolation resistor can be placed as shown in Figure 1. The
combination of the isolation resistor and the load capacitor
forms a pole to increase stability by adding more phase mar-
gin to the overall system. The desired performance depends
upon the value of the isolation resistor; the bigger the isolation
resistor, the more damped (slow) the pulse response be-
comes. For LM6172, a 50Ω isolation resistor is recommended
for initial evaluation.
Printed Circuit Boards And High Speed Op Amps
There are many things to consider when designing PC boards
for high speed op amps. Without proper caution, it is very easy
to have excessive ringing, oscillation and other degraded AC
performance in high speed circuits. As a rule, the signal traces
should be short and wide to provide low inductance and low
impedance paths. Any unused board space needs to be
grounded to reduce stray signal pickup. Critical components
should also be grounded at a common point to eliminate volt-
age drop. Sockets add capacitance to the board and can
affect frequency performance. It is better to solder the ampli-
fier directly into the PC board without using any socket.
Using Probes
Active (FET) probes are ideal for taking high frequency mea-
surements because they have wide bandwidth, high input
impedance and low input capacitance. However, the probe
ground leads provide a long ground loop that will produce er-
rors in measurement. Instead, the probes can be grounded
directly by removing the ground leads and probe jackets and
using scope probe jacks.
20159445
Components Selection And Feedback Resistor
FIGURE 1. Isolation Resistor Used
to Drive Capacitive Load
It is important in high speed applications to keep all compo-
nent leads short because wires are inductive at high frequen-
cy. For discrete components, choose carbon composition-
type resistors and mica-type capacitors. Surface mount
components are preferred over discrete components for min-
imum inductive effect.
Large values of feedback resistors can couple with parasitic
capacitance and cause undesirable effects such as ringing or
oscillation in high speed amplifiers. For LM6172, a feedback
resistor less than 1kΩ gives optimal performance.
COMPENSATION FOR INPUT CAPACITANCE
The combination of an amplifier's input capacitance with the
gain setting resistors adds a pole that can cause peaking or
oscillation. To solve this problem, a feedback capacitor with
a value
20159451
CF > (RG × CIN)/RF
FIGURE 2. The LM6172 Driving a 510pF Load
can be used to cancel that pole. For LM6172, a feedback ca-
pacitor of 2pF is recommended. Figure 4 illustrates the com-
pensation circuit.
with a 30Ω Isolation Resistor
20159452
20159446
FIGURE 3. The LM6172 Driving a 220 pF Load
FIGURE 4. Compensating for Input Capacitance
with a 50Ω Isolation Resistor
POWER SUPPLY BYPASSING
Bypassing the power supply is necessary to maintain low
power supply impedance across frequency. Both positive and
negative power supplies should be bypassed individually by
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14
placing 0.01μF ceramic capacitors directly to power supply
pins and 2.2μF tantalum capacitors close to the power supply
pins.
To minimize reflection, coaxial cable with matching charac-
teristic impedance to the signal source should be used. The
other end of the cable should be terminated with the same
value terminator or resistor. For the commonly used cables,
RG59 has 75Ω characteristic impedance, and RG58 has
50Ω characteristic impedance.
POWER DISSIPATION
The maximum power allowed to dissipate in a device is de-
fined as:
PD = (TJ(max) − TA)/θJA
Where PD is the power dissipation in a device
TJ(max) is the maximum junction temperature
TA is the ambient temperature
θ
JA is the thermal resistance of a particular package
For example, for the LM6172 in a SO-16 package, the maxi-
mum power dissipation at 25°C ambient temperature is
1000mW.
20159447
FIGURE 5. Power Supply Bypassing
Thermal resistance, θJA, depends on parameters such as die
size, package size and package material. The smaller the die
size and package, the higher θJA becomes. The 8-pin DIP
package has a lower thermal resistance (95°C/W) than that
of 8-pin SO (160°C/W). Therefore, for higher dissipation ca-
pability, use an 8-pin DIP package.
TERMINATION
In high frequency applications, reflections occur if signals are
not properly terminated. Figure 6 shows a properly terminated
signal while Figure 7 shows an improperly terminated signal.
The total power dissipated in a device can be calculated as:
PD = PQ + PL
PQ is the quiescent power dissipated in a device with no load
connected at the output. PL is the power dissipated in the de-
vice with a load connected at the output; it is not the power
dissipated by the load.
Furthermore,
PQ: = supply current x total supply voltage with no load
PL:
=
output current x (voltage difference between supply
voltage and output voltage of the same supply)
For example, the total power dissipated by the LM6172 with
VS = ±15V and both channels swinging output voltage of 10V
into 1kΩ is
PD:
=
PQ + PL
20159453
:
:
:
=
2[(2.3mA)(30V)] + 2[(10mA)(15V − 10V)]
138mW + 100mW
FIGURE 6. Properly Terminated Signal
=
=
238mW
20159454
FIGURE 7. Improperly Terminated Signal
15
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Application Circuits
I- to -V Converters
20159448
Differential Line Driver
20159449
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16
Revision History
Released
Revision
Section
Changes
12/08/2010
A
New Release, Corporate format
1 MDS data sheet converted into one Corp. data
sheet format. MNLM6172AM-X-RH Rev 0A0 will be
archived.
10/05/2011
B
Features, Ordering Information, Abs Max
Ratings, Footnotes
Update Radiation, Add new ELDRS FREE die id,
'GW' NSID'S w/coresponding SMD numbers. Add
'GW' Theta JA & Theta JC along with weight.Add
Note 15, Modify Note 14. LM6172QML Rev A will be
archived.
17
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Ceramic Dual-In-Line Package
ONS Package Number J08A
16-Lead Ceramic SOIC Package
NS Package Number WG16A
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18
Notes
19
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Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
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