5962-9550404Q2A [TI]
Advanced LinCMOS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS; 高级LinCMOS轨到轨运算放大器
| 型号： | 5962-9550404Q2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Advanced LinCMOS RAIL-TO-RAIL OPERATIONAL AMPLIFIERS |
| 文件： | 总55页 (文件大小：1181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
D
D
D
D
Output Swing Includes Both Supply Rails
Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
D
D
Low Input Offset Voltage
950 µV Max at T = 25°C (TLV226xA)
A
Wide Supply Voltage Range
2.7 V to 8 V
Fully Specified for Both Single-Supply and
Split-Supply Operation
D
Macromodel Included
D
Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
D
Low Power . . . 500 µA Max
Common-Mode Input Voltage Range
Includes Negative Rail
D
description
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
The TLV2262 and TLV2264 are dual and quad low
voltage operational amplifiers from Texas Instru-
ments. Both devices exhibit rail-to-rail output
performance for increased dynamic range in
single or split supply applications. The TLV226x
family offers a compromise between the micro-
power TLV225x and the ac performance of the
TLC227x. It has low supply current for battery-
powered applications, while still having adequate
ac performance for applications that demand it.
This family is fully characterized at 3 V and 5 V and
is optimized for low-voltage applications. The
noise performance has been dramatically im-
proved over previous generations of CMOS
amplifiers. Figure 1 depicts the low level of noise
voltage for this CMOS amplifier, which has only
200 µA (typ) of supply current per amplifier.
4
V
= 3 V
DD
3.5
3
T
= −55°C
A
2.5
2
T
A
= 125°C
T
A
= 25°C
= 85°C
1.5
1
T
A
T
A
= −40°C
0.5
0
The TLV226x, exhibiting high input impedance
and low noise, are excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the micro-
power dissipation levels combined with 3-V
0
500
1000
1500
2000
| I
| − High-Level Output Current − µA
OH
Figure 1
operation, these devices work well in hand-held monitoring and remote-sensing applications. In addition, the
rail-to-rail output feature with single or split supplies makes this family a great choice when interfacing with
analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available and has a
maximum input offset voltage of 950 µV.
The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output
dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to
be used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption, make them ideal for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
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Copyright 2001, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262 AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
CERAMIC
FLATPACK
(U)
IO
T
A
TSSOP
(PW)
AT 25°C
(JG)
(P)
0°C to 70°C
2.5 mV
TLV2262CD
—
—
TLV2262CP TLV2262CPWLE
—
950 µV
2.5 mV
TLV2262AID
TLV2262ID
—
—
—
—
TLV2262AIP TLV2262AIPWLE
—
—
−40°C to 125°C
TLV2262IP
—
950 µV
2.5 mV
TLV2262AQD
TLV2262QD
—
—
—
—
—
—
—
—
—
—
−40°C to 125°C
−55°C to 125°C
950 µV
2.5 mV
—
—
TLV2262AMFK TLV2262AMJG
TLV2262MFK TLV2262MJG
—
—
—
—
TLV2262AMU
TLV2262MU
†
‡
§
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262CDR).
The PW package is available only left-end taped and reeled.
Chips are tested at 25°C.
TLV2264 AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
CERAMIC
FLATPACK
(W)
IO
T
A
TSSOP
(PW)
AT 25°C
(J)
(N)
−40°C to
125°C
950 µV
2.5 mV
TLV2264AID
TLV2264ID
—
—
—
—
TLV2264AIN
TLV2264IN
TLV2264AIPWLE
—
—
—
−40°C to
125°C
950 µV
2.5 mV
TLV2264AQD
TLV2264QD
—
—
—
—
—
—
—
—
—
—
−55°C to
125°C
950 µV
2.5 mV
—
—
TLV2264AMFK
TLV2264MFK
TLV2264AMJ
TLV2264MJ
—
—
—
—
TLV2264AMW
TLV2264MW
†
‡
§
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262IDR).
The PW package is available only left-end taped and reeled.
Chips are tested at 25°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262C, TLV2262AC
TLV2262I, TLV2262AI
TLV2262Q, TLV2262AQ
D, P, OR PW PACKAGE
(TOP VIEW)
TLV2264I, TLV2264AI
TLV2264Q, TLV2264AQ
D, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
1OUT
1IN−
1IN+
V
DD+
1
2
3
4
8
7
6
5
2OUT
2IN−
2IN+
V
V
/GND
DD+
DD−
V
/GND
DD−
2IN+
2IN−
2OUT
3IN+
3IN−
3OUT
8
TLV2262M, TLV2262AM
JG PACKAGE
(TOP VIEW)
TLV2264M, TLV2264AM
J OR W PACKAGE
(TOP VIEW)
1OUT
V
DD+
1
2
3
4
8
7
6
5
1IN−
1IN+
/GND
2OUT
2IN−
2IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
V
DD−
TLV2662M, TLV2262AM
U PACKAGE
V
V
/GND
DD+
2IN+
2IN−
DD−
3IN+
3IN−
3OUT
(TOP VIEW)
8
2OUT
NC
NC
V
1
10
9
1OUT
1IN −
1IN +
/GND
+
2
3
4
5
CC
2OUT
2IN −
2IN +
8
TLV2264M, TLV2264AM
FK PACKAGE
7
V
6
CC−
(TOP VIEW)
TLV2262M, TLV2262AM
FK PACKAGE
3
2
1
20 19
18
(TOP VIEW)
4IN+
1IN+
NC
4
5
6
7
8
NC
V
17
16
15
14
/GND
V
CC−
CC+
NC
NC
3
2
1
20 19
18
3IN+
2IN+
NC
NC
4
5
6
7
8
9 10 11 12 13
2OUT
NC
1IN−
NC
17
16
15
14
2IN−
NC
1IN+
NC
9 10 11 12 13
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Template Release Date: 7−11−94
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
V
ID
DD
−0.3 V to V
I
DD−
DD+
Input current, I (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
DD+
DD−
Total current out of V
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, P, and PW packages . . . . . . . 260°C
FK, J, JG, U, AND W packages . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to V
.
DD −
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below V − 0.3 V.
DD−
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 85°C
T = 125°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
377 mW
494 mW
715 mW
715 mW
—
POWER RATING
145 mW
190 mW
275 mW
275 mW
210 mW
—
A
D−8
D−14
FK
725 mW
5.8 mW/°C
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
8.4 mW/°C
9.2 mW/°C
8.0 mW/°C
4.2 mW/°C
5.6 mW/°C
5.5 mW/°C
5.5 mW/°C
950 mW
1375 mW
1375 mW
1050 mW
1150 mW
1000 mW
525 mW
J
JG
N
598 mW
520 mW
273 mW
364 mW
—
P
200 mW
105 mW
—
PW−8
PW−14
U
700 mW
700 mW
150 mW
150 mW
W
700 mW
370 mW
recommended operating conditions
I SUFFIX
Q SUFFIX
M SUFFIX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Supply voltage, V
DD
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ꢁ
ꢂ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
2.7
16
2.7
16
2.7
16
V
V
Input voltage range, V
V
V
V
−1.3
−1.3
V
V
V
−1.3
−1.3
V
V
V
−1.3
−1.3
I
DD−
DD+
DD−
DD+
DD−
DD+
Common-mode input voltage, V
IC
V
V
V
V
DD−
−40
DD+
125
DD−
−40
DD+
125
DD−
−55
DD+
125
Operating free-air temperature, T
°C
A
NOTE 1: All voltage values, except differential voltages, are with respect to V
.
DD −
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262I electrical characteristics at specified free-air temperature, V
noted)
= 3 V (unless otherwise
DD
TLV2262I
TLV2262AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
300 2500
3000
MIN
TYP MAX
25°C
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
2
2
µV/°C
Input offset voltage
long-term drift
(see Note 4)
25°C
0.003
0.003
0.5
µV/mo
V
V
=
1.5 V,
V
= 0,
DD
= 0,
IC
R
= 50 Ω
S
O
25°C
85°C
0.5
60
150
800
60
60
150
800
60
I
I
Input offset current
Input bias current
pA
IO
Full range
25°C
1
1
85°C
150
800
150
800
pA
V
IB
Full range
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
V
V
R
= 50 Ω,
|V | ≤5 mV
IO
ICR
OH
OL
S
0
to
0
to
Full range
1.7
1.7
I
I
= −20 µA
25°C
25°C
2.99
2.99
OH
2.85
2.85
2.825
2.7
= −100 µA
High-level output
voltage
OH
Full range 2.825
V
25°C
Full range
25°C
2.7
I
= −400 µA
= 1.5 V,
OH
2.65
2.65
V
I
I
= 50 µA
10
10
IC
IC
OL
25°C
100
100
V
= 1.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
150
300
150
300
mV
200
100
100
200
100
100
V
= 1.5 V,
I
= 1 ꢈA
IC
OL
Full range
25°C
60
30
60
30
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
V
= 1.5 V,
= 1 V to 2 V
L
L
IC
O
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
270
75
270
77
25°C
Full range
25°C
65
60
80
80
65
60
80
80
Common-mode
rejection ratio
V
IC
V
O
= 0 to 1.7 V,
= 1.5 V,
CMRR
dB
dB
R
= 50 Ω
S
95
100
Supply voltage rejection
ratio (∆V /∆V
DD IO
V
DD
V
IC
= 2.7 V to 8 V,
k
SVR
)
= V
/2,
No load
Full range
DD
†
‡
Full range is − 40°C to 125°C.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢃ
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ꢀ
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ꢂ
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ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 3 V (unless otherwise
DD
TLV2262I
TLV2262AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
Full range
400
500
500
400
500
500
I
Supply current
V
O
= 1.5 V,
No load
µA
DD
†
Full range is − 40°C to 125°C.
TLV2262I operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2262I
TLV2262AI
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
TYP MAX MIN
TYP MAX
0.35
0.55
0.35
0.55
25°C
‡
V
C
= 1.1 V to 1.9 V,
R
= 50 kΩ ,
L
O
L
SR
Slew rate at unity gain
Full
range
‡
= 100 pF
0.3
0.3
f = 10 Hz
f = 1 kHz
25°C
25°C
43
12
43
12
Equivalent input noise
voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.6
1
0.6
1
V
I
µV
N(PP)
Equivalent input noise
current
25°C
25°C
25°C
25°C
0.6
0.6
fA/√Hz
n
V
= 0.5 V to 2.5 V,
A
= 1
0.03%
0.05%
0.03%
O
V
Total harmonic
distortion plus noise
f = 20 kHz,
R
THD + N
A
V
= 10
0.05%
0.67
‡
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 1 kHz,
R
= 50 kΩ ,
L
0.67
395
MHz
kHz
‡
C
= 100 pF
L
Maximum
output-swing
bandwidth
V
R
= 1 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
395
‡
‡
C = 100 pF
L
A
= −1,
V
To 0.1%
5.6
5.6
Step = 1 V to 2 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
12.5
12.5
‡
Phase margin at
unity gain
φ
m
25°C
25°C
55°
55°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is − 40°C to 125°C.
Referenced to 1.5 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢄ
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ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262I electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLV2262I
TLV2262AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
300 2500
3000
MIN
TYP MAX
25°C
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
2
2
µV/°C
Input offset voltage
long-term drift
(see Note 4)
25°C
0.003
0.003
0.5
µV/mo
V
V
=
2.5 V,
V
= 0,
DD
= 0,
IC
R
= 50 Ω
O
S
25°C
85°C
0.5
60
150
800
60
60
150
800
60
I
I
Input offset current
Input bias current
pA
IO
Full range
25°C
1
1
85°C
150
800
150
800
pA
V
IB
Full range
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
V
V
|V | ≤5 mV,
IO
R
= 50 Ω
S
ICR
OH
OL
0
to
0
to
Full range
3.5
3.5
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
OH
4.85
4.82
4.7
4.85
4.82
4.7
= −100 µA
OH
Full range
25°C
High-level output voltage
Low-level output voltage
V
4.85
4.85
I
= −400 µA
= 2.5 V,
OH
Full range
25°C
4.6
4.6
V
I
I
= 50 µA
0.01
0.09
0.01
0.09
IC
IC
OL
25°C
0.15
0.15
0.3
0.15
0.15
0.3
V
= 2.5 V,
= 500 µA
OL
Full range
25°C
V
0.2
170
550
0.2
170
550
V
= 2.5 V,
I
= 1 ꢈA
IC
OL
Full range
25°C
0.3
0.3
80
55
80
55
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
V
= 2.5 V,
= 1 V to 4 V
L
L
IC
O
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
240
83
240
83
25°C
Full range
25°C
70
70
80
80
70
70
80
80
Common-mode rejection
ratio
V
V
= 0 to 2.7 V,
= 2.5 V,
IC
O
CMRR
dB
dB
R
= 50 Ω
S
95
95
Supply voltage rejection
V
= 4.4 V to 8 V,
DD
k
SVR
ratio (∆V
DD
/∆V
IO
)
V
IC
= V
/2,
No load
Full range
DD
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 5 V (unless otherwise
DD
TLV2262I
TLV2262AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
400
500
500
400
500
500
I
Supply current
V
O
= 2.5 V,
No load
µA
DD
Full range
†
Full range is − 40°C to 125°C.
TLV2262I operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2262I
TLV2262AI
TYP
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
TYP
MAX MIN
MAX
0.35
0.55
0.35
0.55
25°C
‡
Slew rate at unity
gain
V
C
= 1.5 V to 3.5 V,
R
= 50 kΩ ,
L
O
L
SR
Full
range
‡
= 100 pF
0.3
0.3
f = 10 Hz
f = 1 kHz
25°C
25°C
40
12
40
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.3
0.7
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.017%
0.03%
0.017%
0.03%
O
V
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.71
0.71
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
V
= 1,
O(PP)
L
B
OM
185
6.4
185
6.4
‡
‡
C = 100 pF
L
A
V
= −1,
To 0.1%
Step = 0.5 V to 2.5 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
14.1
14.1
‡
Phase margin at
unity gain
φ
m
25°C
25°C
56°
56°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264I electrical characteristics at specified free-air temperature, V
noted)
= 3 V (unless otherwise
DD
TLV2264I
TLV2264AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
300 2500
3000
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
2
2
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
V
= 1.5 V,
= 0,
= 0,
25°C
0.003
0.5
0.003
0.5
µV/mo
DD
IC
O
25°C
85°C
60
150
800
60
60
150
800
60
R = 50 Ω
S
I
I
Input offset current
Input bias current
pA
IO
Full range
25°C
1
1
85°C
150
800
150
800
pA
V
IB
Full range
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
V
V
R
= 50 Ω,
|V | ≤5 mV
IO
ICR
OH
OL
S
0
to
0
to
Full range
1.7
1.7
I
I
= −20 µA
25°C
25°C
2.99
2.99
OH
2.85
2.85
2.825
2.7
= −100 µA
High-level output
voltage
OH
Full range 2.825
V
25°C
Full range
25°C
2.7
I
= −400 µA
= 1.5 V,
OH
2.65
2.65
V
I
I
= 50 µA
10
10
IC
IC
OL
25°C
100
100
V
= 1.5 V,
= 500 µA
OL
Full range
25°C
150
300
150
300
Low-level output voltage
mV
200
100
100
200
100
100
V
= 1.5 V,
I
= 1 ꢈA
IC
OL
Full range
25°C
60
30
60
30
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
L
L
V
V
= 1.5 V,
= 1 to 2 V
IC
O
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
N package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
270
75
270
77
V
V
V
V
= 0 to 1.7 V,
= 1.5 V,
25°C
Full range
25°C
65
60
80
80
65
60
80
80
Common-mode
rejection ratio
IC
O
CMRR
dB
dB
R
= 50 Ω
S
= 2.7 V to 8 V,
95
100
Supply voltage rejection
DD
k
SVR
ratio (∆V
DD
/∆V )
IO
= V
DD
/2, No load
Full range
IC
†
‡
Full range is − 40°C to 125°C.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔ
ꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 3 V (unless otherwise
DD
TLV2264I
TLV2264AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
0.8
1
1
0.8
1
1
Supply current
(four amplifiers)
I
V
O
= 1.5 V,
No load
mA
DD
Full range
†
Full range is − 40°C to 125°C.
TLV2264I operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2264I
TLV2264AI
TYP
†
T
PARAMETER
TEST CONDITIONS
UNIT
V/µs
A
MIN
TYP
MAX MIN
MAX
25°C
0.35
0.55
0.35
0.55
‡
Slew rate at unity
gain
V
C
= 0.7 V to 1.7 V,
R
= 50 kΩ ,
L
O
L
SR
Full
range
‡
= 100 pF
0.3
0.3
f = 10 Hz
f = 1 kHz
25°C
25°C
43
12
43
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.6
1
0.6
1
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.03%
0.05%
0.03%
0.05%
O
V
f = 20 kHz,
R
THD + N
A
V
= 10
‡
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 1 kHz,
R
= 50 kΩ ,
L
0.67
395
0.67
395
MHz
kHz
‡
C
= 100 pF
L
Maximum
output-swing
bandwidth
V
R
= 1 V,
‡,
A
= 1,
O(PP)
L
V
B
OM
‡
C = 100 pF
L
= 50 kΩ
A
= −1,
V
To 0.1%
5.6
5.6
Step = 1 V to 2 V,
‡,
t
s
Settling time
25°C
µs
R
C
= 50 kΩ
= 100 pF
L
L
To 0.01%
12.5
12.5
‡
Phase margin at
unity gain
φ
m
25°C
25°C
55°
55°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is − 40°C to 125°C.
Referenced to 1.5 V
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264I electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLV2264I
TLV2264AI
UNIT
†
T
PARAMETER
TEST CONDITIONS
A
MIN
TYP MAX
300 2500
3000
MIN
TYP MAX
25°C
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
2
2
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
V
= 2.5 V,
= 0,
= 0,
= 50 Ω
25°C
0.003
0.003
0.5
µV/mo
pA
DD
IC
O
25°C
85°C
0.5
60
150
800
60
60
150
800
60
R
S
I
I
Input offset current
Input bias current
IO
Full range
25°C
1
1
85°C
150
800
150
800
pA
IB
Full range
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
|V | ≤5 mV,
IO
R
= 50 Ω
V
V
ICR
S
0
to
3.5
0
to
3.5
Full range
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
OH
4.85
4.85
4.82
4.7
= −100 µA
High-level output
voltage
OH
Full range 4.82
V
V
OH
25°C
Full range
25°C
4.7
4.6
4.85
4.85
I
= −400 µA
= 2.5 V,
OH
4.6
V
I
I
= 50 µA
0.01
0.09
0.01
0.09
IC
IC
OL
25°C
0.15
0.15
0.3
0.15
0.15
0.3
V
= 2.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
V
OL
0.2
170
550
0.2
170
550
V
IC
= 2.5 V,
I
= 1 ꢈA
OL
Full range
25°C
0.3
0.3
80
55
80
55
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
N package
= 10
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
240
83
240
83
25°C
Full range
25°C
70
70
80
80
70
70
80
80
Common-mode rejection
ratio
V
R
= 0 to 2.7 V,
= 50 Ω
V
= 2.5 V,
O
IC
S
CMRR
dB
dB
95
95
Supply voltage rejection
V
= 4.4 V to 8 V,
DD
k
SVR
ratio (∆V
DD
/∆V
IO
)
V
IC
= V /2, No load
Full range
DD
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢃ
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ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 5 V (unless otherwise
DD
TLV2264I
TLV2264AI
UNIT
†
T
A
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
MIN
TYP MAX
25°C
0.8
1
1
0.8
1
1
Supply current
(four amplifiers)
I
V
O
= 2.5 V,
No load
mA
DD
Full range
†
Full range is − 40°C to 125°C.
TLV2264I operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2264I
TLV2264AI
TYP
†
T
PARAMETER
TEST CONDITIONS
UNIT
V/µs
A
MIN
TYP
MAX MIN
MAX
25°C
0.35
0.55
0.35
0.55
‡
Slew rate at unity
gain
V
O
= 1.4 V to 2.6 V,
R
= 50 kΩ ,
L
SR
Full
range
‡
C = 100 pF
L
0.3
0.3
f = 10 Hz
f = 1 kHz
25°C
25°C
40
12
40
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.3
0.7
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.017%
0.03%
0.017%
0.03%
O
V
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.71
0.71
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
V
= 1,
O(PP)
L
B
OM
185
6.4
185
6.4
‡
‡
C = 100 pF
L
A
V
= −1,
To 0.1%
Step = 0.5 V to 2.5 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
14.1
14.1
‡
Phase margin at
unity gain
φ
m
25°C
25°C
56°
56°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
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ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 3 V
DD
TLV2262Q,
TLV2262M
TLV2262AQ,
TLV2262AM
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
300 2500
3000
300
2
950
V
Input offset voltage
µV
IO
Full range
1500
Temperature coefficient
of input offset voltage
25°C
to 125°C
α
VIO
2
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
=
1.5 V,
V
= 0,
DD
= 0,
IC
25°C
0.003
0.5
0.003
0.5
µV/mo
R
= 50 Ω
S
O
25°C
125°C
25°C
60
800
60
60
800
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
800
800
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
V
V
R
= 50 Ω,
|V | ≤5 mV
IO
V
V
ICR
OH
OL
S
0
to
1.7
0
to
1.7
Full range
I
I
= −20 µA
25°C
25°C
2.99
2.99
OH
2.85
2.82
2.7
2.85
2.82
2.7
= −100 µA
High-level output
voltage
OH
Full range
25°C
I
= −400 µA
= 1.5 V,
OH
Full range
25°C
2.55
2.55
V
I
I
= 50 µA
10
10
IC
IC
OL
25°C
100
150
165
300
300
100
150
165
300
300
V
= 1.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
mV
200
100
100
200
100
100
V
IC
= 1.5 V,
I
= 1 ꢈA
OL
Full range
25°C
60
25
60
25
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 1.5 V,
= 1 V to 2 V
L
L
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
= 10
270
75
270
77
25°C
Full range
25°C
65
60
80
80
65
60
80
80
Common-mode
rejection ratio
V
IC
V
O
= 0 to 1.7 V,
= 1.5 V,
CMRR
dB
dB
R
= 50 Ω
S
95
100
Supply voltage rejection
V
DD
V
IC
= 2.7 V to 8 V,
k
SVR
ratio (∆V
DD
/∆V
IO
)
= V
/2,
No load
Full range
DD
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔ
ꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 3 V
DD
TLV2262Q,
TLV2262M
TLV2262AQ,
TLV2262AM
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
400 500
25°C
400
500
500
I
Supply current
V
O
= 1.5 V,
No load
µA
DD
Full range
500
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2262Q and TLV2262M operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2262Q,
TLV2262M
TLV2262AQ,
TLV2262AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX MIN
TYP MAX
0.35
0.55
0.35
0.55
25°C
‡
V
C
= 0.5 V to 1.7 V,
= 100 pF
R
= 50 kΩ ,
L
O
L
SR
Slew rate at unity gain
V/µs
Full
range
‡
0.25
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
43
12
43
12
Equivalent input noise
voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input noise
voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.6
1
0.6
1
V
I
µV
N(PP)
Equivalent input noise
current
25°C
25°C
25°C
25°C
0.6
0.6
fA/√Hz
n
V
= 0.5 V to 2.5 V,
A
= 1
0.03%
0.05%
0.03%
0.05%
O
V
Total harmonic
distortion plus noise
f = 20 kHz,
R
THD + N
A
V
= 10
‡
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 1 kHz,
R
= 50 kΩ ,
L
0.67
395
0.67
395
MHz
kHz
‡
C
= 100 pF
L
Maximum
output-swing
bandwidth
V
R
= 1 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
‡
‡
C = 100 pF
L
A
= −1,
V
To 0.1%
5.6
5.6
Step = 1 V to 2 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
12.5
12.5
‡
Phase margin at unity
gain
φ
m
25°C
25°C
55°
55°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 5 V
DD
TLV2262Q,
TLV2262M
TLV2262AQ,
TLV2262AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
300 2500
3000
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient of
input offset voltage
25°C
to 125°C
α
VIO
2
2
µV/°C
Input offset voltage
long-term drift (see Note 4)
V
V
=
2.5 V,
V
= 0,
DD
= 0,
IC
R
25°C
0.003
0.5
0.003
0.5
µV/mo
= 50 Ω
O
S
25°C
125°C
25°C
60
800
60
60
800
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
800
800
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
V
V
|V | ≤5 mV,
IO
R
= 50 Ω
S
V
V
ICR
OH
OL
0
to
3.5
0
to
3.5
Full range
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
OH
4.85
4.85
4.82
4.7
= −100 µA
OH
Full range 4.82
High-level output voltage
Low-level output voltage
25°C
Full range
25°C
4.7
4.5
4.85
4.85
I
= −400 µA
= 2.5 V,
OH
4.5
V
I
I
= 50 µA
0.01
0.01
IC
IC
OL
25°C
0.09 0.15
0.15
0.09 0.15
0.15
V
= 2.5 V,
= 500 µA
OL
Full range
25°C
V
0.2
0.3
0.3
0.2
0.3
0.3
V
IC
= 2.5 V,
I
= 1 ꢈA
OL
Full range
25°C
80
50
170
80
50
170
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
550
12
550
12
= 1 MΩ
Ω
Ω
r
r
Differential input resistance
25°C
10
10
i(d)
i(c)
Common-mode input
resistance
12
8
12
8
25°C
25°C
25°C
10
10
Common-mode input
capacitance
c
z
f = 10 kHz,
P package
pF
i(c)
o
Closed-loop output
impedance
Ω
f = 100 kHz,
A
V
= 10
240
83
240
83
25°C
Full range
25°C
70
70
80
80
70
70
80
80
Common-mode rejection
ratio
V
IC
V
O
= 0 to 2.7 V,
= 2.5 V,
CMRR
dB
dB
R
= 50 Ω
S
95
95
Supply voltage rejection
V
= 4.4 V to 8 V,
DD
k
SVR
ratio (∆V
DD
/∆V
IO
)
V
IC
= V
/2,
No load
Full range
DD
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2262Q and TLV2262M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 5 V
DD
TLV2262Q,
TLV2262M
TLV2262AQ,
TLV2262AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
400 500
500
25°C
400
500
500
I
Supply current
V
O
= 2.5 V,
No load
µA
DD
Full range
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2262Q and TLV2262M operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2262Q,
TLV2262M
TLV2262AQ,
TLV2262AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX MIN
TYP
MAX
0.35
0.55
0.35
0.55
25°C
‡
Slew rate at unity
gain
V
C
= 0.5 V to 3.5 V,
‡
= 100 pF
R
= 50 kΩ
O
L
L
SR
V/µs
Full
range
0.25
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
40
12
40
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.3
0.7
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.017%
0.03%
0.017%
0.03%
O
V
f = 20 kHz,
R
THD + N
A
V
= 10
‡
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
0.71
185
0.71
185
MHz
kHz
‡
C
= 100 pF
L
Maximum
output-swing
bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
‡
‡
C = 100 pF
L
A
= −1,
V
To 0.1%
6.4
6.4
Step = 0.5 V to 2.5 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
14.1
14.1
‡
Phase margin at
unity gain
φ
m
25°C
25°C
56°
56°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 3 V
DD
TLV2264Q,
TLV2264M
TLV2264AQ,
TLV2264AM
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
300 2500
3000
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient
of input offset voltage
25°C
to 125°C
α
2
2
µV/°C
VIO
V
V
V
= 1.5 V,
= 0,
= 0,
= 50 Ω
DD
IC
O
Input offset voltage
long-term drift
(see Note 4)
25°C
0.003
0.5
0.003
0.5
µV/mo
R
S
25°C
125°C
25°C
60
800
60
60
800
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
800
800
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
V
V
R
= 50 Ω,
S
|V | ≤5 mV
IO
V
V
ICR
OH
OL
0
to
1.7
0
to
1.7
Full range
I
I
= −20 µA
25°C
25°C
2.99
2.99
OH
2.85
2.85
2.82
2.7
= −100 µA
High-level output
voltage
OH
Full range 2.82
25°C
Full range
25°C
2.7
2.6
I
= −400 µA
= 1.5 V,
OH
2.6
V
I
I
= 50 µA
10
10
IC
IC
OL
25°C
100
150
150
300
300
100
150
150
300
300
V
= 1.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
mV
200
100
100
200
100
100
V
IC
= 1.5 V,
I
= 1 ꢈA
OL
Full range
25°C
60
25
60
25
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 1.5 V,
= 1 V to 2 V
L
L
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
N package
= 10
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
270
75
270
77
25°C
Full range
25°C
65
60
80
80
65
60
80
80
Common-mode rejection
ratio
V
R
= 0 to 1.7 V,
= 50 Ω
V
= 1.5 V,
O
IC
S
CMRR
dB
dB
V
= 2.7 V to 8 V,
95
100
Supply voltage rejection
DD
= V
k
SVR
ratio (∆V
DD
/∆V )
IO
V
IC
/2,
DD
No load
Full range
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 3 V
DD
TLV2264Q,
TLV2264M
TLV2264AQ,
TLV2264AM
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
0.8
1
1
0.8
1
1
Supply current (four
amplifiers)
I
V
O
= 1.5 V,
No load
mA
DD
Full range
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2264Q and TLV2264M operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2264Q,
TLV2264M
TLV2264AQ,
TLV2264AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX MIN
TYP
MAX
25°C
0.35
0.55
0.35
0.55
‡
Slew rate at unity
gain
V
C
= 0.5 V to 1.7 V,
= 100 pF
R
= 50 kΩ ,
L
O
L
SR
V/µs
Full
range
‡
0.25
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
43
12
43
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.6
1
0.6
1
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.03%
0.05%
0.03%
0.05%
O
V
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 1 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.67
0.67
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 1 V,
= 50 kΩ ,
A
V
= 1,
O(PP)
L
B
OM
395
5.6
395
5.6
‡
‡
C = 100 pF
L
A
V
= −1,
To 0.1%
Step = 1 V to 2 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
12.5
12.5
‡
Phase margin at
unity gain
φ
m
25°C
25°C
55°
55°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 5 V
DD
TLV2264Q,
TLV2264M
TLV2264AQ,
TLV2264AM
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
300 2500
3000
300
950
V
IO
Input offset voltage
µV
Full range
1500
Temperature coefficient of
input offset voltage
25°C
to 125°C
α
2
2
µV/°C
VIO
V
V
V
= 2.5 V,
= 0,
= 0,
= 50 Ω
DD
IC
O
Input offset voltage
long-term drift
(see Note 4)
25°C
0.003
0.5
0.003
0.5
µV/mo
R
S
25°C
125°C
25°C
60
800
60
60
800
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
800
800
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
|V | ≤5 mV,
IO
R
= 50 Ω
V
V
ICR
S
0
to
3.5
0
to
3.5
Full range
I
I
= −20 µA
25°C
25°C
4.99
4.94
4.99
4.94
OH
4.85
4.85
4.82
4.7
= −100 µA
OH
Full range 4.82
V
V
High-level output voltage
Low-level output voltage
OH
25°C
Full range
25°C
4.7
4.5
4.85
4.85
I
= −400 µA
= 2.5 V,
OH
4.5
V
I
I
= 50 µA
0.01
0.09
0.01
0.09
IC
IC
OL
25°C
0.15
0.15
0.3
0.15
0.15
0.3
V
= 2.5 V,
= 500 µA
OL
Full range
25°C
V
OL
0.2
170
550
0.2
170
550
V
IC
= 2.5 V,
I
= 1 ꢈA
OL
Full range
25°C
0.3
0.3
80
50
80
50
‡
R
R
= 50 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
A
V/mV
VD
‡
25°C
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
N package
= 10
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
f = 100 kHz,
A
V
240
83
240
83
25°C
Full range
25°C
70
70
80
80
70
70
80
80
Common-mode rejection
ratio
V
R
= 0 to 2.7 V,
= 50 Ω
V
= 2.5 V,
O
IC
S
CMRR
dB
dB
V
= 4.4 V to 8 V,
95
95
Supply voltage rejection
DD
= V
k
SVR
ratio (∆V
DD
/∆V )
IO
V
IC
/2,
DD
No load
Full range
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TLV2264Q and TLV2264M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 5 V
DD
TLV2264Q,
TLV2264M
TLV2264AQ,
TLV2264AM
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
Full range
0.8
1
1
0.8
1
1
Supply current (four
amplifiers)
I
V
O
= 2.5 V,
No load
mA
DD
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2264Q and TLV2264M operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2264Q,
TLV2264M
TLV2264AQ,
TLV2264AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX MIN
TYP MAX
25°C
0.35
0.55
0.35
0.25
0.55
‡
Slew rate at unity
gain
V
C
= 0.5 V to 3.5 V,
= 100 pF
R
= 50 kΩ ,
L
O
L
SR
V/µs
Full
range
‡
0.25
f = 10 Hz
f = 1 kHz
25°C
25°C
40
12
40
12
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.3
0.7
1.3
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.017%
0.03%
0.017%
O
V
f = 20 kHz,
R
THD + N
A
V
= 10
0.03%
0.71
‡
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
0.71
185
MHz
kHz
‡
C
= 100 pF
L
Maximum
output-swing
bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
185
‡
‡
C = 100 pF
L
A
= −1,
V
To 0.1%
6.4
6.4
Step = 0.5 V to 2.5 V,
‡
t
s
Settling time
25°C
µs
R
C
= 50 kΩ ,
= 100 pF
L
L
To 0.01%
14.1
14.1
‡
Phase margin at
unity gain
φ
m
25°C
25°C
56°
56°
‡
‡
C = 100 pF
L
R
= 50 kΩ ,
L
Gain margin
11
11
dB
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution
vs Common-mode voltage
2 − 5
6, 7
V
IO
Input offset voltage
α
Input offset voltage temperature coefficient
Input bias and input offset currents
Distribution
8 − 11
12
VIO
I
/I
vs Free-air temperature
IB IO
vs Supply voltage
vs Free-air temperature
13
14
V
I
Input voltage
V
V
V
High-level output voltage
vs High-level output current
vs Low-level output current
vs Frequency
15, 18
16, 17, 19
20
OH
Low-level output voltage
OL
Maximum peak-to-peak output voltage
O(PP)
vs Supply voltage
vs Free-air temperature
21
22
I
Short-circuit output current
OS
V
Differential input voltage
vs Output voltage
vs Load resistance
23, 24
25
ID
A
VD
Differential voltage amplification
vs Frequency
vs Free-air temperature
26, 27
28, 29
A
Large-signal differential voltage amplification
Output impedance
VD
z
vs Frequency
30, 31
o
vs Frequency
vs Free-air temperature
32
33
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36, 37
k
Supply-voltage rejection ratio
Supply current
SVR
I
vs Free-air temperature
38, 39
DD
vs Load capacitance
vs Free-air temperature
40
41
SR
Slew rate
V
O
V
O
V
O
V
O
V
n
Inverting large-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Voltage-follower small-signal pulse response
Equivalent input noise voltage
42, 43
44, 45
46, 47
48, 49
50, 51
52
vs Frequency
Input noise voltage
Over a 10-second period
vs Frequency
Integrated noise voltage
53
THD + N
Total harmonic distortion plus noise
vs Frequency
54
vs Supply voltage
vs Free-air temperature
55
56
Gain-bandwidth product
Phase margin
vs Frequency
vs Load capacitance
26, 27
57
φ
m
Gain margin
vs Load capacitance
vs Load capacitance
vs Load capacitance
58
59
60
B
1
Unity-gain bandwidth
Overestimation of phase margin
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
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ꢁ
ꢔ
ꢙ
ꢔ
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
15
12
9
15
12
9
841 Amplifiers From 2 Wafer Lots
841 Amplifiers From 2 Wafer Lots
V
T
=
2.5 V
V
T
=
1.5 V
DD
DD
= 25°C
= 25°C
A
A
6
3
0
6
3
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 2
Figure 3
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
20
16
12
20
16
12
2272 Amplifiers From 2 Wafer Lots
1.5 V
= 25°C
2272 Amplifiers From 2 Wafer Lots
2.5 V
T = 25°C
A
V
T
A
=
V
DD
=
DD
8
4
0
8
4
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 4
Figure 5
23
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ꢄ
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ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†
†
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
1
1
0.5
0
V
R
T
A
= 3 V
= 50 Ω
= 25°C
DD
S
V
R
T
A
= 5 V
= 50 Ω
= 25°C
DD
S
0.5
0
−0.5
−0.5
−1
−1
−1 −0.5
0
0.5
1
1.5
2
2.5
3
−1
0
1
2
3
4
5
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 6
Figure 7
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
25
20
15
10
5
30
25
20
15
10
5
128 Amplifiers From 2 Wafer Lots
128 Amplifiers From 2 Wafer Lots
V
=
2.5 V
P Package
= 25°C to 85°C
V
=
1.5 V
P Package
= 25°C to 85°C
DD
DD
T
T
A
A
0
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
α
− Temperature Coefficient − µV/°C
α
− Temperature Coefficient − µV/°C
VIO
VIO
Figure 8
Figure 9
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢄ
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ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
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ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
35
30
25
20
15
10
35
30
25
20
15
10
128 Amplifiers From
2 Wafer Lots
128 Amplifiers From
2 Wafer Lots
V
=
1.5 V
N Package
= 25°C to 125°C
DD
V
=
2.5 V
N Package
= 25°C to 125°C
DD
T
A
T
A
5
0
5
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
α
− Temperature Coefficient
α
VIO
− Temperature Coefficient
of Input Offset Voltage − µV/°C
VIO
of Input Offset Voltage − µV/°C
Figure 10
Figure 11
†
INPUT BIAS AND INPUT OFFSET CURRENTS
INPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
35
30
25
2.5
2
R = 50 Ω
S
A
V
V
V
=
= 0
2.5 V
DD
T
= 25°C
IC
O
= 0
1.5
1
R
= 50 Ω
S
I
IB
0.5
0
20
15
| V | ≤5 mV
IO
−0.5
−1
−1.5
−2
I
IO
10
5
0
−2.5
25
45
65
85
105
125
1
1.5
2
2.5
3
3.5
4
T
A
− Free-Air Temperature − °C
|V
DD
| − Supply Voltage − V
Figure 12
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†‡
†‡
INPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
5
4
3.5
3
V
DD
= 5 V
V
DD
= 3 V
4
3
2
1
T
A
= −55°C
2.5
2
T
A
= 125°C
| V | ≤5 mV
IO
T
= 25°C
= 85°C
A
1.5
1
T
A
0
T
A
= −40°C
0.5
0
−1
0
500
1000
1500
2000
−55 −35 −15
5
25
45
65 85 105 125
T
A
− Free-Air Temperature − °C
| I
OH
| − High-Level Output Current − µA
Figure 14
Figure 15
‡
LOW-LEVEL OUTPUT VOLTAGE
vs
†‡
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
1.2
1
1.4
1.2
1
V
T
A
= 3 V
DD
= 25°C
V
V
= 3 V
= 1.5 V
DD
IC
T
A
= 125°C
V
= 0
IC
0.8
0.6
0.4
0.2
0
T
= 85°C
A
V
IC
= 0.75 V
0.8
0.6
T
A
= 25°C
V
IC
= 1.5 V
T
= − 55°C
A
0.4
T
A
= − 40°C
0.2
0
0
1
2
3
4
5
0
1
2
3
4
5
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 16
Figure 17
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
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ꢁ
ꢗ
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ꢏ
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ꢔꢑ
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SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†‡
†‡
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
6
5
4
3
2
1.4
1.2
V
V
= 5 V
= 2.5 V
DD
IC
V
= 5 V
DD
T
A
= −55°C
1
T
A
= 85°C
T
= −40°C
= 25°C
0.8
A
T
= 25°C
A
T
A
0.6
0.4
0.2
0
T
A
= 125°C
T
A
= 125°C
T
= −55°C
A
T
A
= 85°C
T
A
= −40°C
1
0
0
500
| I
1000
1500
2000
2500
3000
0
1
2
3
4
5
6
| − High-Level Output Current − µA
I
− Low-Level Output Current − mA
OH
OL
Figure 18
Figure 19
‡
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
FREQUENCY
SUPPLY VOLTAGE
5
12
10
V
T
= V /2
= 25°C
R = 10 kΩ
IC
A
DD
V
DD
= 5 V
I
V
ID
= −100 mV
T
= 25°C
A
4
8
6
3
2
V
DD
= 3 V
4
2
1
0
0
V
ID
= 100 mV
4
−2
3
4
5
6
10
10
10
10
2
3
5
6
7
8
V
DD
− Supply Voltage − V
f − Frequency − Hz
Figure 20
Figure 21
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V = 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD DD
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
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ꢀ
ꢑ
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ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†
‡
SHORT-CIRCUIT OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE
12
10
1000
800
V
V
= 2.5 V
O
V
= 3 V
DD
R = 50 kΩ
= 5 V
DD
I
V
T
= 1.5 V
= 25°C
IC
V
ID
= −100 mV
600
A
8
6
4
2
0
400
200
0
−200
−400
−600
−800
V
ID
= 100 mV
−2
−4
−1000
−75 −50 −25
0
25
50
75
100 125
0
0.5
1
1.5
2
2.5
3
T
A
− Free-Air Temperature − °C
V
O
− Output Voltage − V
Figure 22
Figure 23
‡
‡
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
OUTPUT VOLTAGE
LOAD RESISTANCE
1000
800
1000
100
V
= 2 V
V
V
R
= 5 V
O(PP)
DD
IC
L
= 2.5 V
= 50 kΩ
= 25°C
T
A
= 25°C
600
T
A
V
DD
= 5 V
400
200
V
DD
= 3 V
0
−200
−400
−600
−800
10
1
10
−1000
3
4
5
6
10
10
10
0
1
2
3
4
5
V
O
− Output Voltage − V
R
L
− Load Resistance − kΩ
Figure 24
Figure 25
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢄ
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ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
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ꢋ
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ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
180°
135°
V
= 5 V
DD
C = 100 pF
L
T
A
= 25°C
40
90°
45°
Phase Margin
20
0
Gain
0°
−20
−40
−45°
−90°
3
4
10
5
10
6
10
7
10
10
f − Frequency − Hz
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
†
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
180°
135°
V
C
T
A
= 3 V
= 100 pF
= 25°C
DD
L
40
20
90°
45°
Phase Margin
Gain
0
−20
−40
0°
−45°
−90°
3
4
10
5
10
6
10
7
10
10
f − Frequency − Hz
Figure 27
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
†‡
†‡
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1000
100
10
10000
1000
V
V
V
= 5 V
= 2.5 V
= 1 V to 4 V
DD
IC
O
R
= 1 MΩ
L
R
= 1 MΩ
= 50 kΩ
R
= 50 kΩ
L
L
R
R
L
L
R
= 10 kΩ
L
100
10
= 10 kΩ
V
V
V
= 3 V
= 1.5 V
DD
IC
O
= 0.5 V to 2.5 V
−75 −50 −25
0
25
50
75 100
125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 28
Figure 29
‡
‡
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
1000
100
10
1000
100
10
V
T
A
= 3 V
= 25°C
DD
V
T
A
= 5 V
= 25°C
DD
A
= 100
V
A
= 100
V
A
= 10
= 1
V
A
= 10
= 1
V
A
V
A
V
1
1
0.1
0.1
2
3
4
5
10
10
10
10
2
3
4
5
10
10
10
10
f− Frequency − Hz
f− Frequency − Hz
Figure 30
Figure 31
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢄ
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ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†
†‡
COMMON-MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
100
80
90
88
86
84
82
80
78
76
74
72
70
V
V
= 5 V
= 2.5 V
T
A
= 25°C
DD
IC
V
V
= 5 V
= 1.5 V
DD
IC
V
V
= 5 V
DD
60
40
20
0
= 3 V
DD
4
5
6
10
1
2
3
10
10
10
10
10
− 75 − 50 − 25
0
25 50
75 100
125
f − Frequency − Hz
T
− Free-Air Temperature − °C
A
Figure 32
Figure 33
†
†
SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
80
100
80
V
T
= 3 V
V
T
= 5 V
DD
= 25°C
DD
= 25°C
A
A
60
60
k
k
SVR+
SVR+
40
40
k
k
SVR−
SVR−
20
0
20
0
−20
−20
6
1
2
3
4
5
10
6
1
2
3
4
5
10
10
10
10
10
10
10
10
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 34
Figure 35
†
‡
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
= 3 V, all loads are referenced to 1.5 V.
DD
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
TLV2262
TLV2264
SUPPLY-VOLTAGE REJECTION RATIO
vs
†
SUPPLY-VOLTAGE REJECTION RATIO
†
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
110
105
110
105
V
V
= 2.7 V to 8 V
DD
= V = V /2
DD
V
V
= 2.7 V to 8 V
DD
= V = V /2
DD
IC
O
IC
O
100
95
100
95
90
90
−75
−75 −50 −25
0
25
50
75 100
125
−50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 36
Figure 37
TLV2264
†‡
TLV2262
SUPPLY CURRENT
†‡
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1200
600
500
1000
V
V
= 5 V
V
= 5 V
DD
DD
= 2.5 V
V
O
= 2.5 V
O
800
600
400
300
V
V
= 3 V
V
= 3 V
DD
DD
= 1.5 V
V
O
= 1.5 V
O
400
200
−75 −50 −25
0
25
50
75 100 125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 38
Figure 39
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔ
ꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†‡
†
SLEW RATE
vs
SLEW RATE
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
1
1.2
1
SR−
0.8
0.6
SR−
0.8
0.6
0.4
0.2
0
SR+
SR+
0.4
V
= 5 V
DD
0.2
0
R
C
A
= 50 kΩ
= 100 pF
= 1
L
L
V
V
A
T
A
= 5 V
DD
= −1
V
= 25°C
−75 −50 −25
0
25
50
75 100
125
1
2
3
4
10
10
10
10
T
A
− Free-Air Temperature − °C
C
− Load Capacitance − pF
L
Figure 40
Figure 41
INVERTING LARGE-SIGNAL PULSE
INVERTING LARGE-SIGNAL PULSE
†
†
RESPONSE
RESPONSE
3
2.5
2
5
4
V
= 3 V
V
R
C
A
T
= 5 V
DD
DD
R
C
A
T
= 50 kΩ
= 100 pF
= −1
= 50 kΩ
= 100 pF
= −1
L
L
V
L
L
V
= 25°C
= 25°C
A
A
3
2
1.5
1
1
0
0.5
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 42
Figure 43
†
‡
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
= 3 V, all loads are referenced to 1.5 V.
DD
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢄ
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ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
VOLTAGE-FOLLOWER LARGE-SIGNAL
†
†
PULSE RESPONSE
PULSE RESPONSE
3
2.5
2
5
4
V
= 5 V
= 50 kΩ
= 100 pF
= −1
V
= 3 V
= 50 kΩ
= 100 pF
= −1
DD
DD
R
C
A
T
R
C
A
T
L
L
V
L
L
V
= 25°C
= 25°C
A
A
3
2
1.5
1
1
0
0.5
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 44
Figure 45
INVERTING SMALL-SIGNAL
INVERTING SMALL-SIGNAL
†
PULSE RESPONSE
†
PULSE RESPONSE
0.95
0.9
2.65
V
= 3 V
DD
V
R
C
= 5 V
DD
L
L
R
C
A
= 50 kΩ
= 100 pF
= − 1
L
L
V
= 50 kΩ
= 100 pF
= −1
2.6
2.55
2.5
A
V
A
T
A
= 25°C
0.85
0.8
T
= 25°C
0.75
0.7
2.45
2.4
0.65
0.6
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 46
Figure 47
†
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢄ
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ꢆ
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ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER SMALL-SIGNAL
VOLTAGE-FOLLOWER SMALL-SIGNAL
†
PULSE RESPONSE
†
PULSE RESPONSE
0.95
0.9
2.65
2.6
V
= 3 V
= 50 kΩ
= 100 pF
= 1
DD
L
L
V
R
C
= 5 V
= 50 kΩ
= 100 pF
= 1
DD
L
L
R
C
A
V
A
A
V
A
T
= 25°C
T
= 25°C
0.85
0.8
2.55
2.5
0.75
0.7
2.45
2.4
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 48
Figure 49
†
†
EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
60
50
60
V
R
T
A
= 3 V
= 20 Ω
= 25°C
DD
S
V
R
S
T
A
= 5 V
= 20 Ω
= 25°C
DD
50
40
30
40
30
20
10
0
20
10
0
1
2
3
4
10
10
10
10
1
2
3
4
10
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 50
Figure 51
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢂ
ꢃ
ꢃ
ꢄ
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ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
INTEGRATED NOISE VOLTAGE
vs
INPUT NOISE VOLTAGE OVER
†
FREQUENCY
A 10-SECOND PERIOD
100
1000
750
Calculated Using Ideal Pass-Band Filter
Lower Frequency = 1 Hz
T
A
= 25°C
500
10
250
0
−250
−500
−750
−1000
1
V
= 5 V
DD
f = 0.1 Hz
to 10 Hz
T
A
= 25°C
0.1
1
2
3
4
5
0
2
4
6
8
10
1
10
10
10
10
10
t − Time − s
f − Frequency − Hz
Figure 52
Figure 53
†
TOTAL HARMONIC DISTORTION PLUS NOISE
GAIN-BANDWIDTH PRODUCT
vs
vs
FREQUENCY
SUPPLY VOLTAGE
−1
10
900
860
820
A
= 100
V
−2
10
A
A
= 10
= 1
V
V
780
740
700
V
R
T
A
= 5 V
= 50 kΩ
= 25°C
DD
L
−3
10
10
1
2
3
4
4
10
10
10
10
0
1
2
3
4
5
6
7
8
f − Frequency − Hz
V
− Supply Voltage − V
DD
Figure 54
Figure 55
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔ
ꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
†‡
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
75°
60°
45°
1200
V
= 5 V
DD
f = 10 kHz
= 100 pF
T
A
= 25°C
C
L
R
= 100 Ω
null
1000
800
R
= 50 Ω
null
R
= 20 Ω
= 10 Ω
null
30°
R
null
50 kΩ
600
400
V
15°
0°
DD +
DD −
50 kΩ
R
null
V
−
+
I
C
L
R
= 0
null
V
/GND
2
3
4
10
10
10
10
−75 −50 −25
0
25
50
75
100
125
C
− Load Capacitance − pF
L
T
A
− Free-Air Temperature − °C
Figure 56
Figure 57
GAIN MARGIN
vs
LOAD CAPACITANCE
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
20
15
10
1000
R
A
T
A
= 50 kΩ
= 1
= 25°C
L
V
T
A
= 25°C
R
= 100 Ω
null
800
600
400
200
R
= 50 Ω
null
R
= 20 Ω
null
5
0
R
= 10 Ω
null
R
= 0
null
2
3
4
2
3
4
10
10
10
10
10
10
10
10
C
− Load Capacitance − pF
C
− Load Capacitance − pF
L
L
Figure 58
Figure 59
†
‡
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
†
OVERESTIMATION OF PHASE MARGIN
vs
LOAD CAPACITANCE
14°
T
A
= 25°C
12°
10°
R
= 100 Ω
null
8°
6°
4°
2°
0
R
= 50 Ω
null
R
= 10 Ω
null
R
= 20 Ω
null
2
3
4
10
10
10
10
C
− Load Capacitance − pF
L
†
See application information
Figure 60
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
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ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
APPLICATION INFORMATION
driving large capacitive loads
The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51
and Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase
margins (R
= 0).
null
A smaller series resistor (R ) at the output of the device (see Figure 61) improves the gain and phase margins
null
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of
10 Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero
to the transfer function and the second is that it reduces the frequency of the pole associated with the output
load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation (1) can be used.
–1
ǒ2 × π × UGBW × R
LǓ
(1)
∆θ
Where :
+ tan
× C
m1
null
∆θ
+ improvement in phase margin
m1
UGBW + unity-gain bandwidth frequency
R
+ output series resistance
+ load capacitance
null
C
L
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To
use equation 1, UGBW must be approximated from Figure 53.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in equation 2.
1
F +
(2)
1 ) g × R
m
null
Where :
F + factor reducing frequency of pole
–3
g
+ small-signal output transconductance (typically 4.83 × 10
+ output series resistance
mhos)
m
R
null
For the TLV226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with C : at C = 10 pF, use 70 MHz, at C = 1000 pF, use 700 kHz, and so on.
L
L
L
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the equation 1 to better approximate the improvement
in phase margin.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢚ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢑꢖ ꢗ ꢓꢇꢀ ꢔ ꢑꢘ ꢇ ꢁ ꢇꢐ ꢖꢁ ꢔ ꢙꢔ ꢗꢓ ꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
APPLICATION INFORMATION
driving large capacitive loads (continued)
ȱUGBW
ȳ
UGBW
–1
–1ȧ
ȧ
∆θ
+ tan
– tan ǒ Ǔ
(3)
m2
P
ǒF×P
Ǔ
2
Ȳ
2 ȴ
Where :
∆θ
+ reduction in phase margin
m2
UGBW + unity-gain bandwidth frequency
F + factor from equation (2)
P
+ unadjusted pole (70 MHz @ 10 pF, 7 MHz @100 pF, etc.)
2
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
50 kΩ
V
DD+
50 kΩ
R
null
V
I
−
+
C
L
V
DD−
/GND
Figure 61. Series-Resistance Circuit
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢚ
ꢇꢈ
ꢉ
ꢊ
ꢋꢌ
ꢍ
ꢑ
ꢈ
ꢖ
ꢁ
ꢗ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢔꢑ
ꢘ
ꢇ
ꢁ
ꢇ
ꢐ
ꢖ
ꢁ
ꢔ
ꢙ
ꢔ
ꢗ
ꢓ
ꢒ
SLOS186B − FEBRUARY 1997 − REVISED MARCH 2001
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 62 are generated using
the TLV226x typical electrical and operating characteristics at T = 25°C. Using this information, output
A
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
99
DLN
3
EGND
+
−
V
CC+
92
9
FB
+
91
90
RSS
ISS
RO2
−
+
−
+
VB
DLP
RP
2
VLP
VLN
HLIM
−
+
−
10
+
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
−
DE
VAD
5
54
V
CC−
−
+
4
VE
OUT
.SUBCKT TLV226x 1 2 3 4 5
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
60
60
8
11
12
5
15.92E3
15.92E3
135
C1
11
6
12
7
5.5E−12
20.00E−12
DX
C2
DC
5
53
5
7
99
4
135
DE
54
90
92
4
DX
3
15.87E3
18.18E6
−.5
DLP
DLN
DP
91
90
3
DX
10
60
9
99
4
DX
DX
0
DC 0
EGND
FB
99
7
0
99
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
3
53
4
DC .615
DC .615
DC 0
54
7
+ VLN 0 8.84E6 −10E6 10E6 10E6 −10E6
VLIM
VLP
VLN
8
GA
6
0
6
11
10
12 62.83E−6
99 12.34E−9
91
0
0
DC 1
DC 5.1
GCM
ISS
HLIM
J1
0
92
3
10
0
DC 11.05E−6
VLIM 1K
10 JX
.MODEL DX D (IS=800.0E−18)
90
11
12
6
.MODEL JX PJF (IS=500.0E−15 BETA=325E−6
2
1
+ VTO=−.08)
.ENDS
J2
10 JX
R2
9
100.0E3
Figure 62. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-9550401Q2A
5962-9550401QHA
5962-9550401QPA
5962-9550402Q2A
5962-9550402QCA
5962-9550402QDA
5962-9550403Q2A
5962-9550403QHA
5962-9550403QPA
5962-9550404Q2A
5962-9550404QCA
5962-9550404QDA
TLV2262AID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
U
20
10
8
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
CDIP
LCCC
CDIP
CFP
JG
FK
J
20
14
14
20
10
8
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
W
FK
U
LCCC
CFP
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
CDIP
LCCC
CDIP
CFP
JG
FK
J
20
14
14
8
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
W
D
SOIC
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262AIDR
TLV2262AIDRG4
TLV2262AIP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
8
8
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLV2262AIPE4
TLV2262AIPW
TLV2262AIPWG4
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TSSOP
TSSOP
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262AIPWLE
TLV2262AIPWR
OBSOLETE TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262AIPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262AMFKB
TLV2262AMJGB
TLV2262AMUB
TLV2262AQD
TLV2262AQDR
TLV2262ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
10
8
1
SOIC
SOIC
SOIC
D
75
2500
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
D
8
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262IDG4
TLV2262IDR
TLV2262IDRG4
TLV2262IP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
P
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
Orderable Device
TLV2262IPE4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
P
8
8
8
8
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLV2262IPW
TSSOP
TSSOP
TSSOP
PW
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262IPWR
TLV2262IPWRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262MFKB
TLV2262MJGB
TLV2262MUB
TLV2262QD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
10
8
1
SOIC
SOIC
SOIC
D
75
2500
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
TLV2262QDR
TLV2264AID
D
8
D
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264AIDG4
TLV2264AIDR
TLV2264AIDRG4
TLV2264AIN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TLV2264AINE4
TLV2264AIPW
TLV2264AIPWG4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TSSOP
TSSOP
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264AIPWLE
TLV2264AIPWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264AIPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264AMFKB
TLV2264AMJB
TLV2264AMWB
TLV2264AQD
TLV2264AQDR
TLV2264ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
14
14
14
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
W
D
1
SOIC
SOIC
SOIC
50
2500
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264IDG4
TLV2264IDR
TLV2264IDRG4
TLV2264IN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
N
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
Orderable Device
TLV2264INE4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TLV2264IPW
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264IPWG4
TLV2264IPWR
TLV2264IPWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264MFKB
TLV2264MJ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
CFP
FK
J
20
14
14
14
14
14
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
TLV2264MJB
TLV2264MWB
TLV2264QD
TLV2264QDR
J
1
W
D
D
1
SOIC
SOIC
50
2500
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP001A – JANUARY 1995 – REVISED DECEMBER 1995
U (S-GDFP-F10)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.250 (6,35)
0.246 (6,10)
0.045 (1,14)
0.026 (0,66)
0.008 (0,20)
0.004 (0,10)
0.080 (2,03)
0.050 (1,27)
0.300 (7,62) MAX
0.019 (0,48)
0.015 (0,38)
1
10
0.050 (1,27)
0.280 (7,11)
0.230 (5,84)
5
6
4 Places
0.005 (0,13) MIN
0.350 (8,89)
0.250 (6,35)
0.350 (8,89)
0.250 (6,35)
4040179/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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