5962-9314801Q2X [TI]
ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20;
| 型号： | 5962-9314801Q2X |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20 信息通信管理 输出元件 逻辑集成电路 触发器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54ABT377
54ABT377 Octal D-Type Flip-Flop with Clock Enable
Literature Number: SNOS045
July 1998
54ABT377
Octal D-Type Flip-Flop with Clock Enable
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’ABT273 for master reset version
n See ’ABT373 for transparent latch version
n See ’ABT374 for TRI-STATE® version
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
n Non-destructive hot insertion capability
n Disable time less than enable time to avoid bus
contention
Features
n Clock enable for address and data synchronization
n Standard Microcircuit Drawing (SMD) 5962-9314801
applications
Ordering Code:
Military
Package
Number
Package Description
54ABT377J-QML
J20A
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
54ABT377W-QML
54ABT377E-QML
W20A
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin Assignment for LCC
Pin Assignment for
DIP and Cerpack
DS100216-11
Pin
Description
Names
DS100216-1
D0–D7 Data Inputs
CE
CP
Clock Enable (Active LOW)
Clock Pulse Input
Q0–Q7 Data Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100216
www.national.com
Truth Table
Mode Select-Function Table
Operating Mode
Inputs
Output
CP CE Dn
Qn
Load “1”
Load “0”
Hold
I
I
h
I
H
L
h
H
X
X
No Change
No Change
(Do Nothing)
X
=
=
=
=
H
h
L
I
X
=
HIGH Voltage Level
HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
LOW Voltage Level
LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
Immaterial
=
LOW-to-HIGH Clock Transition
Logic Diagram
DS100216-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings (Note 1)
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup
−500 mA
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
−65˚C to +150˚C
VCC + 4.5V
−55˚C to +125˚C
−55˚C to +175˚C
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
VCC Pin Potential to
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
−55˚C to +125˚C
−30 mA to +5.0 mA
Supply Voltage
Military
+4.5V to +5.5V
(∆V/∆t)
Minimum Input Edge Rate
Data Input
Power-Off State
−0.5V to +4.75V
−0.5V to VCC
50 mV/ns
20 mV/ns
in the HIGH State
Enable Input
Current Applied to Output
in LOW State (Max)
Twice the rated IOL (mA)
DC Electrical Characteristics
Symbol
Parameter
ABT377
Typ
Units VCC
Conditions
Min
Max
VIH
Input HIGH Voltage
2.0
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
=
Min IIN −18 mA
VCD
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
−1.2
V
V
=
Min IOH −3 mA
54ABT
54ABT
54ABT
2.5
2.0
=
IOH −24 mA
=
Min IOL 48 mA
VOL
IIH
Output LOW Voltage
Input HIGH Current
0.55
V
=
Max VIN 2.7V (Note 4)
5
5
7
µA
=
VIN VCC
=
Max VIN 7.0V
IBVI
Input HIGH Current
Breakdown Test
µA
µA
V
=
Max VIN 0.5V (Note 4)
IIL
Input LOW Current
−5
−5
=
VIN 0.0V
=
VID
Input Leakage Test
4.75
0.0
IID 1.9 µA
All Other Pins Grounded
=
Max VOUT 0.0V
IOS
Output Short-Circuit Current
Output High Leakage Current
Power Supply Current
−100
−275
50
mA
µA
=
ICEX
ICCH
ICCL
ICCT
Max VOUT VCC
50
µA
Max All Outputs HIGH
Max All Outputs LOW
Power Supply Current
30
mA
=
VI VCC − 2.1V
Maximum ICC/Input
Outputs Enabled
No Load
=
1.5
0.3
mA
Max Data Input VI VCC − 2.1V
All Others at VCC or GND
ICCD
Dynamic ICC
mA/ Max Outputs Open (Note 3)
MHz One bit Toggling, 50% Duty Cycle
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions
is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
<
Note 3: For 8 bits toggling, I
CCD
0.5 mA/MHz.
Note 4: Guaranteed but not tested.
3
www.national.com
AC Electrical Characteristics
Symbol
Parameter
54ABT
TA −55˚C to +125˚C
Units
=
=
VCC 4.5V to 5.5V
=
CL 50 pF
Min
Max
fmax
Max Clock
150
MHz
ns
Frequency
tPLH
tPHL
Propagation Delay
CP to On
2.2
2.8
6.0
6.8
AC Operating Requirements
54ABT
=
TA −55˚C to +125˚C
=
Symbol
Parameter
VCC 4.5V to 5.5V
Units
=
CL 50 pF
Min
Max
ts(H)
Setup Time, HIGH
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Setup Time, HIGH
or LOW CE to CP
Hold Time, HIGH
or LOW CE to CP
Pulse Width, CP,
HIGH or LOW
2.0
2.0
1.8
1.8
3.0
3.0
1.0
1.0
3.3
3.3
ns
ns
ns
ns
ns
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Typ
5
Units
Conditions
= =
VCC 0V, TA 25˚C
CIN
COUT (Note 5)
pF
pF
=
VCC 5.0V
9
=
C is measured at frequency f 1 MHz, per MIL-STD-883B, Method 3012.
OUT
Note 5:
www.national.com
4
AC Loading
DS100216-4
*Includes jig and probe capacitance
DS100216-5
FIGURE 1. Standard AC Test Load
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100216-6
=
FIGURE 2. VM 1.5V
DS100216-9
Input Pulse Requirements
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude Rep. Rate
3.0V 1 MHz
tw
tr
2.5 ns
tf
500 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100216-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Ceramic Chip Carrier
NS Package Number E20A
www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Dual-In-Line Package
NS Package Number J20A
20-Lead Ceramic Flatpack
NS Package Number W20A
7
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with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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相关型号：
5962-9314801QSX
ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20
TI
5962-9314901M2A
Bus Driver, ABT Series, 1-Func, 8-Bit, True Output, BICMOS, CQCC20, CERAMIC, LCC-20
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