5962-9222101M3A [TI]
8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS; 8位锁存户籍收发器,三态输出型号: | 5962-9222101M3A |
厂家: | TEXAS INSTRUMENTS |
描述: | 8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
文件: | 总12页 (文件大小:316K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
CY54FCT543T . . . D PACKAGE
CY74FCT543T . . . Q OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced V
of Equivalent FCT Functions
(Typically = 3.3 V) Versions
OH
LEBA
OEBA
1
24
V
CC
2
23 CEBA
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
A
A
A
A
A
A
A
A
3
22
21
20
19
18
17
16
15
14
13
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
5
I
Supports Partial-Power-Down Mode
off
6
Operation
7
Matched Rise and Fall Times
8
Fully Compatible With TTL Input and
Output Logic Levels
9
10
11
12
3-State Outputs
CEAB
GND
LEAB
OEAB
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Separation Controls for Data Flow in Each
Direction
Back-to-Back Latches for Storage
CY54FCT543T
– 48-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT543T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT543T octal latched transceivers contain two sets of eight D-type latches with separate latch-enable
(LEAB, LEBA) and output-enable (OEAB, OEBA) inputs for each set to permit independent control of input and
output in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB) input
must be low in order to enter data from A or to take data from B, as indicated in the function table. With CEAB
low, a low signal on the A-to-B latch-enable (LEAB) input makes the A-to-B latches transparent; a subsequent
low-to-high transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB low, the 3-state B-output buffers are active and reflect the data
present at the output of the A latches. Control of data from B to A is similar, but uses CEBA, LEBA, and OEBA
inputs.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
PIN DESCRIPTION
NAME
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
DESCRIPTION
A-to-B output-enable input (active low)
B-to-A output-enable input (active low)
A-to-B enable input (active low)
B-to-A enable input (active low)
A-to-B latch-enable input (active low)
B-to-A latch-enable input (active low)
A-to-B data inputs or B-to-A 3-state outputs
B-to-A data inputs or A-to-B 3-state outputs
B
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
TOP-SIDE
MARKING
†
T
PACKAGE
A
PART NUMBER
CY74FCT543CTQCT
CY74FCT543CTSOC
CY74FCT543CTSOCT
CY74FCT543ATQCT
CY74FCT543ATSOC
CY74FCT543ATSOCT
CY74FCT543TQCT
CY74FCT543TSOC
CY74FCT543TSOCT
CY54FCT543TDMB
CY54FCT543TLMB
QSOP – Q
SOIC – SO
QSOP – Q
SOIC – SO
QSOP – Q
SOIC – SO
Tape and reel
Tube
5.3
5.3
5.3
6.5
6.5
6.5
8.5
8.5
8.5
10
FCT543C
FCT543C
FCT543A
FCT543A
FCT543
Tape and reel
Tape and reel
Tube
–40°C to 85°C
Tape and reel
Tape and reel
Tube
FCT543
Tape and reel
Tube
–55°C to 125°C
CDIP – D
Tube
10
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡
FUNCTION TABLE
INPUTS
LATCH
A TO B
OUTPUT
B
§
CEAB
LEAB
OEAB
H
X
X
L
X
H
X
L
X
X
H
L
Storing
Storing
X
Z
X
Z
Transparent
Storing
Current A inputs
Previous A inputs
L
H
L
H = High logic level, L = Low logic level, X = Don’t care,
Z = High-impedance state
‡
A-to-Bdataflowshown;B-to-Aflowcontrolisthesame, exceptuses
CEBA, LEBA, and OEBA.
Before LEAB low-to-high transition
§
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
logic diagram (positive logic)
2
OEBA
23
CEBA
1
LEBA
13
OEAB
11
CEAB
14
LEAB
LE
3
A
0
22
Q
B
D
0
LE
D
Q
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
JA
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY54FCT543T
CY74FCT543T
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–12
48
0.8
–32
64
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
–40
85
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CY54FCT543T
CY74FCT543T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
= 4.75 V,
= 4.5 V,
I
I
I
I
I
I
I
= –18 mA
= –18 mA
–0.7
–1.2
CC
CC
CC
IN
V
V
IK
–0.7
–1.2
IN
= –12 mA
= –32 mA
= –15 mA
= 48 mA
= 64 mA
2.4
3.3
OH
OH
OH
OL
OL
V
OH
2
V
V
CC
= 4.75 V
2.4
3.3
V
V
= 4.5 V,
0.3
0.2
0.55
CC
V
V
V
V
OL
= 4.75 V,
0.3
0.2
0.55
CC
All inputs
hys
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
5
±1
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
IN
IN
IN
IN
IN
IN
CC
CC
I
I
I
I
I
µA
I
5
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
µA
µA
µA
µA
IH
±1
IL
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
= 0 V
10
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OZH
OZL
10
–10
–225
–10
–60
–120
‡
mA
µA
I
I
I
OS
= 0 V
–60
–120
–225
±1
= 4.5 V
±1
off
= 5.5 V,
= 5.25 V,
≤ 0.2 V,
V
V
≥ V
≥ V
– 0.2 V
– 0.2 V
0.1
0.5
0.2
IN
IN
IN
CC
mA
CC
≤ 0.2 V,
0.1
0.5
0.2
2
IN
CC
§
V
= 5.5 V, V = 3.4 V , f = 0, Outputs open
IN
2
CC
CC
CC
1
∆I
mA
CC
§
V
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
1
V
= 5.5 V, Outputs open,
One input switching at 50% duty cycle,
CEAB and OEAB = low, CEBA = high,
0.06
0.12
V
≤ 0.2 V or V ≥ V
– 0.2 V
mA/
MHz
IN
IN CC
¶
I
CCD
V
CC
= 5.25 V, Outputs open,
One input switching at 50% duty cycle,
CEAB and OEAB = low, CEBA = high,
0.06
0.12
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
IN CC
†
‡
Typical values are at V
= 5 V, T = 25°C.
CC
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, I
Per TTL-driven input (V = 3.4 V); all other inputs at V
This parameter is derived for use in total power-supply calculations.
tests should be performed last.
OS
§
¶
or GND
IN CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CY54FCT543T
CY74FCT543T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
One bit
switching
V
IN
V
IN
≤ 0.2 V or
0.7
1.4
≥ V
– 0.2 V
CC
at f = 5 MHz
1
V
= 5.5 V,
CC
= 10 MHz,
at 50% duty
cycle
f
0
V
IN
= 3.4 V or GND
1.2
3.4
Outputs open,
CEAB and OEAB =
low, CEBA = high,
Eight bits
switching
V
IN
V
IN
≤ 0.2 V or
||
5.6
2.8
≥ V
– 0.2 V
CC
f
0
= LEAB = 10 MHz
at f = 5 MHz
1
at 50% duty
cycle
||
V
= 3.4 V or GND
5.1 14.6
IN
#
I
C
mA
One bit
switching
V
IN
V
IN
≤ 0.2 V or
0.7
1.4
3.4
≥ V
– 0.2 V
CC
at f = 5 MHz
1
V
= 5.25 V,
CC
= 10 MHz,
at 50% duty
cycle
f
0
V
IN
= 3.4 V or GND
1.2
Outputs open,
CEAB and OEAB =
low, CEBA = high,
Eight bits
switching
V
IN
V
IN
≤ 0.2 V or
||
5.6
2.8
≥ V
– 0.2 V
CC
f
0
= LEAB = 10 MHz
at f = 5 MHz
1
at 50% duty
cycle
||
V
IN
= 3.4 V or GND
5.1 14.6
C
C
5
9
10
12
5
9
10
12
pF
pF
i
o
†
#
Typical values are at V
CC
= 5 V, T = 25°C.
A
I
I
∆I
D
N
= I
+ ∆I D N + I
(f /2 + f N )
C
CC
CC
H
CC
= Quiescent current with CMOS input levels
= Power-supply current for a TTL high input (V = 3.4 V)
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
CC H T CCD 0
1 1
IN
T
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
formula.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT543T
MIN MAX
CY74FCT543T CY74FCT543AT CY74FCT543CT
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, LEAB or LEBA
5
5
5
ns
ns
ns
Setup time, data before LEAB↓ or LEBA↓
Hold time, data after LEAB↓ or LEBA↓
3
2
2
2
2
2
2
2
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
switching characteristics over operating free-air temperature range (see Figure 1)
CY54FCT543T
MIN
CY74FCT543T CY74FCT543AT CY74FCT543CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MAX
10
10
14
14
14
14
14
14
13
13
13
13
MIN
2.5
2.5
2.5
2.5
2
MAX
8.5
8.5
12.5
12.5
12
12
12
12
9
MIN
2.5
2.5
2.5
2.5
2
MAX
6.5
6.5
8
MIN
2.5
2.5
2.5
2.5
2
MAX
5.3
5.3
7
t
t
t
t
t
t
t
t
t
t
t
t
2
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
A or B
B or A
A or B
A or B
A or B
A or B
A or B
2
2.5
2.5
2
ns
LEBA or LEAB
OEBA or OEAB
CEBA or CEAB
OEBA or OEAB
CEBA or CEAB
8
7
9
8
ns
2
2
2
9
2
8
2
2
2
9
2
8
ns
2
2
2
9
2
8
2
2
2
7.5
7.5
7.5
7.5
2
6.5
6.5
6.5
6.5
ns
2
2
9
2
2
2
2
9
2
2
ns
2
2
9
2
2
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT543T, CY74FCT543T
8-BIT LATCHED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCCS030A – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
Test
Point
From Output
Under Test
TEST
S1
t
t
/t
Open
7 V
C
= 50 pF
C = 50 pF
L
(see Note A)
PLH PHL
t
L
500 Ω
500 Ω
/t
(see Note A)
PLZ PZL
/t
PHZ PZH
Open
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
Timing Input
Data Input
0 V
t
w
t
h
t
su
3 V
0 V
3 V
0 V
1.5 V
1.5 V
Input
Input
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
t
t
t
t
t
PLZ
PLH
PHL
PLH
PZL
PZH
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
LCCC
Drawing
5962-9222101M3A
5962-9222101MLA
CY54FCT543TDMB
CY54FCT543TLMB
CY74FCT543ATQCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
28
24
24
28
24
1
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
JT
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
JT
FK
POST-PLATE N / A for Pkg Type
SSOP/
QSOP
DBQ
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT543ATQCTE4
CY74FCT543ATQCTG4
CY74FCT543ATSOC
CY74FCT543ATSOCE4
CY74FCT543ATSOCG4
CY74FCT543ATSOCT
CY74FCT543ATSOCTE4
CY74FCT543ATSOCTG4
CY74FCT543CTQCT
CY74FCT543CTQCTE4
CY74FCT543CTQCTG4
CY74FCT543CTSOC
CY74FCT543CTSOCE4
CY74FCT543CTSOCG4
CY74FCT543CTSOCT
CY74FCT543CTSOCTE4
CY74FCT543CTSOCTG4
CY74FCT543TQCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP/
QSOP
DBQ
DBQ
DW
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
DBQ
DBQ
DBQ
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
DBQ
DBQ
DBQ
DW
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
CY74FCT543TQCTE4
CY74FCT543TQCTG4
CY74FCT543TSOC
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CY74FCT543TSOCE4
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
CY74FCT543TSOCG4
CY74FCT543TSOCT
CY74FCT543TSOCTE4
CY74FCT543TSOCTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CY74FCT543ATQCT
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CY74FCT543ATSOCT
CY74FCT543CTQCT
SOIC
DW
24
24
2000
2500
330.0
330.0
24.4
16.4
10.75
6.5
15.7
9.0
2.7
2.1
12.0
8.0
24.0
16.0
Q1
Q1
SSOP/
QSOP
DBQ
CY74FCT543CTSOCT
CY74FCT543TQCT
SOIC
DW
24
24
2000
2500
330.0
330.0
24.4
16.4
10.75
6.5
15.7
9.0
2.7
2.1
12.0
8.0
24.0
16.0
Q1
Q1
SSOP/
QSOP
DBQ
CY74FCT543TSOCT
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CY74FCT543ATQCT
CY74FCT543ATSOCT
CY74FCT543CTQCT
CY74FCT543CTSOCT
CY74FCT543TQCT
CY74FCT543TSOCT
SSOP/QSOP
SOIC
DBQ
DW
24
24
24
24
24
24
2500
2000
2500
2000
2500
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
41.0
33.0
41.0
33.0
41.0
SSOP/QSOP
SOIC
DBQ
DW
SSOP/QSOP
SOIC
DBQ
DW
Pack Materials-Page 2
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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