5962-9174301M2A [TI]

OP-AMP, 1600uV OFFSET-MAX, CQCC20, LCC-20;


型号：	5962-9174301M2A
厂家：	TEXAS INSTRUMENTS
描述：	OP-AMP, 1600uV OFFSET-MAX, CQCC20, LCC-20
文件：	总14页 (文件大小：373K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

January 2001

CLC502

Clamping, Low Gain Op Amp with Fast 14-bit Settling

General Description

Features

n Output clamping with fast recovery

n 0.0025% settling in 25ns (32ns max)

n Low power, 170mW

The CLC502 is an operational amplifier designed for low

gain applications requiring output voltage clamping. This

feature allows the designer to set maximum positive and

negative output voltage levels for the amplifier – thus allow-

ing the CLC502 to protect downstream circuitry, such as

delicate converter systems from destructive transients or

signals which would otherwise cause saturation. The over-

load recovery time of only 8ns permits systems to resume

operation quickly after overdrive.

n Low distortion. −50dBc at 20MHz

Applications

n Output clamping applications

n High accuracy A/D systems (12-14 bits)

n High accuracy D/A converters

n Pulse amplitude modulation systems

High accuracy systems will also benefit from the CLC502’s

fast, accurate settling. Settling to 0.0025% in 25ns (32ns

guaranteed over temperature), the CLC502 is ideal as the

input amplifier in high accuracy (12 bits and above) A/D

systems. Unlike most other high speed op amps, the

CLC502 is free of settling tails. And, as the settling plots

show, settling to 0.01% accuracy is an even faster 18ns

typical.

Clamped Pulse Response (8x Overdrive)

The CLC502 is also useful in other applications which re-

quire low gain amplification ( 1 to 8) and the clamping or

overload recovery features. For example, even low resolu-

tion imaging circuits, which often have to cope with overload-

ing signal levels, can benefit from clamping and overload

recovery.

The CLC502 is available in several versions to meet a

variety of requirements. A three-letter suffix determines the

version:

Enhanced Solutions (Military/Aerospace)

SMD Number: 5962-91743

DS012754-1

Space level versions also available.

For more information, visit http://www.national.com/mil

Connection Diagram

DS012754-2

Pinout

DIP & SOIC

Ordering Information

Package

Temperature Range

Industrial

Part Number

Package

Marking

NSC

Drawing

N08E

8-pin Plastic DIP

−40˚C to +85˚C

CLC502AJP

CLC502AJE

CLC502AJP

CLC502AJE

8-pin Plastic SOIC

M08A

DS012754

www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Temperature Range

Storage Temperature Range

Lead Solder Duration (+300˚C)

ESD (Human Body Model)

−40˚C to +85˚C

−65˚C to +150˚C

10 sec

1000V

Supply Voltage (V_CC

I_OUT

Output is short circuit protected to

ground, but maximum reliability will

be maintained if I_OUTdoes not

exceed...

)

Operating Ratings

Thermal Resistance

Package

MDIP

θ_JC

θ_JA

60mA

65˚C/W

60˚C/W

120˚C/W

140˚C/W

Common Mode Input Voltage

Junction Temperature

V_CC

+150˚C

SOIC

Electrical Characteristics

5V, R_L=100Ω, R_f= 250Ω, V_H= +3V, V_L= −3V)

(A_V= +2, V_CC

Symbol

Parameter

Conditions

Typ

Max/Min Ratings (Note 2)

Units

Ambient Temperature

Frequency Domain Performance

CLC502AJ

+25˚C

−40˚C

+25˚C

+85˚C

100

SSBW

LSBW

-3dB Bandwidth

V_OUT0.5V_PP

150

100

110

MHz

V_OUT5V_PP

Gain Flatness

Peaking

V_OUT0.5V_PP

GFPL

GFPH

GFR

DC to 25MHz

0.4

0.7

1.0

1.2

0.3

0.5

1.0

0.4

0.7

1.0

1.2

Peaking

25MHz

Rolloff (Note 5)

Linear Phase Deviation

DC to 50MHz

0.5

0.4

LPD

deg

Time Domain Performance

TRS

TRL

TS14

TSP

TSS

Rise and Fall Time

0.5V Step

5V Step

2V Step

0.5V Step

2.7

5.0

3.5

3.2

3.5

500

Settling Time to 0.0025%

0.01%

0.1%

Overshoot

Slew Rate

800

V/µs

Distortion And Noise Performance

HD2

HD3

2nd Harmonic Distortion

3rd Harmonic Distortion

Equivalent Input Noise

Noise Floor

2V_PP, 20MHz

−50

−60

−38

−53

−43

−53

−43

−53

dBc

−155

SNF

INV

1MHz

−157

−155

dBm

(1Hz)

Integrated Noise

1MHz to

150MHz

µV

Differential Gain (Note 4)

Differential Phase (Note 4)

0.01

0.05

–

deg

Clamp performance

OVC

TSO

VOC

ICL

Overshoot in Clamp

2x Overdrive

–

Overload Recovery from Clamp

Clamp Accuracy(Note 3)

Input Bias Current on V_H, or V_L

−3dB Bandwidth

0.2

0.3

µA

MHz

CBW

V_Lor V_H

2V_PP

–

3.3

CMC

Clamp Voltage Range

V_Hor V_L

3.0

3.3

Static, DC Performance

2.8

VIO

Input Offset Voltage (Note 3)

0.5

2.6

1.6

www.national.com

Electrical Characteristics (Continued)

5V, R_L=100Ω, R_f= 250Ω, V_H= +3V, V_L= −3V)

(A_V= +2, V_CC

Symbol

Parameter

Conditions

Typ

Max/Min Ratings (Note 2)

Units

Static, DC Performance

DVIO

Average Temperature

Coefficient

–

µV/˚C

IBN

Input Bias Current (Note 3)

Non-Inverting

Inverting

µA

DIBN

Average Temperature

Coefficient

100

250

–

100

nA/˚C

IBI

Input Bias current (Note 3)

µA

DIBI

Average Temperature

Coefficient

100

250

–

100

nA/˚C

PSRR

CMRR

ICC

Power Supply Rejection Ratio

Common Mode Rejection Ratio

Supply Current (Note 3)

No Load

Miscellaneous Performance

RIN

CIN

Non-Inverting Input

Resistance

Capacitance

at DC

150

5.5

0.2

2.0

5.5

0.2

2.5

5.5

0.2

2.5

kΩ

Ω

Output Impedance

0.1

3.0

CMIR

Common Mode Input Range

Output Voltage Range

Output Current

3.2

No Load

3.5V

3.0

3.2

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined

from tested parameters.

Note 3: AJ-level: spec. is 100% tested at +25˚C.

Note 4: Differential gain and phase measure at A = +2V, R = 250Ω

Note 5: R = 150Ω, 1V equivalent video signal, 0-100 IRE, 40 IRE 0 IRE = 0 volts, at 75Ω load and 3.58 MHz

Typical Performance Characteristics (T_A= 25˚, A_V= +2, V_CC

5V, R_L= 100Ω, R_f= 250Ω, V_H

+3V, V_L= −3V)

Non-Inverting Frequency Response

Inverting Frequency Response

DS012754-5

DS012754-3

www.national.com

5V, R_L= 100Ω, R_f= 250Ω, V_H=

Typical Performance Characteristics (T_A= 25˚, A_V= +2, V_CC

+3V, V_L= −3V)) (Continued)

Frequency Response for Various R_Ls

Open-Loop Transimpedance Gain, Z(s)

DS012754-5

DS012754-6

2nd and 3rd Harmonic Distortion

2-Tone, 3rd Order Intermodulation Intercept

DS012754-8

DS012754-7

Equivalent Input Noise

CMRR and PSRR

DS012754-9

DS012754-10

www.national.com

5V, R_L= 100Ω, R_f= 250Ω, V_H=

Typical Performance Characteristics (T_A= 25˚, A_V= +2, V_CC

+3V, V_L= −3V)) (Continued)

Clamped Pulse Response (8x Overdrive)

Settling, Clamped (4x overdrive)

DS012754-11

DS012754-12

Long-Term Settling, Clamped (4x overdrive)

Nonlinearity Near Clamp Voltage

DS012754-14

DS012754-13

Settling, Umclamped

Long-Term Settling, Unclamped

DS012754-15

DS012754-16

www.national.com

5V, R_L= 100Ω, R_f= 250Ω, V_H=

Typical Performance Characteristics (T_A= 25˚, A_V= +2, V_CC

+3V, V_L= −3V)) (Continued)

Settling Time vs. Capacitive Load

DS012754-17

Application Division

DS012754-18

FIGURE 1. Recommended Non-Inverting Gain Circuit

www.national.com

Application Division (Continued)

DS012754-19

FIGURE 2. Recommended Inverting Gain Circuit

DS012754-20

FIGURE 3. Location of Damping Resistors (R_Q)

www.national.com

longer trying to drive the output voltage above the clamp

voltage. When this occurs, there is typically a 5-10ns “over-

load recovery from clamp,” which is the time it takes for the

op amp to resume linear operation. The normal op amp

parameters, such as the rise time, apply when the op amp is

in linear operation.

Application Division (Continued)

Clamp Operation

The maximum positive or negative excursion of the output

voltage is determined by voltages applied to the clamping

pins, V_Hand V_L. V_Hdetermines the positive clamping level;

V_Ldetermines the negative level. For example, if V_His set at

+2V and V_Lis set at −0.5V the output voltage is restricted

within this −0.5V to +2V range. When the output voltage tries

to exceed this level, the amplifier goes into “clamp mode”

and the output voltage limits at the clamp voltage.

Optimizing Settling Time Performance

To obtain the best possible settling time performance for the

CLC502, some additional design criteria must be consid-

ered, particularly when driving loads of less than 500Ω.

When driving a 100Ω load, a step of a few volts on the output

will create a large step of current in the power supplies. In

some cases, this step will cause a small ringing on the power

supply due to the bypass capacitor (.1µF) oscillating with the

inductance in the power supply trace. The critical trace is the

power supply trace between the two capacitors (a trace

inductance of 20nH will be enough to degrade settling time

performance). The frequency of the ring can be determined

Clamp Accuracy and Amplifier Linearity

Ideally, the clamped output voltage and the clamp voltage

should be identical. In practice, however, there are two

sources of clamp inaccuracy: the inherent clamp accuracy

(which is shown in the specification page) and resistor di-

vider action of open-loop output resistance of 10Ω and the

load resistor. Or, in equation form,

(1)

(3)

When settling the clamp voltages, the designer should also

recognize that within about 200mV of the clamp voltages,

amplifier linearity begins to deteriorate. (See plot on previous

page.)

and any reduction in this frequency will improve performance

due to better power supply rejection at lower frequencies . To

obtain the best performance, small resistor, R_Q, may be

added in the trace to dampen the circuit (SeeFigure 3). An

Biasing V_Hand V_L

R_Qof 5-10Ω will result in excellent settling performance and

Each of the clamping pins is buffered internally so simple

resistive voltage divider circuits work well in providing the

clamp voltages. V_Land V_Hcan be set by choosing the

divider resistors using:

will have only minor impact on other performance character-

istics. No provision for R_Qhas been made on the evaluation

board available from National as part 730013. It can, how-

ever, be easily added by cutting a trace and adding a 5- 10Ω

resistor, as shown in Figure 3, for both supplies.

DC Accuracy and Notes

(2)

Since the two inputs for the CLC502 are quite dissimilar, the

noise and offset error performance differs somewhat from

that of a standard differential input amplifier. The two input

bias currents are physically unrelated rendering bias current

cancellation through matching of the inverting and

non-inverting source resistance ineffective.

As a general guideline, let R₁+ R₂R₃+ R₄5kΩ.

V_Hshould be biased more positively than V_L. V_Hmay be

biased below 0V; however, with this biasing, the output

voltage will actually clamp at 0V unless a simple pull down

circuit is added to the op amp output (when clamped against

V_H, the output cannot sink current). An analogous situation

and design solution exists for V_Lwhen it is biased above 0V,

but in this case, a pull up circuit is used to source current

when the amplifier is clamped against V_L.

In Equation 3, the output offset is the algebraic sum of the

equivalent input voltage and current sources that influence

DC operation. Output noise is determine similarly except that

a root-sum-of-squares replaces the algebraic sum. R_sis the

non-inverting pin source resistance.

The clamp voltage range rating is that for normal operation.

Problems in over driven linearity may occur if the clamps are

set outside this range so this is not suggested under any

conditions. If the clamping capability is not required, the

CLC402 (low gain op amp with fast 14-bit settling) may be a

more appropriate part.

Output Offset V_o

IBN x R_s(1 + R_f/R_g)

VIO (1+ R_f/R_g) IBI x R_f

Printed Circuit Layout

As with any high frequency device, a good PCB layout will

enhance performance. Ground plane construction and good

power supply bypassing close to the package are critical to

achieving full performance. In the non-inverting configura-

tion, the amplifier is sensitive to stray capacitance to ground

at the inverting input. Hence, the inverting node connections

should be small with minimal coupling to the ground plane.

Shunt capacitance across the feedback resistor should not

be used to compensate for this effect.

The clamps, which have a bandwidth of about 50MHz, may

be driven by high frequency signal source. This allows the

clamping level to be modulated, which is useful in many

applications such as pulse amplitude modulation. The

source resistance of the signal source should be less than

500Ω to ensure stability.

Clamp-Mode Dynamics

As can be seen in the clamped pulse response plot, clamp-

ing is virtually instantaneous. Note, however, that there can

be a small amount of overshoot, as indicated on the speci-

fication page. The output voltage stays at the clamp voltage

level as long as the product of the input voltage and the gain

setting exceeds the clamp voltage. When the input voltage

decreases, it will eventually reach a point where it is no

The device is also very sensitive to parasitic capacitance on

the output pin. The plots include a suggested series R_Sto

de-couple this effect. Evaluation boards (part number

730013 for through-hole and 730027 for SOIC) for the

CLC502 are available.

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

8-Pin SOIC

NS Package Number M08A

8-Pin MDIP

NS Package Number N08E

www.national.com

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

See Scanners Products

CLC502 Product Folder

Clamping, Low Gain Op Amp with Fast 14-bit Settling

Generic P/N 502

General

Description

Package

& Models

Samples

& Pricing

Design

Tools

Application

Notes

Features

Datasheet

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Feb-

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CLC502 Clamping, Low Gain Op Amp with Fast 14-bit

Settling

297

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CLC502 Clamping, Low Gain Op Amp with Fast 14-bit

Settling (JAPANESE)

371

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Receive via

178

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CLC502 Mil-Aero Datasheet MNCLC502A-X

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Package Availability, Models, Samples & Pricing

Budgetary

Package

Type Pins MSL

Models

Samples &

Electronic

Orders

Std

Pack

Size

Pricing

$US

each

Package

Marking

Part

Number

Status

SPICE IBIS

Qty

rail

[logo]¢2¢T

CLC50

SOIC

NARROW

Lifetime

buy

MSL

clc502.cir

CLC502AJE

N/A

1K+ $3.2900

Buy Now

2AJE

reel

2500

[logo]¢2¢T

CLC50

SOIC

NARROW

CLC502AJE-

TR13

Lifetime

buy

2AJE

[logo]¢Z¢S¢4¢A

CLC502AE-

QML $E

5962-91743

01M2A

rail

5962-

9174301M2A

Full

production

LCC

MSL

clc502.cir

N/A

25+ $46.0000 of

rail [logo]¢Z¢S¢4¢A$E

N/A

CLC502AJ-

MPR

CERDIP

Preliminary

CLC502AJ-MPR

PROTO

[logo]¢Z¢S¢4¢A$E

CLC502AJ-QML

5962-9174301

MPA

rail

25+ $31.0000 of

5962-

9174301MPA

Full

production

CERDIP

MSL

clc502.cir

N/A

Buy Now

rail

500+ $23.7000 of

Lifetime

buy

[logo]¢U¢Z¢2¢T¢P

CLC502AJ

CERDIP

SIDEBRAZE

CERDIP

MSL

clc502.cir

CLC502AJ

N/A

rail

N/A

[logo]¢Z¢S¢4¢A

CLC502AD

CLC502AD-

MLS

Lifetime

buy

-MLS $E

rail

N/A

CLC502AJ-

MLS

[logo]¢Z¢S¢4¢A$E

CLC502AJ-MLS

Preliminary

General Description

The CLC502 is an operational amplifier designed for low gain applications requiring output voltage clamping.

This feature allows the designer to set maximum positive and negative output voltage levels for the amplifier

- thus allowing the CLC502 to protect downstream circuitry, such as delicate converter systems from

destructive transients or signals which would otherwise cause saturation. The overload recovery time of only

8ns permits systems to resume operation quickly after overdrive.

High accuracy systems will also benefit from the CLC502's fast, accurate settling. Settling to 0.0025% in

25ns (32ns guaranteed over temperature), the CLC502 is ideal as the input amplifier in high accuracy (12

bits and above) A/D systems. Unlike most other high speed op amps, the CLC502 is free of settling tails.

And, as the settling plots show, settling to 0.01% accuracy is an even faster 18ns typical.

The CLC502 is also useful in other applications which require low gain amplification (± 1 to ±8) and the

clamping or overload recovery features. For example, even low resolution imaging circuits, which often have

to cope with overloading signal levels, can benefit from clamping and overload recovery.

The CLC502 is available in several versions to meet a variety of requirements. A three-letter suffix

determines the version:

Enhanced Solutions (Military/Aerospace)

SMD Number: 5962-91743

*Space level versions also available.

*For more information, visit http://www.national.com/mil

Features

●

Output clamping with fast recovery

0.0025% settling in 25ns (32ns max)

Low power, 170mW

Low distortion. -50dBc at 20MHz

Applications

●

Output clamping applications

High accuracy A/D systems (12-14 bits)

High accuracy D/A converters

Pulse amplitude modulation systems

Design Tools

Title

Size in Kbytes Date

Receive via Email

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View Online

Amplifiers Selection Guide

software for Windows

12-Jun-

2002

View

7 Kbytes

CLC730013EB 8-pin Op Amp

Evaluation Board

15-May-

2001

View Online Download Receive via Email

130 Kbytes

CLC730027EB 8-Pin SOIC

Evaluation Board

15-May-

2001

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Application Notes

Size in

Kbytes

Title

Date

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via Email

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CLC730013EB:

CLC730013EB/CLC730027EB/CLC730077EB 8-pin Op

Amp Evaluation Boards

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130

Kbytes

2-Jan-

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CLC730027EB:

CLC730013EB/CLC730027EB/CLC730077EB 8-pin Op

Amp Evaluation Boards

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CLC730077EB:

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Amp Evaluation Boards

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130

Kbytes

2-Jan-

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OA-07: OA-07 Current- Feedback Op Amp Applications 308

28-Oct-

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Circuit Guide

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OA-11: OA-11 A Tutorial on Applying Op Amps to RF

Applications

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OA-12: OA-12 Noise Analysis for Comlinear's Op Amps

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OA-14: OA-14 Improving Amplifier Noise Figure for

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OA-15: OA-15 Frequent Faux Pas in Applying

Wideband Current Feedback Amplifiers

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OA-16: OA-16 Wideband AGC Amplifier as a

Differential Amplifier

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OA-18: OA-18 Simulation SPICE Models for

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OA-20: OA-20 Current Feedback Myths Debunked

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OA-30: OA-30 Current vs. Voltage Feedback Amplifiers

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[Information as of 5-Aug-2002]

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