5962-9052401MEA [TI]
具有三态输出的高速 CMOS 逻辑 8 输入多路复用器 | J | 16 | -55 to 125;
| 型号： | 5962-9052401MEA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的高速 CMOS 逻辑 8 输入多路复用器 | J | 16 | -55 to 125 复用器 |
| 文件： | 总11页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC251, CD74HC251,
CD54HCT251, CD74HCT251
Data sheet acquired from Harris Semiconductor
SCHS169C
High-Speed CMOS Logic
8-Input Multiplexer, Three-State
November 1997 - Revised October 2003
Features
Description
• Selects One of Eight Binary Data Inputs
• Three-State Output Capability
• True and Complement Outputs
The ’HC251 and ’HCT251 are 8-channel digital multiplexers
with three-state outputs, fabricated with high-speed silicon-
gate CMOS technology. Together with the low power
consumption of standard CMOS integrated circuits, they
possess the ability to drive 10 LSTTL loads. The three-state
feature makes them ideally suited for interfacing with bus
lines in a bus-oriented system.
[ /Title
(CD74
HC251
,
• Typical (Data to Output) Propagation Delay of 14ns at
o
V
= 5V, C = 15pF, T = 25 C
L A
CC
CD74
HCT25
1)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Input
Multi-
plexer;
Three-
• Fanout (Over Temperature Range)
This multiplexer features both true (Y) and complement (Y)
outputs as well as an output enable (OE) input. The OE must
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads be at a low logic level to enable this device. When the OE
input is high, both outputs are in the high-impedance state.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
When enabled, address information on the data select inputs
determines which data input is routed to the Y and Y
outputs. The ’HCT251 logic family is speed, function, and
pin-compatible with the standard ’LS251.
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• Alternate Source is Philips
• HC Types
TEMP. RANGE
o
- 2V to 6V Operation
PART NUMBER
CD54HC251F3A
CD54HCT251F3A
CD74HC251E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
CD74HC251M
V = 0.8V (Max), V = 2V (Min)
IL IH
CD74HC251MT
CD74HC251M96
CD74HCT251E
CD74HCT251M
CD74HCT251MT
CD74HCT251M96
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
Pinout
CD54HC251, CD54HCT251
(CERDIP)
CD74HC251, CD74HCT251
(PDIP, SOIC)
TOP VIEW
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
I
I
I
I
1
2
3
4
5
6
7
8
16 V
CC
3
2
1
0
15 I
14 I
13 I
12 I
4
5
6
7
Y
Y
11 S0
10 S1
OE
9
S2
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Functional Diagram
OE
7
4
3
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
2
1
CHANNEL
INPUTS
15
14
13
12
5
6
Y
Y
OUTPUTS
11
10
9
S
S
S
0
1
2
DATA
SELECT
TRUTH TABLE
INPUTS
OUTPUT
SELECT
OUTPUT
S2
X
L
S1
X
L
S0
X
L
CONTROL OE
Y
Y
H
L
L
L
L
L
L
L
L
Z
Z
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance
(Off), I , I ...I = the level of the respective input.
0
1
7
2
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
3.15
-
3.15
-
3.15
4.2
-
0.5
1.35
1.8
-
4.2
-
0.5
1.35
1.8
-
4.2
-
Low Level Input
Voltage
V
-
2
-
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
1.9
4.4
5.9
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
-
5.9
-
5.9
-
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
5.2
-
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
0.1
0.1
0.1
-
0.1
0.1
0.1
-
OL
4.5
6
-
-
Low Level Output
Voltage
TTL Loads
-
-
4
4.5
6
0.26
0.26
0.33
0.33
-
0.4
0.4
5.2
-
3
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
Input Leakage
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
Current
GND
Quiescent Device
Current
I
V
GND
or
0
6
6
-
-
-
-
8
-
-
80
-
-
160
µA
µA
CC
CC
Three-State Leakage
Current
-
V
or V
V
V
=
or
±0.5
±5.0
±10
IL
IH
O
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
0.02
4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
5.5
5.5
6
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
-
160
±10
CC
CC
GND
Three-State Leakage
Current
-
V
or V
V =
O
±0.5
±5.0
IL
IH
V
or
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
S0, S1, S2
UNIT LOADS
0.55
0.5
I0 - I7
OE
2.65
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
4
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP
MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Select to Outputs
t
t
t
t
C = 50pF
2
-
-
-
245
49
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
305
61
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
370
74
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C =15pF
21
-
L
C = 50pF
6
42
175
35
-
52
220
44
-
63
265
53
-
L
Data to Outputs
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C =15pF
12
-
L
C = 50pF
6
30
140
28
-
37
175
35
-
45
210
42
-
L
Enable to High Z and Enable
from High Z
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C =15pF
11
-
L
C = 50pF
6
24
75
15
13
10
15
30
95
19
16
10
15
36
110
22
19
10
15
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
IN
Three-State Output
Capacitance
CO
-
-
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
60
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay
Select to Outputs
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
42
-
-
-
-
-
-
-
-
-
-
53
-
-
-
-
-
-
-
-
-
63
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
C =15pF
18
-
L
Data to Outputs
t
t
, t
PLH PHL
C = 50pF
4.5
5
35
-
44
-
53
-
L
C =15pF
12
L
Enable to High Z and Enable
from High Z
, t
PLH PHL
C = 50pF
4.5
5
30
-
38
-
45
-
L
C =15pF
12
-
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
C
-
-
-
IN
Power Dissipation Capacitance
(Notes 3, 4)
C
5
60
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
2
PD
4. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
i
L
5
CD54HC251, CD74HC251, CD54HCT251, CD74HCT251
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
5962-9052401MEA
CD54HC251F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
16
1
1
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
CD54HC251F3A
CD54HCT251F3A
CD74HC251E
J
1
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC251M
CD74HC251M96
CD74HC251MT
CD74HCT251E
CD74HCT251M
CD74HCT251M96
CD74HCT251MT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
D
D
D
N
D
D
D
16
16
16
16
16
16
16
40
2500
250
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
2500
250
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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