5962-8869801EA [TI]
具有双时钟的同步 4 位加/减二进制计数器 | J | 16 | -55 to 125;
| 型号： | 5962-8869801EA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双时钟的同步 4 位加/减二进制计数器 | J | 16 | -55 to 125 时钟 逻辑集成电路 触发器 计数器 |
| 文件： | 总8页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
SN54ALS193A . . . J PACKAGE
SN74ALS193A . . . D OR N PACKAGE
(TOP VIEW)
Look-Ahead Circuitry Enhances Cascaded
Counters
Fully Synchronous in Count Modes
Parallel Asynchronous Load for Modulo-N
Count Lengths
B
V
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
Q
Q
B
A
CLR
BO
CO
LOAD
C
Asynchronous Clear
DOWN
UP
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
Q
C
Q
D
GND
D
description
SN54ALS193A . . . FK PACKAGE
(TOP VIEW)
The ’ALS193A are synchronous, reversible, 4-bit
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous (ripple-
clock) counters.
3
2
1
20 19
18
CLR
BO
Q
4
5
6
7
8
A
DOWN
NC
17
16
15
14
NC
CO
UP
LOAD
Q
C
9 10 11 12 13
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of either count/clock
(UP or DOWN) input. The direction of the count is
determined by which count input is pulsed while
the other count input is high.
NC – No internal connection
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on
the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the
data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent
of the count and LOAD inputs. The UP, DOWN, and LOAD inputs are buffered to lower the drive requirement,
which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words.
These counters are designed to be cascaded without the need for external circuitry. The borrow (BO) output
produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the
carry (CO) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input
is low. The counters can then be easily cascaded by feeding BO and CO to the count-down and count-up inputs,
respectively, of the succeeding counter.
The SN54ALS193A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS193A is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
†
logic symbol
CTRDIV16
14
CLR
UP
CT = 0
12
13
5
1CT = 15
2CT = 0
CO
BO
2+
G1
1–
4
DOWN
LOAD
G2
C3
11
15
1
3
2
6
7
[1]
Q
A
A
B
C
D
3D
[2]
[4]
[8]
Q
B
10
9
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
logic diagram (positive logic)
14
CLR
12
CO
13
11
BO
LOAD
5
UP
4
DOWN
S
R
15
A
S
3
Q
C1
1D
A
R
1
B
S
2
C1
Q
B
1D
R
10
C
S
6
C1
Q
C
1D
R
9
D
S
7
Q
C1
D
1D
R
Pin numbers shown are for the D, J, and N packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
typical clear, load, and count sequence
the following sequence is illustrated below:
1. Clear outputs to zero
2. Load (preset) to binary 13
3. Count up to 14, 15 (carry), 0, 1, and 2
4. Count down to 1, 0 (borrow), 15, 14, and 13
CLR
LOAD
A
B
Data
Inputs
C
D
UP
DOWN
Q
A
Q
B
Q
C
Q
D
Data
Outputs
CO
BO
0
13
14
15
0
1
2
1
0
15
14
13
Sequence
Illustrated
Count Up
Count Down
Clear
Preset
NOTES: A. Clear overrides load, data, and count inputs.
B. When counting up, count-down input must be high; when counting down, count-up input must be high.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS193A . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74ALS193A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS193A
MIN NOM MAX
SN74ALS193A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
10
25
30
25
20
20
5
20
0
10
20
16.5
20
20
20
5
30
CLR high
t
w
t
su
t
h
Pulse duration
Setup time
LOAD low
ns
ns
UP or DOWN high or low
Data before LOAD↑
CLR inactive before UP or DOWN
LOAD inactive before UP or DOWN
Data after LOAD↑
Hold time
UP high after DOWN↑
DOWN high after UP↑
5
0
ns
5
0
T
A
Operating free-air temperature
–55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS193A
SN74ALS193A
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
– 2
V
CC
– 2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 7 V
I
0.1
20
0.1
mA
I
CC
V = 2.7 V
I
20
µA
IH
IL
CC
UP or DOWN
All others
–0.2
–0.1
–112
22
–0.2
–0.1
– 112
22
I
V
CC
= 5.5 V,
V = 0.4 V
I
mA
§
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 2.25 V
O
–20
–30
mA
mA
O
CC
See Note 1
12
12
CC
CC
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
NOTE 1:
I
is measured with the clear and load inputs grounded and all other inputs at 4.5 V.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = R2 = 500 Ω,
T
A
FROM
(INPUT)
TO
(OUTPUT)
†
= MIN to MAX
PARAMETER
UNIT
SN54ALS193A SN74ALS193A
MIN
25
3
MAX
MIN
30
3
MAX
f
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PHL
20
21
20
22
27
23
38
37
20
16
18
16
18
19
17
30
28
17
UP
CO
3
5
4
4
DOWN
ns
ns
BO
5
5
3
3
UP or DOWN
Any Q
4
4
7
7
Any Q
Any Q
ns
ns
LOAD
CLR
8
8
5
5
†
For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS193A, SN74ALS193A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
WITH DUAL CLOCK AND CLEAR
SDAS211C – DECEMBER 1982 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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