5962-8688501JA [TI]
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 八路总线收发器和寄存器具有三态输出
| 型号： | 5962-8688501JA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
| 文件： | 总18页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
CD54HC646 . . . F PACKAGE
CD74HCT646 . . . M PACKAGE
(TOP VIEW)
2-V to 6-V V
Operation (CD54HC646)
CC
4.5-V to 5.5-V V
Operation (CD74HCT646)
CC
Wide Operating Temperature Range of
–55°C to 125°C
1
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
2
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
Balanced Propagation Delays and
Transition Times
3
4
Standard Outputs Drive Up To 15 LS-TTL
Loads
5
6
Significant Power Reduction Compared to
LS-TTL Logic ICs
7
8
Inputs Are TTL-Voltage Compatible
(CD74HCT646)
9
10
11
12
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
B8
description/ordering information
The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops,
and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal
registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate
clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can
be performed with these devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either or both registers.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be
stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one
of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
SOIC – M
CDIP – F
Tape and reel
Tube
CD74HCT646M96 HCT646M
CD54HC646F3A CD54HC646F3A
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
FUNCTION TABLE
DATA I/O
INPUTS
OPERATION OR FUNCTION
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
OE
X
X
H
H
L
†
†
†
↑
X
Unspecified
Input
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
21
3
1
23
2
22
SBA
L
21
3
DIR
H
1
23
CLKAB CLKBA SAB
L
2
22
SBA
X
DIR CLKAB CLKBA SAB
L
OE
L
OE
L
X
X
X
X
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
21
3
1
23
2
22
21
OE
L
3
DIR
L
1
23
2
22
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
X
H or L
X
X
H
X
H
X
X
L
H
H or L
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
logic diagram (positive logic)
21
OE
3
DIR
2
To Channels
SAB
2–8
22
SBA
1
CLKAB
23
CLKBA
CLK
D
V
CC
P
4
A1
N
V
CC
GND
P
20
B1
N
GND
Q
C
C
C
C
P
N
P
N
D
24
12
P N
C
P N
C
V
CC
C
C
GND
F/F
One of Eight Identical Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output drain current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2) M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
CC
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for CD54HC646 (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
2
1.5
6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
V
High-level input voltage
= 4.5 V
= 6 V
3.15
4.2
V
V
= 2 V
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
ns
t
T
–55
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions for CD74HCT646 (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
V
Supply voltage
5.5
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
V
V
V
V
CC
Output voltage
V
O
CC
t
Input transition (rise and fall) time
Operating free-air temperature
500
125
ns
°C
t
T
–55
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
electrical characteristics for CD54HC646 over recommended operating free-air temperature range
(unless otherwise noted)
T
= –55°C
T = –40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
1.9
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
I
= –20 µA
4.4
4.4
OH
V
V = V or V
IH
5.9
5.9
V
OH
OL
I
IL
IL
I
I
= –6 mA
4.5 V
6 V
3.98
5.48
3.84
5.34
OH
= –7.8 mA
OH
2 V
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
8
0.1
0.1
0.1
0.4
0.4
±1
0.1
0.1
0.1
0.33
0.33
±1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
V
I
IH
I
I
= 6 mA
4.5 V
6 V
OL
= 7.8 mA
OL
I
I
I
V = V
or 0
6 V
µA
µA
µA
pF
pF
I
I
CC
CC
V
O
= V
or 0
6 V
±10
160
10
±5
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
80
C
C
10
10
i
20
20
20
o
electrical characteristics for CD74HCT646 over recommended operating free-air temperature
range (unless otherwise noted)
T
= –55°C
T = –40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –6 mA
= 20 µA
= 6 mA
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
V
V
OH
I
IL
3.98
3.7
3.84
0.1
0.26
±0.1
±0.5
8
0.1
0.4
±1
0.1
0.33
±1
V = V or V
OL
I
IH
IL
I
I
I
V = V
I
to GND
5.5 V
5.5 V
5.5 V
µA
µA
µA
I
CC
V
O
= V or 0
CC
±10
160
±5
OZ
CC
V = V
I
or 0,
I
O
= 0
80
CC
One input at V
Other inputs at 0 or V
CC
– 2.1 V,
CC
†
4.5 V to 5.5 V
100
360
490
450
µA
∆I
CC
C
C
10
20
10
20
10
20
pF
pF
i
o
†
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
HCT INPUT LOADING TABLE
†
INPUT
UNIT LOAD
1.3
OE
DIR
0.75
CLKAB or CLKBA
SAB or SBA
0.6
0.45
0.3
A or B
†
Unit Load is ∆I
electrical characteristics table (e.g.,
limit specified in
CC
360 µA max at 25°C).
timing requirements for CD54HC646 over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 2)
T
= –55°C
T = –40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
V
CC
UNIT
MIN
MAX
6
MIN
MAX
MIN
MAX
5
2 V
4.5 V
6 V
4
20
23
f
t
t
t
Clock frequency
30
25
MHz
clock
35
29
2 V
80
16
14
60
12
10
35
7
120
24
20
90
18
15
55
11
9
100
20
17
75
15
13
45
9
Pulse duration, CLKBA or CLKAB high or low
Setup time, A before CLKAB↑ or B before CLKBA↑
Hold time, A after CLKAB↑ or B after CLKBA↑
4.5 V
6 V
ns
ns
ns
w
2 V
4.5 V
6 V
su
h
2 V
4.5 V
6 V
6
8
timing requirements for CD74HCT646 over recommended operating free-air temperature range,
= 4.5 V (unless otherwise noted) (see Figure 3)
V
CC
T
= –55°C
T = –40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
UNIT
MIN
MAX
MIN
MAX
17
MIN
MAX
f
t
t
t
Clock frequency
25
20
MHz
ns
clock
Pulse duration, CLKBA or CLKAB high or low
Setup time, A before CLKAB↑ or B before CLKBA↑
Hold time, A after CLKAB↑ or B after CLKBA↑
25
12
5
38
18
5
31
15
5
w
ns
su
h
ns
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
switching characteristics for CD54HC646 over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 2)
T
= –55°C
T = –40°C
A
A
T
A
= 25°C
FROM
(INPUT)
TO
LOAD
TO 125°C
TO 85°C
PARAMETER
V
UNIT
CC
(OUTPUT) CAPACITANCE
MIN
6
TYP
MAX
MIN
4
MAX
MIN
5
MAX
2 V
4.5 V
6 V
C
C
C
C
C
C
C
C
C
C
C
C
C
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
30
35
20
23
25
29
L
L
L
L
L
L
L
L
L
L
L
L
L
f
t
t
MHz
max
5 V
60
18
12
14
14
14
2 V
220
44
330
66
275
55
4.5 V
6 V
CLKBA or
CLKAB
A or B
B or A
A or B
A or B
37
56
47
5 V
2 V
135
27
205
41
170
34
4.5 V
6 V
A or B
ns
pd
23
35
29
5 V
2 V
170
34
255
51
215
43
4.5 V
6 V
SBA or
†
SAB
29
43
37
5 V
2 V
175
35
265
53
220
44
4.5 V
6 V
OE
ns
en
30
45
37
5 V
2 V
175
35
265
53
220
44
4.5 V
6 V
t
t
OE
A or B
Any
ns
ns
dis
30
45
37
5 V
2 V
60
12
10
90
18
15
75
15
13
4.5 V
6 V
t
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
switching characteristics for CD74HCT646 over recommended operating free-air temperature
range (unless otherwise noted) (see Figure 3)
T
= –55°C
T = –40°C
A
A
T
A
= 25°C
FROM
(INPUT)
TO
LOAD
TO 125°C
TO 85°C
PARAMETER
V
CC
UNIT
(OUTPUT) CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
C
C
C
C
C
C
C
C
C
C
C
C
C
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
4.5 V
5 V
25
17
20
L
L
L
L
L
L
L
L
L
L
L
L
L
f
t
t
MHz
max
pd
45
18
15
19
19
14
4.5 V
5 V
44
37
46
45
35
12
66
56
69
68
53
18
55
46
58
56
44
15
CLKBA or
CLKAB
A or B
B or A
A or B
A or B
A or B
4.5 V
5 V
A or B
ns
4.5 V
5 V
SBA or
†
SAB
4.5 V
5 V
ns
OE
en
4.5 V
5 V
t
t
ns
ns
OE
dis
4.5 V
t
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
52
pF
pd
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION – CD54HC646
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
Point
R
= 1 kΩ
L
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
or t
t
t
w
LOAD CIRCUIT
V
CC
Input
50% V
50% V
CC
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Reference
Input
V
CC
50% V
CC
CLR
Input
50% V
CC
0 V
0 V
t
t
h
su
t
rec
V
CC
CC
0 V
Data
Input
90%
90%
V
CC
50%
10%
50% V
10%
50% V
CC
CC
CLK
t
t
f
0 V
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
V
CC
Input
50% V
50% V
CC
Output
Control
50% V
50% V
CC
CC
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
Output
Waveform 1
(see Note B)
CC
50%
10%
50% V
10%
CC
50% V
CC
V
OL
10%
V
OL
t
t
f
r
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
50% V
10%
50%
10%
Output
Waveform 2
(see Note B)
V
OH
CC
90%
50% V
OL
CC
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. includes probe and test-fixture capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
pd
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC646, CD74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCHS278B – APRIL 2003 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION – CD74HCT646
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
1 kΩ
Point
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
or t
t
t
w
LOAD CIRCUIT
3 V
0 V
1.3 V
1.3 V
Input
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
Reference
Input
3 V
0 V
1.3 V
CLR
Input
1.3 V
t
t
h
su
t
rec
3 V
0 V
Data
Input
2.7 V
2.7 V
3 V
0 V
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
CLK
t
t
f
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
Input
1.3 V
1.3 V
Output
Control
1.3 V
1.3 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
CC
Output
Waveform 1
(see Note B)
1.3 V
10%
1.3 V
10%
1.3 V
V
OL
10%
V
OL
t
t
r
f
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
1.3 V
10%
1.3 V
10%
Output
Waveform 2
(see Note B)
V
OH
90%
1.3 V
OL
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
5962-8688501JA
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
CDIP
CDIP
SOIC
SOIC
SOIC
J
24
24
24
24
24
1
TBD
Call TI
N / A for Pkg Type
5962-8688501JA
CD54HC646F3A
CD54HC646F3A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
1
TBD
Call TI
N / A for Pkg Type
5962-8688501JA
CD54HC646F3A
CD74HCT646M96
CD74HCT646M96E4
CD74HCT646M96G4
DW
DW
DW
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
HCT646M
HCT646M
HCT646M
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC646 :
Catalog: CD74HC646
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HCT646M96
SOIC
DW
24
2000
330.0
24.4
10.75 15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
CD74HCT646M96
2000
Pack Materials-Page 2
MECHANICAL DATA
MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
B
13
24
C
12
1
0.065 (1,65)
0.045 (1,14)
Lens Protrusion (Lens Optional)
0.010 (0.25) MAX
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
0.140 (3,56)
A
Seating Plane
0.018 (0,46) MIN
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
24
28
32
40
PINS **
DIM
”A”
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
MIN
MAX
MIN
”B”
”C”
MAX
MIN
4040084/C 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).
D. This package can be hermetically sealed with a ceramic lid using glass frit.
E. Index point is provided on cap for terminal identification.
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