5962-8404801VCA [TI]
航天类 3 通道、3 输入、2V 至 6V 与门 | J | 14 | -55 to 125;
| 型号： | 5962-8404801VCA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 航天类 3 通道、3 输入、2V 至 6V 与门 | J | 14 | -55 to 125 CD 逻辑集成电路 |
| 文件： | 总31页 (文件大小：1932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74HC11, SN54HC11
ZHCSRL9E –DECEMBER 1982 –REVISED APRIL 2021
SNx4HC11 三路3 输入与门
1 特性
3 说明
• 缓冲输入
• 宽工作电压范围：2V 至6V
• 宽工作温度范围：
–40°C 至+85°C
• 支持多达10 个LSTTL 负载的扇出
• 与LSTTL 逻辑IC 相比，可显著降低功耗
此器件包含三个独立 3 输入与门。每个逻辑门以正逻
辑执行布尔函数Y = A ●B ●C。
器件信息(1)
封装尺寸（标称值）
器件型号
SN74HC11DR
SN74HC11NR
SN74HC11NSR
SN74HC11PWR
SN54HC11JR
SN54HC11WR
SN54HC11FKR
封装
SOIC (14)
PDIP (14)
SO (14)
8.70mm × 3.90mm
19.30mm × 6.40mm
10.20mm × 5.30mm
5.00mm × 4.40mm
21.30mm × 7.60mm
9.20mm × 6.29mm
8.90mm × 8.90mm
2 应用
TSSOP (14)
CDIP (14)
CFP (14)
• 将电源正常信号进行结合
• 使能数字信号
LCCC (20)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1
2
3
4
5
6
7
14
1A
1B
VCC
13
1C
12
2A
2B
1Y
11
3C
10
2C
2Y
3B
9
3A
8
GND
3Y
功能引脚分配
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS084
SN74HC11, SN54HC11
ZHCSRL9E –DECEMBER 1982 –REVISED APRIL 2021
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................13
11 Layout...........................................................................13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Documentation Support.......................................... 14
12.2 Related Links.......................................................... 14
12.3 支持资源..................................................................14
12.4 Trademarks.............................................................14
12.5 静电放电警告.......................................................... 14
12.6 术语表..................................................................... 14
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 Recommended Operating Conditions.........................4
6.3 Thermal Information....................................................4
6.4 Electrical Characteristics - 74..................................... 5
6.5 Electrical Characteristics - 54..................................... 5
6.6 Switching Characteristics - 74.....................................6
6.7 Switching Characteristics - 54.....................................6
6.8 Operating Characteristics........................................... 6
6.9 Typical Characteristics................................................6
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
Information.................................................................... 14
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (August 2003) to Revision E (April 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新至全新的数据表标准.................................................................................................................................... 1
• Increased thermals for D, PW and NS packages and decreased N package thermals..................................... 4
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5 Pin Configuration and Functions
1B 1A NC VCC 1C
1A
1B
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
1C
3
2
1
20 19
18 1Y
2A
NC
2B
4
5
6
7
8
2A
2B
1Y
3C
17 NC
16 3C
15 NC
14 3B
2C
2Y
3B
3A
3Y
NC
2C
GND
8
9
10 11 12 13
图5-1. D, N, NS, PW, J, or W Package
14-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP
Top View
GND NC 3Y 3A
2Y
图5-2. FK Package
20-Pin LCCC
Top View
Pin Functions
PIN
I/O
DESCRIPTION
D, N, NS,
PW, J, or W
NAME
FK
1A
1B
2A
2B
2C
2Y
GND
3Y
3A
3B
3C
1Y
1C
VCC
1
2
2
3
Input
Input
Input
Input
Input
Output
Channel 1, Input A
Channel 1, Input B
Channel 2, Input A
Channel 2, Input B
Channel 2, Input C
Channel 2, Output Y
Ground
3
4
4
6
5
8
6
9
7
10
12
13
14
16
18
19
20
—
8
Output
Input
Input
Input
Output
Input
Channel 3, Output Y
Channel 3, Input A
Channel 3, Input B
Channel 3, Input C
Channel 1, Output Y
Channel 1, Input C
Positive Supply
9
10
11
12
13
14
—
—
1, 5, 7, 11, 15,
17
NC
Not internally connected
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VCC
IIK
Supply voltage
7
±20
±20
±25
±50
150
150
–0.5
Input clamp current(2)
VI < 0 V or VI > VCC
VO < 0 V or VO > VCC
VO = 0 to VCC
mA
mA
mA
mA
°C
IOK
IO
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
Storage temperature
TJ
Tstg
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
UNIT
VCC
Supply voltage
5
6
V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
1.5
3.15
4.2
VIH
High-level input voltage
V
V
0.5
1.35
1.8
VIL
Low-level input voltage
VI
Input voltage
0
0
VCC
VCC
1000
500
400
125
85
V
V
VO
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
SN54HC00
SN74HC00
Input transition rise and fall rate
Operating free-air temperature
ns
°C
Δt/Δv
–55
–40
TA
6.3 Thermal Information
SN74HC11
THERMAL METRIC(1)
D (SOIC)
14 PINS
N (PDIP)
NS (SOP)
14 PINS
PW (TSSOP)
14 PINS
UNIT
14 PINS
Junction-to-ambient thermal
resistance
RθJA
133.6
89.0
89.5
45.5
65.2
122.6
81.8
83.8
45.4
151.7
79.4
94.7
25.2
°C/W
°C/W
°C/W
°C/W
Rθ
Junction-to-case (top) thermal
resistance
52.9
44.9
32.5
JC(top)
Junction-to-board thermal
resistance
RθJB
Junction-to-top characterization
parameter
ΨJT
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SN74HC11
N (PDIP)
THERMAL METRIC(1)
D (SOIC)
14 PINS
NS (SOP)
14 PINS
PW (TSSOP)
14 PINS
UNIT
14 PINS
Junction-to-board characterization
parameter
89.1
N/A
44.7
83.4
N/A
94.1
N/A
°C/W
°C/W
ΨJB
Rθ
Junction-to-case (bottom) thermal
resistance
N/A
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Electrical Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
TYP
-40°C to 85°C
MIN TYP
UNIT
MIN
1.9
MAX
MAX
2 V
1.998
4.499
5.999
4.3
1.9
4.4
IOH = -20 µA
4.5 V
6 V
4.4
High-level
output voltage
VI = VIH
or VIL
VOH
5.9
5.9
V
IOH = -4 mA
4.5 V
6 V
3.98
5.48
3.84
5.34
IOH = -5.2 mA
5.8
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
IOL = 20 µA
4.5 V
6 V
Low-level output VI = VIH
VOL
0.1
0.1
V
voltage
or VIL
IOL = 4 mA
4.5 V
6 V
0.26
0.26
0.33
0.33
IOL = 5.2 mA
0.15
Input leakage
current
II
VI = VCC or 0
6 V
6 V
±0.1
2
±1
20
10
µA
µA
pF
VI = VCC
ICC
Ci
Supply current
IO = 0
or 0
Input
capacitance
2 V to 6 V
3
10
6.5 Electrical Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
TYP MAX
UNIT
–40°C to 85°C
–55°C to 125°C
MIN
MIN
1.9
4.4
5.9
TYP MAX
MIN
1.9
4.4
5.9
TYP MAX
2 V
1.9 1.998
4.4 4.499
5.9 5.999
IOH = –20
µA
4.5 V
6 V
High-level
output voltage
VI = VIH or
VOH
V
IOH = –4
VIL
4.5 V
6 V
3.98
5.48
4.3
5.8
mA
IOH = –5.2
mA
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.4
IOL = 20
µA
4.5 V
6 V
Low-level output VI = VIH or
0.1
0.1
VOL
V
voltage
VIL
IOL = 4 mA 4.5 V
0.26
0.33
IOL = 5.2
6 V
0.15
0.26
0.33
0.4
mA
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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCC
25°C
TYP MAX
UNIT
–40°C to 85°C
MIN TYP MAX
–55°C to 125°C
MIN TYP MAX
MIN
Input leakage
current
II
VI = VCC or 0
6 V
±0.1
2
±1
20
10
±1
40
10
µA
µA
pF
VI = VCC or
ICC Supply current
IO = 0
6 V
0
Input
Ci
2 V to
6 V
3
10
capacitance
6.6 Switching Characteristics - 74
over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
25°C
TYP
PARAMETER
Propagation delay
Transition-time
FROM
TO
VCC
UNIT
ns
–40°C to 85°C
MIN TYP
MIN
MAX
100
20
MAX
125
25
2 V
35
10
8
tpd
A, B, or C
Y
Y
4.5 V
6 V
17
21
2 V
25
7
75
95
tt
4.5 V
6 V
15
19
ns
5
13
16
6.7 Switching Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER
Propagation delay
Transition-time
FROM
TO
VCC
25°C
UNIT
–40°C to 85°C
–55°C to 125°C
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2 V
35
10
8
100
20
17
75
15
13
125
25
21
95
19
16
150
A, B, or
C
tpd
Y
Y
4.5 V
6 V
30 ns
25
2 V
25
7
110
tt
4.5 V
6 V
22 ns
19
5
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Power dissipation capacitance
per gate
Cpd
No load
2 V to 6 V
25
pF
6.9 Typical Characteristics
TA = 25°C
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7
6
5
4
3
2
1
0.3
0.25
0.2
2-V
4.5-V
6-V
0.15
0.1
2-V
4.5-V
6-V
0.05
0
0
0
1
2
3
IOH Output High Current (mA)
4
5
6
0
1
2
3
IOL Output Low Current (mA)
4
5
6
图6-1. Typical output voltage in the high state
(VOH
图6-2. Typical output voltage in the low state (VOL)
)
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7 Parameter Measurement Information
• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.
Test
Point
VCC
0 V
VOH
VOL
90%
10%
90%
Input
10%
tf(1)
tr(1)
From Output
Under Test
(1)
90%
10%
90%
CL
Output
10%
tf(1)
tr(1)
A. CL= 50 pF and includes probe and jig capacitance.
A. tt is the greater of tr and tf.
图7-1. Load Circuit
图7-2. Voltage Waveforms Transition Times
VCC
Input
50%
50%
0 V
(1)
(1)
tPLH
tPHL
VOH
Output
50%
50%
VOL
(1)
(1)
tPHL
tPLH
VOH
Output
50%
50%
VOL
A. The maximum between tPLH and tPHL is used for tpd
.
图7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y = A ●B
●C in positive logic.
8.2 Functional Block Diagram
xA
xB
xC
xY
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
The SN74HC11 can drive a load with a total capacitance less than or equal to the maximum load listed in the
Switching Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the
provided load value. If larger capacitive loads are required, it is recommended to add a series resistor between
the output and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in
parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.
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8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in 图8-1.
CAUTION
Voltages beyond the values specified in the 节 6.1 table can cause damage to the device. The
recommended input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
+IIK
+IOK
Input
Output
Logic
GND
-IIK
-IOK
图8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
表8-1. Function Table
INPUTS
OUTPUT
A
H
L
B
H
X
L
C
H
X
X
L
Y
H
L
X
X
L
X
L
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
In this application, this device is used to directly control the RESET pin of a motor controller. The controller
requires three input signals to all be HIGH before being enabled, and should be disabled in the event that any
one signal goes LOW. The 3-input AND gate function combines the three individual reset signals into a single
active-low reset signal.
9.2 Typical Application
Power Supply
Motor Controller
PG
ON/OFF
RESET
OC
Over
Current
Detection
On/Off Switch
图9-1. Typical application schematic
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC11 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
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for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HC11, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC11 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates
can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to 节8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly,
the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics - 74.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to 节8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in 节11.
2. Ensure the capacitive load at the output is ≤70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC11
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
PG
OC
ON
OFF
Reset
图9-2. Typical application timing diagram
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SN74HC11, SN54HC11
ZHCSRL9E –DECEMBER 1982 –REVISED APRIL 2021
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
节 6.2. Each VCC terminal should have a bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is
recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of
noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power terminal as possible for best results, as shown in 图11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1 ꢀF
Unused input
tied to VCC
Unused
inputs tied to
GND
1A
1B
14
VCC
1
2
3
4
5
6
7
13
12
11
10
9
1C
1Y
3C
3B
3A
3Y
Unused
output left
floating
2A
2B
2C
2Y
Avoid 90°
corners for
signal lines
GND
8
图11-1. Example layout for the SN74HC11
Copyright © 2023 Texas Instruments Incorporated
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SN74HC11, SN54HC11
ZHCSRL9E –DECEMBER 1982 –REVISED APRIL 2021
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
PACKAGING INFORMATION
Orderable Device
5962-8404801VCA
84048012A
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
CDIP
J
14
20
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
N / A for Pkg Type
5962-8404801VC
Samples
Samples
A
SNV54HC11J
ACTIVE
LCCC
FK
1
Non-RoHS
& Green
SNPB
-55 to 125
84048012A
SNJ54HC
11FK
8404801CA
8404801DA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
J
14
14
14
14
14
1
1
1
1
1
Non-RoHS
& Green
SNPB
SNPB
SNPB
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8404801CA
SNJ54HC11J
Samples
Samples
Samples
Samples
Samples
Non-RoHS
& Green
8404801DA
SNJ54HC11W
JM38510/65204BCA
M38510/65204BCA
SN54HC11J
CDIP
CDIP
CDIP
Non-RoHS
& Green
JM38510/
65204BCA
J
Non-RoHS
& Green
JM38510/
65204BCA
J
Non-RoHS
& Green
SN54HC11J
SN74HC11DR
SN74HC11N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SO
D
N
14
14
14
14
20
2500 RoHS & Green
NIPDAU | SN
NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
HC11
Samples
Samples
Samples
Samples
Samples
25 RoHS & Green
SN74HC11N
HC11
SN74HC11NSR
SN74HC11PWR
SNJ54HC11FK
NS
PW
FK
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
TSSOP
LCCC
NIPDAU | SN
SNPB
HC11
1
Non-RoHS
& Green
84048012A
SNJ54HC
11FK
SNJ54HC11J
SNJ54HC11W
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
Non-RoHS
& Green
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
8404801CA
SNJ54HC11J
Samples
Samples
W
Non-RoHS
& Green
8404801DA
SNJ54HC11W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC11, SN54HC11-SP, SN74HC11 :
Catalog : SN74HC11, SN54HC11
•
Military : SN54HC11
•
Space : SN54HC11-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
Military - QML certified for Military and Defense Applications
•
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC11DR
SN74HC11NSR
SN74HC11PWR
SN74HC11PWR
SOIC
SO
D
14
14
14
14
2500
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
6.6
9.3
2.1
2.5
1.6
1.6
8.0
12.0
8.0
16.0
16.2
12.0
12.0
Q1
Q1
Q1
Q1
NS
PW
PW
8.45 10.55
TSSOP
TSSOP
6.85
6.9
5.45
5.6
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HC11DR
SN74HC11NSR
SN74HC11PWR
SN74HC11PWR
SOIC
SO
D
14
14
14
14
2500
2000
2000
2000
366.0
356.0
366.0
356.0
364.0
356.0
364.0
356.0
50.0
35.0
50.0
35.0
NS
PW
PW
TSSOP
TSSOP
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
84048012A
8404801DA
FK
W
N
LCCC
CFP
20
14
14
14
20
14
1
1
506.98
506.98
506
12.06
26.16
13.97
13.97
12.06
26.16
2030
6220
NA
NA
SN74HC11N
SN74HC11N
SNJ54HC11FK
SNJ54HC11W
PDIP
PDIP
LCCC
CFP
25
25
1
11230
11230
2030
4.32
4.32
NA
N
506
FK
W
506.98
506.98
1
6220
NA
Pack Materials-Page 3
GENERIC PACKAGE VIEW
FK 20
8.89 x 8.89, 1.27 mm pitch
LCCC - 2.03 mm max height
LEADLESS CERAMIC CHIP CARRIER
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
5962-8405601CA
HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, FRIT SEALED, CERDIP-14
RENESAS
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