5962-01-121-2314 [TI]
IC IC,LATCH,SINGLE,8-BIT,S-TTL,DIP,20PIN,PLASTIC, Bus Driver/Transceiver;
| 型号： | 5962-01-121-2314 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC IC,LATCH,SINGLE,8-BIT,S-TTL,DIP,20PIN,PLASTIC, Bus Driver/Transceiver |
| 文件： | 总14页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
SN74LS374 . . . DB, DW, N, OR NS PACKAGE
SN74S373 . . . DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OC
1Q
V
CC
Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
8Q
8D
7D
7Q
6Q
6D
5D
5Q
1D
P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
2D
2Q
3Q
description
3D
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
4D
4Q
†
GND
C
high-impedance
3-state
and
increased
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
15
14
9 10 11 12 13
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74LS373N
SN74LS374N
SN74S373N
SN74LS373N
SN74LS374N
SN74S373N
SN74S374N
Tube
PDIP – N
Tube
Tube
SN74S374N
Tube
SN74LS373DW
SN74LS373DWR
SN74LS374DW
SN74LS374DWR
SN74S373DW
SN74S373DWR
SN74S374DW
SN74S374DWR
SN74LS373NSR
SN74LS374NSR
SN74S374NSR
SN74LS374DBR
SN54LS373J
LS373
LS374
S373
Tape and reel
Tube
Tape and reel
Tube
0°C to 70°C
SOIC – DW
Tape and reel
Tube
S374
Tape and reel
Tape and reel
Tape and reel
Tape and reel
74LS373
SOP – NS
74LS374
74S374
SSOP – DB Tape and reel
LS374A
Tube
Tube
Tube
SN54LS373J
SNJ54LS373J
SN54LS374J
SNJ54LS374J
SN54S373J
SNJ54S373J
SN54S374J
SNJ54S374J
SNJ54LS373W
SNJ54LS374W
SNJ54S374W
SNJ54LS373FK
SNJ54LS374FK
SNJ54S373FK
SNJ54S374FK
SNJ54LS373J
SN54LS374J
Tube
CDIP – J
SNJ54LS374J
SN54S373J
Tube
Tube
Tube
Tube
Tube
SNJ54S373J
SN54S374J
–55°C to 125°C
SNJ54S374J
SNJ54LS373W
SNJ54LS374W
SNJ54S374W
SNJ54LS373FK
SNJ54LS374FK
SNJ54S373FK
SNJ54S374FK
CFP – W
Tube
Tube
Tube
Tube
Tube
Tube
LCCC – FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
Function Tables
’LS373, ’S373
(each latch)
INPUTS
OUTPUT
Q
OC
L
C
D
H
L
H
H
L
L
H
L
L
X
X
Q
0
H
X
Z
’LS374, ’S374
(each latch)
INPUTS
CLK
OUTPUT
Q
OC
L
D
H
L
↑
↑
H
L
L
L
L
X
X
X
Q
0
H
Z
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
logic diagrams (positive logic)
’LS373, ’S373
’LS374, ’S374
Transparent Latches
Positive-Edge-Triggered Flip-Flops
1
1
OC
C
OC
11
11
CLK
C1
1D
C1
1D
2
5
2
5
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
3
3
1D
2D
3D
4D
5D
6D
7D
8D
1D
2D
3D
4D
5D
6D
7D
8D
C1
1D
C1
1D
4
4
C1
1D
C1
1D
6
6
7
7
C1
1D
C1
1D
9
9
8
8
C1
1D
C1
1D
12
15
16
19
12
15
16
19
13
14
17
18
13
14
17
18
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
for ’S373 Only
for ’S374 Only
Pin numbers shown are for DB, DW, J, N, NS, and W packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
schematic of inputs and outputs
’LS373
TYPICAL OF ALL OUTPUTS
V
EQUIVALENT OF DATA INPUTS
EQUIVALENT OF ENABLE- AND
OUTPUT-CONTROL INPUTS
V
V
CC
CC
CC
100 Ω NOM
R
= 20 kΩ NOM
17 kΩ NOM
eq
Input
Input
Output
’LS374
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF DATA INPUTS
EQUIVALENT OF CLOCK- AND
OUTPUT-CONTROL INPUTS
V
CC
V
CC
V
CC
100 Ω NOM
30 kΩ NOM
17 kΩ NOM
Input
Input
Output
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(’LS devices)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54LS’
MIN NOM
SN74LS’
UNIT
MAX
5
MIN NOM
MAX
5.25
5.5
V
V
Supply voltage
4.5
5
4.75
5
V
V
CC
High-level output voltage
High-level output current
Low-level output current
5.5
–1
OH
I
I
–2.6
24
mA
mA
OH
12
OL
w
CLK high
CLK low
’LS373
15
15
15
15
t
t
t
Pulse duration
Data setup time
ns
ns
5↓
5↓
su
h
’LS374
20↑
20↓
5↑
20↑
20↓
0↑
’LS373
Data hold time
ns
‡
’LS374
T
A
Operating free-air temperature
–55
125
0
70
°C
‡
The t specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).
h
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS’
SN74LS’
†
PARAMETER
UNIT
TEST CONDITIONS
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
High-level input voltage
Low-level input voltage
Input clamp voltage
2
2
V
V
V
IH
0.7
0.8
IL
V
= MIN,
= MIN,
= V max,
IL
I = –18 mA
–1.5
–1.5
IK
CC
I
V
V
V
= 2 V,
= MAX
CC
IL
IH
V
High-level output voltage
Low-level output voltage
2.4
3.4
2.4
3.1
V
V
OH
OL
I
OH
I
= 12 mA
= 24 mA
0.25
0.4
0.25
0.35
0.4
0.5
V
V
= MIN,
= V max
IL
V
IH
V
IH
V
IH
= 2 V, OL
CC
IL
V
I
OL
Off-state output current,
high-level voltage applied
V
V
= MAX,
= 2.7 V
= 2 V,
= 2 V,
CC
O
I
I
I
20
–20
0.1
20
–20
0.1
A
OZH
OZL
I
Off-state output current,
low-level voltage applied
V
= MAX,
CC
A
V
O
= 0.4 V
Input current at maximum
input voltage
V
CC
= MAX,
V = 7 V
I
mA
I
I
I
High-level input current
Low-level input current
Short-circuit output current
V
V
V
= MAX,
= MAX,
= MAX
V = 2.7 V
20
–0.4
–130
40
20
–0.4
–130
40
A
mA
mA
IH
CC
CC
CC
I
V = 0.4 V
I
IL
§
–30
–30
OS
’LS373
’LS374
24
27
24
27
V
CC
= MAX,
I
Supply current
mA
CC
Output control at 4.5 V
40
40
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
CC
A
’LS373
’LS374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
MHz
ns
MIN
TYP
MAX
MIN
TYP
MAX
R
R
R
R
= 667 Ω C = 45 pF,
L
L
L
L
L
f
35
50
max
See Note 3
t
t
t
t
12
12
20
18
15
25
15
18
18
30
30
28
36
25
PLH
PHL
PLH
PHL
PZH
= 667 Ω C = 45 pF,
L
Data
C or CLK
OC
Any Q
Any Q
Any Q
See Note 3
15
19
20
21
15
28
28
26
28
28
= 667 Ω C = 45 pF,
L
ns
ns
See Note 3
t
= 667 Ω C = 45 pF,
L
See Note 3
t
PZL
PHZ
t
Any Q
R
= 667 Ω C = 5 pF
ns
OC
L
L
t
12
20
12
20
PLZ
NOTE 3: Maximum clock frequency is tested with all outputs loaded.
f
t
t
t
t
t
t
= maximum clock frequency
max
PLH
PHL
PZH
PZL
PHZ
PLZ
= propagation delay time, low-to-high-level output
= propagation delay time, high-to-low-level output
= output enable time to high level
= output enable time to low level
= output disable time from high level
= output disable time from low level
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
schematic of inputs and outputs
’S373 and ’S374
’S373 and ’S374
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
V
CC
V
CC
50 Ω NOM
2.8 kΩ NOM
Input
Output
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(’S devices)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54S’
MIN NOM
SN74S’
UNIT
MAX
5.5
5.5
–2
MIN NOM
MAX
5.25
5.5
V
V
Supply voltage
4.5
5
4.75
5
V
V
CC
High-level output voltage
High-level output current
OH
I
–6.5
mA
OH
High
6
7.3
0↓
6
7.3
0↓
t
Pulse duration, clock/enable
Data setup time
ns
ns
w
su
h
Low
’S373
’S374
’S373
’S374
t
t
5↑
5↑
10↓
2↑
10↓
2↑
Data hold time
ns
T
A
Operating free-air temperature
–55
125
0
70
°C
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)
†
‡
TYP
PARAMETER
MIN
MAX
UNIT
TEST CONDITIONS
V
2
V
V
V
IH
V
V
0.8
IL
V
V
= MIN,
= MIN,
I = –18 mA
–1.2
IK
CC
I
SN54S’
SN74S’
2.4
2.4
3.4
3.1
V
OH
V
IH
= 2 V,
V
= 0.8 V,
I
I
= MAX
V
CC
IL
OH
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN,
= MAX,
= MAX,
= MAX,
= MAX,
= MAX,
= MAX
V
IH
V
IH
V
IH
= 2 V,
= 2 V,
= 2 V,
V
IL
V
O
V
O
= 0.8 V,
= 2.4 V
= 0.5 V
= 20 mA
0.5
50
V
A
OL
OZH
OZL
I
OL
I
I
I
I
I
I
–50
1
A
V = 5.5 V
I
mA
A
V = 2.7 V
I
50
IH
V = 0.5 V
I
–250
–100
160
160
190
110
140
160
180
A
IL
§
–40
mA
OS
Outputs high
Outputs low
’S373
’S374
Outputs disabled
Outputs high
Outputs low
I
V
CC
= MAX
mA
CC
Outputs disabled
CLK and OC at 4 V, D inputs at 0 V
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
CC
A
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, V
= 5 V, T = 25°C (see Figure 2)
CC
A
’S373
’S374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
MHz
ns
MIN
TYP
MAX
MIN
TYP
MAX
R
R
R
R
= 280 Ω C = 15 pF,
L
L
L
L
L
f
75
100
max
See Note 3
t
t
t
t
t
t
t
t
7
7
12
12
14
18
15
18
9
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
= 280 Ω C = 15 pF,
L
Data
C or CLK
OC
Any Q
Any Q
Any Q
Any Q
See Note 3
7
8
11
8
15
17
15
18
9
= 280 Ω C = 15 pF,
L
ns
ns
ns
See Note 3
12
8
= 280 Ω C = 15 pF,
L
See Note 3
11
6
11
5
R
= 280 Ω C = 5 pF
OC
L
L
8
12
7
12
NOTE 3. Maximum clock frequency is tested with all outputs loaded.
f
t
t
t
t
t
t
= maximum clock frequency
max
PLH
PHL
PZH
PZL
PHZ
PLZ
= propagation delay time, low-to-high-level output
= propagation delay time, high-to-low-level output
= output enable time to high level
= output enable time to low level
= output disable time from high level
= output disable time from low level
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time with one input transition per measurement.
H. All parameters and waveforms are not applicable to all devices .
Figure 1. Load Circuits and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54S/74S DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
1 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
1.5 V
V
OH
Output
(see Note D)
1.5 V
1.5 V
1.5 V
V
OL
+ 0.5 V
V
OL
V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
– 0.5 V
Out-of-Phase
Output
V
V
OH
1.5 V
1.5 V
≈1.5 V
(see Note D)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
PLZ PZH
; S1 is closed and S2 is open for t .
PZL
PLH PHL PHZ
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series
O
r
f
54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.
r
f
F. The outputs are measured one at a time with one input transition per measurement.
G. All parameters and waveforms are not applicable to all devices .
Figure 2. Load Circuits and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
TYPICAL APPLICATION DATA
Bidirectional Bus Driver
Output
Control 1
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
’LS374
or
’S374
Bidirectional
Data Bus 1
Bidirectional
Data Bus 2
C
Clock 1
Clock 2
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
C
’LS374
or
’S374
Output
Control 2
H
Clock 1
Bus
Exchange
Clock
H
Clock 2
Clock Circuit for Bus Exchange
Expandable 4-Word by 8-Bit General Register File
’LS374 or ’S374
1/2 SN74LS139
or SN74S139
Y0
Y1
Y2
Y3
G
’LS374 or ’S374
’LS374 or ’S374
A
B
Enable Select
’LS374 or ’S374
Y0
A
Y1
Y2
Y3
1/2 SN74LS139
or SN74S139
B
G
Clock
Select
Clock
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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