5962-0051101NXD [TI]
14 位、8MSPS ADC 单通道、差动输入、DSP/uP 接口、可编程增益放大器、内部 S&H | PHP | 48 | -55 to 125;型号: | 5962-0051101NXD |
厂家: | TEXAS INSTRUMENTS |
描述: | 14 位、8MSPS ADC 单通道、差动输入、DSP/uP 接口、可编程增益放大器、内部 S&H | PHP | 48 | -55 to 125 放大器 转换器 |
文件: | 总32页 (文件大小:1043K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢀ ꢇꢈ ꢇꢉ ꢊꢋ ꢌꢋ ꢆ ꢍꢋ ꢌ ꢂꢎ ꢏ ꢊꢌꢐꢑꢒ ꢃꢓ ꢔ ꢐꢕ ꢐ ꢓꢏ ꢖꢂ ꢑꢏ ꢂ ꢍꢒ ꢖꢒ ꢑꢐ ꢓ
ꢎ ꢏ ꢕꢗ ꢔꢘ ꢑꢔꢘ ꢋ ꢙꢒ ꢑꢚ ꢒ ꢕꢑꢔ ꢘ ꢕꢐꢓ ꢘꢔ ꢛꢔ ꢘꢔ ꢕꢎ ꢔ ꢐꢕ ꢍ ꢌ ꢖꢐ
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
D
D
D
D
14-Bit Resolution
1, 3, and 8 MSPS Speed Grades Available
The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8
MSPS, single supply analog-to-digital converters (ADCs)
with an internal reference, differential inputs,
Differential Nonlinearity (DNL) 0.6 LSB Typ
Integral Nonlinearity (INL) 1.5 LSB Typ
Internal Reference
programmable
input
gain,
and
an
on-chip
sample-and-hold amplifier.
Implemented with a CMOS process, the device has
outstanding price/performance and power/speed ratios.
The THS1401, THS1403, and THS1408 are designed for
use with 3.3-V systems, and with a high-speed µP-
compatible parallel interface, making them the first choice
for solutions based on high-performance DSPs such as
the TI TMS320C6000 series.
Differential Inputs
Programmable Gain Amplifier
µP-Compatible Parallel Interface
Timing Compatible With TMS320C6000 DSP
3.3-V Single Supply
The THS1401, THS1403, and THS1408 are available in a
TQFP-48 package in standard commercial and industrial
temperature ranges. The THS1401, THS1403, and
THS1408 are also available in a PQFP-48 package in
automotive temperature range, and the THS1408 is
available in a PQFP-48 package in military temperature
range.
Power-Down Mode
Monolithic CMOS Design
APPLICATIONS
D
D
D
D
D
xDSL Front Ends
Communication
Industrial Control
Instrumentation
Automotive
VBG
REF+
REF−
REF
1.5 V
BG
IN+
IN−
14
15
PGA
0..7 dB
14-Bit
ADC
D[13:0] + OV bit
Buffer
6
A[1:0]
CONTROL
LOGIC
CLK
CS
WR
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright 1999−2005, Texas Instruments Incorporated
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted.
(1)
Supply voltage, (AV
Supply voltage, (DV
to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V
DD
DD
Reference input voltage range, VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to AV
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to AV
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to DV
+ 0.3 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
Operating free-air temperature range, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Q-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
A[1:0]
AGND
NO.
40, 41
I
Address input
Analog ground
Analog power supply
Clock input
7,8, 44, 45, 46
AV
DD
2, 43, 47
CLK
32
I
I
CML
CS
4
Reference midpoint. This pin requires a 0.1-µF capacitor to AGND.
Chip select input. Active low.
Digital ground
37
DGND
9, 15, 25, 33, 34
14, 20, 26, 30, 31, 42
DV
DD
Digital power supply
D[13:0]
11, 12, 13, 16, 17, 18,
19, 21, 22, 23, 24, 27,
28, 29
I/O
Data inputs/outputs
NC
IN+
38, 39
48
1
No connection; do not use. Reserved.
I
I
Positive differential analog input
IN−
Negative differential analog input
OE
35
10
5
I
Output enable. Active low.
OV
O
O
O
I
Out-of-range output
REF+
REF−
VBG
WR
Positive reference output. This pin requires a 0.1-µF capacitor to AGND.
Negative reference output. This pin requires a 0.1-µF capacitor to AGND.
Reference input. This pin requires a 1-µF capacitor to AGND.
Write signal. Active low.
6
3
36
I
2
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PFB AND PHP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
WR
36
35
34
33
32
31
30
29
28
27
26
25
IN−
1
2
3
4
5
6
7
8
9
10
OE
AV
DD
DGND
DGND
CLK
VBG
CML
REF+
REF−
AGND
AGND
DGND
OV
DV
DD
DV
DD
D0
D1
D2
DV
DD
DGND
D13 11
D12 12
13 14 15 16 17 18 19 20 21 22 23 24
NC − No internal connection
AVAILABLE OPTIONS
PACKAGED DEVICE
T
A
TQFP
(PFB)
PQFP (Power Pad)
(PHP)
THS1401CPFB,
THS1403CPFB,
THS1408CPFB
0°C to 70°C
—
—
THS1401IPFB,
THS1403IPFB,
THS1408IPFB
−40°C to 85°C
THS1401QPHP,
THS1403QPHP,
THS1408QPHP
−40°C to 125°C
−55°C to 125°C
—
—
THS1408MPHP
3
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
(1)
THERMAL CHARACTERISTICS
TYP
85.9
28.8
19.6
0.79
UNIT
PFB package
PHP package
PFB package
PHP package
Thermal resistance, junction-to-ambient, Θ
JA
°C/W
°C/W
Thermal resistance, junction-to-case, Θ
JC
(1)
Thermal resistance is modeled data, is not production tested, and is given for informational purposes only.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
UNIT
V
Supply voltage, AV , DV
DD DD
3
2
3.3
3.3
0
3.6
High level digital input, V
IH
V
Low level digital input, V
IL
V
0.8
15
Load capacitance, C
5
pF
L
THS1401
THS1403
THS1408
C- and I-suffix
Q- and M-suffix
C-suffix
0.1
0.1
0.1
40
1
1
3
MHz
MHz
MHz
3
Clock frequency, f
CLK
8
8
50
50
25
25
25
25
60
55
70
85
125
125
Clock duty cycle
%
45
0
I-suffix
−40
−40
−55
Operating free-air temperature
°C
Q-suffix
M-suffix
4
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, AVDD = DVDD = 3.3V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
I
I
Analog supply current
Digital supply current
Power
AV
DD
= 3.6 V
= 3.6 V
81
5
90
10
mA
mA
mW
µA
DDA
DV
DDD
DD
DD
AV
= DV
DD
= 3.6 V
270
20
360
Power down current
DC Characteristics
Resolution
14
0.6
1.5
1.5
2
Bits
DNL
INL
Differential nonlinearity
1
2.5
2.5
3
LSB
THS1401
THS1403C/I
THS1403Q
THS1408C/I
THS1408Q/M
Integral nonlinearity
Best fit
LSB
3
5
3.5
7.5
Offset error
Gain error
IN+ = IN−, PGA = 0 dB
PGA = 0 dB
0.3 %FSR
%FSR
C and I suffix
1
Q and M suffix
1.75 %FSR
AC Characteristics
ENOB
Effective number of bits
11.2
11.5
−81
−78
−77
72
Bits
dB
THS1401/3/8
THS1403/8
f = 100 kHz
i
f = 1 MHz
i
THD
Total harmonic distortion
THS1408
f = 4 MHz
i
THS1401/3/8
THS1403/8
f = 100 kHz
i
f = 1 MHz
i
70
69
72
SNR
Signal-to-noise ratio
dB
dB
THS1408
f = 4 MHz
i
71
THS1401/3/8
THS1403/8
f = 100 kHz
i
70
f = 1 MHz
i
70
SINAD Signal-to-noise ratio + distortion
THS1408
f = 4 MHz
i
70
THS1401/3/8
THS1403C/I, THS1408C/I
THS1403Q, THS1408Q/M
THS1408
f = 100 kHz
80
i
73
71
80
SFDR
Spurious-free dynamic range
Analog input bandwidth
f = 1 MHz
i
dB
80
f = 4 MHz
i
80
140
MHz
5
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS (Cont.)
Over operating free-air temperature range, AVDD = DVDD = 3.3V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference Voltage
Bandgap voltage, internal mode
Input impedance
1.425
1.5 1.575
V
kΩ
V
40
2.5
0.5
2
Positive reference voltage, REF+
Negative reference voltage, REF−
Reference difference, ∆REF, REF+ − REF−
Accuracy, internal reference
Temperature coefficient
V
V
5%
40
ppm/°C
Voltage coefficient
200
ppm/V
Analog Inputs
Positive analog input, IN+
Negative analog input, IN−
Analog input voltage difference
Input impedance
0
0
AV
AV
V
V
DD
DD
∆A = IN+ − IN−, V
IN REF
= REF+ − REF− −V
V
REF
V
REF
25
1
kΩ
dB
dB
dB
PGA range
0
7
PGA step size
PGA gain error
0.25
Digital Inputs
V
V
High-level digital input
Low-level digital input
Input capacitance
Input current
2
V
V
IH
0.8
1
IL
5
pF
µA
Digital Outputs
V
V
High-level digital output
I
I
= 50 µA
= 50 µA
2.6
V
V
OH
OH
Low-level digital output
0.4
10
OL
OL
I
Output current, high impedance
µA
OZ
Clock Timing (CS low)
†
THS1401
THS1403
THS1408
0.1
1
3
8
1
3
MHz
MHz
MHz
ns
†
0.1
f
t
Clock frequency
CLK
†
0.1
8
Output delay time
Latency
25
d
9.5
Cycles
†
This parameter is not production tested for Q- and M-suffix devices.
6
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
appear on the digital output 9.5 clock cycles after the input signal was sampled.
S11
S12
S9
S10
Analog
Input
t
t
w(CLK)
w(CLK)
CLK
t
d
Data
Out
C3
C1
C2
Figure 1. Sample Timing
The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register,
and the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are
available at address 0.
The timing of the control signals is described in the following sections.
7
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
read timing (15-pF load)
PARAMETER
Address and chip select setup time
MIN
TYP
MAX
UNIT
t
t
t
t
t
4
ns
ns
ns
ns
ns
su(OE−ACS)
Output enable
15
en
Output disable
10
dis
Address hold time
Chip select hold time
1
0
h(A)
h(CS)
NOTE: All timing parameters refer to a 50% level.
CS
t
h(CS)
OE
t
t
en
t
su(OE−ACS)
dis
DATA
D[13:0]
O V
t
h(A)
A[1:0]
X
ADDRESS
X
Figure 2. Read Timing
8
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
write timing (15-pF load)
PARAMETER
MIN
4
TYP
MAX
UNIT
ns
t
t
t
t
t
Chip select setup time
su(WE−CS)
Data and address setup time
Data and address hold time
Chip select hold time
29
0
ns
su(DA)
ns
h(DA)
0
ns
h(CS)
Write pulse duration high
15
ns
wH(WE)
NOTE: All timing parameters refer to a 50% level.
CS
t
h(CS)
WE
t
su(WE−CS)
t
su(DA)
X
X
X
DATA
D[13:0]
t
h(DA)
A
ADDRESS
X
Figure 3. Write Timing
9
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
POWER
vs
SUPPLY CURRENT
vs
FREQUENCY
TIME
90
80
70
60
50
40
30
20
284
282
280
278
276
274
272
270
268
10
0
0
50
100
150
200
250
300
0.1
1
10
f − Frequency − MHz
t − Time − ns
Figure 4
Figure 5
FAST FOURIER TRANSFORM
0
−20
f
= 1 MSPS,
s
f = 100 kHz,
I
−1 dB
−40
−60
−80
−100
−120
−140
0
100
200
300
400
500
f − Frequency − kHz
Figure 6
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM
0
−20
−40
f
= 3 MSPS,
s
f = 1 MHz,
I
−1 dB
−60
−80
−100
−120
−140
0.1
0.4
0.7
1
1.3
f − Frequency − MHz
Figure 7
FAST FOURIER TRANSFORM
0
f
= 8 MSPS,
s
−20
f = 1 MHz,
I
−1 dB
−40
−60
−80
−100
−120
−140
2.2
0.1
0.4
0.7
1
1.3
1.6
1.9
2.5
2.8
3.1
3.4
3.7
4
f − Frequency − MHz
Figure 8
INTEGRAL NONLINEARITY
2
f
s
= 1 MSPS
1.5
1
0.5
0
−0.5
−1
−1.5
−2
0
2048
4096
6144
8192
10240
12288
14336
16384
Samples
Figure 9
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
2
f
s
= 3 MSPS
1.5
1
0.5
0
−0.5
−1
−1.5
−2
0
2048
4096
6144
8192
10240
12288
14336
16384
Samples
Figure 10
INTEGRAL NONLINEARITY
4
3
f
s
= 8 MSPS
2
1
0
−1
−2
−3
−4
0
2048
4096
6144
8192
10240
12288
14336
16384
Samples
Figure 11
DIFFERENTIAL NONLINEARITY
1
0.8
0.6
f
s
= 1 MSPS
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
2048
4096
6144
8192
10240
12288
14336
16384
Samples
Figure 12
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
1
0.8
0.6
0.4
0.2
f
s
= 3 MSPS
0
−0.2
−0.4
−0.6
−0.8
−1
0
2048
4096
6144
8192
10240
12288
14336
16384
Samples
Figure 13
DIFFERENTIAL NONLINEARITY
1
f
s
= 8 MSPS
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
2048
4096
6144
8192
10240
12288
14336
16384
Samples
Figure 14
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
−70
−72
−74
−76
−78
−80
−82
−84
−86
−88
−90
−70
−72
−74
−76
−78
−80
−82
−84
−86
−88
−90
f
= 8 MSPS,
f
= 3 MSPS,
s
s
f at −1 dB
I
f at −1 dB
I
10
100
1000
4000
10
100
1000 1500
f − Frequency − Hz
f − Frequency − Hz
Figure 15
Figure 16
SIGNAL-TO-NOISE RATIO
SIGNAL-TO-NOISE RATIO
vs
vs
FREQUENCY
FREQUENCY
80
78
76
74
72
70
68
66
64
62
60
80
78
76
74
72
70
68
66
64
62
60
f
= 8 MSPS,
f
= 3 MSPS,
s
s
f at −1 dB
I
f at −1 dB
I
100
10
1000 1500
100
10
1000
4000
f − Frequency − Hz
f − Frequency − Hz
Figure 18
Figure 17
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PRINCIPLES OF OPERATION
registers
The device contains several registers. The A register is selected by the values of bits A1 and A0:
A1
0
A0
0
Register
Conversion result
PGA
0
1
1
0
Offset
1
1
Control
Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default
values (were applicable) show the state after a power-on reset.
Table 1. Conversion Result Register, Address 0, Read
BIT
D13
D12
...
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
MSB
…
…
…
…
…
…
…
…
…
…
…
LSB
The output can be configured for 2s complement or straight binary format (see D11/control register).
The output code is given by:
2s complement:
Straight binary:
−8192 at ∆IN = −∆REF
0
at ∆IN = −∆REF
0
at ∆IN = 0
8192 at ∆IN = 0
8191 ∆IN = +∆REF − 1 LSB
16383 at ∆IN = + ∆REF − 1 LSB
2DREF
16384
1 LSB +
Table 2. PGA Gain Register, Address 1, Read/Write
BIT
D13
X
D12
X
D11
X
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
G2
0
D1
G1
0
D0
G0
0
Function
Default
0
0
0
0
0
0
0
0
0
0
0
The PGA gain is determined by writing to G2−0.
Gain (dB) = 1dB × G2−0. max = 7dB. The range of G2−0 is 0 to 7.
Table 3. Offset Register, Address 2, Read/Write
BIT
D13
X
D12
X
D11
X
D10
X
D9
X
D8
X
D7
MSB
0
D6
…
0
D5
…
0
D4
…
0
D3
…
0
D2
…
0
D1
…
0
D0
LSB
0
Function
Default
0
0
0
0
0
0
The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC.
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
PRINCIPLES OF OPERATION
Table 4. Control Register, Address 3, Read
BIT
D13
D12
REF
D11
D10
TM2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
PWD
FOR
TM1
TM0
OFF
RES
RES
RES
RES
RES
RES
RES
Table 5. Control Register, Address 3, Write
BIT
D13
PWD
0
D12
REF
0
D11
FOR
0
D10
TM2
0
D9
TM1
0
D8
TM0
0
D7
OFF
0
D6
RES
0
D5
RES
0
D4
RES
0
D3
RES
0
D2
RES
0
D1
RES
0
D0
RES
0
Function
Default
PWD:
REF:
FOR:
Power down
0 = normal operation
0 = internal reference
0 = straight binary
1 = power down
Reference select
Output format
1 = external reference
1 = 2s complement
TM2−0: Test mode
000 = normal operation
001 = both inputs = REF−
010 = IN+ at V
(Voltage at CML pin), IN− at REF−
CM
011 = IN+ at REF+, IN− at REF−
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF−, IN− at V
(Voltage at CML pin)
CM
111 = IN+ at REF−, IN− at REF+
OF:
Offset correction
Reserved
0 = enable
1 = disable
RES
Must be set to 0.
APPLICATION INFORMATION
driving the analog input
The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR,
SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended
input.
There are three basic input configurations:
Fully differential
D
D
D
Transformer coupled single-ended to differential
Single-ended
fully differential configuration
In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN−.
22 Ω
IN+
100 pF
THS1401/3/8
22 Ω
IN−
100 pF
Figure 19. Differential Input
16
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve
as first order low pass filters to attenuate out of band noise.
The input range on both inputs is 0 V to AV . The full-scale value is determined by the voltage reference. The
DD
positive full-scale output is reached, if ∆IN equals ∆REF, the negative full-scale output is reached, if ∆IN equals
−∆REF.
∆IN [V]
−∆REF
0
OUTPUT
− full scale
0
∆REF
+ full scale
APPLICATION INFORMATION
transformer coupled single-ended to differential configuration
If the application requires the best SNR, SFDR, and THD performance, the input should be transformer
coupled.
The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus
increasing the ADC ac performance.
22 Ω
IN+
100 pF
R
THS1401/3/8
22 Ω
IN−
CML
100 pF
+
1 µF
0.1 µF
Figure 20. Transformer Coupled
The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale
output:
IN [V
]
OUTPUT [
]
PEAK
PEAK
†
−∆REF
− full scale
0
0
†
∆REF
n = 1 (winding ratio)
+ full scale
†
The resistor R of the transformer coupled input configuration must be set to match the signal source impedance
2
R = n Rs, where Rs is the source impedance and n is the transformer winding ratio.
APPLICATION INFORMATION
single-ended configuration
In this configuration, the input signal is level shifted by ∆REF/2.
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
10 kΩ + 10 kΩ
REF+
IN+
10 kΩ 10 kΩ
100 pF
THS1401/3/8
22 Ω
−
+
IN−
REF−
100 pF
10 kΩ
10 kΩ
Figure 21. Single-Ended With Level Shift
The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale
output:
∆IN+ [V]
−∆REF
0
OUTPUT
− full scale
0
∆REF
+ full scale
Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be
trimmed by varying the values of the resistors.
Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve
(best linearity around zero) and therefore may introduce unacceptable distortion. For ac signals, an alternative
is described in the following section.
APPLICATION INFORMATION
AC-coupled single-ended configuration
If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 21 is not
necessary.
10 kΩ
10 kΩ
REF+
IN+
10 kΩ
10 kΩ
100 pF
100 pF
THS1401/3/8
10 nF
−
+
IN−
REF−
22 Ω
10 kΩ
10 kΩ
Figure 22. Single-Ended With Level Shift
Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within
the linear region of the op-amp transfer function, thus increasing the overall ac performance.
IN [V
]
OUTPUT [ ]
PEAK
PEAK
−∆REF
− full scale
0
0
∆REF
+ full scale
Compared to the transformer-coupled configuration, the swing on IN− is twice as big, which can decrease the
ac performance (SNR, SFD, and THD).
18
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
APPLICATION INFORMATION
conditioning circuitry. If the offset compensation is
enabled (D7 (OFF) in the control register), the
value in the offset register (address 2) is
automatically added to the output of the ADC.
internal/external reference operation
The THS1401/3/8 ADC can either be operated
using the built-in band gap reference or using an
external precision reference in case very high dc
accuracy is needed.
In order to set the correct value of the offset
compensation register, the ADC result when the
input signal is 0 must be read by the host
processor and written to the offset register
(address 2).
The REF+ and REF+ outputs are given by:
2
3
REF )+ VBG 1 )
and REF–
test modes
The ADC core operation can be tested by
selecting one of the available test modes (see
control register description). The test modes
apply various voltages to the differential input
depending on the setting in the control register.
If the built-in reference is used, VBG equals 1.5 V
which results in REF+ = 2.5 V, REF− = 0.5 V and
∆REF = 2 V.
The internal reference can be disabled by writing
1 to D12 (REF) in the control register (address 3).
The band gap reference is then disconnected and
can be substituted by a voltage on the VBG pin.
digital I/O
The digital inputs and outputs of the THS1401/3/8
ADC are 3-V CMOS compatible. In order to avoid
current feed back errors, the capacitive load on
the digital outputs should be as low as possible (50
pF max). Series resistors (100 Ω) on the digital
outputs can improve the performance by limiting
the current during output transitions.
programmable gain amplifier
The on-chip programmable gain amplifier (PGA)
has eight gain settings. The gain can be changed
by writing to the PGA gain register (address 1).
The range is 0 to 7dB in steps of one dB.
The parallel interface of the THS1401/3/8 ADC
features 3-state buffers, making it possible to
directly connect it to a data bus. The output buffers
are enabled by driving the OE input low.
out of range indication
The OV output of the ADC indicates an out of
range condition. Every time the difference on the
analog inputs exceeds the differential reference,
this signal is asserted. This signal is updated the
same way as the digital data outputs and therefore
subject to the same pipeline delay.
Refer to the read and write timing diagrams in the
parameter measurement information section for
information on read and write access.
offset compensation
With the offset register it is possible to
automatically compensate system offset errors,
including errors caused by additional signal
19
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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
Revision History
DATE
REV
PAGE
SECTION
DESCRIPTION
1
1
2
2
3
3
—
—
—
—
—
—
Updated page 1 format and layout.
Moved funtional block diagram from page 2.
Moved Terminal Function table from page 3.
Moved Absolute Maximum table from page 4.
Moved package pinout from page 1.
Moved Ordering Options table from page 2.
9/05
D
Table 1. In section 2s complement: 8191 DIN = − DREF − 1 LSB changed to
8191 DIN = +DREF − 1 LSB. In section Straight Binary: 16383 at DIN = − DREF
− 1 LSB should be changed to 16383 DIN = +DREF − 1 LSB
15
16
Principles of Operation
Principles of Operation
Table 5. In section TM2−0: Test Mode: 010 = IN+ at V
REF
/2, IN− at REF−,
(Voltage at CML pin), IN− at REF−. Same section:
changed to, 010 = IN+ at V
CM
110 = IN+ at REF−, IN− at V
/2, changed to, 110 = IN+ at REF−, IN− at V
REF
CM
(Voltage at CML pin)
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
20
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-0051101NXD
ACTIVE
HTQFP
PHP
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-55 to 125
0051101
NXD
THS1401IPFB
THS1403IPFB
THS1408IPFB
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
250
250
250
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
TJ1401
TJ1403
TJ1408
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS1408, THS1408M :
Catalog: THS1408
•
Enhanced Product: THS1408-EP, THS1408-EP
•
Military: THS1408M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
5962-0051101NXD
THS1401IPFB
THS1403IPFB
THS1408IPFB
PHP
PFB
PFB
PFB
HTQFP
TQFP
TQFP
TQFP
48
48
48
48
250
250
250
250
10 x 25
10 x 25
10 x 25
10 x 25
150
150
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
Pack Materials-Page 1
GENERIC PACKAGE VIEW
PHP 48
7 x 7, 0.5 mm pitch
TQFP - 1.2 mm max height
QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
www.ti.com
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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