54F399FMQB [TI]

F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20, CERAMIC, FP-20;
54F399FMQB
型号: 54F399FMQB
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20, CERAMIC, FP-20

CD 输出元件 逻辑集成电路 触发器
文件: 总10页 (文件大小:164K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
May 1995  
54F/74F398 54F/74F399  
#
Quad 2-Port Register  
General Description  
Features  
Y
Select inputs from two data sources  
The ’F398 and ’F399 are the logical equivalents of a quad  
2-input multiplexer feeding into four edge-triggered flip-  
flops. A common Select input determines which of the two  
4-bit words is accepted. The selected data enters the flip-  
flops on the rising edge of the clock. The ’F399 is the 16-pin  
version of the ’F398, with only the Q outputs of the flip-flops  
available.  
Y
Fully positive edge-triggered operation  
Y
Both true and complement outputsÐ’F398  
Y
Guaranteed 4000V minimum ESD protectionÐ’F399  
Package  
Commercial  
74F398PC  
Military  
Package Description  
Number  
N20A  
J20A  
20-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F398DM (Note 2)  
20-Lead Ceramic Dual-In-Line  
74F398SC (Note 1)  
74F399PC  
M20B  
W20A  
E20A  
N20A  
J20A  
20-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
54F398FM (Note 2)  
54F398LM (Note 2)  
20-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
20-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F399DM (Note 2)  
20-Lead Ceramic Dual-In-Line  
74F399SC (Note 1)  
74F399SJ (Note 1)  
M20B  
M20D  
W20A  
E20A  
20-Lead (0.300 Wide) Molded Small Outline, JEDEC  
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F399FM (Note 2)  
54F399LM (Note 2)  
20-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 1: Devices also available in 13 reel. Use suffix  
SCX and SJX.  
×
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
e
DMQB, FMQB and LMQB.  
Connection Diagrams  
’F398  
Pin Assignment  
for LCC  
Pin Assignment  
for DIP, SOIC and Flatpak  
TL/F/9533–5  
TL/F/9533–6  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9533  
RRD-B30M75/Printed in U. S. A.  
Connection Diagrams (Continued)  
’F399  
TL/F/9533–8  
TL/F/9533–7  
TL/F/9533–2  
TL/F/9533–4  
Logic Symbols  
’F398  
IEEE/IEC  
’F398  
’F399  
TL/F/9533–1  
’F399  
TL/F/9533–3  
Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
Output I /I  
HIGH/LOW  
OH OL  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
S
Common Select Input  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33.3  
50/33.3  
CP  
Clock Pulse Input (Active Rising Edge)  
Data Inputs from Source 0  
I
I
–I  
0a 0d  
–I  
1a 1d  
Data Inputs from Source 1  
b
b
Q Q  
a
Register True Outputs  
1 mA/20 mA  
1 mA/20 mA  
d
d
Q Q  
a
Register Complementary Outputs (’F398)  
2
Function Table  
Functional Description  
The ’F398 and ’F399 are high-speed quad 2-port registers.  
They select four bits of data from either of two sources  
(Ports) under control of a common Select input (S). The  
selected data is transferred to a 4-bit output register syn-  
chronous with the LOW-to-HIGH transition of the Clock in-  
put (CP). The 4-bit D-type output register is fully edge-trig-  
Inputs  
Outputs  
S
I
I
Q
Q*  
0
1
I
I
I
X
X
I
L
H
L
H
L
h
X
X
h
h
H
L
gered. The Data inputs (I , I ) and Select input (S) must be  
0x 1x  
h
H
stable only a setup time prior to and hold time after the  
LOW-to-HIGH transition of the Clock input for predictable  
operation. The ’F398 has both Q and Q outputs.  
e
e
e
H
L
h
HIGH Voltage Level  
LOW Voltage Level  
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock  
transition  
e
transition  
I
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock  
e
X
Immaterial  
*’F398 only  
Logic Diagram  
TL/F/9533–9  
*’F398 Only  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
3
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
Recommended Operating  
Conditions  
Free Air Ambient Temperature  
Military  
Commercial  
b
a
55 C to 125 C  
§
0 C to 70 C  
§
§
b
b
a
65 C to 150 C  
Storage Temperature  
§
§
§
§
§
a
§
a
55 C to 125 C  
Ambient Temperature under Bias  
§
Supply Voltage  
Military  
Commercial  
b
b
a
a a  
4.5V to 5.5V  
a a  
4.5V to 5.5V  
Junction Temperature under Bias  
Plastic  
55 C to 175 C  
§
§
a
55 C to 150 C  
V
Pin Potential to  
CC  
Ground Pin  
b
a
0.5V to 7.0V  
b
a
0.5V to 7.0V  
Input Voltage (Note 2)  
Input Current (Note 2)  
Voltage Applied to Output  
b
a
30 mA to 5.0 mA  
e
in HIGH State (with V  
Standard Output  
0V)  
CC  
b
0.5V to 5.5V  
0.5V to V  
CC  
b
a
TRI-STATE Output  
É
Current Applied to Output  
in LOW State (Max)  
twice the rated I (mA)  
OL  
ESD Last Passing Voltage (Min)Ð’F399  
4000V  
Note 1: Absolute maximum ratings are values beyond which the device may  
be damaged or have its useful life impaired. Functional operation under  
these conditions is not implied.  
Note 2: Either voltage limit or current limit is sufficient to protect inputs.  
DC Electrical Characteristics  
54F/74F  
Symbol  
Parameter  
Units  
V
CC  
Conditions  
Min  
Typ  
Max  
V
V
V
V
Input HIGH Voltage  
2.0  
V
V
V
Recognized as a HIGH Signal  
Recognized as a LOW Signal  
IH  
Input LOW Voltage  
0.8  
IL  
b
e b  
18 mA  
Input Clamp Diode Voltage  
1.2  
Min  
Min  
I
IN  
CD  
OH  
e b  
e b  
e b  
Output HIGH  
Voltage  
54F 10% V  
2.5  
2.5  
2.7  
I
I
I
1 mA  
1 mA  
1 mA  
CC  
OH  
OH  
OH  
74F 10% V  
74F 5% V  
V
CC  
CC  
e
e
V
Output LOW  
Voltage  
54F 10% V  
74F 10% V  
0.5  
I
I
20 mA  
20 mA  
OL  
CC  
OL  
V
Min  
Max  
Max  
Max  
0.0  
0.5  
CC  
OL  
e
I
I
I
Input HIGH Current  
54F  
74F  
20.0  
5.0  
V
V
V
2.7V  
IH  
IN  
mA  
mA  
mA  
V
e
Input HIGH Current  
Breakdown Test  
54F  
74F  
100  
7.0  
7.0V  
BVI  
IN  
e
V
CC  
Output HIGH  
54F  
74F  
250  
50  
CEX  
OUT  
Leakage Current  
e
All Other Pins Grounded  
V
ID  
Input Leakage  
Test  
I
ID  
1.9 mA  
74F  
74F  
4.75  
e
IOD  
I
Output Leakage  
Circuit Current  
V
150 mV  
OD  
3.75  
mA  
0.0  
All Other Pins Grounded  
b
e
0.5V  
I
I
I
I
I
I
Input LOW Current  
0.6  
mA  
mA  
mA  
mA  
mA  
mA  
Max  
Max  
Max  
Max  
Max  
Max  
V
V
V
V
V
V
IL  
IN  
b
b
e
OUT  
Output Short-Circuit Current  
Power Supply Current (’F398)  
Power Supply Current (’F398)  
Power Supply Current (’F399)  
Power Supply Current (’F399)  
60  
150  
0V  
HIGH  
LOW  
HIGH  
LOW  
OS  
e
25  
25  
22  
22  
38  
38  
34  
34  
CCH  
CCL  
CCH  
CCL  
O
e
O
e
O
e
O
4
AC Electrical Characteristics  
74F  
54F  
74F  
e a  
T
25 C  
§
5.0V  
A
e
50 pF  
e
50 pF  
T
, V  
CC  
e
Mil  
T
, V  
A CC  
Com  
A
e a  
Symbol  
Parameter  
V
Units  
CC  
e
C
C
L
L
e
C
50 pF  
L
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
f
Input Clock Frequency  
100  
140  
80  
100  
MHz  
ns  
max  
t
t
Propagation Delay  
CP to Q or Q  
3.0*  
3.0  
5.7  
6.8  
7.5  
9.0  
3.0  
3.0  
9.5  
3.0  
3.0  
8.5  
PLH  
11.5  
10.0  
PHL  
*’F398 3.3 ns  
AC Operating Requirements  
74F  
54F  
74F  
e a  
e a  
T
25 C  
§
5.0V  
A
e
e
Symbol  
Parameter  
T
, V  
CC  
Mil  
Max  
T
, V  
A CC  
Com  
Max  
Units  
A
V
CC  
Min  
Max  
Min  
Min  
t (H)  
s
Setup Time, HIGH or LOW  
3.0  
3.0  
4.5  
4.5  
3.0  
3.0  
t (L)  
s
I to CP  
n
ns  
t (H)  
h
Hold Time, HIGH or LOW  
I to CP  
n
1.0  
1.0  
1.5  
1.5  
1.0  
1.0  
t (L)  
h
t (H)  
s
Setup Time, HIGH or LOW  
S to CP (’F398)  
7.5  
7.5  
10.5  
10.5  
8.5  
8.5  
t (L)  
s
t (H)  
s
Setup Time, HIGH or LOW  
S to CP (’F399)  
7.5  
7.5  
9.5  
9.5  
8.5  
8.5  
ns  
ns  
t (L)  
s
t (H)  
h
Hold Time, HIGH or LOW  
S to CP  
0
0
0
0
0
0
t (L)  
h
t
t
(H)  
(L)  
CP Pulse Width  
HIGH or LOW  
4.0  
5.0  
4.0  
7.0  
4.0  
5.0  
w
w
5
Ordering Information  
The device number is used to form part of a simplified purchasing code where the package type and temperature range are  
defined as follows:  
74F 398/399  
S
C
X
Temperature Range Family  
Special Variations  
e
e
e
74F  
54F  
Commercial  
Military  
QB  
Military grade device with  
environmental and burn-in  
processing  
Device Type  
e
X
Devices shipped in 13 reel  
×
Package Code  
Temperature Range  
e
e
e
e
e
e
P
D
F
L
S
SJ  
Plastic DIP  
Ceramic DIP  
Flatpak  
Leadless Chip Carrier (LCC)  
Small Outline SOIC JEDEC  
Small Outline SOIC EIAJ (74F399 only)  
e
e
a
C
M
Commercial (0 C to 70 C)  
§
§
b a  
Military ( 55 C to 125 C)  
§
§
6
Physical Dimensions inches (millimeters)  
20-Lead Ceramic Leadless Chip Carrier (L)  
NS Package Number E20A  
20-Lead Ceramic Dual-In-Line Package (D)  
NS Package Number J20A  
7
Physical Dimensions inches (millimeters) (Continued)  
20-Lead (0.300 Wide) Molded Small Outline Package, JEDEC (S)  
×
NS Package Number M20B  
20-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)  
×
NS Package Number M20D  
8
Physical Dimensions inches (millimeters) (Continued)  
20-Lead (0.300 Wide) Molded Dual-In-Line Package (P)  
×
NS Package Number N20A  
9
Physical Dimensions inches (millimeters) (Continued)  
20-Lead Ceramic Flatpak (F)  
NS Package Number W20A  
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant  
into the body, or (b) support or sustain life, and whose  
failure to perform, when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
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