54F163AFM [TI]

F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, FP-16;
54F163AFM
型号: 54F163AFM
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

F/FAST SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, FP-16

CD 逻辑集成电路 触发器
文件: 总12页 (文件大小:425K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
54F161A,54F163A  
54F161A/54F163A Synchronous Presettable Binary Counter  
Literature Number: SNOS159A  
November 1994  
54F/74F161A 54F/74F163A  
#
Synchronous Presettable Binary Counter  
General Description  
Features  
Y
Synchronous counting and loading  
The ’F161A and ’F163A are high-speed synchronous modu-  
lo-16 binary counters. They are synchronously presettable  
for application in programmable dividers and have two types  
of Count Enable inputs plus a Terminal Count output for  
versatility in forming synchronous multi-stage counters. The  
’F161A has an asynchronous Master-Reset input that over-  
rides all other inputs and forces the outputs LOW. The  
Y
High-speed synchronous expansion  
Y
Typical count frequency of 120 MHz  
Y
Guaranteed 4000V minimum ESD protection  
’F163A has  
a Synchronous Reset input that overrides  
counting and parallel loading and allows the outputs to be  
simultaneously reset on the rising edge of the clock. The  
’F161A and ’F163A are high-speed versions of the ’F161  
and ’F163.  
Package  
Number  
Commercial  
74F161APC  
Military  
Package Description  
N16E  
J16A  
16-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F161ADM (Note 2)  
16-Lead Ceramic Dual-In-Line  
74F161ASC (Note 1)  
74F161ASJ (Note 1)  
M16A  
M16D  
W16A  
E20A  
N16E  
J16A  
16-Lead (0.150 Wide) Molded Small Outline, JEDEC  
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F161AFM (Note 2)  
54F161ALM (Note 2)  
16-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
74F163APC  
16-Lead (0.300 Wide) Molded Dual-In-Line  
×
54F163ADM (Note 2)  
16-Lead Ceramic Dual-In-Line  
74F163ASC (Note 1)  
74F163ASJ (Note 1)  
M16A  
M16D  
W16A  
E20A  
16-Lead (0.150 Wide) Molded Small Outline, JEDEC  
×
16-Lead (0.300 Wide) Molded Small Outline, EIAJ  
×
54F163AFM (Note 2)  
54F163ALM (Note 2)  
16-Lead Cerpack  
20-Lead Ceramic Leadless Chip Carrier, Type C  
e
Note 2: Military grade device with environmental and burn-in processing. Use suffix  
Note 1: Devices also available in 13 reel. Use suffix  
SCX and SJX.  
×
e
DMQB, FMQB and LMQB.  
Connection Diagrams  
Pin Assignment  
for DIP, SOIC and Flatpak  
’F161A  
Pin Assignment  
for LCC  
’F161A  
Pin Assignment  
for DIP, SOIC and Flatpak  
’F163A  
Pin Assignment  
for LCC  
’F163A  
Obsolete  
TL/F/9486–7  
TL/F/9486–1  
TL/F/9486–8  
TL/F/9486–2  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9486  
RRD-B30M75/Printed in U. S. A.  
Logic Symbols  
’F161A  
’F163A  
TL/F/9486–3  
TL/F/9486–9  
IEEE/IEC  
’F161A  
IEEE/IEC  
’F163A  
TL/F/9486–6  
TL/F/948610  
Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
HIGH/LOW  
Output I /I  
OH OL  
b
20 mA/ 0.6 mA  
b
20 mA/ 1.2 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 0.6 mA  
CEP  
Count Enable Parallel Input  
1.0/1.0  
1.0/2.0  
1.0/1.0  
1.0/1.0  
1.0/2.0  
1.0/1.0  
1.0/2.0  
50/33.3  
50/33.3  
CET  
Count Enable Trickle Input  
CP  
Clock Pulse Input (Active Rising Edge)  
Asynchronous Master Reset Input (Active LOW)  
Synchronous Reset Input (Active LOW)  
Parallel Data Inputs  
MR (’F161A)  
SR (’F163A)  
b
20 mA/ 1.2 mA  
b
20 mA/ 0.6 mA  
b
20 mA/ 1.2 mA  
P P  
0
3
PE  
Parallel Enable Input (Active LOW)  
Flip-Flop Outputs  
b
b
Q Q  
0
1 mA/20 mA  
1 mA/20 mA  
3
TC  
Terminal Count Output  
Obsolete  
2
Functional Description  
The ’F161A and ’F163A count in modulo-16 binary se-  
quence. From state 15 (HHHH) they increment to state 0  
(LLLL). The clock inputs of all flip-flops are driven in parallel  
through a clock buffer. Thus all changes of the Q outputs  
(except due to Master Reset of the ’F161A) occur as a re-  
sult of, and synchronous with, the LOW-to-HIGH transition  
of the CP input signal. The circuits have four fundamental  
modes of operation, in order of precedence: asynchronous  
reset (’F161A), synchronous reset (’F163A), parallel load,  
count-up and hold. Five control inputsÐMaster Reset (MR,  
’F161A), Synchronous Reset (SR, ’F163A), Parallel Enable  
(PE), Count Enable Parallel (CEP) and Count Enable Trickle  
(CET)Ðdetermine the mode of operation, as shown in the  
Mode Select Table. A LOW signal on MR overrides all other  
inputs and asynchronously forces all outputs LOW. A LOW  
signal on SR overrides counting and parallel loading and  
allows all outputs to go LOW on the next rising edge of CP.  
A LOW signal on PE overrides counting and allows informa-  
flip-flops on the next rising edge of CP. With PE and MR  
(’F161A) or SR (’F163A) HIGH, CEP and CET permit count-  
ing when both are HIGH. Conversely, a LOW signal on ei-  
ther CEP or CET inhibits counting.  
The ’F161A and ’F163A use D-type edge triggered flip-flops  
and changing the SR, PE, CEP and CET inputs when the CP  
is in either state does not cause errors, provided that the  
recommended setup and hold times, with respect to the ris-  
ing edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is HIGH  
and the counter is in state 15. To implement synchronous  
multi-stage counters, the TC outputs can be used with the  
CEP and CET inputs in two different ways. Please refer to  
the ’F568 data sheet. The TC output is subject to decoding  
spikes due to internal race conditions and is therefore not  
recommended for use as a clock or asynchronous reset for  
flip-flops, counters or registers.  
e
Logic Equations: Count Enable  
CEP CET PE  
#
#
CET  
tion on the Parallel Data (P ) inputs to be loaded into the  
n
e
TC  
Q
Q
Q
Q
#
#
#
#
3
0
1
2
State Diagram  
Mode Select Table  
Action on the Rising  
*SR  
PE  
CET  
CEP  
Clock Edge (L)  
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)  
Load (PnxQ )  
n
H
H
H
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
X
*For ’F163A only  
e
e
e
H
HIGH Voltage Level  
L
LOW Voltage Level  
Immaterial  
X
TL/F/9486–5  
Obsolete  
3
Block Diagram  
Obsolete  
4
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
Recommended Operating  
Conditions  
Free Air Ambient Temperature  
Military  
Commercial  
b
a
55 C to 125 C  
§
0 C to 70 C  
§
§
b
b
b
a
65 C to 150 C  
Storage Temperature  
§
§
§
§
§
a
§
a
55 C to 125 C  
Ambient Temperature under Bias  
§
Supply Voltage  
Military  
Commercial  
a
a a  
4.5V to 5.5V  
a a  
4.5V to 5.5V  
Junction Temperature under Bias  
Plastic  
55 C to 175 C  
§
b
a
55 C to 150 C  
§
V
Pin Potential to  
CC  
Ground Pin  
b
a
0.5V to 7.0V  
b
a
0.5V to 7.0V  
Input Voltage (Note 2)  
Input Current (Note 2)  
Voltage Applied to Output  
b
a
30 mA to 5.0 mA  
e
in HIGH State (with V  
Standard Output  
0V)  
CC  
b
0.5V to 5.5V  
0.5V to V  
CC  
b
a
TRI-STATE Output  
É
Current Applied to Output  
in LOW State (Max)  
twice the rated I (mA)  
OL  
ESD Last Passing Voltage (Min)  
4000V  
Note 1: Absolute maximum ratings are values beyond which the device may  
be damaged or have its useful life impaired. Functional operation under  
these conditions is not implied.  
Note 2: Either voltage limit or current limit is sufficient to protect inputs.  
DC Electrical Characteristics  
54F/74F  
Typ  
Symbol  
Parameter  
Units  
Max  
V
CC  
Conditions  
Min  
V
V
V
V
Input HIGH Voltage  
2.0  
V
Recognized as a HIGH Signal  
Recognized as a LOW Signal  
IH  
Input LOW Voltage  
0.8  
V
V
IL  
b
e b  
18 mA  
Input Clamp Diode Voltage  
1.2  
Min  
Min  
I
I
CD  
OH  
IN  
e b  
Output HIGH  
Voltage  
54F 10% V  
2.5  
2.5  
2.7  
1 mA  
CC  
OH  
74F 10% V  
74F 5% V  
V
CC  
CC  
e
e
e
V
Output LOW  
Voltage  
54F 10% V  
74F 10% V  
0.5  
0.5  
I
20 mA  
2.7V  
OL  
CC  
OL  
V
Min  
Max  
Max  
Max  
0.0  
CC  
I
I
I
Input HIGH  
Current  
54F  
74F  
20.0  
5.0  
V
V
V
IH  
IN  
IN  
mA  
mA  
mA  
V
Input HIGH Current  
Breakdown Test  
54F  
74F  
100  
7.0  
7.0V  
BVI  
e
V
CC  
Output HIGH  
54F  
74F  
250  
50  
CEX  
OUT  
Leakage Current  
e
All Other Pins Grounded  
V
Input Leakage  
Test  
I
1.9 mA  
ID  
OD  
IL  
ID  
74F  
4.75  
e
All Other Pins Grounded  
I
I
Output Leakage  
Circuit Current  
V
150 mV  
IOD  
74F  
3.75  
mA  
0.0  
b
e
0.5V (CEP, CP, MR, P P )  
Input LOW Current  
0.6  
mA  
Max  
V
Obsolete  
IN  
0
3
b
e
1.2  
mA  
mA  
mA  
Max  
Max  
Max  
V
0.5V (CET, PE, SR)  
IN  
b
b
e
0V  
I
I
Output Short-Circuit Current  
Power Supply Current  
60  
150  
V
OS  
CC  
OUT  
37  
55  
5
AC Electrical Characteristics  
74F  
54F  
74F  
e a  
T
25 C  
§
5.0V  
A
e
50 pF  
e
50 pF  
T
, V  
CC  
e
Mil  
T
, V  
A CC  
Com  
A
e a  
Symbol  
Parameter  
V
Units  
CC  
e
C
C
L
L
e
C
50 pF  
L
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
f
Maximum Count Frequency  
Propagation Delay  
100  
120  
75  
90  
MHz  
ns  
max  
t
t
3.5  
3.5  
5.5  
7.5  
7.5  
3.5  
3.5  
9.0  
3.5  
3.5  
8.5  
PLH  
CP to Q (PE Input HIGH)  
n
10.0  
11.5  
11.0  
PHL  
t
t
Propagation Delay  
4.0  
4.0  
6.0  
6.0  
8.5  
8.5  
4.0  
4.0  
10.0  
10.0  
4.0  
4.0  
9.5  
9.5  
PLH  
CP to Q (PE Input LOW)  
n
PHL  
t
t
Propagation Delay  
CP to TC  
5.0  
5.0  
10.0  
10.0  
14.0  
14.0  
5.0  
5.0  
16.5  
15.5  
5.0  
5.0  
15.0  
15.0  
PLH  
ns  
ns  
ns  
ns  
PHL  
t
t
Propagation Delay  
CET to TC  
2.5  
2.5  
4.5  
4.5  
7.5  
7.5  
2.5  
2.5  
9.0  
9.0  
2.5  
2.5  
8.5  
8.5  
PLH  
PHL  
t
Propagation Delay  
PHL  
5.5  
4.5  
9.0  
8.0  
12.0  
10.5  
5.5  
4.5  
14.0  
12.5  
5.5  
4.5  
13.0  
11.5  
MR to Q (’F161A)  
n
t
Propagation Delay  
MR to TC (’F161A)  
PHL  
AC Operating Requirements  
74F  
54F  
74F  
e a  
T
25 C  
§
5.0V  
A
e
e
Symbol  
Parameter  
T
, V  
CC  
Mil  
Max  
T
, V  
A CC  
Com  
Max  
Units  
A
e a  
V
CC  
Min  
Max  
Min  
Min  
t (H)  
s
Setup Time, HIGH or LOW  
5.0  
5.0  
5.5  
5.5  
5.0  
5.0  
t (L)  
s
P to CP  
n
ns  
t (H)  
h
Hold Time, HIGH or LOW  
P to CP  
n
2.0  
2.0  
2.5  
2.5  
2.0  
2.0  
t (L)  
h
t (H)  
s
Setup Time, HIGH or LOW  
PE or SR to CP  
11.0  
8.5  
13.5  
10.5  
11.5  
9.5  
t (L)  
s
ns  
t (H)  
h
Hold Time, HIGH or LOW  
PE or SR to CP  
2.0  
0
3.6  
0
2.0  
0
t (L)  
h
t (H)  
s
Setup Time, HIGH or LOW  
CEP or CET to CP  
11.0  
5.0  
13.0  
6.0  
11.5  
5.0  
t (L)  
s
ns  
t (H)  
h
Hold Time, HIGH or LOW  
CEP or CET to CP  
0
0
0
0
0
0
t (L)  
h
t
t
(H)  
(L)  
Clock Pulse Width (Load)  
HIGH or LOW  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
w
ns  
ns  
w
t
t
(H)  
(L)  
Clock Pulse Width (Count)  
HIGH or LOW  
4.0  
6.0  
5.0  
8.0  
4.0  
7.0  
w
w
Obsolete  
t
(L)  
MR Pulse Width, LOW  
(’F161A)  
w
5.0  
5.0  
5.0  
ns  
t
Recovery Time  
rec  
6.0  
6.0  
6.0  
ns  
MR to CP (’F161A)  
6
Ordering Information  
The device number is used to form part of a simplified purchasing code where the package type and temperature range are  
defined as follows:  
74F 161A/163A  
S
C
X
Temperature Range Family  
e
e
54F Military  
Special Variations  
e
74F Commercial  
QR  
Commercial grade device  
with burn-in  
e
QB  
Military grade device with  
environmental and burn-in  
processing  
Device Type  
Package Code  
e
X
Devices shipped in 13 reel  
×
e
e
e
e
e
e
P
D
F
L
S
SJ  
Plastic DIP  
Ceramic DIP  
Flatpak  
Leadless Chip Carrier (LCC)  
Small Outline Package SOIC JEDEC  
Small Outline Package SOIC EIAJ  
Temperature Range  
e
a
C
M
Commercial (0 C to 70 C)  
§
§
e
b a  
Military ( 55 C to 125 C)  
§
§
Physical Dimensions inches (millimeters)  
20-Lead Ceramic Leadless Chip Carrier (L)  
NS Package Number E20A  
Obsolete  
7
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Ceramic Dual-In-Line Package (D)  
NS Package Number J16A  
Obsolete  
16-Lead (0.150 Wide) Molded Small Outline Package, JEDEC (S)  
NS Package Number M16A  
×
8
Physical Dimensions inches (millimeters) (Continued)  
16-Lead (0.300 Wide) Molded Small Outline Package, EIAJ (SJ)  
×
NS Package Number M16D  
Obsolete  
16-Lead (0.300 Wide) Molded Dual-In-Line Package (P)  
×
NS Package Number N16E  
9
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Ceramic Flatpak (F)  
NS Package Number W16A  
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failure to perform, when properly used in accordance  
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