54ACT16841WD [TI]
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS; 20位总线接口D类锁存器具有三态输出
| 型号： | 54ACT16841WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总6页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
54ACT16841 . . . WD PACKAGE
74ACT16841 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
Provide Extra Bus Driving/Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
2
3
4
5
Flow-Through Architecture Optimizes
PCB Layout
6
7
V
V
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
CC
CC
8
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
9
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Packages,
300-mil Shrink Small-Outline (DL) Packages
Using 25-mil Center-to-Center Pin
Spacings, and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages Using 25-mil
Center-to-Center Pin Spacings
description
V
V
CC
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
2D7
2D8
GND
2D9
2D10
2LE
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’ACT16841 can be used as two 10-bit latches
or one 20-bit latch. The 20 latches are transparent
D-type. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit
latch follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels that
were set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
description (continued)
The 74ACT16841 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16841 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16841 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
1
EN2
C1
1OE
1LE
56
28
29
EN4
C3
2OE
2LE
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
2
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
1D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
2
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
3D
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
logic diagram (positive logic)
28
1
1OE
2OE
56
29
42
2LE
2D1
1LE
C1
1D
C1
1D
15
2
2Q1
1Q1
55
1D1
To Nine Other Channels
To Nine Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . 1 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA
A
DL package . . . . . . . . . . . 1.4 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16841
MIN NOM
74ACT16841
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
10
0
10
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16841
74ACT16841
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
=–50 µA
OH
5.4
5.4
5.4
V
3.94
4.94
3.8
3.8
V
OH
OL
I
I
I
= –24 mA
= –75 mA
= 50 µA
OH
OH
OL
4.8
4.8
†
3.85
3.85
0.1
0.1
0.1
0.1
0.1
0.1
V
0.36
0.36
0.44
0.44
1.65
±1
0.44
0.44
1.65
±1
V
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
V = V
or GND
±0.1
±0.5
8
µA
µA
µA
I
I
CC
V
= V
or GND
±5
±5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
80
I
CC
One input at 3.4 V,
Other inputs at V
‡
5.5 V
0.9
1
1
mA
∆I
CC
or GND
CC
or GND
C
C
V = V
5 V
5 V
3
pF
pF
i
I
CC
= V or GND
CC
V
11
o
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
= 25°C
54ACT16841
74ACT16841
A
UNIT
MIN
4
MAX
MIN
4
MAX
MIN
4
MAX
t
t
Pulse duration, LE high
ns
ns
w
Setup time, data before LE↓
1.5
3
1.5
3
1.5
3
su
High
t
h
Hold time, data after LE↓
ns
Low
4.5
4.5
4.5
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
7.1
54ACT16841
74ACT16841
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
4
MAX
10.3
11
MIN
4
MAX
11.8
12.2
12.7
12.7
11.3
13.7
10.2
9.6
MIN
4
MAX
11.8
12.2
12.7
12.7
11.3
13.7
10.2
9.6
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
3.2
4.5
4.3
3.1
3.8
4
6.9
3.2
4.5
4.3
3.1
3.8
4
3.2
4.5
4.3
3.1
3.8
4
7.7
11.3
11.4
10.1
12.1
9.5
LE
ns
7.8
6.4
ns
OE
OE
7.6
7.3
ns
4
6.8
8.9
4
4
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
41
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance
C
= 50 pF,
L
f = 1 MHz
pF
pd
10
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
Timing Input
(see Note B)
1.5 V
0 V
3 V
0 V
t
w
t
h
t
3 V
su
Input
1.5 V
1.5 V
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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