54ACT11533 [TI]
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS; 八路D型透明锁存器带3态输出
| 型号： | 54ACT11533 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢊ ꢃꢄꢂꢋꢈꢌ ꢍꢄꢎ ꢏꢐꢈ ꢄ ꢑꢂꢒꢓꢏꢂꢑꢐ ꢒꢄ ꢈ ꢋꢂꢄꢃ ꢔ ꢐ
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SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
• Eight Latches in a Single Package
• 3-State Bus-Driving Inverting Outputs
• Full Parallel Access for Loading
• Buffered Control Inputs
54ACT11533 . . . JT PACKAGE
74ACT11533 . . . DW OR NT PACKAGE
(TOP VIEW)
1Q
2Q
OC
1D
2D
3D
4D
1
24
23
22
21
20
19
18
17
16
15
14
13
2
• Inputs Are TTL-Voltage Compatible
3Q
3
• Flow-Through Architecture Optimizes
4Q
4
PCB Layout
GND
GND
GND
GND
5Q
5
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
CC
6
V
V
CC
CC
7
• EPICt (Enhanced-Performance Implanted
8
5D
6D
7D
8D
C
CMOS) 1-mm Process
9
• 500-mA Typical Latch-Up Immunity at 125°C
10
11
12
6Q
7Q
• Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
8Q
54ACT11533 . . . FK PACKAGE
(TOP VIEW)
description
These eight latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
4
3
2 1 28 27 26
5
6
7
8
9
25
24 8D
7D
2D
1D
OC
NC
1Q
2Q
3Q
23
22
21
20
19
C
NC
8Q
7Q
6Q
The eight latches of the ′ACT11533 are
transparent D-type latches. While the enable (C)
is high, the Q outputs will follow the complements
of the (D) inputs. When the output control OC is
taken low, the Q outputs will be latched. The
′ACT11533 is functionally equivalent to the
′ACT11373 except for having inverted outputs.
10
11
12 13 14 15 16 17 18
NC − No internal connection
A buffered output-control (OC) input can be used
to place the eight outputs in either a normal
logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pullup components.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OC
L
C
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
The output control (OC) does not affect the
internal operations of the latches. Old data can be
retained or new data can be entered while the
outputs are off.
H
X
Z
The 54ACT11533 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT11533 is characterized for operation from − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1993, Texas Instruments Incorporated
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2−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢅ ꢀꢆ ꢆ ꢇ ꢈ ꢉ ꢁꢂ ꢃꢄ ꢅꢅ ꢀ ꢆꢆ
ꢊꢃ ꢄꢂ ꢋꢈ ꢌ ꢍꢄ ꢎꢏ ꢐꢈ ꢄ ꢑꢂꢒꢓ ꢏꢂꢑ ꢐꢒ ꢄꢈ ꢋꢂꢄ ꢃꢔꢐꢓ
ꢕꢖ ꢄ ꢔ ꢈꢆ ꢍꢓ ꢄꢂꢄꢐ ꢈ ꢊ ꢗꢄ ꢏꢗꢄ ꢓ
ꢘ
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
†
logic diagram (positive logic)
logic symbol
24
24
OC
C
EN
C1
OC
13
C
13
23
22
21
20
17
16
15
14
1
2
C1
1D
1
2
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
23
1Q
1D
2D
3D
4D
5D
6D
7D
8D
3
C1
1D
4
22
21
20
17
16
15
14
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9
10
11
12
C1
1D
3
C1
1D
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
C1
1D
9
C1
1D
10
11
12
C1
1D
C1
1D
Pin numbers shown are for the DW, JT, and NT packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
recommended operating conditions
54ACT11533
74ACT11533
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
mA
mA
ns/V
°C
OH
OL
Dt/Dv
0
10
0
10
T
−55
125
− 40
85
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT11533
74ACT11533
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
5.4
3.8
4.8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
I
I
= − 50 mA
OH
5.4
5.4
3.94
4.94
3.7
= − 24 mA
V
OH
V
OH
4.7
{
{
3.85
I
I
= − 50 mA
OH
3.85
= − 75 mA
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
I
= 50 mA
OL
0.36
0.36
0.5
0.44
0.44
= 24 mA
V
OL
V
OL
0.5
{
1.65
I
I
= 50 mA
OL
{
5.5 V
5.5 V
5.5 V
5.5 V
1.65
5
= 75 mA
OL
I
I
I
V
= V
or GND
0.5
0.1
8
10
1
mA
mA
mA
OZ
O CC
V = V
or GND
or GND,
1
I
I
CC
V = V
I = 0
O
160
80
CC
I
CC
One input at 3.4 V,
Other inputs at GND or V
}
5.5 V
0.9
1
1
mA
DI
CC
CC
C
C
V = V
CC
or GND
or GND
5 V
5 V
4
pF
pF
i
I
V = V
O CC
10
o
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
2−3
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ꢊꢃ ꢄꢂ ꢋꢈ ꢌ ꢍꢄ ꢎꢏ ꢐꢈ ꢄ ꢑꢂꢒꢓ ꢏꢂꢑ ꢐꢒ ꢄꢈ ꢋꢂꢄ ꢃꢔꢐꢓ
ꢕꢖ ꢄ ꢔ ꢈꢆ ꢍꢓ ꢄꢂꢄꢐ ꢈ ꢊ ꢗꢄ ꢏꢗꢄ ꢓ
ꢘ
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
54ACT11533
74ACT11533
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, C high
ns
ns
ns
Setup time, data before C↓
Hold time, data after C↓
3.5
3.5
3.5
3.5
3.5
3.5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
7
54ACT11533
74ACT11533
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
10.1
8.4
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
11.9
10.2
14.1
13.2
13.6
12.9
13.1
10.7
MIN
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
MAX
11.3
9.5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
Q
D
C
6.5
8.5
11.3
10.7
10.7
10.9
12.1
9.5
13
ns
Any Q
Any Q
Any Q
8.5
12.2
12.5
12
7.5
OC
OC
ns
7.5
10.5
7.5
12.8
10.3
ns
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
69
58
C
Power dissipation capacitance per latch
C
pF
pd
2−4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢕ ꢖꢄ ꢔꢈ ꢆ ꢍꢓꢄꢂꢄ ꢐꢈ ꢊ ꢗꢄ ꢏꢗ ꢄ
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
Open
GND
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
/t
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Timing Input
(see Note B)
1.5 V
t
w
t
h
t
3 V
0 V
su
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
Data Input
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
1.5 V
1.5 V
0 V
t
PZL
3 V
0 V
PLH
t
PLZ
Input
(see Note B)
Output
Waveform 1
[ V
1.5 V
1.5 V
CC
50% V
CC
20% V
S1 at 2 × V
(see Note C)
CC
CC
V
OL
t
t
PHL
t
PHZ
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
80% V
CC
50% V
CC
50% V
CC
V
Output
50% V
CC
[ 0 V
OL
(see Note C)
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
PDIP
PDIP
Drawing
74ACT11533DW
74ACT11533DWR
74ACT11533DWR
74ACT11533NT
74ACT11533NT
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
DW
24
24
24
24
24
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
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Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DW
DW
NT
NT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
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