54ACT109DM [TI]
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16;
| 型号： | 54ACT109DM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16 CD 输出元件 |
| 文件： | 总12页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54AC109 • 54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
Simultaneous LOW on CD and SD makes both Q and Q
General Description
HIGH
The ’AC/’ACT109 consists of two high-speed completely in-
dependent transition clocked JK flip-flops. The clocking op-
eration is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Features
n ICC reduced by 50%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC109: 5962-89551
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
— ’ACT109: 5962-88534
Logic Symbol
IEEE/IEC
DS100267-1
DS100267-7
Pin Names
J1, J2, K1, K2
CP1, CP2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
C
D1, CD2
D1, SD2
Q1, Q2, Q1, Q2
S
DS100267-2
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100267
www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100267-3
DS100267-4
Truth Table
(each half)
Inputs
Outputs
SD
L
CD
H
L
CP
X
J
X
X
X
L
K
X
X
X
L
Q
Q
L
H
L
H
L
X
H
H
H
L
X
H
L
N
N
N
N
H
H
H
H
H
H
H
H
H
H
H
L
L
Toggle
H
H
X
Q0
H
Q0
L
H
X
L
Q0
Q0
=
=
H
L
HIGH Voltage Level
LOW Voltage Level
N =
LOW-to-HIGH Transition
Immaterial
=
X
=
Q (Q ) Previous Q (Q ) before LOW-to-HIGH Transition of Clock
0
0
0
0
Logic Diagram (one half shown)
DS100267-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
=
IOH −12 mA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
=
IOH −24 mA
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 2)
=
VIN VIL or VIH
=
IOL 12 mA
3.0
4.5
5.5
5.5
0.5
0.5
0.5
=
IOL 24 mA
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
(Note 3)
Minimum Dynamic
Output Current
=
VOLD 1.65V Max
IOLD
IOHD
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
−50
3
www.national.com
DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
ICC
Maximum Quiescent
Supply Current
5.5
40.0
µA
VIN VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA −55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 5)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 5)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum
1.0
µA
mA
VI VCC, GND
=
VI VCC − 2.1V
ICCT
5.5
1.6
I
CC/Input
(Note 6)
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
40.0
=
VIN VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
I for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 7:
www.national.com
4
AC Electrical Characteristics
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 8)
Min
Max
fmax
tPLH
tPHL
tPLH
tPHL
Maximum Clock
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
65
95
MHz
ns
Frequency
Propagation Delay
CPn to Qn or Qn
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
17.5
12.0
13.5
10.0
13.0
9.5
Propagation Delay
CPn to Qn or Qn
ns
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
ns
14.0
10.5
ns
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
=
VCC
(V)
TA −55˚C
Fig.
Symbol
Parameter
to +125˚C
Units
No.
=
(Note 9)
CL 50 pF
Guaranteed
Minimum
8.0
ts
Setup Time, HIGH or LOW
Jn or Kn to CPn
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
ns
ns
ns
ns
5.5
th
Hold Time, HIGH or LOW
Jn or Kn to CPn
0
0.5
tw
Pulse Width
8.0
CDn or SDn or CPn
Recovery Time
5.5
trec
0.5
CDn or SDn to CPn
0.5
±
Note 9: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
5
www.national.com
AC Electrical Characteristics
54ACT
=
VCC
(V)
TA −55˚C
Symbol
Parameter
to +125˚C
Units
=
(Note 10)
CL 50 pF
Min
Max
fmax
tPLH
tPHL
tPLH
tPHL
Maximum Clock
5.0
5.0
5.0
5.0
5.0
85
MHz
ns
Frequency
Propagation Delay
CPn to Qn or Qn
1.0
1.0
1.0
1.0
14.0
12.0
11.5
12.5
Propagation Delay
CPn to Qn or Qn
ns
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
ns
ns
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
=
VCC
TA −55˚C
Symbol
Parameter
(V)
to +125˚C
Units
=
(Note 11)
CL 50 pF
Guaranteed
Minimum
2.5
ts
Setup Time, HIGH or LOW
Jn or Kn to CPn
5.0
5.0
5.0
5.0
ns
ns
ns
ns
th
Hold Time, HIGH or LOW
Jn or Kn to CPn
2.0
5.0
0.5
tw
Pulse Width
CPn or CDn or SDn
Recovery Time
trec
CDn or SDn to CPn
±
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
=
VCC 5.0V
CPD
35.0
pF
www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National Semiconductor Company
Design
Purchasing Quality Company Jobs
Products > Military/Aerospace > Logic > FACT ACT > 54ACT109
Product Folder
54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
Contents
l
l
l
l
General Description
Features
Datasheet
Package Availability, Models, Samples
& Pricing
l
Application Notes
General Description
The 'AC/'ACT109 consists of two high-speed completely independent transition clocked
JK# flip-flops. The clocking operation is independent of rise and fall times of the clock
waveform. The JK# design allows operation as a D flip-flop (refer to 'AC/'ACT74 data
sheet) by connecting the J and K# inputs together.
Asynchronous Inputs:
LOW input to S# (Set) sets Q to HIGH level
D
LOW input to C# (Clear) sets Q to LOW level
D
Clear and Set are independent of clock
Simultaneous LOW on C# and S# makes both Q and Q#
D
D
HIGH
Features
l
I
reduced by 50%
CC
l
l
l
Outputs source/sink 24 mA
'ACT109 has TTL-compatible inputs
Standard Military Drawing (SMD) -'AC109: 5962-89551 -'ACT109: 5962-88534
Datasheet
Size
(in Kbytes)
Title
Date
Receive via Email
Download
View Online
54AC109 54ACT109 Dual J K Positive Edge-Triggered Flip-Flop 167 Kbytes 17-Aug-98 View Online Download Receive via Email
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
Package Availability, Models, Samples & Pricing
Samples
Package
Models
Budgetary Pricing
Quantity $US each
Std
Pack
Size
&
Package
Marking
Part Number
5962-88534012A
5962R88534012A
Status
Electronic
Orders
Type # pins
SPICE IBIS
[logo]¢Z¢S¢4¢A
54ACT109
LMQB /Q¢M$E
5962-
tube
of
50
.
Order Parts
LCC
LCC
20 Full production N/A N/A
20 Full production N/A N/A
50+
50+
$7.7500
88534012A
[logo]¢Z¢S¢4¢A
54ACT109
Q¢M$E
R88534012A
tube
$69.0000 of
50
.
tube
of
25
[logo]¢Z¢S¢4¢A$E
54ACT109DMQB /Q¢M
5962-8853401EA
.
Order Parts
5962-8853401EA
5962R8853401EA
Cerdip 16 Full production N/A N/A
Cerdip 16 Full production N/A N/A
50+
50+
$2.5000
tube
[logo]¢Z¢S¢4¢A$E
.
.
$69.0000 of 54ACT109DMQB-RH /Q¢M
25
5962R8853401EA
[logo]¢Z¢S¢4¢A$E
54ACT109FMQB
Q¢M 5962-
tube
of
19
Order Parts
5962-8853401FA
Cerpack 16 Full production N/A N/A
50+
50+
$7.7500
8853401FA
[logo]¢Z¢S¢4¢A$E
54ACT109FMQB
-RH Q¢M 5962
R8853401FA
tube
$69.0000 of
19
5962R8853401FA Cerpack 16 Full production N/A N/A
.
.
[logo]¢Z¢S¢4¢A
54ACT109E
RQMLV $E
5962R
tube
$138.0000 of
50
5962R8853401V2A LCC
20 Full production N/A N/A
50+
8853401V2A
tube
$138.0000 of
25
[logo]¢Z¢S¢4¢A$E
54ACT109JRQMLV
5962R8853401VEA
5962R8853401VEA Cerdip 16 Full production N/A N/A
5962R8853401VFA Cerpack 16 Full production N/A N/A
.
.
.
50+
50+
[logo]¢Z¢S¢4¢A$E
54ACT109W
tube
$138.0000 of
19
RQMLV 5962
R8853401VFA
tube
$152.0000 of
25
[logo]¢Z¢S¢4¢A$E
54ACT109DM-MLS
54ACT109DM-MLS Cerdip 16
54ACT109FM-MLS Cerpack 16
Lifetime buy
Lifetime buy
N/A N/A
N/A N/A
50+
50+
tube
$152.0000 of
19
[logo]¢Z¢S¢4¢A$E
54ACT109FM
-MLS
.
.
54ACT109 MDS
die
Full production N/A N/A
N/A
-
Application Notes
Size
(in Kbytes)
Title
Date
Receive via Email
Download
View Online
AN-925: Radiation Design Test Data for Advanced CMOS Product 194 Kbytes 5-Aug-95 View Online Download Receive via Email
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
[Information as of 2-Sep-2000]
Quick Search
Parametric
Search
System
Diagrams
Product
Tree
Home
About Languages . About the Site . About "Cookies"
National is QS 9000 Certified . Privacy/Security
Copyright © National Semiconductor Corporation
Preferences . Feedback
相关型号：
54ACT109FM
J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, CDFP16, CERAMIC, FP-16
FAIRCHILD
54ACT109FMQB
ACT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, FP-16
TI
©2020 ICPDF网 联系我们和版权申明