54ACQ646 [TI]
54ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs; 54ACTQ646静音系列八路收发器/寄存器与3态输出
| 型号： | 54ACQ646 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 54ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs |
| 文件： | 总11页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54ACQ646,54ACTQ646
54ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs
Literature Number: SNOS135
September 1998
54ACTQ646
Quiet Series Octal Transceiver/Register with 3-STATE
Outputs
General Description
Features
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
The ACTQ646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops, and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus
will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental handling functions available
are illustrated in Figures 1, 2, 3, 4.
n Independent registers for A and B busses
n Multiplexed real-time and stored data transfers
n 300 mil slim dual-in-line package
n Outputs source/sink 24 mA
n Faster prop delays than the standard AC/ACT646
n 4 kV minimum ESD immunity
The ACTQ utilizes FSC Quiet Series technology to guaran-
tee quiet output switching and improved dynamic threshold
n Standard Microcircuit Drawing (SMD) 5962-9219601
™
™
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Logic Symbols
IEEE/IEC
DS100326-1
DS100326-2
Pin Descriptions
Pin Names
Description
A0–A7
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
B0–B7
CPAB,
CPBA
SAB, SBA
Transmit/Receive Inputs
™
GTO is a trademark of National Semiconductor Corporation
™
™
FACT and FACT Quiet Series are trademarks of Fairchild Semiconductor Corporation
© 1998 National Semiconductor Corporation
DS100326
www.national.com
Logic Symbols (Continued)
Pin Descriptions (Continued)
Pin Names
Description
Output Enable Input
Direction Control Input
G
DIR
Connection Diagram
Pin Assignment
for DIP and Flatpack
DS100326-3
Pin Assignment
for LCC
DS100326-4
www.national.com
2
Real Time Transfer
A-Bus to B-Bus
Storage from
Bus to Register
DS100326-7
DS100326-5
FIGURE 3.
FIGURE 1.
Transfer from
Register to Bus
Real Time Transfer
B-Bus to A-Bus
DS100326-8
DS100326-6
FIGURE 4.
FIGURE 2.
Function Table
Inputs
Data I/O (Note 1)
Function
G
H
H
H
L
DIR CPAB CPBA SAB SBA A0–A7
B0–B7
X
X
X
H
H
H
H
L
H or L
H or L
X
X
X
L
X
X
X
X
X
X
X
L
Isolation
N
X
Input
Input
Input
Clock An Data into A Register
X
N
Clock Bn Data into B Register
X
X
An to Bn — Real Time (Transparent Mode)
L
N
X
L
Output Clock An Data into A Register
A Register to Bn (Stored Mode)
L
H or L
X
H
H
X
X
X
X
L
N
X
X
X
X
X
X
Clock An Data into A Register and Output to Bn
Bn to An — Real Time (Transparent Mode)
L
L
L
N
L
Output
Input
Clock Bn Data into B Register
L
L
H or L
N
H
H
B Register to An (Stored Mode)
L
L
Clock Bn Data into B Register and Output to An
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
=
N
LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
3
www.national.com
Logic Diagram
DS100326-9
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
4
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature (TJ)
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
)
Supply Voltage (VCC
)
=
VI −0.5V
−20 mA
+20 mA
ACTQ
4.5V to 5.5V
0V to VCC
0V to VCC
=
VI VCC + 0.5V
Input Voltage (VI)
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Output Voltage (VO
)
DC Output Diode Current (IOK
)
Operating Temperature (TA)
54ACTQ
=
VO −0.5V
−20 mA
+20 mA
−55˚C to +125˚C
=
VO VCC + 0.5V
Minimum Input Edge Rate ∆V/∆t
ACTQ Devices
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
VIN from 0.8V to 2.0V
±
±
or Sink Current (IO
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not recom-
)
50 mA
Storage Temperature (TSTG
DC Latch-Up Source
or Sink Current
)
−65˚C to +150˚C
™
mend operation of FACT circuits outside databook specifications.
±
300 mA
DC Electrical Characteristics for ACTQ
=
Symbol
Parameter
VCC
TA
Units
Conditions
(V)
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 3)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.7
4.7
0.1
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 3)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.5
0.5
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum I/O
1.0
µA
VI VCC, GND
=
IOZT
VI VIL, VIH
=
±
Leakage Current
(An, Bn Inputs)
Maximum ICC/Input
(Note 4)
5.5
5.5
10.0
1.6
50
µA
VO VCC, GND
=
VI VCC − 2.1V
ICCT
mA
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
mA
mA
µA
=
VOHD 3.85V Min
−50
=
160.0
VIN VCC
or GND (Note 5)
5
www.national.com
DC Electrical Characteristics for ACTQ (Continued)
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
1.5
VOLP
Quiet Output
5.0
5.0
V
V
Maximum Dynamic
VOL
(Note 6)
VOLV
Quiet Output
-1.2
Minimum Dynamic
VOL
(Note 6)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
I for 54ACTQ 25˚C is identical to 74ACQ 25˚C.
CC
Note 5:
@
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output GND.
AC Electrical Characteristics
=
Symbol
Parameter
VCC (V)
TA −55˚C to +125˚C
Units
=
CL 50 pF
(Note 7)
Min
Max
tPLH
tPHL
tPLH
tPHL
,
Propagation Delay
Clock to Bus
5.0
5.0
2.0
11.0
ns
ns
,
Propagation Delay
Bus to Bus
2.0
12.0
tPLH,
tPHL
Propagation Delay
SBA or SAB to An or Bn
(w/An or Bn HIGH or LOW)
Enable Time
5.0
5.0
5.0
5.0
5.0
2.0
1.5
1.5
1.5
1.5
12.5
15.0
12.0
15.0
12.0
ns
ns
ns
ns
ns
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
,
G to An or Bn
,
,
,
Disable Time
G to An or Bn
Enable Time
DIR to An or Bn
Disable Time
DIR to An or Bn
±
Note 7: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
=
Symbol
Parameter
VCC (V)
TA −55˚C to +125˚C
Units
=
CL 50 pF
(Note 8)
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Bus to Clock
5.0
5.0
5.0
3.0
ns
ns
ns
tH
Hold Time, HIGH or LOW
Bus to Clock
1.5
4.0
tW
Clock Pulse Width
HIGH or LOW
±
Note 8: Voltage Range 5.0 is 5.0V 0.5V
www.national.com
6
Capacitance
Symbol
Parameter
Max
15
Units
pF
Conditions
VCC OPEN
=
CIN
Input Capacitance
Input/Output Capacitance
Power Dissipation
Capacitance
=
VCC 5.0V
CI/O
CPD
20.0
100.0
pF
=
VCC 5.0V
pF
7
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Ceramic Dual-In-Line
Package Number J24A
24-Lead Cerpack
Package Number W24C
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Leadless Chip Carrier
Package Number E28A
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相关型号：
54ACQ646DMQB
IC AC SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24, Bus Driver/Transceiver
TI
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