54AC11112 [TI]
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET; 双JK负边沿触发触发器具有清零和预设
| 型号： | 54AC11112 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
| 文件： | 总7页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS073A – JUNE 1989 – REVISED APRIL 1993
54AC11112 . . . J PACKAGE
74AC11112 . . . D OR N PACKAGE
(TOP VIEW)
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V
and GND Configuration
Minimizes High-Speed Switching Noise
CC
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2J
1J
1K
1CLK
1CLR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
V
CC
2CLR
2CLK
2K
• ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
• Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic
300-mil DIPs
54AC11112 . . . FK PACKAGE
(TOP VIEW)
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), dataattheJandKinputsmeetingthesetup
time requirements are transferred to the outputs
on the negative-going edge of the clock pulse.
Clocktriggeringoccursatavoltagelevelandisnot
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
3
2
1
20 19
18
2CLK
17 2K
1K
1J
4
5
6
7
8
16
15
14
NC
NC
2J
1PRE
1Q
2PRE
9 10 11 12 13
NC – No internal connection
The 54AC11112 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC11112 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUTS
PRE
L
CLK
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
CLR
H
H
L
X
H
L
L
X
H
H
H
H
↓
Q
Q
O
O
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle
H
H
H
Q
Q
O
O
†
This configuration is nonstable; that is, it will not persist
when either PRE or CLR returns to its inactive (high) level.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS073A – JUNE 1989 – REVISED APRIL 1993
†
logic symbol
1
S
1PRE
1J
16
14
15
13
2
3
1J
1Q
1Q
1CLK
1K
C1
1K
R
1CLR
7
S
2PRE
2J
8
6
5
2J
2Q
2Q
10
9
2CLK
2K
C2
2K
R
11
2CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each flip-flop (positive logic)
PRE
C
J
C
TG
C
Q
TG
C
C
TG
C
K
C
TG
C
CLK
C
C
Q
CLR
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS073A – JUNE 1989 – REVISED APRIL 1993
recommended operating conditions
54AC11112
MIN NOM
74AC11112
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
3
2.1
5
5.5
3
2.1
5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
–4
CC
–4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
0
10
ns/V
T
A
–55
125
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54AC11112
74AC11112
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
I
= – 50 µA
4.4
4.4
OH
5.4
5.4
I
I
= – 4 mA
2.58
3.94
4.94
2.48
3.8
OH
V
OH
V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
= – 24 mA
= – 50 mA
OH
4.8
†
I
I
OH
†
= –75 mA
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
0.1
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.5
0.44
0.44
0.44
OL
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
0.5
OL
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
±1
OL
I
I
V = V
or GND
or GND,
or GND
±0.1
±1
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
4
80
40
CC
I
C
V = V
3.5
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS073A – JUNE 1989 – REVISED APRIL 1993
timing requirements, V
= 3.3 V ± 0.3 V (see Figure 1)
CC
T
= 25°C
54AC11112
74AC11112
A
UNIT
MHz
ns
MIN
0
MAX
MIN
0
MAX
70
MIN
0
MAX
70
f
t
Clock frequency
Pulse duration
100
clock
PRE or CLR low
5
5
5
w
CLK low or CLK high
Data high or low
5
5
5
5
5
5
t
t
Setup time before CLK↓
Hold time after CLK↓
ns
ns
su
PRE or CLR inactive
2.5
0.5
2.5
0.5
2.5
0.5
h
timing requirements, V
= 5 V ± 0.5 V (see Figure 1)
CC
T
= 25°C
54AC11112
74AC11112
A
UNIT
MHz
ns
MIN
0
MAX
MIN
0
MAX
125
MIN
0
MAX
125
f
t
Clock frequency
Pulse duration
125
clock
PRE or CLR low
4
4
4
w
CLK low or CLK high
Data high or low
4
4
4
3.5
2
3.5
2
3.5
2
t
t
Setup time before CLK↓
Hold time after CLK↓
ns
ns
su
PRE or CLR inactive
1
1
1
h
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
150
4.9
7
54AC11112
74AC11112
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
100
1.5
1.5
1.5
1.5
MAX
MIN
100
1.5
1.5
1.5
1.5
MAX
MIN
100
1.5
1.5
1.5
1.5
MAX
f
t
t
t
t
max
PLH
PHL
PLH
PHL
6.7
9.2
7.1
7.9
7.6
10.3
7.9
9
7.3
9.9
7.6
8.5
PRE or CLR
CLK
Q or Q
Q or Q
5.4
6
ns
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
175
3.3
54AC11112
74AC11112
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
125
1.5
1.5
1.5
1.5
MAX
MIN
125
1.5
1.5
1.5
1.5
MAX
MIN
125
1.5
1.5
1.5
1.5
MAX
f
t
t
t
t
max
PLH
PHL
PLH
PHL
5.1
6.7
5.1
6.3
5.6
7.7
5.8
7.4
5.4
7.3
5.6
7
PRE or CLR
CLK
Q or Q
Q or Q
4.6
3.4
ns
4.2
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance per gate
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
37
UNIT
C
C
pF
pd
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
54AC11112, 74AC11112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS073A – JUNE 1989 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
t
w
V
CC
C
= 50 pF
L
500 Ω
(see Note A)
Input
50%
50%
0 V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
V
CC
Input
(see Note B)
50%
50%
0 V
V
CC
Timing Input
(see Note B)
t
t
PHL
PLH
50%
V
OH
0 V
In-Phase
Output
50% V
CC
t
50% V
50% V
h
CC
t
V
OL
su
V
CC
t
PLH
t
50%
50%
PHL
Data Input
0 V
V
OH
Out-of-Phase
Output
50% V
CC
CC
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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