2U3824-33QDBVRG4Q1 概述
PROCESSOR SUPERVISORY CIRCUITS 处理器监控电路 电源监控芯片 电源管理电路
2U3824-33QDBVRG4Q1 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Active | 零件包装代码: | SOT-23 |
包装说明: | SOT-23, 5 PIN | 针数: | 5 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | Factory Lead Time: | 1 week |
风险等级: | 5.68 | Is Samacsys: | N |
其他特性: | RESET THRESHOLD VOLTAGE IS 2.93V; POWER-ON RESET GENERATOR | 可调阈值: | NO |
模拟集成电路 - 其他类型: | POWER SUPPLY MANAGEMENT CIRCUIT | JESD-30 代码: | R-PDSO-G5 |
JESD-609代码: | e4 | 长度: | 2.9 mm |
湿度敏感等级: | 1 | 信道数量: | 1 |
功能数量: | 1 | 端子数量: | 5 |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | LSSOP |
封装等效代码: | TSOP5/6,.11,37 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE, LOW PROFILE, SHRINK PITCH | 峰值回流温度(摄氏度): | 260 |
电源: | 1.1/5.5 V | 认证状态: | Not Qualified |
筛选级别: | AEC-Q100 | 座面最大高度: | 1.45 mm |
子类别: | Power Management Circuits | 最大供电电流 (Isup): | 0.025 mA |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 1.1 V |
标称供电电压 (Vsup): | 3.3 V | 表面贴装: | YES |
温度等级: | AUTOMOTIVE | 端子面层: | Nickel/Palladium/Gold (Ni/Pd/Au) |
端子形式: | GULL WING | 端子节距: | 0.95 mm |
端子位置: | DUAL | 阈值电压标称: | 2.93 |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 宽度: | 1.6 mm |
Base Number Matches: | 1 |
2U3824-33QDBVRG4Q1 数据手册
通过下载2U3824-33QDBVRG4Q1数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
TPS3820, TPS3823, TPS3828 . . . DBV PACKAGE
FEATURES
(TOP VIEW)
D
Qualified for Automotive Applications
1
2
3
5
V
DD
RESET
GND
D
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Using Human
Body Model (C = 100 pF, R = 1500 Ω)
Power-On Reset Generator With Fixed
Delay Time of 200 ms (TPS3823/4/5/8)
or 25 ms (TPS3820)
4
WDI
MR
TPS3824 . . . DBV PACKAGE
(TOP VIEW)
D
D
Manual Reset Input (TPS3820/3/5/8)
Reset Output Available in Active-Low
(TPS3820/3/4/5), Active-High (TPS3824) and
Open-Drain (TPS3828)
1
2
3
5
V
DD
RESET
GND
D
Supply Voltage Supervision Range
2.5 V, 3 V, 3.3 V, 5 V
4
WDI
RESET
D
D
D
Watchdog Timer (TPS3820/3/4/8)
Supply Current of 15 μA (Typ)
SOT23-5 Package
TPS3825 . . . DBV PACKAGE
(TOP VIEW)
1
2
3
5
V
DD
RESET
GND
APPLICATIONS
D
Applications Using Automotive DSPs,
Microcontrollers, or Microprocessors
4
MR
RESET
D
D
D
D
D
D
Industrial Equipment
Programmable Controls
Automotive Systems
typical application
3.3 V
Battery-Powered Equipment
Intelligent Instruments
100 nF
V
DD
V
DD
Wireless Communications Systems
RESET
RESET
TPS3823-33
MR WDI
MSP430C325
I/O
GND
GND
description
The TPS382x family of supervisors provides circuit initialization and timing supervision, primarily for DSP and
processor-based systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
description (continued)
During power-on, RESET is asserted when supply voltage V becomes higher than 1.1 V. Thereafter, the
DD
supply voltage supervisor monitors V and keeps RESET active as long as V remains below the threshold
DD
DD
voltage V . An internal timer delays the return of the output to the inactive state (high) to ensure proper system
IT−
reset. The delay time, t , starts after V has risen above the threshold voltage V . When the supply voltage
d
DD
IT−
drops below the threshold voltage V , the output becomes active (low) again. No external components are
IT−
required. All the devices of this family have a fixed-sense threshold voltage V set by an internal voltage
IT−
divider.
The TPS3820/3/5/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become
active. The TPS3824/5 devices include a high-level output RESET. TPS3820/3/4/8 have a watchdog timer that
is periodically triggered by a positive or negative transition at WDI. When the supervising system fails to retrigger
the watchdog circuit within the time-out interval, t , RESET becomes active for the time period t . This event
tout
d
also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog.
In applications where the input to the WDI pin may be active (transitioning high and low) when the
TPS3820/3/4/8 is asserting RESET, the TPS3820/3/4/8 does not return to a non-reset state when the input
voltage is above Vt. If the application requires that input to WDI is active when RESET is asserted, WDI must
be decoupled from the active signal. This can be accomplished by using an N-channel FET in series with the
WDI pin, with the gate of the FET connected to the RESET output as shown in Figure 1.
TPS3824
WDI
WDI External
RESET
Figure 1
The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available
in a 5-pin SOT23-5 package. The TPS382x-xxQ devices are characterized for operation over a temperature
range of −40°C to 125°C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated
circuits.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
{}
PACKAGE INFORMATION
DEVICE NAME
TPS3820-33QDBVRQ1
THRESHOLD VOLTAGE
MARKING
PDEQ
PDDQ
PAPQ
PAQQ
PARQ
PASQ
PATQ
§
2.93 V
4.55 V
2.25 V
2.63 V
2.93 V
4.55 V
2.25 V
2.63 V
2.93 V
4.55 V
§
TPS3820-50QDBVRQ1
§
TPS3823-25QDBVRQ1
§
TPS3823-30QDBVRQ1
§
TPS3823-33QDBVRQ1
§
TPS3823-50QDBVRQ1
§
TPS3824-25QDBVRQ1
§
TPS3824-30QDBVRQ1
PAUQ
PAVQ
§
TPS3824-33QDBVRQ1
§
TPS3824-50QDBVRQ1
PAWQ
§
TPS3825-33QDBVRQ1
2.93 V
4.55 V
2.93 V
4.55 V
PDGQ
PDFQ
PDIQ
§
TPS3825-50QDBVRQ1
§
TPS3828-33QDBVRQ1
§
TPS3828-50QDBVRQ1
PDHQ
†
For the most current package and ordering information, see the Package Option
Addendum at the end of this document, or see the TI web site at
http://www.ti.com.
Package drawings, thermal data, and symbolization are available at
http://www.ti.com/packaging.
‡
§
The DBVR package indicates tape and reel of 3000 parts.
FUNCTION/TRUTH TABLE
INPUTS
OUTPUTS
‡
§
MR
L
V
DD
>V
RESET
RESET
IT
0
L
L
H
H
H
L
L
1
0
1
H
L
H
H
‡
§
TPS3820/3/5/8
TPS3824/5
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
functional block diagram
V
DD
†
Reset
Watchdog
Timer Logic
Reset
Logic
Reset
52 kΩ
+
_
‡
MR
40 kΩ
V
ref
Transition
Detector
WDI
†
TPS3824/5
TPS3820/3/5/8
‡
timing diagram
V
IT
V
DD
1.1 V
t
t
t
t
d
d
d
t(out)
undefined
undefined
RESET
WDI
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
DD
RESET, RESET, MR, WDI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (V + 0.3 V)
DD
Maximum low output current, I
Maximum high output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA
OL
OH
Input clamp current range, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
IK
I
I
DD
Output clamp current range, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
OK
O
O
DD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Storage temperature range, T
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
T
≤ 25°C
OPERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
DBV
437 mW
3.5 mW/°C
280 mW
227 mW
87 mW
recommended operating conditions
MIN
1.1
MAX
UNIT
V
Supply voltage, V
5.5
DD
Input voltage, V
0
V
DD
+ 0.3
V
I
High-level input voltage at MR and WDI, V
0.7 × V
V
IH
DD
Low-level input voltage, V
0.3 × V
100
V
IL
DD
Input transition rise and fall rate at MR or WDI, Δt/ΔV
ns/V
°C
Operating free-air temperature range, T
−40
125
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
I
= V + 0.2 V
= −20 μA
DD
IT−
TPS382x-25
OH
0.8 × V
DD
TPS382x-30
TPS382x-33
V = V + 0.2 V
DD IT−
RESET
V
I
= −30 μA
OH
V
I
= V + 0.2 V
IT−
= −120 μA
DD
TPS382x-50
V
DD
− 1.5 V
OH
TPS3824-25
TPS3825-25
V
DD
≥ 1.8 V, I = −100 μA
V
OH
High-level output voltage
OH
TPS3824-30
TPS3825-30
RESET
0.8 × V
V
DD
TPS3824-33
TPS3825-33
V
V
≥ 1.8 V, I = −150 μA
DD
OH
TPS3824-50
TPS3825-50
TPS3824-25
TPS3825-25
= V + 0.2 V
IT−
= 1 mA
DD
I
OL
TPS3824-30
TPS3825-30
V
= V + 0.2 V
IT−
= 1.2 mA
DD
RESET
0.4
V
I
OL
TPS3824-33
TPS3825-33
TPS3824-50
TPS3825-50
V
= V + 0.2 V
= 3 mA
DD IT−
V
OL
Low-level output voltage
I
OL
V
= V − 0.2 V
IT−
= 1 mA
DD
TPS382x-25
I
OL
TPS382x-30
TPS382x-33
V
= V −0.2 V
IT−
= 1.2 mA
DD
RESET
0.45
V
I
OL
V
= V − 0.2 V
IT−
= 3 mA
DD
TPS382x-50
I
OL
Power-up reset voltage (see Note 2)
V
≥ 1.1 V, I = 20 μA
0.4
2.30
2.69
3
V
V
DD
OL
TPS382x-25
TPS382x-30
TPS382x-33
TPS382x-50
TPS382x-25
TPS382x-30
TPS382x-33
TPS382x-50
TPS382x-25
TPS382x-30
TPS382x-33
TPS382x-50
2.21
2.59
2.88
4.49
2.19
2.55
2.84
4.44
2.25
2.63
2.93
4.55
2.25
2.63
2.93
4.55
T = 0°C to 85°C
A
4.64
2.30
2.69
3
Negative-going input threshold
voltage (see Note 3)
V
V
IT−
T = −40°C to 125°C
A
V
4.65
30
50
Hysteresis at V input
mV
hys
DD
NOTES: 2. The lowest supply voltage at which RESET becomes active. t
≥ 15 μs/V
r, VDD
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near the supply terminals.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
ꢀ
ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WDI = V
time average (dc = 88%)
,
DD
I
I
Average high-level input current
120
IH(AV)
WDI
WDI = 0.3 V, V = 5.5 V
time average (dc = 12%)
DD
Average low-level input current
High-level input current
−15
140
−40
IL(AV)
WDI
MR
WDI = V
190
−60
DD
μA
I
MR = V × 0.7,
IH
IL
DD
V
DD
= 5.5 V
WDI
WDI = 0.3 V, V = 5.5 V
140
190
DD
I
Low-level input current
MR
MR = 0.3 V, V = 5.5 V
−110
−160
DD
TPS382x-25
TPS382x-30
TPS382x-33
TPS382x-50
−400
Output short-circuit current
(see Note 4)
V
V
= V
= 0 V
+ 0.2 V,
DD
IT, max
I
I
RESET
μA
μA
OS
O
−800
25
WDI and MR unconnected,
Outputs unconnected
Supply current
15
DD
Internal pullup resistor at MR
Input capacitance at MR, WDI
52
5
kΩ
C
V = 0 V to 5.5 V
I
pF
i
NOTE 4: The RESET short-circuit current is the maximum pullup current when RESET is driven low by a μP bidirectional reset pin.
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
at V
TEST CONDITIONS
MIN
MAX
UNIT
μs
V
DD
V
DD
V
DD
= V + 0.2 V,
V
V
V
= V - 0.2 V
6
DD
IT−
DD
IT-
t
w
Pulse width
at MR
≥ V + 0.2 V,
= 0.3 x V
,
,
V
V
= 0.7 x V
= 0.7 x V
1
μs
IT−
IL
IL
DD
DD
IH
DD
at WDI
≥ V + 0.2 V,
= 0.3 x V
100
ns
IT−
IH
DD
switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
TPS3820
TEST CONDITIONS
MIN
TYP
200
1.6
MAX
310
2.5
UNIT
ms
s
112
0.9
15
V
≥ V + 0.2 V,
DD
IT−
t
t
Watchdog time out
Delay time
tout
d
See Timing Diagram
TPS3823/4/8
TPS3820
25
37
V
≥ V + 0.2 V,
DD
IT−
ms
See timing diagram
TPS3823/4/5/8
120
200
300
V
V
V
≥ V + 0.2 V,
IT−
DD
MR to RESET delay
(TPS3820/3/5/8)
= 0.3 x V
,
0.1
25
IL
DD
Propagation (delay) time,
high-to-low-level output
= 0.7 x V
IH
DD
t
μs
PHL
PLH
V
V
= V - 0.2 V,
IT-
IL
V
DD
to RESET delay
= V + 0.2 V
IH
IT-
V
V
V
≥ V + 0.2 V,
DD
IT−
MR to RESET delay (TPS3824/5)
= 0.3 x V
,
0.1
25
IL
DD
Propagation (delay) time,
low-to-high-level output
= 0.7 x V
IH
DD
t
μs
V
V
= V - 0.2 V,
IT-
IL
V
DD
to RESET delay (TPS3824/5)
= V + 0.2 V
IH
IT-
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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ꢀ
SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
1.001
1
19
17
15
MR = Open
WDI = Open
T
= 25°C
A
13
11
9
0.999
0.998
TPS382x-33
7
5
0.997
0.996
0.995
3
1
−1
−0.5
−40
−15
10
35
60
85
0.5
1.5
2.5
3.5
4.5
5.5
6.5
T − Free-Air Temperature − °C
A
V
DD
− Supply Voltage − V
Figure 2
Figure 3
INPUT CURRENT
vs
INPUT VOLTAGE AT MR
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
50
0
3
2.5
2
V
= 2.66 V
V
= 5.5 V
DD
DD
WDI = Open
MR = Open
WDI = Open
−50
−40°C
1.5
85°C
−100
−150
−200
1
0.5
0
85°C
−40°C
−1
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
V − Input Voltage at MR − V
I
I
− Low-Level Output Current − mA
OL
Figure 4
Figure 5
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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PROCESSOR SUPERVISORY CIRCUITS
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SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
3
6
5
4
3
V
= 3.2 V
DD
V
= 5.5 V
DD
WDI = Open
MR = Open
WDI = Open
MR = Open
2.5
2
−40°C
−40°C
1.5
85°C
85°C
2
1
0
1
0.5
0
0
−50
−100
−150
−200
−250
0
−100 −200 −300 −400 −500 −600
−700
I
− High-Level Output Current − μA
OH
I
− High-Level Output Current − μA
OH
Figure 6
Figure 7
MINIMUM PULSE DURATION AT VDD
vs
V
DD THRESHOLD OVERDRIVE
10
8
WDI = Open
MR = Open
6
4
2
0
0
200
400
600
800
1000
V
DD
− Threshold Overdrive − mV
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
2T25-50QFRG4Q1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
2T28-33QDBVRG4Q1
2U3820-50QDBVRG4Q1
2U3823-25QDBVRG4Q1
2U3823-30QDBVRG4Q1
2U3823-33QDBVRG4Q1
2U3823-50QDBVRG4Q1
2U3824-25QDBVRG4Q1
2U3824-33QDBVRG4Q1
2U3824-50QDBVRG4Q1
2U3825-33QDBVRG4Q1
TPS3820-33QDBVRQ1
TPS3820-50DBVRQ1G4
TPS3820-50QDBVRQ1
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
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Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS3823-25QDBVRQ1
TPS3823-30QDBVRQ1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000
3000
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Green (RoHS
& no Sb/Br)
Request Free Samples
TPS3823-33QDBVRQ1
TPS3823-50QDBVRQ1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
Request Free Samples
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TBD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2010
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS3824-25QDBVRQ1
TPS3824-30QDBVRQ1
TPS3824-33QDBVRQ1
TPS3824-50QDBVRQ1
TPS3825-33QDBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
3000
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Request Free Samples
Request Free Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS3825-50QDBVRQ1
TPS3828-33QDBVRQ1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000
3000
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
TPS3828-50QDBVRG4Q
TPS3828-50QDBVRQ1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2010
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3820-33-Q1, TPS3820-50-Q1, TPS3823-25-Q1, TPS3823-30-Q1, TPS3823-33-Q1, TPS3823-50-Q1, TPS3824-25-Q1,
TPS3824-30-Q1, TPS3824-33-Q1, TPS3824-50-Q1, TPS3825-33-Q1, TPS3825-50-Q1, TPS3828-33-Q1, TPS3828-50-Q1 :
Catalog: TPS3820-33, TPS3820-50, TPS3823-25, TPS3823-30, TPS3823-33, TPS3823-50, TPS3824-25, TPS3824-30, TPS3824-33, TPS3824-50, TPS3825-33,
TPS3825-50, TPS3828-33, TPS3828-50
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
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2U3824-33QDBVRG4Q1 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
2U3824-25QDBVRG4Q1 | TI | PROCESSOR SUPERVISORY CIRCUITS | 类似代替 |
2U3824-33QDBVRG4Q1 相关器件
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2U3825-33QDBVRG4Q1 | TI | PROCESSOR SUPERVISORY CIRCUITS | 获取价格 | |
2U3836E18QDBVRG4Q1 | TI | Nanopower Supervisory Circuits for Automotive 5-SOT-23 -40 to 125 | 获取价格 | |
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