1P2GU04QDRYRQ1 [TI]
汽车类 2 通道、1.65V 至 5.5V 反相器 | DRY | 6 | -40 to 125;
| 型号： | 1P2GU04QDRYRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2 通道、1.65V 至 5.5V 反相器 | DRY | 6 | -40 to 125 光电二极管 逻辑集成电路 |
| 文件： | 总26页 (文件大小：1523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74LVC2GU04-Q1
SCES902 –SEPTEMBER 2019
SN74LVC2GU04-Q1 Dual Unbuffered Inverter
1 Features
2 Applications
1
•
AEC-Q100 Qualified for automotive applications:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AV receivers
Blu-ray players and home theaters
DVD recorders and players
Desktop or notebook PCs
Digital radio or internet radio players
Digital video cameras (DVC)
Embedded PCs
–
Device temperature grade 1: –40°C to +125°C,
TA
•
•
•
•
•
•
Supports 5-V VCC operation
Inputs accept voltages to 5.5 V
Max tpd of 3.7 ns at 3.3 V
Low power consumption, 10-µA max ICC
±24-mA Output drive at 3.3 V
GPS: Personal navigation devices
Mobile internet devices
Network projector front-ends
Portable media players
Pro audio mixers
Typical VOLP (output ground bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
•
•
Typical VOHV (output VOH undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Can be used as a down translator to translate
inputs from a max of 5.5 V down
to the VCC level
Smoke detectors
Solid-state drive (SSD): enterprise
High-definition (HDTV)
Tablets: enterprise
•
Unbuffered outputs
Audio docks: portable
DLP front projection systems
DVR and DVS
Digital picture frame (DPF)
Digital still cameras
3 Description
This dual inverter is designed for 1.65-V to 5.5-V VCC
operation.
The SN74LVC2GU04-Q1 device contains two
inverters with unbuffered outputs and performs the
Boolean function Y = A.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
SN74LVC2GU04QDRYRQ1 SON (6)
1.45 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
6
1A
1Y
3
4
2A
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2GU04-Q1
SCES902 –SEPTEMBER 2019
www.ti.com
Table of Contents
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ..................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Switching Characteristics.......................................... 7
6.8 Operating Characteristics.......................................... 7
6.9 Typical Characteristic................................................ 7
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1 Receiving Notification of Documentation Updates 14
12.2 Support Resources ............................................... 14
12.3 Trademarks........................................................... 14
12.4 Electrostatic Discharge Caution............................ 14
12.5 Glossary................................................................ 14
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
DATE
REVISION
NOTES
September 2019
*
Initial release.
2
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5 Pin Configuration and Functions
DRY Package
6-Pin SON
Top View
1A
1Y
1
2
3
6
5
4
GND
2A
VCC
2Y
Pin Functions
PIN
I/O
DESCRIPTION
NAME
1A
DRY Package(1)
1
6
3
4
5
2
I
Input
1Y
O
I
Output
Input
2A
2Y
O
—
—
Output
VCC
GND
Positive Supply
Ground
(1) See Package drawing at the end of the data sheet for dimensions
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
6.5
V
VO
IIK
Voltage range applied to any output in the high or low state(2)(3)
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
VO < 0
–50
–50
mA
mA
mA
mA
°C
IOK
IO
Output clamp current
Continuous output current
±50
Continuous current through VCC or GND
Operating free-air temperature
Operating junction temperature
Storage temperature
±100
TA
–40
–65
125
150
150
TJ
°C
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
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6.2 ESD Ratings
MAX UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions(1)
MIN
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
1.65
5.5
V
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
IO = –100 µA
IO = 100 µA
0.75 × VCC
0.25 × VCC
0
0
5.5
VCC
–4
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
DRY
THERMAL METRIC(1)
UNIT
°C/W
(6 PINS)
233.4
144.6
119.9
15.8
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
119.3
—
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C
–40°C to 125°C
MIN TYP(1)
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
VCC – 0.1
1.2
TYP(1)
MAX
MAX
IOH = –100 µA
1.65 V to 5.5 V
1.65 V
VCC – 0.1
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
1.9
VOH
VIL = 0 V
V
2.4
3 V
2.3
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
0.1
0.45
0.3
0.1
0.45
0.3
IOL = 8 mA
2.3 V
VOL
VIH = VCC
V
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.4
0.4
3 V
0.55
0.55
±5
0.55
0.55
±5
4.5 V
0 to 5.5 V
1.65 V to 5.5 V
3.3 V
II
A inputs
VI = 5.5 V or GND
VI = 5.5 V or GND,
VI = VCC or GND
µA
µA
pF
ICC
CI
IO = 0
10
10
7
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Parameter Measurement Information)
–40°C to 85°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN
MAX
5.5
MIN
MAX
MIN
MAX
3.7
MIN
MAX
tpd
A
Y
1.2
1
4
1.1
1
3
ns
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Parameter Measurement Information)
–40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
PARAMETER
UNIT
MIN
MAX
6.3
MIN
MAX
4.5
MIN
MAX
4.2
MIN
MAX
3.5
tpd
A
Y
1.2
1
1.1
1
ns
6.8 Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
7
7
8
23
pF
6.9 Typical Characteristic
5
4
3
2
1
0
tpd(MAX)
tpd(ns)
tpd(MIN)
1
2
3
4
5
6
V
CC (V)
Figure 1. tpd vs VCC
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7 Parameter Measurement Information
VLOAD
Open
GND
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC2GU04-Q1 device contains two inverters with unbuffered outputs with a maximum sink current of
32 mA.
8.2 Functional Block Diagram
Logic Diagram (Positive Logic)
1
6
1A
1Y
3
4
2A
2Y
8.3 Feature Description
8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high-drive capability of this device
creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be
followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst-case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using Ohm's law (R = V ÷ I).
Signals that are applied to the inputs need to have fast edge rates, as shown by Δt/Δv in the Recommended
Operating Conditions, to avoid excessive current consumption and oscillations. If a slow or noisy input signal is
required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard
CMOS input.
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Feature Description (continued)
8.3.3 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as shown in Figure 3.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
Figure 3. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.5 Unbuffered Logic
A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function,
and the output inverter. Some devices have multiple stages at the input or output for various reasons. An
unbuffered CMOS logic function eliminates the extra input and output stages; the device only contains the
required logic function which is directly driven from the inputs and directly drives the outputs.
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. To learn more about how to use
an unbuffered inverter in an oscillator circuit, see Use of the CMOS Unbuffered Inverter in Oscillator Circuits.
8.4 Device Functional Modes
Table 1. Function Table (Each
Inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. An example application circuit is
shown in Figure 4. To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use
of the CMOS Unbuffered Inverter in Oscillator Circuits application report.
9.2 Typical Application
RF ~2.2 Mꢀ
U
CL
RS
~1 kꢀ
C1
~32 pF
C2
~32 pF
Crystal
Figure 4. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use of the CMOS
Unbuffered Inverter in Oscillator Circuits application report.
1. Recommended Input Conditions
–
–
Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
Inputs are overvoltage tolerant allowing them to go as high as (VI max) in Recommended Operating
Conditions at any valid VCC
.
2. Absolute Maximum Output Conditions
–
–
Load currents must not exceed (IO max) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in Absolute Maximum Ratings.
Outputs must not be pulled above the voltage rated in the Absolute Maximum Ratings.
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Typical Application (continued)
9.2.3 Application Curve
1600
Icc 1.8V
Icc 2.5V
Icc 3.3V
Icc 5V
1400
1200
1000
800
600
400
200
0
0
20
40
Frequency - MHz
60
80
D001
Figure 5. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1-
µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin
as possible for best results.
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11 Layout
11.1 Layout Guidelines
Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners.
An example layout is given in Figure 6 for the DRY (SON) package. This example layout includes a 0402 (metric)
capacitor and uses the measurements found in the example board layout appended to this end of this datasheet.
A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be used to trace
out the center pin connection through another board layer, or it can be left out of the layout
11.2 Layout Example
Bypass capacitor
placed close to
the device
VCC
GND
0402
0.1 ꢀF
VCC
2Y
1Y
1A
2A
Avoid 90°
corners for
signal lines
GND
GND
Recommend GND pour for
improved signal isolation,
noise reduction,
and thermal dissipation
Figure 6. Layout example for DRY package
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DRY0006B
USON - 0.55 mm max height
S
C
A
L
E
8
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
1.5
1.4
C
0.55 MAX
SEATING PLANE
0.08 C
0.05
0.00
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
PIN 1 ID
(OPTIONAL)
0.1
C A
C
B
0.05
0.35
0.25
6X
4222207/B 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2019, Texas Instruments Incorporated
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Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
SCES902 –SEPTEMBER 2019
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006B
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222207/B 02/2016
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
16
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Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
www.ti.com
SCES902 –SEPTEMBER 2019
EXAMPLE STENCIL DESIGN
DRY0006B
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222207/B 02/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2019, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Links: SN74LVC2GU04-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
1P2GU04QDRYRQ1
ACTIVE
SON
DRY
6
5000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2GU04-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Catalog: SN74LVC2GU04
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
1P2GU04QDRYRQ1
SON
DRY
6
5000
180.0
9.5
1.2
1.65
0.7
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DRY
SPQ
Length (mm) Width (mm) Height (mm)
189.0 185.0 36.0
1P2GU04QDRYRQ1
6
5000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006B
USON - 0.55 mm max height
S
C
A
L
E
8
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
1.5
1.4
C
0.55 MAX
SEATING PLANE
0.08 C
0.05
0.00
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
PIN 1 ID
(OPTIONAL)
0.1
C A
C
B
0.05
0.35
0.25
6X
4222207/B 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006B
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222207/B 02/2016
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006B
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222207/B 02/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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Copyright © 2023, Texas Instruments Incorporated
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