28529-DSH-001-K [TE]
Inverse Multiplexing for ATM (IMA) Family;
| 型号： | 28529-DSH-001-K |
| 厂家： | 
TE CONNECTIVITY |
| 描述： | Inverse Multiplexing for ATM (IMA) Family ATM 异步传输模式 |
| 文件： | 总309页 (文件大小：2612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28525/9 Data Sheet
Inverse Multiplexing for ATM (IMA) Family
The M2852x family of devices provides system designers with a complete integrated IMA solution for up to 32 ports.
All devices include a Transmission Convergence block to perform cell delineation, 512 K internal RAM to meet ATM
forum requirements for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer interface.
Source code for all required software functions is available from Mindspeed. The M28529 supports 32 IMA groups
with 1-32 links per group.
The TC block is capable of bit level cell delineation, which allows for direct connection DSL serial data streams
without a frame sync pulse. Individual ports can be operated in a 'pass thru' mode without the IMA overhead.
The M28529 provides direct connection to 32 serial/interleaved highway links or a PHY side UTOPIA bus. In
addition, an external memory bus allows the differential delay memory to access up to 2 Mbytes of external
RAM.The M28529 supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001
Distinguishing Features
• Complete IMA solution in a single package
• 16 port, M28525
• 32 port, M28529
• Field tested software available
• Up to 32 IMA groups with 1-32 links/group
• Supports 50 ms (beyond the IMA standard requirements for 25 ms)
differential delay with 512K Internal memory
• Memory expandable to 2 M bytes via external bus
• UTOPIA level 2 interfaces
• Glueless serial and interleaved highway interfaces to Mindspeed
Framers
• Octet or Bit level cell delineation
• Variable link data rates (64K–8.192 Mb/s)
Functional Block Diagram
E xte rn a l M e m o ry
In te rfa c e
M 2 8 5 2 9
T C B lo c k
C e ll
p ro c e s s o r
L in e in t e rf a c e
0
C e ll
p ro c e s s o r
L in e in t e rf a c e
1
I M A
B lo c k
I n t e rn a l
5 1 2 K x 8
S R A M
0
1
e
x
tm
e m s e l p in
Di if f e r e n t ia l D e la y
m
e m o ry in t e rf a c e
R x lo c k a n d
B
P a s s t h ro u g h
C e ll
L in e in t e r f a c e 3 0
L in e in t e r f a c e 3 1
p ro c e s s o r
I M A
E n g in e
C e ll
p ro c e s s o r
T
x
B
lo c k a n d
P a s s t h ro u g h
TC
C o u n te r s
T C S ta tu s
R e g is te r s
T C C o n tr o l
R e g is te r s
O
n e S e c
M ic r o
I n t e r f a c e
M
ic r o
IM
A
c lo c ks
J T A G
C lo c ks
* N o t e : T h e M 2 8 5 2 5 o n ly s u p p o rt s 1 6 T C P o rt s
®
28529-DSH-001-K
Mindspeed Technologies
September 2007
Mindspeed Proprietary and Confidential
Ordering Information
Manufacturing Part
Number
Operating
Temperature
Model Number
Product Revision
Package
M28525
M28525G*
M28529
M28525-12
M28525G-12
M28529-12
M28529G-12
B
B
B
B
27mm PBGA, 484 pins
27mm PBGA, 484 pins
27mm PBGA, 484 pins
27mm PBGA, 484 pins
–40 °C to 85 °C
–40 °C to 85 °C
–40 °C to 85 °C
–40 °C to 85 °C
M28529G*
*The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information.
Revision History
Revision
Level
Date
Description
A
B
C
D
E
F
Advance
Advance
April 2003
May 2003
Advance A version
Advance B version
Advance C version
Advance D version
Advance E version
Preliminary F version
Preliminary G version
Released H version
Advance
July 2003
Advance
August 2003
October 2003
February 2004
May 2004
Advance
Preliminary
Preliminary
Released
Released
G
H
I
July 2004
September 2004 Released I version.
Added note to IMA_FE_TX_LNKn_GRP_ID, IMA_FE_TX_LNKn_CFG and
ATM Cell Capture registers to indicate conditions under which these
registers will be undefined.
J
Released
Released
August 2006
Changes made to explain limitations in Dual-Clav mode, like, only addresses
0 through 0xF are supported and that multiple M28529 devices cannot
share the Utopia bus with an ATM-layer device.
K
September 2007 Clarified configuration of pass-through operation. Corrected minumum
parameter for “disable from atmutxclk rise edge.” Other misc. corrections.
®
28529-DSH-001-K
Mindspeed Technologies
ii
Mindspeed Proprietary and Confidential
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1.1
1.1.2
Introduction to IMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Introduction To Inverse Multiplexing for ATM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1.2.1
1.1.2.2
1.1.2.3
1.1.2.4
1.1.2.5
IMA Framing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
IMA Control Protocol Cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Link State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Transmit Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Differential Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1.3
Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.1.3.1
1.1.3.2
1.1.3.3
1.1.3.4
1.1.3.5
1.1.3.6
Software Subsystems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Configuration (CF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Diagnostics (DG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Failure Monitoring (FM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Performance Monitoring (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Group State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.2.1
1.2.2
1.2.3
1.2.4
IMA Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Diagnostics/Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Cell Delineation Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.2.4.1
1.2.4.2
1.2.4.3
1.2.4.4
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
ATM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Counters/Status Register Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.3 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.4 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.4.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
®
28529-DSH-001-K
Mindspeed Technologies
iii
Mindspeed Proprietary and Confidential
Table of Contents
1.4.2
1.4.3
DSLAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Wireless NodeB/RNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.1
1.5.2
1.5.3
Pin Diagram and Definitions (UTOPIA-to-Serial Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Pin Diagram and Definitions (UTOPIA-to-UTOPIA Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Interleaved Highway Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
1.6 Stand Alone Cell Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
1.7 Source Loopbacks (UTOPIA-to-Serial Configuration Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
1.7.1
1.7.2
Source Loopback Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Source Loopback Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
1.8
Far-End Line Loopback (Serial Configuration Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
1.9 IMA Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
1.10 IMA System Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
1.10.1 IMA System Loopback 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
1.10.2 IMA System Loopback 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
1.11 Reference Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
1.12 IMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
1.12.1 IMA Link Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
1.12.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
1.12.2.1 Aggregate Cell Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
1.12.2.2 Serial Clock Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
1.12.2.3 Clock Generator Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
1.12.3 Summary Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
1.12.4 Typical Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
1.12.4.1 Serial Mode (using internal TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
1.12.4.2 UTOPIA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
1.12.5 IMA Internal Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
1.12.5.1 T1/E1 Using Internal Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
1.12.5.2 DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
1.13 UTOPIA Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
1.13.1 General UTOPIA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
1.13.2 UTOPIA 8-bit and 16-bit Bus Widths (PHY and ATM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
1.13.3 UTOPIA Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
1.13.3.1 IMA UTOPIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
1.13.3.2 TC Block UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
1.13.3.3 PHY-Side UTOPIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
1.13.4 Dual Clav/Enb Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
1.14 Transmission Convergence Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
1.14.1 ATM Cell Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
1.14.1.1 HEC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
1.14.2 ATM Cell Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
1.14.2.1 Cell Delineation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
1.14.2.2 Cell Delineation Control Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
1.14.2.3 Cell Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
1.14.2.4 Cell Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
®
28529-DSH-001-K
Mindspeed Technologies
iv
Mindspeed Proprietary and Confidential
Table of Contents
1.14.2.5 Framing Modes (UTOPIA-to-Serial Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
1.15 General Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
1.15.1 Micro Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
1.15.1.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
1.15.1.2 Counters (TC Block Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
2.0 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
2.2 TC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
0x00—SUMINT (Summary Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
0x01—ENSUMINT (Summary Interrupt Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
0x04—PMODE (Port Mode Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
0x05—IOMODE (Input/Output Mode Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
0x08—CGEN (Cell Generation Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
0x09—HDRFIELD (Header Field Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
0x0A—IDLPAY (Transmit Idle Cell Payload Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
0x0B—ERRPAT (Error Pattern Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
0x0C—CVAL (Cell Validation Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
2.2.10 0x0D—UTOP1 (UTOPIA Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
2.2.11 0x0E—UTOP2 (UTOPIA Control Register 2) (TC Block). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
2.2.12 0x0F—UDF2 (UDF2 Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
2.2.13 0x10—TXHDR1 (Transmit Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
2.2.14 0x11—TXHDR2 (Transmit Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
2.2.15 0x12—TXHDR3 (Transmit Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
2.2.16 0x13—TXHDR4 (Transmit Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
2.2.17 0x14—TXIDL1 (Transmit Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
2.2.18 0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
2.2.19 0x16—TXIDL3 (Transmit Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
2.2.20 0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
2.2.21 0x18—RXHDR1 (Receive Cell Header Control Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
2.2.22 0x19—RXHDR2 (Receive Cell Header Control Register 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
2.2.23 0x1A—RXHDR3 (Receive Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
2.2.24 0x1B—RXHDR4 (Receive Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
2.2.25 0x1C—RXMSK1 (Receive Cell Mask Control Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
2.2.26 0x1D—RXMSK2 (Receive Cell Mask Control Register 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
2.2.27 0x1E—RXMSK3 (Receive Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
2.2.28 0x1F—RXMSK4 (Receive Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
2.2.29 0x20—RXIDL1 (Receive Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
2.2.30 0x21—RXIDL2 (Receive Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
2.2.31 0x22—RXIDL3 (Receive Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
2.2.32 0x23—RXIDL4 (Receive Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
2.2.33 0x24—IDLMSK1 (Receive Idle Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
2.2.34 0x25—IDLMSK2 (Receive Idle Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
2.2.35 0x26—IDLMSK3 (Receive Idle Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
2.2.36 0x27—IDLMSK4 (Receive Idle Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
2.2.37 0x28—ENCELLT (Transmit Cell Interrupt Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
2.2.38 0x29—ENCELLR (Receive Cell Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
2.2.39 0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . . . . . . .171
®
28529-DSH-001-K
Mindspeed Technologies
v
Mindspeed Proprietary and Confidential
Table of Contents
2.2.40 0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . . . . . . . .172
2.2.41 0x2E—TXCELL (Transmit Cell Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
2.2.42 0x2F—RXCELL (Receive Cell Status Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
2.2.43 0x30—IDLCNTL (Idle Cell Receive Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
2.2.44 0x31—IDLCNTH (Idle Cell Receive Counter [High Byte]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
2.2.45 0x33—LOCDCNT (LOCD Event Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
2.2.46 0x34—TXCNTL (Transmitted Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
2.2.47 0x35—TXCNTH (Transmitted Cell Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
2.2.48 0x37—CORRCNT (Corrected HEC Error Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
2.2.49 0x38—RXCNTL (Received Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
2.2.50 0x39—RXCNTH (Received Cell Counter [High Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
2.2.51 0x3B—UNCCNT (Uncorrected HEC Error Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
2.2.52 0x3C—NONCNTL (Non-matching Cell Counter [Low Byte]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
2.2.53 0x3D—NONCNTH (Non-matching Cell Counter [High Byte]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
2.3 General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
0xF00—GENCTRL (General Device Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
0xF01—PARTNUM (Part and Version Number Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
0xF02—PHYINTFC (PHY-side Interface Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
0xF03—ATMINTFC (ATM-side Interface Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
0xF04—STATOUT (Output Status Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
0xF05—SUMPORT0 (Summary Port Interrupt Status Register for TC ports 0-7) . . . . . . . . . . . . . . . . .181
0xF06—ENSUMPORT0 (Summary Port Interrupt Control Register for TC Ports 0-7) . . . . . . . . . . . . . .181
0xF07—SUMPORT1 (Summary Port Interrupt Status Register for TC ports 8-15) . . . . . . . . . . . . . . . .182
0xF08—ENSUMPORT1 (Summary Port Interrupt Control Register for TC Ports 8-15) . . . . . . . . . . . . .182
2.3.10 0xF09—SUMPORT2 (Summary Port Interrupt Status Register for TC ports 16-23) . . . . . . . . . . . . . . .183
2.3.11 0xF0A—ENSUMPORT2 (Summary Port Interrupt Control Register for TC Ports 16-23) . . . . . . . . . . . .183
2.3.12 0xF0B—SUMPORT3 (Summary Port Interrupt Status Register for TC ports 24-31) . . . . . . . . . . . . . . .184
2.3.13 0xF0C—ENSUMPORT3 (Summary Port Interrupt Control Register for TC Ports 24-31) . . . . . . . . . . . .184
2.3.14 0xF0F—SCRATCH (Scratch Pad Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
2.3.15 0xF10—TCCTRL0 (TC Control Register for TC ports 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
2.3.16 0xF11—TCCTRL1 (TC Control Register for TC ports 4-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
2.3.17 0xF12—TCCTRL2 (TC Control Register for TC ports 8-11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
2.3.18 0xF13—TCCTRL3 (TC Control Register for TC ports 12-15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
2.3.19 0xF14—TCCTRL4 (TC Control Register for TC ports 16-19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
2.3.20 0xF15—TCCTRL5 (TC Control Register for TC ports 20-23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
2.3.21 0xF16—TCCTRL6 (TC Control Register for TC ports 24-27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
2.3.22 0xF17—TCCTRL7 (TC Control Register for TC ports 28-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
2.3.23 0xF18—ONESECINT (One Second Interrupt Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
2.3.24 0xF19—ONESECINT (One Second Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
2.4 IMA Subsystem Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
0x800—IMA_VER_1_CONFIG (IMA Type and Version Code I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
0x801—IMA_VER_2_CONFIG (IMA Version Codes II and III) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
0x802—IMA_SUBSYS_CONFIG (IMA Configuration Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
0x803—IMA_MISC_STATUS (IMA Miscellaneous Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
0x804—IMA_MISC_CONFIG (IMA Miscellaneous Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
0x805—IMA_MEM_LOW_TEST (IMA Memory Test Address (Bits 0–7)) . . . . . . . . . . . . . . . . . . . . . . .191
0x806—IMA_MEM_HI_TEST (IMA Memory Test Address (Bits 8–15)) . . . . . . . . . . . . . . . . . . . . . . . .192
0x807—IMA_MEM_TEST_CTL (IMA Memory Test Control / Address MSBs) . . . . . . . . . . . . . . . . . . . .192
0x808—IMA_MEM_TEST_DATA (IMA Memory Test Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
®
28529-DSH-001-K
Mindspeed Technologies
vi
Mindspeed Proprietary and Confidential
Table of Contents
2.4.10 0x809—IMA_LNK_DIAG_CTL (IMA Link Diagnostic Control Register) . . . . . . . . . . . . . . . . . . . . . . . . .192
2.4.11 0x80A—IMA_LNK_DIFF_DEL (IMA Link Differential Delay Write Counter) . . . . . . . . . . . . . . . . . . . . . .192
2.4.12 0x80B—IMA_RCV_LNK_ANOMALIES (IMA Receive Link Anomalies). . . . . . . . . . . . . . . . . . . . . . . . . .193
2.4.13 0x80C—IMA _PHY_LOOPBACK (IMA Phy Side UTOPIA Loopback) . . . . . . . . . . . . . . . . . . . . . . . . . . .194
2.4.14 0x80E—IMA_DIAG_XOR_BIT (IMA Diagnostic Bit). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
2.4.15 0x80F—IMA_DIAG (IMA Diagnostic Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
2.4.16 0x810—IMA_TIM_REF_MUX_CTL_ADDR (IMA Timing Reference Multiplexer Control Address). . . . .195
2.4.17 0x811—IMA_TIM_REF_MUX_CTL_DATA (IMA Timing Reference Multiplexer Control Data) . . . . . . . .196
2.4.18 0x812—IMA_RX_PERSIST_CONFIG (IMA Receive Persistence Configuration) . . . . . . . . . . . . . . . . . .197
2.4.19 0x813—IMA_ATM_UTOPIA_BUS_CTL (IMA ATM UTOPIA Bus Control) . . . . . . . . . . . . . . . . . . . . . . .197
2.4.20 0x814—IMA_DIFF_DELAY_ADDR (IMA Differential Delay Control Address). . . . . . . . . . . . . . . . . . . . .198
2.4.21 0x815—IMA_DIFF_DELAY_DATA (IMA Differential Delay Control Data) . . . . . . . . . . . . . . . . . . . . . . . .198
2.4.22 0x816—IMA_DSL_CLOCK_GEN_ADDR (IMA DSL Clock Generator Control) . . . . . . . . . . . . . . . . . . . .199
2.4.23 0x817—IMA_DSL_CLOCK_GEN_DATA (IMA_DSL Clock Generator Data) . . . . . . . . . . . . . . . . . . . . . .200
2.4.24 0x818—IMA_RX_TRANS_TABLE (IMA Receive Translation Table Address). . . . . . . . . . . . . . . . . . . . .201
2.4.25 0x819—IMA_RX_ATM_TRANS_TABLE (IMA Receive ATM Translation Table Internal Channel). . . . . .202
2.4.26 0x81B—IMA_TX_TRANS_TABLE (IMA Transmit Translation Table Address) . . . . . . . . . . . . . . . . . . . .203
2.4.27 0x81C—IMA_TX_ATM_TRANS_TABLE (Transmit ATM Translation Table Internal Channel) . . . . . . . .203
2.5 IMA Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.9
0x81F—IMA_GRP_1TO4_SEM (Group Table Control I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
0x91F—IMA_GRP_5TO8_SEM (Group Table Control II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
0xA1F—IMA_GRP_9TO12_SEM (Group Table Control III) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
0xB1F—IMA_GRP_13TO16_SEM (Group Table Control IV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
0xC1F—IMA_GRP_17TO20_SEM (Group Table Control V (M28529 Only)) . . . . . . . . . . . . . . . . . . . . .206
0xC9F—IMA_GRP_21TO24_SEM (Group Table Control V (M28529 Only)) . . . . . . . . . . . . . . . . . . . . .207
0xD1F—IMA_GRP_25TO28_SEM (Group Table Control V (M28529 Only)) . . . . . . . . . . . . . . . . . . . . .207
0xD9F—IMA_GRP_29TO32_SEM (Group Table Control V (M28529 Only)) . . . . . . . . . . . . . . . . . . . . .208
IMA_TX_GRPn_RX_TEST_PATTERN (Transmit Group Rx Test Pattern) . . . . . . . . . . . . . . . . . . . . . . . .208
2.5.10 IMA_TX_GRPn_CTL (Transmit Group Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
2.5.11 IMA_TX_GRPn_FIRST_PHY_ADDR (Transmit First PHY Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
2.5.12 IMA_TX_GRPn_ID (Transmit Group ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
2.5.13 IMA_TX_GRPn_STAT_CTL (Transmit Group Status and Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
2.5.14 IMA_TX_GRPn_TIMING_INFO (Transmit Timing Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
2.5.15 IMA_TX_GRPn_TEST_CTL (Transmit Test Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
2.5.16 IMA_TX_GRPn_TX_TEST_PATTERN (Transmit Group Tx Test Pattern) . . . . . . . . . . . . . . . . . . . . . . . .215
2.5.17 IMA_TX_ATMn_CELL_COUNT_LSB (Transmit Cell Count LSBs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
2.5.18 IMA_TX_ATMn_CELL_COUNT_MSB (Transmit Cell Count MSBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
2.5.19 IMA_RX_ATMn_CELL_COUNT_LSB (Receive Cell Count LSBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
2.5.20 IMA_RX_ATMn_CELL_COUNT_MSB (Receive Cell Count MSBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
2.5.21 IMA_RX_GRPn_CFG (Receive Group Status and Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
2.5.22 IMA_RX_GRPn_CTL (Receive Group Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
2.5.23 IMA_RX_GRPn_FIRST_PHY_ADDR (Receive First PHY Address). . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
2.5.24 IMA_RX_GRPn_ID (Expected Receive Group ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
2.5.25 IMA_RX_GRPn_RX_TEST_PATTERN (Receive Group Rx Test Pattern). . . . . . . . . . . . . . . . . . . . . . . . .224
2.5.26 IMA_RX_GRPn_STAT_CTL_CHANGE (Receive Group Status & Control Change Indication). . . . . . . . .225
2.5.27 IMA_RX_GRPn_ACTUAL_GRP_ID (Actual Receive Group ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
2.5.28 IMA_RX_GRPn_STAT_CTL (Receive Group Status and Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
2.5.29 IMA_RX_GRPn_TIMING_INFO (Receive Timing Information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
2.5.30 IMA_RX_GRPn_TEST_CTL (Receive Test Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
®
28529-DSH-001-K
Mindspeed Technologies
vii
Mindspeed Proprietary and Confidential
Table of Contents
2.5.31 IMA_RX_GRPn_TX_TEST_PATTERN (Receive Group Tx Test Pattern) . . . . . . . . . . . . . . . . . . . . . . . . .230
2.6 IMA Link Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.6.9
0x81E—IMA_LNK_SEM (Link Table Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
IMA_TX_LNKn_CTL (Transmit Link Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
IMA_TX_LNKn_STATE (Transmit Link Status Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
IMA_TX_LNKn_ID (Transmit Link ID Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
IMA_RX_LNKn_CTL (Receive Link Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
IMA_RX_LNKn_STATE (Receive Link Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
IMA_RX_LNKn_DEFECT (Receive Link Defects Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
IMA_FE_TX_LNKn_CFG (FE Transmit Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
IMA_FE_LNKn_STATE (FE Link Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
2.6.10 IMA_RX_LNKn_ID (Receive Link ID Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240
2.6.11 IMA_RX_LNKn_IV_CNT (IMA Violation Counter Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
2.6.12 IMA_RX_LNKn_OIF_CNT (Out-of-IMA Frame Counter Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
2.6.13 IMA_FE_TX_LNKn_GRP_ID (FE Transmit Group ID Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
2.7 ATM Cell Capture Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
2.7.1
2.7.2
2.7.3
2.7.4
0xE00-0xE2F—CELL_CAP_PAYLDn (Capture Payload Contents Register) . . . . . . . . . . . . . . . . . . . . . .244
0xE30—CAP_FAC (Capture Facility Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
0xE31—CAP_CNTL (Capture Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
0xE32—CAP_STAT (Capture Status Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
3.0 Product Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
3.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
3.4 Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
PHY-side Interface Timing (Serial Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
Fractional T1/E1 Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
PHY-side Interface Mode (Interleaved Highway) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
PHY-Side Interface Timing (UTOPIA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
UTOPIA Interface Timing (ATM-Side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
External Memory Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
3.4.10 One-second Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
3.5 Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
3.5.1
Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
3.6 Interface Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
4.0 Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
4.1 IMA Version 1.1 PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Symbols and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
IMA PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
4.1.5.1
Global Statement of Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
®
28529-DSH-001-K
Mindspeed Technologies
viii
Mindspeed Proprietary and Confidential
Table of Contents
4.1.5.2
4.1.5.3
Instructions for Completing the PICS Proforma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
IMA Protocol Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
4.1.6
PICS Proforma References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
4.2 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
4.3 Power Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
®
28529-DSH-001-K
Mindspeed Technologies
ix
Mindspeed Proprietary and Confidential
List of Figures
Figure 1-1. M28525/9 Block Diagram Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1-2. IMA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Figure 1-3. IMA Frame; Length = 16; Number of links = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 1-4. M2852x Connected to a CX28398 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 1-5. M28529 in DSLAM applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 1-6. M28529 in NodeB/RNC Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 1-7. M28529 Logic Diagram (UTOPIA-to-Serial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 1-8. M28529 UTOPIA-to-Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 1-9. M28529 Logic Diagram (UTOPIA-to-UTOPIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 1-10. IMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 1-11. Non-IMA Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 1-12. Source Loopback Diagram (For simplicity the diagram shows the TC Block Only.) . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 1-13. Far-End Line Loopback (This only shows the TC Block.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 1-14. IMA Line Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 1-15. IMA System Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 1-16. M28529 Clock Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 1-17. Typical T1/E1 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Figure 1-18. Serial DSL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 1-19. T1/E1 Configurations (UTOPIA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 1-20. DSL Configurations (UTOPIA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 1-21. T1/E1 using Internal Serial ports; IMA_SysClk equals 24x line rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 1-22. T1/E1 using Internal Serial ports; IMA_RefClk equals line rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 1-23. DSL—UTOPIA-to-UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 1-24. ATM Layer UTOPIA Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 1-25. M28529 Multiple UTOPIA Control Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 1-26. Details of the TC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 1-27. Cell Delineation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 1-28. Header Error Check Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 1-29. CN8370 Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Figure 1-30. CN8370 Interface - T1 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 1-31. CN8370 Interface - E1 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Figure 1-32. Fractional T1 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
®
28529-DSH-001-K
Mindspeed Technologies
ix
Mindspeed Proprietary and Confidential
List of Figures
Figure 1-33. Fractional E1 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Figure 1-34. DSL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Figure 1-35. General Purpose Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Figure 1-36. Interfacing Interleaved Highway to CX2839x (Frame Sync Provided by CX2389x) . . . . . . . . . . . . . . . . . . . . . . .101
Figure 1-37. Interfacing Interleaved Highway to CX2839x (Frame Sync Externally Provided) . . . . . . . . . . . . . . . . . . . . . . . . .102
Figure 1-38. Combined Datastreams on the Interleaved Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Figure 1-39. Full T1 Interleaved Highway Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Figure 1-40. Full E1 Interleaved Highway Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Figure 1-41. Interleaved Highway Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Figure 1-42. Interrupt Indication Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Figure 1-43. Interrupt Indication Diagram (TC Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Figure 3-1. Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Figure 3-2. Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Figure 3-3. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Figure 3-4. Microprocessor Timing —Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Figure 3-5. Microprocessor Timing —Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Figure 3-6. Microprocessor Timing —Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Figure 3-7. Microprocessor Timing —Synchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Figure 3-8. PHY-side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 0, TxDatShft = 0) . . . . . . . . . . . . . . . . . . . . . . .254
Figure 3-9. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 1, TxDatShft = 0) . . . . . . . . . . . . . . . . . . . . . . .254
Figure 3-10. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 0, TxDatShft = 1) . . . . . . . . . . . . . . . . . . . . . . .255
Figure 3-11. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 1, TxDatShft = 1) . . . . . . . . . . . . . . . . . . . . . . .255
Figure 3-12. PHY-side Serial T1/E1/DSL Mode Receive Timing (Positive Clock Edge Timing- RxClkPol = 0) . . . . . . . . . . . . .256
Figure 3-13. PHY-side Serial T1/E1/DSL Mode Receive Timing (Negative Clock Edge Timing- RxClkPol = 1) . . . . . . . . . . . . .256
Figure 3-14. Fractional T1/E1 Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Figure 3-15. Fractional T1/E1 Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Figure 3-16. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 0, IHTxDatShftx = 0)) . . . . . . . . . . . . . . .259
Figure 3-17. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 1, IHTxDatShftx = 0) . . . . . . . . . . . . . . .259
Figure 3-18. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 0, IHTxDatShftx = 1) . . . . . . . . . . . . . . .260
Figure 3-19. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 1, IHTxDatShftx = 1) . . . . . . . . . . . . . . .260
Figure 3-20. PHY-side Interleaved Highway Mode Receive Timing (Positive Edge - IHRxClkPolx = 0) . . . . . . . . . . . . . . . . . .261
Figure 3-21. PHY-side Interleaved Highway Mode Receive Timing (Negative Edge - IHRxClkPolx = 1) . . . . . . . . . . . . . . . . . .261
Figure 3-22. PHY-side UTOPIA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
Figure 3-23. PHY-side UTOPIA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
Figure 3-24. ATM-side UTOPIA Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264
Figure 3-25. ATM-side UTOPIA Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Figure 3-26. External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267
Figure 3-27. JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
Figure 3-28. One-second Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Figure 3-29. M28525/9 Mechanical Drawing (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
®
28529-DSH-001-K
Mindspeed Technologies
x
Mindspeed Proprietary and Confidential
List of Figures
Figure 3-30. M28525/9 Mechanical Drawing (Top and Side Views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271
Figure 3-31. M28529 Pinout Diagram, UTOPIA-to-Serial (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
Figure 3-32. M28525 Pinout Diagram Utopia-to-Serial (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
Figure 3-33. M28525/9 Pinout Diagram UTOPIA-to-UTOPIA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
®
28529-DSH-001-K
Mindspeed Technologies
xi
Mindspeed Proprietary and Confidential
List of Tables
Table 1-1. IMA Overhead Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1-2. IMA Overhead Filler Cell Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 1-3. Link States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 1-4. Memory Requirements for Differential Delay (in bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 1-5. Software Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 1-6. Group State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 1-7. Available Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 1-8. M28529 UTOPIA-to-Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 1-9. M28529 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 1-10. UTOPIA-to-UTOPIA Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 1-11. M2852x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 1-12. Serial Stream Muxing into Interleaved Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 1-13. M28529 Interleaved Highway Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 1-14. Interleaved Highway Port 0 - 3 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 1-15. Interleaved Highway Port 4 - 7 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 1-16. No Connects Per Interleaved Highway Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 1-17. Cell Delineation Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 1-18. Reference Clock Configurations / Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 1-19. IMA Block Clock Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 1-20. Link Rate Resolution for Variable Rate Applications (direct serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 1-21. Link Rate Resolution for Variable Rate Applications (internal bit rate generator) . . . . . . . . . . . . . . . . . . . . . . . . . .73
Table 1-22. Maximum Aggregate Bandwidth Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 1-23. IMA Serial Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Table 1-24. IMA Reference Clock Summary Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 1-25. Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 1-26. Control Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 1-27. Cell Screening—Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table 1-28. Cell Screening—Accept/Reject Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table 2-1. Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 2-2. Device Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 2-3. Port Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 2-4. Cell Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
®
28529-DSH-001-K
Mindspeed Technologies
xi
Mindspeed Proprietary and Confidential
List of Tables
Table 2-5. Cell Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 2-6. UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 2-7. Status and Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 2-8. Status and Interrupt Registers (Offset Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 2-9. Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 2-10. IMA Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 3-1. Absolute Maximum Ratings (General) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Table 3-2. Absolute Maximum Ratings (M28525/M28529) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
Table 3-3. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Table 3-4. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Table 3-5. Power Characteristics (M28529) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Table 3-6. Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Table 3-7. Microprocessor Timing Parameters - Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Table 3-8. Microprocessor Timing Parameters - Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252
Table 3-9. Microprocessor Timing Parameters - Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253
Table 3-10. Microprocessor Timing Parameters - Synchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254
Table 3-11. PHY-side Serial T1/E1/DSL Mode Transmit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
Table 3-12. PHY-side Serial T1/E1/DSL Mode Receive Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
Table 3-13. Fractional T1/E1 Transmit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Table 3-14. Fractional T1/E1 Receive Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Table 3-15. PHY-side Interleaved Highway Mode Transmit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
Table 3-16. PHY-side Interleaved Highway Mode Receive Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
Table 3-17. PHY-side UTOPIA Transmit Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262
Table 3-18. PHY-side UTOPIA Receive Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
Table 3-19. ATM-side UTOPIA Transmit Timing Parameters (IMA Enabled - 16 Bit Mode) . . . . . . . . . . . . . . . . . . . . . . . . . .264
Table 3-20. ATM-side UTOPIA Transmit Timing Parameters (IMA Bypassed - 8/16 Bit Mode, IMA
Enabled - 8 Bit Mode) 265
Table 3-21. ATM-side UTOPIA Receive Timing Parameters (IMA Enabled - 16 Bit Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .266
Table 3-22. ATM-side UTOPIA Receive Timing Parameters (IMA Bypassed - 8/16 Bit Mode, IMA
Enabled - 8 Bit Mode) 266
Table 3-23. External Memory Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
Table 3-24. JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Table 3-25. One Second Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
Table 4-1. Basic IMA Protocol (BIP) Definition Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
Table 4-2. QoS Requirements Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Table 4-3. CTC and ITC Operation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280
Table 4-4. IMA Data Cell (IDC) Rate Implementation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Table 4-5. Link Differential Delay (LDD) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Table 4-6. IMA Interface Operation (IIO) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Table 4-7. IMA Frame Synchronization (IFS) Mechanism Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
®
28529-DSH-001-K
Mindspeed Technologies
xii
Mindspeed Proprietary and Confidential
List of Tables
Table 4-8. IMA Interface OAM Operation Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
Table 4-9. Test Pattern Procedure (TPP) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
Table 4-10. IMA Interaction with Plane Management Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Table 4-11. Management Information Base (MIB) Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
®
28529-DSH-001-K
Mindspeed Technologies
xiii
Mindspeed Proprietary and Confidential
1.0 Functional Description
1.1
Overview
1.1.1
Introduction to IMA
This chapter provides a basic introduction to IMA. It will introduce common terminology, the IMA frame format and
IMA Cell structure. It will also address one of the challenges of IMA: differential delay between links. For detailed
coverage of these topics the reader should refer to the ATM forum's standard for IMA.
The M2852x is composed of the following major functional blocks as shown in Figure 1-1.
Figure 1-1. M28525/9 Block Diagram Example
E
xte rn a l M e m o ry
In te rfa c e
M 2 8 5 2 9
T C B lo c k
C e ll
p ro c e s s o r
L in e in t e rf a c e
0
C e ll
p r o c e s s o r
L in e in t e rf a c e
1
I M A
B lo c k
I n t e rn a l
5 1 2 K x 8
S R A M
0
1
e
x
tm
e m s e l p in
Di if f e re n t ia l D e la y
m
e m o ry in t e r f a c e
R x B lo c k a n d
P
a s s t h r o u g h
C e ll
L in e in t e r f a c e 3 0
L in e in t e r f a c e 3 1
p r o c e s s o r
I M A
E n g in e
C e ll
p r o c e s s o r
T
x
B lo c k a n d
P
a s s t h r o u g h
TC
C o u n te r s
T C S ta tu s
R e g is te r s
T C C o n tr o l
R e g is te r s
O
n e S e c
M ic r o
I n t e rf a c e
M
ic r o
IM
A
c lo c ks
J T A G
C lo c ks
* N o t e : T h e M 2 8 5 2 5 o n ly s u p p o r t s 1 6 T C P o r t s
1.1.2
Introduction To Inverse Multiplexing for ATM
Bandwidth, or the lack thereof, has always been the main challenge of telecommunications. While numerous
standards for high speed connections have been around for years, the cost of these higher speed connections
often prohibit users from deploying them. For example, users who need a data rate higher than the standard T1,
(1.544 Mbps) must pay for an entire DS3 (44 Mbps). Often the extra cost cannot be justified.
®
28529-DSH-001-K
Mindspeed Technologies
1
Mindspeed Proprietary and Confidential
Functional Description
IMA solves this problem by allowing users to purchase bandwidth in smaller increments and combine these smaller
'pipes' into one high speed connection. An example is given in Figure 1-2 where 3 T1 lines are combined into one
4.6 Mbps data link.
At first glance, the concept of IMA is deceptively simple: spread the ATM cells out evenly over the available
individual lines. However, many serious technical issues must be dealt with and a wide range of functions must be
supported. These include IMA framing, differential delay accommodation, link/group state machines, IMA clocking,
and maintenance. Several terms must be defined:
IMA Engine
Link
The logic that performs the actual IMA function. This sits between the ATM layer and the individual links (see
Figure 1-2). An IMA engine can control multiple independent groups.
Refers to an individual physical connection such as a T1 or DSL line. Each link has an individual UTOPIA address or
serial connection to the IMA engine.
Group
An IMA group is composed of links. A group appears as a single UTOPIA address to the ATM layer. Thus an IMA-4
group would have 4 individual links.
Group State Machine
The operation of the IMA group is governed by the Group State Machine (GSM), the Group Traffic State Machine
(GTSM), and the Link Addition and Slow Recovery (LASR) procedure. These three processes ensure reliable
transmission and reception of ATM layer cells across all links in the Active state. This includes the negotiation of
group parameters (i.e., symmetry and M values), the bringing up of the IMA group, and the graceful addition/
recovery and deletion of links to and from the group. For the M28529, this function is performed in the host software.
The software itself is available from Mindspeed.
Link State Machine
A Link State Machine (LSM) is defined for the transmit and receive directions of each IMA link. The IMA protocol is
defined to allow symmetric or asymmetric cell rate transfer over the IMA virtual link. It allows for smooth
introduction of each link in the group. It also allows graceful handling of error conditions and removal of a link. This
function is performed internally by the M28529.
Figure 1-2. IMA Overview
3 - T1 1.544 Mb/s
3
2
1
3
2
1
3
2
1
4.5 Mb/s
4.5 Mb/s
500027_053
1.1.2.1
IMA Framing
The IMA protocol employs a simple frame structure as shown in Figure 1-3. It consists of a single IMA overhead
cell (ICP) and M – 1 ATM layer cells, where M is the IMA frame length. Valid frame lengths are 32, 64, 128 (default),
or 256. This example shows a group composed of three links and an IMA frame length of 16. (An invalid frame
length of 16 is used for brevity, the default frame length is 128.)
®
28529-DSH-001-K
Mindspeed Technologies
2
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-3. IMA Frame; Length = 16; Number of links = 3
Incoming data from the ATM layer (which doesn't
know that the data is being split into frames)
ATM ATM
ATM
34
ATM ATM
ATM ATM ATM ATM
ATM ATM
ATM
x
...
36
35
33
32
5
4
3
2
1
0
This cell was in the
previous frame
This cell will be in
the next frame
Delay between the cells arrival at
the IMA device results in Filler
cells being inserted
Data output into an IMA frame
1 IMA frame
M = 16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ATM ATM ATM
31 28 25
ATM ATM ATM ATM
21 19 17 14
ATM ATM
11
ATM
3
ICP
3
F
F
F
F
F
Link 0
Link 1
8
This link selected as the Timing Reference
Link, (TRL), thus first ICP starts at 0.
ATM ATM ATM ATM ATM ATM
34 32 29 26 23 22
ATM ATM ATM ICP ATM ATM ATM
18 15 13
ATM
0
F
F
3
9
6
4
Always at least 1 ICP cell per frame
ATM ATM ATM ATM
33 30 27 24
ATM ICP ATM
20 16
ATM ATM ATM ATM ATM ATM
12 10
F
F
F
Link 2
3
7
5
2
1
ATM payload;
cell x in the sequence
IMA control Protocol Cell
IFSN = n
ATM
x
ICP
n
F
Filler cell
500027_067
Since the ATM layer data rate is often less than the bandwidth available across the links in the IMA group, the IMA
engine generates IMA Filler cells when no ATM layer cells are available. (The IMA Filler cells perform the same
basic function as Idle cells in a non-IMA ATM system and are discarded by the IMA receiver.)
The IMA frame rate is intentionally set slightly below the available payload bandwidth of the IMA link. To allow for
timing differences between the links in a group, the IMA standard requires that the system insert an extra ICP cell
every 2049 cells. This cell is called the SICP cell and is inserted immediately after the normal ICP cell for that link
and results in the frame being M+1 cells long. Information in the ICP cell payload signals the insertion of these cells
so that the receiver does not lose framing and can identify and discard these cells. For further details consult the
IMA standard.
One link in each group is designated the Timing Reference Link (TRL). All timing issues for the group are relative to
this link.
®
28529-DSH-001-K
Mindspeed Technologies
3
Mindspeed Proprietary and Confidential
Functional Description
1.1.2.2
IMA Control Protocol Cells
The IMA Standard defines three types of IMA cells: IMA Control Protocol (ICP) cells, Filler cells, and ATM layer
cells. ICP cells are the IMA overhead cells that carry the IMA control and status information between both ends of
the link, assuring synchronization and configuration. The purpose of filler cells is rate decoupling; they are inserted
into the IMA stream if no ATM layer cells are available.
Standard ATM 'idle' cells are never transmitted over an IMA link.
NOTE:
ATM layer cells are the data “payload” carried by the IMA group. These are the standard ATM cells being sent from
the ATM layer.
Table 1-1 describes the IMA Overhead Cell definition, and Table 1-2 lists format of the IMA Overhead Stuff Cell.
Table 1-1.
Octet
IMA Overhead Cell Definition (1 of 3)
Field
Description
1-5
ATM Cell Header
OAM cell type: Octet 1 = 0000 0000
Octet 2 = 0000 0000
Octet 3 = 0000 0000
Octet 4 = 0000 1011
Octet 5 = 0110 0100 (valid HEC with Coset)
OAM type field:
6
7
IMA Label
Cell ID
0000 0001—IMA Version 1.0
0000 0011—IMA Version 1.1
Bit 7 Set to 1 for ICP cell
Bits 6–5 Unused and set to 0
Link ID
Bits 4–0 Logical ID for physical link range (0... 31)
8
9
Frame Sequence Number
ICP Cell Offset
Cyclical counter: 0 to 255
Indicates position of ICP cell within the IMA frame of size M cells. Range: (0... M – 1)
Stuff Indication code for link on which ICP cell is being sent
10
Link Stuff Indication (LSI)
Bits 7–3 Unused and set to 0
Bits 2–0 111: no imminent stuff (default)
100: stuff event in 4 ICP cell locations (optional)
011: stuff event in 3 ICP cell locations (optional)
010: stuff event in 2 ICP cell locations (optional)
001: stuff event at the next ICP cell location (mandatory)
000: This is one out of the 2 ICP cells comprising the stuff event (mandatory)
11
12
Status / Control Change
Indication (SCCI)
Status and Control Change Indication: 0 to 255 and cycling (count to be incremented every time there is
a change to octets 12 to 49).
IMA ID
Logical IMA group ID
®
28529-DSH-001-K
Mindspeed Technologies
4
Mindspeed Proprietary and Confidential
Functional Description
Table 1-1.
Octet
IMA Overhead Cell Definition (2 of 3)
Field
Description
13
Group Status & Control
Bits 7–4 Group Status
0000: Start-up
0001: Start-up-Ack
0010: Config-Aborted: Unsupported M
0011: Config-Aborted: Incompatible Symmetry
0100: Config-Aborted: Unsupported IMA version
01xx: Available for other Config Abort reasons
1000: Insufficient-Links
1001: Blocked
1010: Operational
Bits 3–2 Others: Reserved
Symmetry of Group
00: Symmetrical configuration and operation
01: Symmetrical configuration and asymmetric operation
10: Asymmetrical configuration and operation
Bits 1–0 11: Reserved
IMA Frame Length
00: M=32
01: M=64
10: M=128
11: M=256
14
15
Transmit Timing Information Transmit Clock Information
Bits 7–6 Unused, set to 00
Bit 5 Transmit Clock Mode (0: ITC mode, 1: CTC mode)
Bits 4–0 Tx LID of the timing reference link (TRL)—Range: 0 to 31
Test Pattern Command
Tx Test Control
Bits 7–6 Unused, set to 00
Bit 5 Test Link Command (0: inactive, 1: active)
Bits 4–0 Tx LID of test link—Range: 0 to 31
16
17
Tx Test Pattern
Rx Test Pattern
Value from 0 to 255
Value from 0 to 255
®
28529-DSH-001-K
Mindspeed Technologies
5
Mindspeed Proprietary and Confidential
Functional Description
Table 1-1.
Octet
IMA Overhead Cell Definition (3 of 3)
Field
Description
18
Link 0 Information
Link State Machine and Defect Information for link with LID = 0
Bits 7–5 Transmit LSM state
Bits 4–2 Receive LSM state
Bits 1–0 Rx Link defect status
00: no errors
01: Physical Link defect (e.g., LOS, OOF/LOF, LCD)
10: LIF
11: LODS
19–49
50
Link 1–31 Info
Unused
Status and control of link with LID in the range 1–31
Set to 0x6A (as defined in ITU-T I.432)
51
End-to-end channel
CRC Error Control
Proprietary channel (set to 0 if unused). The M2852x does not support this octet.
52–53
Bits 15-10 Reserved field for future use—default value is all zeros
Bits 9-0 CRC-10 as defined in ITU-T Recommendation I.610
Table 1-2.
Octet
IMA Overhead Filler Cell Format
Field
Description
1–5
ATM Cell Header
OAM cell type: Octet 1 = 0000 0000
Octet 2 = 0000 0000
Octet 3 = 0000 0000
Octet 4 = 0000 1011
Octet 5 = 0110 0100 (valid HEC)
6
7
IMA Label
OAM type field:
0000 0001—IMA Version 1.0
0000 0011—IMA Version 1.1
Cell ID
Link ID
Bit 7 Set to 0 for IMA Filler cell
Bits 6–0 Unused and set to 0
8–51
Unused
Set to 0x6A (as defined in ITU-T I.432)
52–53
CRC Error Control
Bits 15-10 Reserved field for future use—default value is all zeros
Bits 9-0 CRC-10 as defined in ITU-T Recommendation I.610
®
28529-DSH-001-K
Mindspeed Technologies
6
Mindspeed Proprietary and Confidential
Functional Description
1.1.2.3
Link State Machine
Management of the individual links is performed by two state machines: the Transmit Link State Machine and the
Receive Link State Machine. Four possible states are available for each link as shown in Table 1-3.
Table 1-3.
Link States
State
Description
Not in Group
Unusable
Usable
this link has not been added to an IMA group
the link is in a group but cannot be used due to line fault etc.
assigned to a group and ready but is waiting for the other end
fully configured and carrying traffic
Active
The Link State Machines are responsible for handling the transition from one state to another. All functions of the
LSM's are performed internally by the M2852x. Further details are covered in Section 1.12 and in the ATM
standard on IMA.
1.1.2.4
Transmit Clocks
The IMA standard provides two options regarding the transmit clocks. The default mode, and most common IMA
application, is Common Transmit Clock (CTC) mode, where all links in the IMA group are generated from the same
source. Thus they are in phase and have the same rate of SICP insertion (1/2049) as the designated TRL link.
The Independent Transmit Clock (ITC) mode is available as an optional feature of the IMA protocol (of course, it is
fully supported by the M2852x family). In this mode, each link runs off of an independent clock at the nominal line
rate. To support these asynchronous links within an IMA group, the rate of SICP insertion is allowed to vary on the
non-TRL links.
The IMA group frame rate for each IMA group must be re-created at the receive end. This regeneration is
necessary to implement the IMA Data Cell Clock and smoothing buffer functionality of the IMA protocol. One
method for generating the Receive IMA group frame rate is to use the line or payload clock recovered from the
receive TRL physical port interface. This clock is a frequency locked reference of the far-end Transmit IMA group
frame rate. Equivalently, the rate of cell transfers (i.e., payload bandwidth) from the TRL link can be used as the
reference for generating the Receive IMA group frame rate. Both methods are available for use by the M2852x
device, depending on the application and configuration.
1.1.2.5
Differential Delay
When dealing with multiple facilities, there is no guarantee that the individual links within a group will take the same
physical path between the terminating equipment. This variation is referred to as Differential Delay. The ATM Forum
specification requires an IMA implementation to absorb a minimum of 25 ms of differential delay between the links.
Each link requires 8 K of memory for every 27.5 ms of delay (at E1; 8 K provides for 34.375 ms at T1 rates). The
M28525/9 provides 512K bytes of on-board memory for the buffering necessary to re-align the links within an IMA
group. This is sufficient to support the 50 ms of delay (at E1 rates) for 32 IMA ports. In addition, an external
memory bus allows this to be expanded to 2 MB, which supports up to 200 ms of delay. Table 1-4 shows the
memory requirements for differential delay.
®
28529-DSH-001-K
Mindspeed Technologies
7
Mindspeed Proprietary and Confidential
Functional Description
Table 1-4.
Memory Requirements for Differential Delay (in bytes)
E1
T1
27.5 ms
55 ms
110 ms
220 ms
275 ms
Number of links
34.375 ms
68.75 ms
137.5 ms
1
2
8 K
16 K
32 K
64 K
128 K
256 K
16 K
32 K
32 K
64 K
64 K
128 K
256 K
512 K
1024 K
2048 K
4
64 K
128 K
256 K
512 K
1024 K
8
128 K
256 K
512 K
16
32
General Note: Shaded areas can be supported by internal memory. Internal memory is disabled when the external bus is used.
The magnitude of the differential delay can be quite large when dealing with T1/E1 links; whereas DSL links
generally follow the same path and have nearly identical delays.
1.1.3
Software Overview
Mindspeed’s software supports both TC and IMA; however, this section only describes IMA
software support.
NOTE:
All IMA devices require a software driver to interface to the system host. Since the GSM's primary function only
occurs during startup; the M2852x family relies on the IMA driver to perform these functions. This allows for
maximum flexibility; simpler device design and requires very little overhead from the host.
Mindspeed provides a complete IMA and device driver in ANSI C to simplify system development. This software
has been field tested and can be ported to virtually all systems. This is also covered in chapter 3, the IMA engine
and the M28529TAP IMA Software Programming Guide.
Table 1-5 summarizes the API of the M28525/9 software. All functions require a pointer to the structure IMA_DEV.
The additional parameters for each function are listed in the following sections. The functions named IMA_xxxx()
are function calls to the M28525/9. The functions named USER_xxxx() are user defined functions called by the
M28525/9. The pointers to the user defined functions are passed to M28525/9 during initialization as fields in the
DRV initialization structure or after initialization using the IMA_subsys_set() function.
Table 1-5.
Class
Software Function Summary (1 of 2)
Function
Short Description
Initialization
IMA_init_default ()
IMA_init ()
Initializes the fields of the M28525/9 initialization structure to default values.
This function initializes the IMA software driver and the IMA device.
Interrupts
IMA_tick ()
This function polls the error counters and failure monitoring registers of the IMA device
and must be called at a regular periodic interval.
IMA_intr ()
This function should be called when the device interrupt line has been asserted.
®
28529-DSH-001-K
Mindspeed Technologies
8
Mindspeed Proprietary and Confidential
Functional Description
Table 1-5.
Class
Software Function Summary (2 of 2)
Function
Short Description
IMA Subsystem
IMA_read ()
This function provides a direct interface to read the registers within the IMA device.
This function provides a direct interface to write the registers within the IMA device.
This function provides a direct interface to set the M28525/9 Subsystem parameters.
IMA_write ()
IMA_subsys_set ()
IMA_subsys_get ()
This function provides a direct interface to retrieve the M28525/9 Subsystem
parameters.
IMA_test ()
This function executes a specified IMA diagnostic test.
IMA_facility_set()
IMA_facility_get()
IMA_group_set ()
IMA_group_get ()
IMA_group_FM_status ()
This function provides a direct interface to set the M28525/9 Facility parameters.
This function provides a direct interface to retrieve the M28525/9 Facility parameters.
This function provides a direct interface to set the M28525/9 Group parameters.
This function provides a direct interface to retrieve the M28525/9 Group parameters.
Group
Interface
This function retrieves the current state of the parameters monitored by the Facility
Monitoring subsystem for the IMA Group layer.
IMA_group_PM_preset ()
IMA_group_PM_status ()
This function allows the user to initialize the IMA Group PM statistics to arbitrary values
for the current interval of the 15 minute accumulation period.
This function retrieves the states (from either the current or previous 15 minute
accumulation interval) of the IMA Group Performance Monitoring parameters.
Link
Interface
IMA_link_set ()
This function provides a direct interface to set the M28525/9 Link parameters.
This function provides a direct interface to retrieve the M28525/9 Link parameters.
IMA_link_get ()
IMA_link_FM_status ()
This function retrieves the current state of the parameters monitored by the Facility
Monitoring subsystem for the IMA Link layer.
IMA_link_PM_preset ()
IMA_link_PM_status ()
IMA_phy_link_set ()
This function allows the user to initialize the IMA Link PM statistics to arbitrary values for
the current interval of the 15 minute accumulation period.
This function retrieves the states (from either the current or previous 15 minute
accumulation interval) of the IMA Link Performance Monitoring parameters.
PHY
Interface
This function provides a direct interface to set the M28525/9 Link parameters, per
facility.
IMA_phy_link_get ()
This function provides a direct interface to retrieve the M28525/9 Link parameters, per
facility.
IMA_phy_link_FM_status ()
IMA_phy_link_PM_preset ()
IMA_phy_link_PM_status ()
This function retrieves the current state of the parameters monitored by the Failure
Monitoring subsystem for the IMA Link layer, per facility.
This function allows the user to initialize the IMA Group PM statistics to arbitrary values
for the current interval of the 15 minute accumulation period.
This function retrieves the states (from either the current or previous 15 minute
accumulation interval) of the IMA Link Performance Monitoring parameters, per facility.
Monitor
IMA_mon()
This function is called to control the M28525/9 debugger.
User Defined
*USER_intr_disable()
This is an application defined function that disables interrupts from the IMA hardware
device.
*USER_intr_enable()
* USER_event ()
This is an application defined function that enables interrupts from the IMA hardware
device.
This is an application defined function that accepts asynchronous event messages from
the M28525/9 software.
®
28529-DSH-001-K
Mindspeed Technologies
9
Mindspeed Proprietary and Confidential
Functional Description
1.1.3.1
Software Subsystems
The internal architecture of the M28529TAP software is composed of five logical subsystems: Configuration (CF),
Diagnostics (DG), IMA Group (GRP), Failure Monitoring (FM), and Performance Monitoring (PM).
The following sections summarize the interfaces of the M28525/9 IMA software device driver. It is important to point
out that the M28525/9 products can be configured to run in different operating environments. As such, not all the
interfaces described below are used in a given application.
1.1.3.2
Configuration (CF)
The CF subsystem is responsible for setting the operating parameters of the IMA device that are associated with
the IMA Link and IMA Group termination entities. Additionally, some of the application specific configurations of the
device are set by this subsystem. The default value for each parameter is used to initialize and set the operating
mode of the device.
1.1.3.3
Diagnostics (DG)
The DG subsystem performs control and testing functions on the IMA device and its environment. One role of the
DG subsystem is configuration, very similar to the CF subsystem but with different parameters. Similar in function
to the Configuration subsystem, the default value for each DG parameter is used to initialize and set the operating
mode of the device. The DG subsystem parameters are typically exercised only during test or maintenance
conditions, and may affect ATM transmission through the device.
1.1.3.4
Failure Monitoring (FM)
The Failure Monitoring (FM) subroutine is responsible for monitoring the IMA links and groups for defects and
anomalies and integrating the defects into failures. The primary role performed by this subsystem is alarm
integration. The M28529TAP program is aware of changes in the state of the underlying defects and anomalies
through periodic polling. The user has control over which Failure indicators are monitored and the length of both
the activation and decay times.
Upon initializing the M28529TAP, the Failure indications required by the ATM MIB are enabled and the activation
and decay times are set at 2.5 and 10 seconds, respectively.
1.1.3.5
Performance Monitoring (PM)
This is the set of functions and capabilities necessary for a Network Element (NE) to gather, store, and report
performance data associated with its monitored digital transmission entities. In contrast with alarm/status
indications, performance parameters are quantitative, not binary, in nature. These performance parameters are
gathered over programmable, predetermined accumulation periods. The M28529TAP calculates these statistics
over 15 minute intervals. The PM data is available to the application grouped in a structure encompassing one of
the two accumulation sets: the current 15 minute interval or the previous 15 minute interval. The PM subsystem
uses the raw anomaly and defect information obtained by the FM subsystem to calculate its performance statistics.
Upon initialization, the PM subsystem is basically disabled: none of the monitored statistics are calculated.
1.1.3.6
Group State Machine
Overall management of each Group is the responsibility of the Group State Machine. This actually involves three
interrelated processes: the Group State Machine (GSM), the Group Traffic State Machine (GTSM), and the Link
Addition and Slow Recovery (LASR) procedure. These three processes are used to ensure reliable transmission
and reception of ATM layer cells across all links in the Active state. This includes the negotiation of group
parameters (i.e., symmetry and M values), the bringing up of the IMA group, and the graceful addition/recovery and
®
28529-DSH-001-K
Mindspeed Technologies
10
Mindspeed Proprietary and Confidential
Functional Description
deletion of links to and from the group. The seven possible states are shown in Table 1-6. Again, this will be
covered in more detail in Chapter 1.12 and in the ATM standard on IMA.
Table 1-6.
State
Group State Machine
Description
Not Configured
Start up
No groups configured
Waiting to establish communications with the other end
Start up Ack
Config Aborted
Insufficient links
Blocked
Start Up acknowledge; has recognized the far end and waiting to enter the Insufficient links state
Results when the Far End doesn’t comply with the requested configuration parameters
Both ends have accepted the group parameters and are waiting for the LSM to provide active links
The host controller has inhibited the group (probably for maintenance reasons)
Fully operational and able to pass data
Operational
1.2
Features
1.2.1
IMA Features
•
Complete IMA solution in a single package
•
•
16 port, M28525
32 port, M28529
•
•
•
•
•
•
Field proven design
All software available
Supports variable link data rates (64K–8.192 Mb/s)
Supports fractional T1/E1 per AF-PHY-0130.00
512 K Internal memory
Supports 50 ms (beyond the IMA standard requirements for 25 ms) differential delay with 512K Internal
memory
•
•
Connects directly to the Mindspeed SARs for inexpensive CPE solutions
M28525 supports 16 facilities
•
Up to 16 independent groups:
Each group can have up to 16 links.
•
M28529 supports 32 facilities
•
Up to 32 independent groups:
Each group can have up to 32 links.
•
•
Memory expandable to 2 M bytes via external bus
Supports IMA versions 1.0 and 1.1
®
28529-DSH-001-K
Mindspeed Technologies
11
Mindspeed Proprietary and Confidential
Functional Description
1.2.2
Diagnostics/Loopbacks
•
•
•
•
•
•
Source Loopback
Far End Line Loopback
IMA Line Loopback
IMA System Loopback
ICP Cell Access
IEEE 1149.1 JTAG Interface
1.2.3
Cell Delineation Section
•
Supports ATM cell interface for:
•
•
Circuit-based physical layer
Cell-based physical layer
•
•
•
Performs single-bit HEC correction and single- or multiple-bit detection
Inserts headers and generates HEC
Direct connection to external Mindspeed components for:
•
•
•
T1/E1
xDSL
General purpose mode
•
Byte-level or bit-level cell delineation
1.2.4
Control and Status
1.2.4.1
Microprocessor Interface
•
•
•
•
•
•
Asynchronous SRAM-like interface mode
8-bit data bus
Open-drain interrupt output
Open-drain ready output
Up to 66 MHz operation
All control registers are read/write
1.2.4.2
ATM Interface
•
ATM-side UTOPIA Interface:
•
•
•
•
8/16-bit UTOPIA Level 2 Slave
Up to 50 MHz operation
Support for dual Clav and Enable signals
Supports 32 ATM addresses
®
28529-DSH-001-K
Mindspeed Technologies
12
Mindspeed Proprietary and Confidential
Functional Description
1.2.4.3
PHY Interfaces
•
PHY-side UTOPIA Interface:
•
•
8/16-bit UTOPIA Level 2 Master
Supports 32 ports via dual CLAV and Enable lines
•
•
•
Serial Interface
Interleaved Highway
Up to 33 MHz operation
1.2.4.4
Counters/Status Register Section
•
•
•
•
Summary interrupt indications
Configuration of interrupt enables
One-second counter latching
Counters for:
•
•
•
•
•
•
•
LOCD events
Corrected HEC errors
Uncorrected HEC errors
Transmitted cells
Matching received cells
Non-matching received cells
Idle cell receive
1.3
General Description
The M2852x family of devices provides system designers with a complete integrated IMA solution for up to 32
ports. All devices include a Transmission Convergence block to perform cell delineation, 512 K internal RAM to
meet ATM forum requirements for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer
interface. Source code for all required software functions is available from Mindspeed. The M28529 supports 32
IMA groups with 1-32 links per group.
The TC block is capable of bit level cell delineation, which allows for direct connection DSL serial data streams
without a frame sync pulse. Individual ports can be operated in a 'pass thru' mode without the IMA overhead.
The M28529 provides direct connection to 32 serial/interleaved highway links or a PHY side UTOPIA bus. In
addition, an external memory bus allows the differential delay memory to access up to 2 Mbytes of external
RAM.The M28529 supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001
®
28529-DSH-001-K
Mindspeed Technologies
13
Mindspeed Proprietary and Confidential
Functional Description
1.4
Applications
1.4.1
Overview
The M2852x is typically used with line framer devices like the CX28398 T1/E1 octal framer or the M28985
ZipWireMulti™ Octal G.shdsl Transceiver with Embedded Microprocessor. Figure 1-4 illustrates a typical application.
Figure 1-4. M2852x Connected to a CX28398 Transceiver
C X28380
Q uad LIU
M 28259
C X28398
LIU
LIU
LIU
LIU
1
2
3
4
P ort
P ort
P ort
P ort
P ort
0
1
2
3
4
TX1
R X1
TX2
R X2
TX3
R X3
TX4
R X4
O ctal T1/E 1
Fram er
C X28380
Q uad LIU
LIU
LIU
LIU
LIU
5
6
7
8
P ort
P ort
P ort
5
6
7
TX5
R X5
TX6
R X6
TX7
R X7
TX8
R X8
C X28398
C X28380
Q uad LIU
LIU
8
P ort
P ort
8
9
TX9
R X9
LIU 10
LIU 11
LIU 12
TX10
R X10
TX11
R X11
P ort 10
P ort 11
P ort 12
TX12
R X12
O ctal T1/E 1
Fram er
C X28380
Q uad LIU
LIU 13
LIU 14
LIU 15
LIU 16
P ort 13
P ort 14
P ort 15
TX13
R X13
U TO P IA
Level
B us
2
TX14
R X14
TX15
R X15
TX16
R X16
A TM S witch or
S A R
IM A
P rocessor
CX28380
Q uad LIU
C X28398
LIU 17
LIU 18
LIU 19
LIU 20
P ort 16
P ort 17
P ort 18
P ort 19
P ort 20
TX17
RX17
TX18
RX18
TX19
RX19
TX20
RX20
O ctal T1/E 1
Fram er
CX28380
Q uad LIU
LIU 21
LIU 22
LIU 23
LIU 24
P ort 21
P ort 22
P ort 23
TX21
RX21
TX22
RX22
TX23
RX23
TX24
RX24
C X28398
CX28380
Q uad LIU
LIU 25
LIU 26
LIU 27
LIU 28
P ort 24
P ort 25
P ort 26
P ort 27
P ort 28
TX25
RX25
TX26
RX26
TX27
RX27
TX28
RX28
O ctal T1/E 1
Fram er
CX28380
Q uad LIU
LIU 29
P ort 29
P ort 30
P ort 31
TX29
RX29
LIU 30
LIU 31
LIU 32
TX30
RX30
TX31
RX31
TX32
RX32
M icroprocessor B us
®
28529-DSH-001-K
Mindspeed Technologies
14
Mindspeed Proprietary and Confidential
Functional Description
1.4.2
DSLAM
Digital Subscriber Line Access Multiplexers (DSLAM) and Broadband Loop Carriers (BLC) are being deployed to
provide broadband services to business and residential customers. Although DSL and T1/E1 services delivers
higher speeds than traditional dial-up connections, customers are increasingly finding the need for higher
bandwidth than is available through a single DSL or T1/E1 line. The IMA protocol helps bridge the gap between
lower cost xDSL solutions and higher cost lines such as T3. IMA allows customers to scale their bandwidth needs
in T1/E1 or xDSL link increments, so they do not have to pay for more than they can use.
Figure 1-5 shows a typical example of how IMA can be used to meet the evolving needs of customers. The DSLAM
can use the M28529 32-port IMA controller with the octal M28985 DSL modem chip for the customer access side.
The CX28225 4-port IMA can be used in the DSL CPE equipment to complete the solution for providing flexible
bandwidth scaling.
On the network side, DSLAMs generally need to backhaul customer traffic to the ATM backbone. This can be done
by bonding multiple T1s together using IMA. This line card is also shown in Figure 1-4. The M28529 can be used
once again with Mindspeed's CX28395 16-port framers and CX28380 quad LIUs. A similar line card is needed at
the ATM/Multiservice Switch.
Figure 1-5. M28529 in DSLAM applications
CPE
CO/Street Cabinet
DSLAM
CO
ATM Switch
nxT1/E1
links
Splitter-less ADSL
Modem (UADSL, G.Lite)
M28529
ATM
CX28395
Framer
LIU
CX28380
x8
IMA
Layer
M28529
IMA
Controller
ATM
Layer
Device
Controller
Device
CX28985
0
0
0
DSL
Utopia
Serial
Serial
Utopia
Utopia
DSLAM Uplink card or ATM Switch card
DSLAM Access line card
1.4.3
Wireless NodeB/RNC
Wireless Base Transceiver Stations (BTS) and NodeB equipment for 3G based networks have a need to send
customer's compressed voice/data from the base station to the Radio Network Controller (RNC). Many times, high
speed fiber links are not available where the equipment is deployed. By using IMA to bond multiple T1 or E1 links
together, the traffic can be backhauled effectively and efficiently.
Figure 1-6 illustrates the NodeB/RNC example. The NodeB can either use a CX28229 for 8-ports or the M28529
for 16 to 32-port applications. The CX28398 framer and CX28380 complete the line card. The RNC can aggregate
traffic from multiple base sites, so the M28529 can be used here. Again, the CX28395 16-port framer and CX8380
quad LIUs can be used to complete the line card solution.
®
28529-DSH-001-K
Mindspeed Technologies
15
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-6. M28529 in NodeB/RNC Application
NodeB
RNC
8xT1/E1
links
RF
Subsystem
M28529
ATM
Layer
IMA
CX28395
Framer
LIU
CX28380
x8
Device
r
Controller
LIU
ATM
CX28229
CX28398
Framer
Serial
Serial
32-port solution
Utopia
CX28380
0
IMA
Layer
x2
Controller
Device
Utopia
Serial
Serial
1.5
Pin Definitions
Two versions of Mindspeed's IMA solution are available: M28525 and the M28529. All use the same software
drivers and are basically pin compatible. Table 1-7 provides a quick comparison of the two devices.
Table 1-7.
Device
Available Parts
Internal memory
External memory
interface
UTOPIA addresses
(PHY side)
Serial ports
(1)
M28525
M28529
Footnote:
512 Kbytes
512 Kbytes
2 Mbyte
0–15, 31 (NULL)
16
32
(1)
(2)
2 Mbyte
0–31
(1) Internal memory is disabled when the external bus is used.
(2) Normally, 0x1F is the NULL address; however, the M28529 can be configured to treat it as a valid port address.
The following three configurations are available:
*
•
•
•
*
UTOPIA-to-Serial
UTOPIA-to-UTOPIA
UTOPIA-to-Interleaved Highway*
Note: Interleaved Highway can be mixed with serial mode on a per group of four channel basis. Interleaved
Highway mode is enabled by setting the EnIHx (x = 0 to 7) bit in the appropriate TCCTRLx (x = 0 to 7) register.
®
28529-DSH-001-K
Mindspeed Technologies
16
Mindspeed Proprietary and Confidential
Functional Description
1.5.1
Pin Diagram and Definitions (UTOPIA-to-Serial Configuration)
Figure 1-7 illustrates a pinout diagram for the M28529 when operating in UTOPIA-to-Serial mode. It is a single
CMOS integrated circuit packaged in a 484-pin PBGA. All unused input pins should be connected to ground or
power. Unused outputs and bi-directional pins should be left unconnected.
UTOPIA-to-Serial configuration is selected by tying the PhyIntFcSel pin high.
NOTE:
Figure 1-8 is a block diagram of an 32 link IMA solution using the device in the UTOPIA-to-serial mode to take
advantage of the internal serial ports. Cell Delineation is performed internally and the M2852x interfaces directly to
the framers. These framers could be T1/E1 or DSL. Further details can be found in the Mindspeed reference
design available online. Configuration information is shown in Table 1-8.
®
28529-DSH-001-K
Mindspeed Technologies
17
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-7. M28529 Logic Diagram (UTOPIA-to-Serial)
Reset I
Reset*
Reset
One Second
Interface
8kHzIn Clock I
8kHzin*
I/O One Second Input/Output
OneSecIO
I Transmit Clock
O Transmit Data
I/O Transmit DataMarker
SPRxClk[0]
SPRxData[0]
SPRxSync[0]
Receive Clock I
Receive Data I
Receive Data Marker I
SPTxClk[0]
SPTxData[0]
SPTxSync[0]
Line Interface
Port 0
Receive Clock I
Receive Data I
Receive Data Marker I
SPTxClk[31]
SPTxData[31]
SPTxSync[31]
I Transmit Clock
O Transmit Data
I/OTransmit Data Marker
SPRxClk[31]
SPRxData[31]
SPRxSync[31]
Line Interface
Port 31
Microprocessor
Interface
PHY Interface Select I
Sync/Async Mode Select I
Microprocessor Clock I
ChipSelect I
PhyIntFcSel(1)
MSyncMode
MicroClk
StatOut [1:0]
O Status Output
*
MCS
MicroInt*
MRdy
MicroData[7:0]
O Summary Interrupt
O Ready
I/O Microprocessor Data Bus
Address Strobe, Write Control I
Write/Read Read Control I
Address Bus I
MAS*, MWr
MW/R, MRd
MicroAddr[11:0]
*
JTAGInterface
*
Test Reset I
Test Clock I
Test Mode Select I
Test Data Input I
Test Enable I
TRST
TCK
TMS
TDI
TestEnable
TestMode
TDO
OTest Data Output
Test Mode I
atmUTxClAv[1:0]
atmUTxSOC
atmUTxPrty
atmUTxData[15:0]
OATMTransmit Cell Available
I ATM Transmit Start Of Cell
I ATM Transmit Parity
ATMUTOPIATransmit
Interface
ATMTransmit Clock I
ATMTransmit Enable I
ATM Transmit Address Bus I
atmUTxCLK
atmUTxENB[1:0]*
atmUTxAddr[4:0]
I ATMTransmit DataBus
OATMReceiveCell Available
O ATM Receive Start Of Cell
O ATM Receive Parity
atmURxClAv[1:0]
atmURxSOC
atmURxPrty
atmURxData[15:0]
ATM UTOPIA Receive
Interface
ATM Receive Clock I
ATMReceive Enable I
ATMReceive Address Bus I
atmURxCLK
atmURxENB[1:0]*
atmURxAddr[4:0]
O ATM Receive Data Bus
IMA Clocks
IMA_SysClk
IMA_RefClk
IMA System Clock I
IMA Reference Clock I
TxTRL[1:0]
O Transmit Reference Clock
External Memory
Interface
MemAddr[19:0]
O Memory Address Bus
O Chip Enable
OOutput Enable
O Write Enable
*
MemCtrl_CE
*
MemCtrl_OE
Memory Data Bus I/O
MemData[15:0]
ExtMemSel
*
MemCtrl_WE
MemCtrl_Clk
O SRAM Clock
External Memory Select I
O Address Enable
MemCtrl_ADSC*
(1)Pulled High
®
28529-DSH-001-K
Mindspeed Technologies
18
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-8. M28529 UTOPIA-to-Serial Mode
Extended Memory
M2852x
TC Block
cell processor
Line interface 0
Line interface 1
cell processor
IMA Block
Internal
512Kx8
SRAM
0
1
extmemsel pin
Differential Delay
memory interface
Rx Block and
Passthrough
cell processor Line interface 30
cell processor Line interface 31
IMA
Engine
Tx Block and
Passthrough
TC
Counters
TC Status
Registers
TC Control
Registers
OneSec
Micro
Clocks
IMA clocks
JTAG
Micro interface
500027_069
Table 1-8.
M28529 UTOPIA-to-Serial Mode
ATMMux [7,6]
(ATMINTFC, 0xF03)
PhyIntFcSel
(Pin AD24)
Description
01
High
IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode using 32 internal serial
ports.
General Note: External memory could be used if desired (M28525/9).
®
28529-DSH-001-K
Mindspeed Technologies
19
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (1 of 19)
Pin Label
Signal Name
No.
I/O
Description
StatOut[0]
Status Output
AB24
AD26
AE24
O
General purpose output pins under software control.
StatOut[1]
MSyncMode
Microprocessor
Synchronous/
Asynchronous Bus Mode
Select
I/PD
Selects synchronous or asynchronous bus mode, which
determines the functions of two pins, MW/R,MRd* (pin W4) and
MAS*,MWr* (pin Y2). A logic 1 selects the synchronous bus
mode. In this mode, these pins are defined as follows: MW/R (W4)
and MAS* (Y2). A logic 0 selects the asynchronous SRAM-type
bus mode. In this mode, the pins are defined as follows: MRd*
(W4) and MWr* (Y2).
Reset*
Device Reset
T4
I/PU
When asserted low, resets the device. The microprocessor clock
must be present before reset is released. If configuring the device
for pass-through operation, a minimum delay of 25 uS for
IMA_Sysclk of 66 MHz or 33us for IMA_Sysclk of 50 MHz is
required from the release of reset to the first access of the
IMA_RX_TRANS_TABLE register or the
IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
8kHzIn
8 kHz Input
AD25
AE26
I
A clock input used to derive OneSecIO. Typically operates at a
frequency of 8 kHz.
OneSecIO
One-Second Input/Output
I/O
Software can configure this pin as an output that equals the input
from the 8kHzIn divided by 8000. When configured as an input,
status registers and counters may be latched on the rising edge of
this input. See Bit 0 of the Genctrl register (0xF00).
MW/R, MRd*
Microprocessor Write/
Read
W4
I
When MSyncMode is asserted high, this pin is a read/write control
pin. In this mode, when MW/R is asserted high, a write access is
enabled and the MicroData[7:0] pin values will be written to the
memory location indicated by the MicroAddr[11:0] pins. Also,
when MW/R is asserted low in this mode, a read access is enabled
and the memory location indicated by the MicroAddr[11:0] pins is
read. Its value is placed on the MicroData[7:0] pins. Both read and
write accesses assume the device is chip selected (MCS* = 0), the
address is valid (MAS* = 0), and the device is not being reset
(Reset* = 1).
When MSyncMode is asserted low, this pin is a read control pin. In
this mode, when MRd* is asserted low, a read access is enabled
and the memory location indicated by the MicroAddr[11:0] pins is
read. Its value is placed on the MicroData[7:0] pins.
MCS*
Microprocessor Chip
Select
V1
I
When asserted low, the device is selected for read and write
accesses. When asserted high, the device will not respond to input
signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*.
Additionally, when MCS* is asserted high, the MicroData[7:0] pins
are in a high-impedance state but the MicroInt* pin remains
operational.
®
28529-DSH-001-K
Mindspeed Technologies
20
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (2 of 19)
Pin Label
Signal Name
No.
I/O
Description
MAS*, MWr*
Microprocessor Address
Strobe
Y2
I
When MSyncMode is asserted high, this pin is an address strobe
pin. When the MAS* pin is asserted low, it indicates a valid
address, MicroAddr[11:0]. This signal is used to qualify read and
write accesses.
When MSyncMode is asserted low, this pin is a write control pin.
When MWr* is asserted low, a write access is enabled and the
MicroData[7:0] pin values will be written to the memory location
indicated by the MicroAddr[11:0] pins. The write access assumes
the device is chip selected (MCS* = 0), a read access is not being
requested (MRd* = 1), and the device is not being reset (Reset* =
1).
MicroAddr[0]
MicroAddr[1]
MicroAddr[2]
MicroAddr[3]
MicroAddr[4]
MicroAddr[5]
MicroAddr[6]
MicroAddr[7]
MicroAddr[8]
MicroAddr[9]
MicroAddr[10]
MicroAddr[11]
MicroData[0]
MicroData[1]
MicroData[2]
MicroData[3]
MicroData[4]
MicroData[5]
MicroData[6]
MicroData[7]
MicroInt*
Microprocessor Address
Bus
U2
T3
I
These 12 bits are an address input for identifying the register to
access.
U1
T2
R4
T1
R3
R2
P4
R1
P3
P2
W3
V4
Y1
W2
V3
U4
W1
V2
AA1
Microprocessor Data Bus
I/O
A bi-directional data bus for reading and writing data to internal
registers.
Microprocessor Interrupt
Request
O
When active low, the device needs servicing. It remains active until
the pending interrupt is processed by the Interrupt Service
Routine. This pin is an open drain output for an OR logic
implementation. An external pull-up resistor is required for this
pin.
®
28529-DSH-001-K
Mindspeed Technologies
21
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (3 of 19)
Pin Label
Signal Name
No.
I/O
Description
MRdy
Microprocessor Ready
Y3
O
When active high, the current read or write transaction has been
completed. For a read transaction, the data is ready to be
transferred to the microprocessor. For a write transaction, the data
provided by the microprocessor has been written. This pin is an
open drain output for an external wired OR logic implementation.
An external pull-up resistor is required for this pin.
MicroClk
Microprocessor Clock
R5
I
In asynchronous mode the microprocessor clock signal input can
be clocked up to 66 MHz. In synchronous mode this pin can be
clocked up to 25 MHz. The device samples the microprocessor
interface pins (MCS*, MW/R, MAS*, MicroAddr[11:0], and
Microdata[7:0]) on the rising edge of this signal. The
microprocessor interface output pins (Microdata[7:0], MicroInt*)
are clocked on the rising edge of MicroClk. Note that this clock is
required for both synchronous and asynchronous operations. See
note in Section 1.15.1.
ExtMemSel
External Memory Enable
AC26
I/PD
When this pin is pulled high, it enables the external differential
delay SRAM bus.
MemData[0]
MemData[1]
MemData[2]
MemData[3]
MemData[4]
MemData[5]
MemData[6]
MemData[7]
MemData[8]
MemData[9]
MemData[10]
MemData[11]
MemData[12]
MemData[13]
MemData[14]
MemData[15]
Differential Delay Memory
Data Bus
M26
N24
N25
N26
P26
P25
P24
P23
R26
P22
R24
T26
R23
T25
T24
U26
I/O/PD Differential delay SRAM Data Bus. ATM cells extracted from the
Receive data stream are stored in the SRAM for the purpose of
differential delay compensation.
This bus is enabled by pulling the ExtMemSel pin high.
®
28529-DSH-001-K
Mindspeed Technologies
22
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (4 of 19)
Pin Label
Signal Name
No.
I/O
Description
MemAddr[0]
Differential Delay Memory
Address Bus
U25
T23
O
Receive SRAM Address Bus
This signal is enabled by pulling the ExtMemSel pin high.
MemAddr[1]
MemAddr[2]
MemAddr[3]
MemAddr[4]
MemAddr[5]
MemAddr[6]
MemAddr[7]
MemAddr[8]
MemAddr[9]
MemAddr[10]
MemAddr[11]
MemAddr[12]
MemAddr[13]
MemAddr[14]
MemAddr[15]
MemAddr[16]
MemAddr[17]
MemAddr[18]
MemAddr[19]
MemCtrl_CE*
V26
U24
V25
W26
U23
V24
W25
Y26
V23
W24
Y25
AA26
W23
Y24
AA25
Y23
AB26
AA24
N23
Chip Enable
O
O
O
O
O
Receive SRAM Device Select (active low) control signal.
This signal is enabled by pulling the ExtMemSel pin high.
Receive SRAM Device Output (active low) control signal.
MemCtrl_OE*
MemCtrl_WE*
MemCtrl_CLK
MemCtrl_ADSC*
Output Enable
Write Enable
SRAM Clock
Address Enable
M25
M24
AB25
L26
This signal is enabled by pulling the ExtMemSel pin high.
Receive SRAM write enable (active low) control signal.
This signal is enabled by pulling the ExtMemSel pin high.
Receive SRAM clock signal.
This signal is enabled by pulling the ExtMemSel pin high.
Receive SRAM address enable (active low) address strobe.
This signal is enabled by pulling the ExtMemSel pin high.
®
28529-DSH-001-K
Mindspeed Technologies
23
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (5 of 19)
Pin Label
Signal Name
No.
I/O
Description
TRST*
Test Reset
C5
I/PU
When asserted, the internal boundary-scan logic is reset. This pin
has a pull-up resistor.
TCK
Test Clock
A2
D5
I/PU
I/PU
Samples the value of TMS and TDI on its rising edge to control the
boundary scan operations.
TMS
Test Mode Select
Controls the boundary-scan Test Access Port (TAP) controller
operation. This pin has a pull-up resistor.
TDI
Test Data Input
C4
I/PU
O
The serial test data input. This pin has a pull-up resistor.
The serial test data output.
TDO
Test Data Output
C3
TestEnable[0]
TestEnable[1]
ScanEnable
Tristate
AF26
AC22
AD23
AE25
AD24
I/PD
Factory test use only, tie to VSS.
I/PD
I /PD
I/PU
Factory test use only, tie to VSS.
Tristate
When this pin is high, all outputs are tristate.
PhyIntFcSel
PHY Interface Select
If this pin is tied low, the PHY UTOPIA Interface mode is selected.
If this pin is tied high, the PHY Serial mode is selected (as shown
in this table).
IMA_SysClk
IMA_RefClk
IMA Subsystem Clock
E18
E16
I/PU
Most of the IMA logic circuits use this clock (or a derivative of it).
It can also be used as a T1/E1 reference clock. Refer to
Section 1.12.
IMA Subsystem Clock
I/PU
O
If Ref_Xclk is to be used as a reference clock, set the frequency as
shown in Section 1.12.
TxTRL[0]
TxTRL[1]
Transmit Reference Clock
A19
B19
Transmit Reference Clocks.
®
28529-DSH-001-K
Mindspeed Technologies
24
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (6 of 19)
Pin Label
Signal Name
No.
I/O
Description
SPRxSync[0]
Frame Sync Input
B17
A17
C16
B16
C11
B10
D11
A9
I/PD
When the PHY serial interface is enabled, this is the frame sync
input.
Note that ports 16-31 are no connects in the M28525.
SPRxSync[1]
SPRxSync[2]
SPRxSync[3]
SPRxSync[4]
SPRxSync[5]
SPRxSync[6]
SPRxSync[7]
SPRxSync[8]
SPRxSync[9]
SPRxSync[10]
SPRxSync[11]
SPRxSync[12]
SPRxSync[13]
SPRxSync[14]
SPRxSync[15]
SPRxSync[16]
SPRxSync[17]
SPRxSync[18]
SPRxSync[19]
SPRxSync[20]
SPRxSync[21]
SPRxSync[22]
SPRxSync[23]
SPRxSync[24]
SPRxSync[25]
SPRxSync[26]
SPRxSync[27]
SPRxSync[28]
SPRxSync[29]
SPRxSync[30]
SPRxSync[31]
(1)
B4
D6
A3
D3
H1
K4
J3
J2
Y4
AA3
AD1
AC2
AE6
AD7
AC8
AF6
AF12
AC13
AD13
AE13
AD18
AE19
AF20
AD19
®
28529-DSH-001-K
Mindspeed Technologies
25
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (7 of 19)
Pin Label
Signal Name
No.
I/O
Description
SPRxClk[0]
Receive Line Clock Input
B18
C17
A18
D16
A11
D12
B11
A10
B5
I/PD
When the PHY serial interface is enabled, this is the receive line
clock input.
Note that ports 16–31 are no-connects in the M28525.
SPRxClk[1]
SPRxClk[2]
SPRxClk[3]
SPRxClk[4]
SPRxClk[5]
SPRxClk[6]
SPRxClk[7]
SPRxClk[8]
SPRxClk[9]
SPRxClk[10]
SPRxClk[11]
SPRxClk[12]
SPRxClk[13]
SPRxClk[14]
SPRxClk[15]
SPRxClk[16]
SPRxClk[17]
SPRxClk[18]
SPRxClk[19]
SPRxClk[20]
SPRxClk[21]
SPRxClk[22]
SPRxClk[23]
SPRxClk[24]
SPRxClk[25]
SPRxClk[26]
SPRxClk[27]
SPRxClk[28]
SPRxClk[29]
SPRxClk[30]
SPRxClk[31]
(1)
D7
C6
B3
G1
J4
H3
H2
AA2
AB1
AC1
AB2
AE5
AD6
AC7
AF5
AC12
AF11
AD12
AE12
AD17
AE18
AF18
AF19
®
28529-DSH-001-K
Mindspeed Technologies
26
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (8 of 19)
Pin Label
Signal Name
No.
I/O
Description
SPRxData[0]
Receive Line Data Input
D15
A16
C15
B15
C10
B9
I/PD
When the PHY serial interface is enabled, this is the receive line
data input.
Note that ports 16–31 are no-connects in the M28525.
SPRxData[1]
SPRxData[2]
SPRxData[3]
SPRxData[4]
SPRxData[5]
SPRxData[6]
SPRxData[7]
SPRxData[8]
SPRxData[9]
SPRxData[10]
SPRxData[11]
SPRxData[12]
SPRxData[13]
SPRxData[14]
SPRxData[15]
SPRxData[16]
SPRxData[17]
SPRxData[18]
SPRxData[19]
SPRxData[20]
SPRxData[21]
SPRxData[22]
SPRxData[23]
SPRxData[24]
SPRxData[25]
SPRxData[26]
SPRxData[27]
SPRxData[28]
SPRxData[29]
SPRxData[30]
SPRxData[31]
(1)
A8
D10
C2
E4
C1
D2
J1
K3
L4
K2
AA4
AB3
AE1
AD2
AE7
AD8
AC9
AF7
AF13
AF14
AC14
AD14
AC18
AE20
AF21
AD20
®
28529-DSH-001-K
Mindspeed Technologies
27
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (9 of 19)
Pin Label
Signal Name
No.
I/O
Description
SPTxSync[0]
Frame Sync Input/ Output
A14
A13
B13
C13
C8
I/O
When the PHY serial interface is enabled, this is the frame sync.
SPTxSync is input only for all port modes except DSL mode. In
DSL Mode, SPTxSync is output only.
SPTxSync[1]
SPTxSync[2]
SPTxSync[3]
SPTxSync[4]
SPTxSync[5]
SPTxSync[6]
SPTxSync[7]
SPTxSync[8]
SPTxSync[9]
SPTxSync[10]
SPTxSync[11]
SPTxSync[12]
SPTxSync[13]
SPTxSync[14]
SPTxSync[15]
SPTxSync[16]
SPTxSync[17]
SPTxSync[18]
SPTxSync[19]
SPTxSync[20]
SPTxSync[21]
SPTxSync[22]
SPTxSync[23]
SPTxSync[24]
SPTxSync[25]
SPTxSync[26]
SPTxSync[27]
SPTxSync[28]
SPTxSync[29]
SPTxSync[30]
SPTxSync[31]
(1)
Note that ports 16–31 are no-connects in the M28525.
Caution: Some of the SPTxSync pins become outputs when the
device is configured for UTOPIA-UTOPIA mode. The designer is
cautioned to ensure that PhyIntFcSel never gets configured low.
B7
A6
C7
G4
F3
E1
F2
L1
M3
N5
M1
AC4
AD4
AF2
AF3
AE9
AD10
AF9
AC11
AD15
AF16
AE16
AC16
AE22
AC20
AD21
AF24
®
28529-DSH-001-K
Mindspeed Technologies
28
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (10 of 19)
Pin Label
Signal Name
No.
I/O
Description
SPTxData[0]
Transmit Line Data Output
D13
A12
E13
C12
D8
O
When the PHY serial interface is enabled, this is the transmit line
data output.
Note that ports 16–31 are no-connects in the M28525.
SPTxData[1]
SPTxData[2]
SPTxData[3]
SPTxData[4]
SPTxData[5]
SPTxData[6]
SPTxData[7]
SPTxData[8]
SPTxData[9]
SPTxData[10]
SPTxData[11]
SPTxData[12]
SPTxData[13]
SPTxData[14]
SPTxData[15]
SPTxData[16]
SPTxData[17]
SPTxData[18]
SPTxData[19]
SPTxData[20]
SPTxData[21]
SPTxData[22]
SPTxData[23]
SPTxData[24]
SPTxData[25]
SPTxData[26]
SPTxData[27]
SPTxData[28]
SPTxData[29]
SPTxData[30]
SPTxData[31]
(1)
B6
A5
A4
H4
G3
F1
G2
N4
N3
N1
P1
AD5
AC6
AE4
AF4
AE10
AF10
AD11
AE11
AD16
AE17
AF17
AC17
AE23
AC21
AD22
AF25
®
28529-DSH-001-K
Mindspeed Technologies
29
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (11 of 19)
Pin Label
Signal Name
No.
I/O
Description
SPTxClk[0]
Transmit Line Clock Input
A15
D14
C14
B14
C9
I/PD
When the PHY serial interface is enabled, this is the transmit line
clock input.
Note that ports 16–31 are no-connects in the M28525.
SPTxClk[1]
SPTxClk[2]
SPTxClk[3]
SPTxClk[4]
SPTxClk[5]
SPTxClk[6]
SPTxClk[7]
SPTxClk[8]
SPTxClk[9]
SPTxClk[10]
SPTxClk[11]
SPTxClk[12]
SPTxClk[13]
SPTxClk[14]
SPTxClk[15]
SPTxClk[16]
SPTxClk[17]
SPTxClk[18]
SPTxClk[19]
SPTxClk[20]
SPTxClk[21]
SPTxClk[22]
SPTxClk[23]
SPTxClk[24]
SPTxClk[25]
SPTxClk[26]
SPTxClk[27]
SPTxClk[28]
SPTxClk[29]
SPTxClk[30]
SPTxClk[31]
(1)
B8
A7
D9
F4
E3
D1
E2
K1
L3
L2
M4
AC3
AB4
AF1
AE2
AE8
AD9
AC10
AF8
AF15
AE14
AC15
AB14
AC19
AE21
AF22
AF23
®
28529-DSH-001-K
Mindspeed Technologies
30
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (12 of 19)
Pin Label
Signal Name
No.
I/O
Description
atmUTxAddr[0]
atmUTxAddr[1]
atmUTxAddr[2]
atmUTxAddr[3]
atmUTxAddr[4]
atmUTxData[0]
atmUTxData[1]
atmUTxData[2]
atmUTxData[3]
atmUTxData[4]
atmUTxData[5]
atmUTxData[6]
atmUTxData[7]
atmUTxData[8]
atmUTxData[9]
atmUTxData[10]
atmUTxData[11]
atmUTxData[12]
atmUTxData[13]
atmUTxData[14]
atmUTxData[15]
atmUTxPrty
ATM UTOPIA Transmit
Address
L23
K25
L24
K26
L25
E26
F25
H23
G24
F26
G25
H24
J23
G26
H25
J24
K23
H26
J25
K24
J26
D26
I
Transmit ATM Cell Bus address.
ATM UTOPIA Transmit
Data
I
Transmit direction ATM side cell data.
I
I
I
I
I
I
I
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I
ATM UTOPIA Transmit
Parity
Parity status signal. In 8 bit UTOPIA mode, a parity calculation is
performed over atmUTxData[7:0] for each clock cycle of
atmUTxClk. Odd parity is used. In 16 bit UTOPIA mode, this signal
is the parity of atmUTxData[15:0]. This signal is optional.
®
28529-DSH-001-K
Mindspeed Technologies
31
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (13 of 19)
Pin Label
Signal Name
No.
I/O
Description
atmUTxClAv[0]
atmUTxClAv[1]
ATM UTOPIA Transmit
Cell Available
G23
E25
O/TS
Cell Available signals for transmit ATM cells (active high). When
atmUTxClAv[1] or atmUTxClAv[0] is active one or more complete
cells can be transferred from the ATM layer.
Only atmUTxClAv[0] is used (atmUTxClAv[1] is ignored) when the
DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is the most common configuration.
atmUTxSOC
ATM UTOPIA Transmit
Start of Cell
F24
I
Start of Cell synchronization signal for transmit ATM cells (active
high). Indicates that the first byte/word of the 53 byte cell is being
placed on the atmUTxData bus.
atmUTxEnb[0]*
atmUTxEnb[1]*
ATM UTOPIA Transmit
Enable
D25
C26
I/PU
Data transfer enable(s) for transmit ATM cells (active low).
Indicates that the first byte/word of the 53 byte cell is being placed
on the atmUTxData bus.
Only atmUTxEnb[0] is used (atmUTxEnb[1] will be ignored) when
the DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is most common configuration. When using single
clav mode (DualClavEnb bit is set to 0), atmUTxEnb[1] must be
pulled up.
atmUTxClk
atmURxSOC
atmURxClk
ATM UTOPIA Transmit
Clock
M23
C19
F23
I
Clock signal used for transfer of transmit ATM cells from the ATM
Layer. The maximum clock rate is 50 MHz (Note: 33 MHz in TC
Only mode).
ATM UTOPIA Receive
Start of Cell
O/TS
I
Start of Cell synchronization signal for receive ATM cells (active
high). Indicates that the first byte/word of the 53 byte cell is being
placed on the atmURxData bus.
ATM UTOPIA Receive
Clock
Clock signal used for transfer of receive ATM cells from the ATM
Layer. The maximum clock rate is 50 MHz. (Note: 33 MHz in TC
Only mode).
atmURxClav[0]
atmURxClav[1]
ATM UTOPIA Receive Cell
Available
B20
A21
O/TS
Cell Available signals for receive ATM cells (active high). When
atmURxClAv[1] or atmURxClaAv[0] is active, one or more
complete cells can be transferred to the ATM Layer.
Only atmURxClAv[0] is used (atmURxClAv[1] is ignored) when the
DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is the most common configuration.
atmURxEnb[0]*
atmURxEnb[1]*
ATM UTOPIA Receive
Enable
A20
D18
I/PU
Enable Data transfer and output enable for receive ATM cells
(active low). When using single Clav mode (DualClavEnb, bit4 in
ATMINTFC register 0xF03, is set low), only atmURxEnb[0] is used
and atmURxEnb[1] is not used but must be pulled up. This is most
common configuration.
®
28529-DSH-001-K
Mindspeed Technologies
32
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (14 of 19)
Pin Label
Signal Name
No.
I/O
Description
atmURxData[0]
atmURxData[1]
atmURxData[2]
atmURxData[3]
atmURxData[4]
atmURxData[5]
atmURxData[6]
atmURxData[7]
atmURxData[8]
atmURxData[9]
atmURxData[10]
atmURxData[11]
atmURxData[12]
atmURxData[13]
atmURxData[14]
atmURxData[15]
atmURxPrty
ATM UTOPIA Receive
Data
C20
B21
A22
D20
C21
B22
A23
A24
D21
C22
B23
B24
C23
D22
B25
A26
D19
O/TS
Receive direction ATM side cell data.
ATM UTOPIA Receive
Parity
O/TS
I
Parity status signal. In 8 bit UTOPIA mode, a parity calculation is
performed over atmURxData[7:0] for each clock cycle of
atmURxClk. Odd parity is used. In 16 bit UTOPIA mode, this signal
is the parity of atmURxData[15:0]. This signal is optional.
atmURxAddr[0]
atmURxAddr[1]
atmURxAddr[2]
atmURxAddr[3]
atmURxAddr[4]
ATM UTOPIA Receive
Address
E23
D24
C25
B26
E24
Receive ATM Cell Bus address. This address determines the
source channel of the Receive ATM cells output from the IMA
subsystem and also selects the channel sourcing the atmURxClAv
signal. All 5 bits are not required in every application.
®
28529-DSH-001-K
Mindspeed Technologies
33
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (15 of 19)
Pin Label
Signal Name
No.
I/O
Description
VDD18
Supply Voltage (1.8 V)
E9
E10
E17
J5
Power supply connections. (1.8 V)
J22
K5
K10
K11
K16
K17
K22
L10
L17
T10
T17
U5
U10
U11
U16
U17
U22
V5
V22
AB9
AB10
AB17
AB18
®
28529-DSH-001-K
Mindspeed Technologies
34
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (16 of 19)
Pin Label
Signal Name
No.
I/O
Description
VDD33
Supply Voltage (3.3 V)
C18
C24
E7
Power supply connections. (3.3 V)
E8
E11
E12
E15
E19
E20
G5
G22
H5
H22
K12
K15
L5
L22
M2
M5
M10
M17
M22
R10
R17
R22
T5
VDD33 (Continued)
Supply Voltage (3.3 V)
(Continued)
T22
U3
Power supply connections. (3.3 V)
U12
U15
W5
W22
Y5
Y22
AB7
AB8
AB11
AB12
AB15
AB16
AB19
AB20
AE3
®
28529-DSH-001-K
Mindspeed Technologies
35
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (17 of 19)
Pin Label
Signal Name
No.
I/O
Description
VSS
Ground
A1
B2
Ground connections.
B12
D17
D23
E5
E6
E14
E21
E22
F5
F22
K13
K14
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
®
28529-DSH-001-K
Mindspeed Technologies
36
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (18 of 19)
Pin Label
Signal Name
No.
I/O
Description
VSS
(Continued)
Ground
(Continued)
N2
Ground connections.
N10
N11
N12
N13
N14
N15
N16
N17
N22
P5
P10
P11
P12
P13
P14
P15
P16
P17
R11
R12
R13
R14
R15
R16
R25
T11
T12
®
28529-DSH-001-K
Mindspeed Technologies
37
Mindspeed Proprietary and Confidential
Functional Description
Table 1-9.
M28529 Pin Descriptions (19 of 19)
Pin Label
Signal Name
No.
I/O
Description
VSS
(Continued)
Ground
(Continued)
T13
T14
Ground connections.
T15
T16
U13
U14
AA5
AA22
AB5
AB6
AB13
AB21
AB22
AC24
AD3
AE15
VGG
Electrostatic Discharge
(ESD) Supply Voltage
AC23
D4
Provides ESD protection when interfacing with 5 V systems. If
using this device in a system with 5 V logic, this pin must be
connected to 5 V. If using 3.3 V system, connect to 3.3 V.
Spare Pins
A25
B1
Spare (unused) pins on the package. Reserved for future use and
should be left unconnected.
AA23
AB23
AC05
AC25
Footnote:
(1) All unused inputs should be tied to ground or left unconnected. All unused outputs or bidirectional pins should be left unconnected.
1.5.2
Pin Diagram and Definitions (UTOPIA-to-UTOPIA Configuration)
Figures 1-9 and 1-10 illustrate the logic and block diagrams of the M2852x’s functional modules. Pin descriptions
are listed in Table 1-11.
Figure 3-33 is the pinout diagram for the M28529 when operating in the UTOPIA-to-UTOPIA mode. It is a single
CMOS integrated circuit packaged in a 484-pin PBGA. All unused input pins should be connected to ground or
power. Unused output and bidirectional pins should be left unconnected.
UTOPIA-to-UTOPIA configuration is selected by tying the PhyIntFcSel pin low.
NOTE:
When using the M28525/9 in Utopia to Utopia configuration, in addition to the standard Utopia Level 2
specification definitions, the device uses the PHY side RX and TX CLAV signals for the following purpose:
- The PHY TX CLAV signals are used to determine the stuffing rate for SICP cells. The M28525/9 will monitor
the CLAV signal to determine the fullness of the downstream device's Utopia FIFO.
- For applications where timing is not available from the RX_TRLs (such as DSL), the M28525/9 can be
configured to use the PHY RX CLAV signals to generate a clock that approximates the payload timing. As such,
the expectation is the RX CLAV signals from the TC/PHY layer approximates an ideal PHY layer device in the
sense that cell boundary times present on the receive physical bus are reproduced with a fixed offset in time to
the cells available on the PHY Utopia bus.
Contact Mindspeed applications engineering for more details.
®
28529-DSH-001-K
Mindspeed Technologies
38
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-9. M28529 Logic Diagram (UTOPIA-to-UTOPIA)
Reset I
Reset*
Reset
One Second
Interface
8kHzIn Clock I
8kHzin*
I/O One Second Input/Output
OneSecIO
PHY UTOPIA Transmit
Interface
phyUTxClAv[1:0]
phyUTxSOC
phyUTxData[15:0]
phyUTxPrty
I PHY Transmit Cell Available
O PHY Transmit Start of Cell
O PHY Transmit Data Bus
O PHY Transmit Parity
phyUTxClk
phyUTxEnb[1:0]*
phyUTxAddr[4:0]
PHY Transmit Clock O
PHY Transmit Enable O
PHY Transmit Address Bus O
phyURxClAv[1:0]
phyURxSOC
phyURxData[15:0]
phyURxPrty
PHY UTOPIA Receive
Interface
I PHY Receive Cell Available
I PHY Receive Start of Cell
I PHY Receive Data Bus
phyURxClk
phyURxEnb[1:0]*
phyURxAddr[4:0]
PHY Receive Clock O
PHY Receive Enable O
PHY Receive Address Bus O
I PHY Receive Parity
StatOut [1:0]
MicroInt*
MRdy
MicroData[7:0]
O Status Output
O Summary Interrupt
O Ready
I/O Microprocessor Data Bus
PHY Interface Select I
Sync/Async Mode Select I
Microprocessor Clock I
Chip Select I
PhyIntFcSel(1)
MSyncMode
MicroClk
Microprocessor
Interface
*
MCS
Address Strobe, Write Control I
Write/Read Read Control I
Address Bus I
MAS*, MWr
MW/R, MRd
MicroAddr[11:0]
*
*
TRST
TCK
Test Reset I
Test Clock I
TDO
O Test Data Output
Test Mode Select I
Test Data Input I
Test Enable I
TMS
TDI
TestEnable
TestMode
JTAGInterface
Test Mode I
ATMUTOPIATransmit
Interface
atmUTxClAv[1:0]
atmUTxSOC
O ATM Transmit Cell Available
I ATM Transmit Start Of Cell
I ATM Transmit Parity
ATM Transmit Clock I
ATM Transmit Enable I
ATMTransmit Address Bus I
atmUTxCLK
atmUTxENB[1:0]*
atmUTxAddr[4:0]
atmUTxPrty
atmUTxData[15:0]
I ATM Transmit Data Bus
OATMReceiveCell Available
O ATM Receive Start Of Cell
O ATM Receive Parity
atmURxClAv[1:0]
atmURxSOC
atmURxPrty
atmURxData[15:0]
ATM UTOPIA Receive
Interface
ATM Receive Clock I
ATM Receive Enable I
ATM Receive Address Bus I
atmURxCLK
atmURxENB[1:0]*
atmURxAddr[4:0]
O ATM Receive Data Bus
IMA_SysClk
IMA_RefClk
IMA Clocks
IMA System Clock I
IMA Reference Clock I
TxTRL[1:0]
O Transmit Reference Clock
External Memory
Interfac e
MemAddr[19:0]
O Memory Address Bus
O Chip Enable
O Output Enable
O Write Enable
Memory Data Bus I/O
MemData[15:0]
ExtMemSel
*
MemCtrl_CE
*
MemCtrl_OE
*
MemCtrl_WE
External Memory Select I
MemCtrl_Clk
O SRAM Clock
O Address Enable
MemCtrl_ADSC*
(1)Pulled High
®
28529-DSH-001-K
Mindspeed Technologies
39
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-10. IMA Block Diagram
and Passthrough
and Passthrough
Table 1-10. UTOPIA-to-UTOPIA Configuration Information
ATMMux [7,6]
(ATMINTFC, 0xF03)
PhyIntFcSel
(Pin AD24)
Description
01
Low
IMA UTOPIA using the PHY Side UTOPIA; Internal TC block and serial ports not used.
General Note: Use of external memory is optional.
®
28529-DSH-001-K
Mindspeed Technologies
40
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (1 of 18)
Pin Label
Signal Name
No.
I/O
Description
StatOut[0]
Status Output
AB24
AD26
AE24
O
General purpose output pins under software control.
StatOut[1]
MSyncMode
Microprocessor
Synchronous/
Asynchronous Bus Mode
Select
I/PD
Selects synchronous or asynchronous bus mode, which
determines the functions of two pins, MW/R, MRd* (pin W4) and
MAS*,MWr* (pin Y2). A logic 1 selects the synchronous bus
mode. In this mode, these pins are defined as follows: MW/R (W4)
and MAS* (Y2). A logic 0 selects the asynchronous SRAM-type
bus mode. In this mode, the pins are defined as follows: MRd*
(W4) and MWr* (Y2).
Reset*
Device Reset
T4
I/PU
When asserted low, resets the device. The microprocessor clock
must be present before reset is released. If configuring the device
for pass-through operation, a minimum delay of 25 uS for
IMA_Sysclk of 66 MHz or 33 uS for IMA_Sysclk of 50 MHz is
required from the release of reset to the first access of the
IMA_RX_TRANS_TABLE register or the
IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
8kHzIn
8 kHz Input
AD25
AE26
I
A clock input used to derive OneSecIO. Typically operates at a
frequency of 8 kHz.
OneSecIO
One-Second Input/Output
I/O
Software can configure this pin as an output that equals the input
from the 8kHzIn divided by 8000. When configured as an input,
status registers and counters may be latched on the rising edge of
this input. See Bit 0 of the Genctrl register (0xF00).
MW/R, MRd*
Microprocessor Write/
Read
W4
I
When MSyncMode is asserted high, this pin is a read/write control
pin. In this mode, when MW/R is asserted high, a write access is
enabled and the MicroData[7:0] pin values will be written to the
memory location indicated by the MicroAddr[11:0] pins. Also,
when MW/R is asserted low in this mode, a read access is enabled
and the memory location indicated by the MicroAddr[11:0] pins is
read. Its value is placed on the MicroData[7:0] pins. Both read and
write accesses assume the device is chip selected (MCS* = 0), the
address is valid (MAS* = 0), and the device is not being reset
(Reset* = 1).
When MSyncMode is asserted low, this pin is a read control pin. In
this mode, when MRd* is asserted low, a read access is enabled
and the memory location indicated by the MicroAddr[11:0] pins is
read. Its value is placed on the MicroData[7:0] pins.
MCS*
Microprocessor Chip
Select
V1
I
When asserted low, the device is selected for read and write
accesses. When asserted high, the device will not respond to input
signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*.
Additionally, when MCS* is asserted high, the MicroData[7:0] pins
are in a high-impedance state but the MicroInt* pin remains
operational.
®
28529-DSH-001-K
Mindspeed Technologies
41
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (2 of 18)
Pin Label
Signal Name
No.
I/O
Description
MAS*, MWr*
Microprocessor Address
Strobe
Y2
I
When MSyncMode is asserted high, this pin is an address strobe
pin. When the MAS* pin is asserted low, it indicates a valid
address, MicroAddr[11:0]. This signal is used to qualify read and
write accesses.
When MSyncMode is asserted low, this pin is a write control pin.
When MWr* is asserted low, a write access is enabled and the
MicroData[7:0] pin values will be written to the memory location
indicated by the MicroAddr[11:0] pins. The write access assumes
the device is chip selected (MCS* = 0), a read access is not being
requested (MRd* = 1), and the device is not being reset (Reset* =
1).
MicroAddr[0]
MicroAddr[1]
MicroAddr[2]
MicroAddr[3]
MicroAddr[4]
MicroAddr[5]
MicroAddr[6]
MicroAddr[7]
MicroAddr[8]
MicroAddr[9]
MicroAddr[10]
MicroAddr[11]
MicroData[0]
MicroData[1]
MicroData[2]
MicroData[3]
MicroData[4]
MicroData[5]
MicroData[6]
MicroData[7]
MicroInt*
Microprocessor Address
Bus
U2
T3
I
These 12 bits are an address input for identifying the register to
access.
U1
T2
R4
T1
R3
R2
P4
R1
P3
P2
W3
V4
Y1
W2
V3
U4
W1
V2
AA1
Microprocessor Data Bus
I/O
A bi-directional data bus for reading and writing data to internal
registers.
Microprocessor Interrupt
Request
O
When active low, the device needs servicing. It remains active until
the pending interrupt is processed by the Interrupt Service
Routine. This pin is an open drain output for an external wired OR
logic implementation. An external pull-up resistor is required for
this pin.
®
28529-DSH-001-K
Mindspeed Technologies
42
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (3 of 18)
Pin Label
Signal Name
No.
I/O
Description
MRdy
Microprocessor Ready
Y3
O
When active high, the current read or write transaction has been
completed. For a read transaction, the data is ready to be
transferred to the microprocessor. For a write transaction, the data
provided by the microprocessor has been written. This pin is an
open drain output for an external wired OR logic implementation.
An external pull-up resistor is required for this pin.
MicroClk
Microprocessor Clock
R5
I
In asynchronous mode the microprocessor clock signal input can
be clocked up to 66 MHz. In synchronous mode this pin can be
clocked up to 25 MHz. The device samples the microprocessor
interface pins (MCS*, MW/R, MRd*, MAS*, MicroAddr[11:0], and
MicroData[7:0]) on the rising edge of this signal. The
microprocessor interface output pins (MicroData[7:0], MicroInt*)
are clocked on the rising edge of MicroClk. Note that this clock is
required for both synchronous and asynchronous operations. See
note in Section 1.15.1.
ExtMemSel
External Memory Enable
AC26
I/PD
When this pin is pulled high, it enables the external differential
delay SRAM bus.
MemData[0]
MemData[1]
MemData[2]
MemData[3]
MemData[4]
MemData[5]
MemData[6]
MemData[7]
MemData[8]
MemData[9]
MemData[10]
MemData[11]
MemData[12]
MemData[13]
MemData[14]
MemData[15]
Differential Delay
Memory Data Bus
M26
N24
N25
N26
P26
P25
P24
P23
R26
P22
R24
T26
R23
T25
T24
U26
I/O/PD Differential delay SRAM Data Bus. ATM cells extracted from the
Receive data stream are stored in the SRAM for the purpose of
differential delay compensation.
®
28529-DSH-001-K
Mindspeed Technologies
43
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (4 of 18)
Pin Label
Signal Name
No.
I/O
Description
MemAddr[0]
Differential Delay
Memory Address Bus
U25
T23
O
Receive SRAM Address Bus.
These signals are enabled by tying the ExtMemSel pin high.
MemAddr[1]
MemAddr[2]
MemAddr[3]
MemAddr[4]
MemAddr[5]
MemAddr[6]
MemAddr[7]
MemAddr[8]
MemAddr[9]
MemAddr[10]
MemAddr[11]
MemAddr[12]
MemAddr[13]
MemAddr[14]
MemAddr[15]
MemAddr[16]
MemAddr[17]
MemAddr[18]
MemAddr[19]
MemCtrl_CE*
V26
U24
V25
W26
U23
V24
W25
Y26
V23
W24
Y25
AA26
W23
Y24
AA25
Y23
AB26
AA24
N23
Chip Enable
O
O
Receive SRAM Device Select (active low) control signal.
This signal is enabled by pulling the ExtMemSel pin high.
MemCtrl_OE*
MemCtrl_WE*
MemCtrl_CLK
MemCtrl_ADSC*
TRST*
Output Enable
Write Enable
SRAM Clock
Address Enable
Test Reset
M25
M24
AB25
L26
C5
Receive SRAM Device Output (active low) control signal.
This signal is enabled by pulling the ExtMemSel pin high.
O
Receive SRAM write enable (active low) control signal.
This signal is enabled by pulling the ExtMemSel pin high.
O
Receive SRAM clock signal.
This signal is enabled by pulling the ExtMemSel pin high.
O
Receive SRAM address enable (active low) address strobe.
This signal is enabled by pulling the ExtMemSel pin high.
I/PU
I/PU
I/PU
When asserted, the internal boundary-scan logic is reset. This pin
has a pull-up resistor.
TCK
Test Clock
A2
Samples the value of TMS and TDI on its rising edge to control the
boundary scan operations.
TMS
Test Mode Select
D5
Controls the boundary-scan Test Access Port (TAP) controller
operation. This pin has a pull-up resistor.
TDI
Test Data Input
C4
C3
I/PU
O
The serial test data input. This pin has a pull-up resistor.
The serial test data output.
TDO
Test Data Output
®
28529-DSH-001-K
Mindspeed Technologies
44
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (5 of 18)
Pin Label
Signal Name
No.
I/O
Description
TestEnable[0]
AF26
AC22
AD23
AE25
AD24
I/PD
Factory test use only, tie to VSS.
TestEnable[1]
ScanEnable
Tristate
I/PD
I/PD
I/PU
Factory test use only, tie to VSS
Tristate
When this pin is high, all outputs are tristate.
PhyIntFcSel
PHY Interface Select
If this pin is tied low, the PHY UTOPIA Interface mode is selected.
This table shows pin configurations with this pin tied low.
If this pin is tied high, the PHY Serial mode is selected.
phyURxClk
UTOPIA Receive Clock
AF9
AF16
AD15
O
O
IMA_SysClk/2
phyURxEnb[0]*
phyURxEnb[1]*
PHY UTOPIA Receive
Enable
Data transfer and output enable for Receive PHY cells (active low).
To support multiple PHY devices, separate enable signals are
provided. Depending on the software configuration, some of the
enable signals may not be available and will be replaced by
additional PHY cell bus address bits. When the PHY Size (bits 4
and 5) of register 0x804 are set to 2 (single clav), phyURxEnb[1]
must be pulled up.
phyURxAddr[0]
phyURxAddr[1]
phyURxAddr[2]
phyURxAddr[3]
phyURxAddr[4]
PHY UTOPIA Receive
Address
AE11
AD11
AF10
AE10
AC11
O
Receive PHY Cell Bus address. The following limitations apply:
Device
Addresses
M28525
M28529
0–15, 31
0–31
phyURxClAv[0]
phyURxClAv[1]
PHY UTOPIA Receive Cell
Available
AF19
AF18
I/PD
I/PD
Cell Available signals for Receive PHY interfaces. phyURxClAv[n] is
active when one or more complete cells can be transferred. To
support different PHY devices, separate cell available signals are
provided. This allows expansion to 32 points.
®
28529-DSH-001-K
Mindspeed Technologies
45
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (6 of 18)
Pin Label
Signal Name
No.
I/O
Description
phyURxData[0]
phyURxData[1]
phyURxData[2]
phyURxData[3]
phyURxData[4]
phyURxData[5]
phyURxData[6]
phyURxData[7]
phyURxData[8]
phyURxData[9]
phyURxData[10]
phyURxData[11]
phyURxData[12]
phyURxData[13]
phyURxData[14]
phyURxData[15]
phyURxSOC
PHY UTOPIA Receive
Data
AB14
AC15
AE14
AF15
AD14
AC14
AF14
AF13
AE13
AD13
AC13
AF12
AE12
AD12
AF11
AC12
AD17
I/PD
Received 16 bit PHY Cell Data. All received cells are passed to the
internal IMA processor.
PHY UTOPIA Start of Cell
I/PD
Start of Cell synchronization signal for Receive PHY cells (active
high). Indicates that the first byte of the cell is being placed on the
PhyURxData[7:0] bus.
phyURxPrty
PHY UTOPIA Receive
Parity
AE18
I/PD
O
Odd parity calculated over phyURxData[15:0] pins in 16-bit mode
and over phyURxData[7:0] pins in 8-bit mode.
phyUTxAddr[0]
phyUTxAddr[1]
phyUTxAddr[2]
phyUTxAddr[3]
phyUTxAddr[4]
PHY UTOPIA Transmit
Address
G2
F1
Transmit PHY Cell Bus address. The following limitations apply:
Device
Addresses
G3
H4
F2
M28525
M28529
0–15, 31
0–31
phyUTxClAv[0]
phyUTxClAv[1]
PHY UTOPIA Transmit
Cell Available
E2
I/PD
O
Cell Available signals for Transmit ATM cells. When phyUTxClAv[n]
is active high, the PHY has space available for one or more
complete cells. To support different PHY devices, separate cell
available signals are provided.
D1
phyUTxClk
PHY UTOPIA Transmit
Clock
G4
IMA_SysClk divided by two.
®
28529-DSH-001-K
Mindspeed Technologies
46
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (7 of 18)
Pin Label
Signal Name
No.
I/O
Description
phyUTxData[0]
phyUTxData[1]
phyUTxData[2]
phyUTxData[3]
phyUTxData[4]
phyUTxData[5]
phyUTxData[6]
phyUTxData[7]
phyUTxData[8]
phyUTxData[9]
phyUTxData[10]
phyUTxData[11]
phyUTxData[12]
phyUTxData[13]
phyUTxData[14]
phyUTxData[15]
phyUTxEnb[0]*
phyUTxEnb[1]*
PHY UTOPIA Transmit
Data
AF4
AE4
AC6
AD5
AF3
AF2
AD4
AC4
P1
O
8 bit PHY Cell Data to be sent out the PHY facility.
8 bit UTOPIA interface used to transmit data to the external TC
devices.
N1
N3
N4
M1
N5
M3
L1
PHY UTOPIA Transmit
Enable
E1
O
O
Data transfer enable for Transmit PHY cells (active low signal). To
support different PHY devices, separate enable signals are
provided. When the PHY Size (bits 4 and 5) of register 0x804 are
set to 2 (single clav), phyUTxEnb[1] must be pulled up.
F3
phyUTxSOC
PHY UTOPIA Transmit
Start of Cell
AE9
Start of Cell synchronization signal for Transmit PHY cells (active
high). Indicates that the first byte of a cell is being placed on the
phyUTxData[7:0] bus.
phyUTxPrty
IMA_SysClk
IMA_RefClk
PHY UTOPIA Transmit
Parity
AD10
E18
O
Odd parity calculated over phyUTxData[15:0] pins in 16-bit mode
and over phyUTxData[7:0] pins in 8-bit mode.
IMA Subsystem Clock
I/PU
I/PU
O
Most of the IMA logic circuits use this clock (or a derivative of it). It
can also be used as a T1/E1 reference clock. Refer to Section 1.12.
IMA Reference Clock
E16
If this is to be used as a reference clock, set the frequency as
shown in Section 1.12.
TxTRL[0]
TxTRL[1]
Transmit Reference
Clocks
A19
B19
Transmit Reference Clocks.
®
28529-DSH-001-K
Mindspeed Technologies
47
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (8 of 18)
Pin Label
Signal Name
No.
I/O
Description
atmUTxAddr[0]
atmUTxAddr[1]
atmUTxAddr[2]
atmUTxAddr[3]
atmUTxAddr[4]
atmUTxData[0]
atmUTxData[1]
atmUTxData[2]
atmUTxData[3]
atmUTxData[4]
atmUTxData[5]
atmUTxData[6]
atmUTxData[7]
atmUTxData[8]
atmUTxData[9]
atmUTxData[10]
atmUTxData[11]
atmUTxData[12]
atmUTxData[13]
atmUTxData[14]
atmUTxData[15]
atmUTxPrty
ATM UTOPIA Transmit
Address
L23
K25
L24
K26
L25
E26
F25
H23
G24
F26
G25
H24
J23
G26
H25
J24
K23
H26
J25
K24
J26
D26
I
Transmit ATM Cell Bus address.
ATM UTOPIA Transmit
Data
I
Transmit direction ATM side cell data.
I
I
I
I
I
I
I
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I
ATM UTOPIA Transmit
Parity
Parity status signal. In 8 bit UTOPIA mode, a parity calculation is
performed over atmUTxData[7:0] for each clock cycle of
atmUTxClk. Odd parity is used. In 16 bit UTOPIA mode, this signal
is the parity of atmUTxData[15:0]. This signal is optional.
®
28529-DSH-001-K
Mindspeed Technologies
48
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (9 of 18)
Pin Label
Signal Name
No.
I/O
Description
atmUTxClAv[0]
atmUTxClav[1]
ATM UTOPIA Transmit
Cell Available
G23
E25
O/TS
Cell Available signals for transmit ATM cells (active high). When
atmUTxClAv[1] or atmUTxClAv[0] is active one or more complete
cells can be transferred from the ATM layer.
Only atmUTxClAv[0] is used (atmUTxClAv[1] is ignored) when the
DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is the most common configuration.
atmUTxSOC
ATM UTOPIA Transmit
Start of Cell
F24
I
Start of Cell synchronization signal for transmit ATM cells (active
high). Indicates that the first byte/word of the 53 byte cell is being
placed on the atmUTxData bus.
atmUTxEnb[0]*
atmUTxEnb[1]*
ATM UTOPIA Transmit
Enable
D25
C26
I/PU
I/PU
Enable Data transfer enable(s) for transmit ATM cells (active low).
Indicates that the first byte/word of the 53 byte cell is being placed
on the atmUTxData bus.
When using single Clav mode (DualClavEnb, bit4 in ATMINTFC
register 0xF03, is set low), only atmUTxEnb[0] is used and
atmUTxEnb[1] is not used but must be pulled up. This is most
common configuration.
atmUTxClk
atmURxSOC
atmURxClk
ATM UTOPIA Transmit
Clock
M23
C19
F23
I
Clock signal used for transfer of transmit ATM cells from the ATM
Layer. The maximum clock rate is 50 MHz. (Note: 33 MHz for TC
Only mode.)
ATM UTOPIA Receive
Start of Cell
O/TS
I
Start of Cell synchronization signal for receive ATM cells (active
high). Indicates that the first byte/word of the 53 byte cell is being
placed on the atmURxData bus.
ATM UTOPIA Receive
Clock
Clock signal used for transfer of receive ATM cells from the ATM
Layer. The maximum clock rate 50 MHz. (Note: 33 MHz for TC Only
mode.)
atmURxClAv[0]
atmURxClAv[1]
ATM UTOPIA Receive Cell
Available
B20
A21
O/TS
Cell Available signals for receive ATM cells (active high). When
atmURxClAv[1] or atmURxClaAv[0] is active, one or more
complete cells can be transferred to the ATM Layer.
Only atmURxClAv[0] is used (atmURxClAv[1] is ignored) when the
DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is the most common configuration.
atmURxEnb[0]*
atmURxEnb[1]*
ATM UTOPIA Receive
Enable
A20
D18
I/PU
I/PU
Data transfer and output enable for receive ATM cells (active low).
Only atmURxEnb[0] is used (atmURxEnb[1] will be ignored) when
the DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is most common configuration. When using single
clav mode (DualClavEnb bit is set to 0), atmURxEnb[1] must be
pulled up.
®
28529-DSH-001-K
Mindspeed Technologies
49
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (10 of 18)
Pin Label
Signal Name
No.
I/O
Description
atmURxData[0]
atmURxData[1]
atmURxData[2]
atmURxData[3]
atmURxData[4]
atmURxData[5]
atmURxData[6]
atmURxData[7]
atmURxData[8]
atmURxData[9]
atmURxData[10]
atmURxData[11]
atmURxData[12]
atmURxData[13]
atmURxData[14]
atmURxData[15]
atmURxPrty
ATM UTOPIA Receive
Data
C20
B21
A22
D20
C21
B22
A23
A24
D21
C22
B23
B24
C23
D22
B25
A26
D19
O/TS
Receive direction ATM side cell data.
ATM UTOPIA Receive
Parity
O/TS
I
Parity status signal. In 8 bit UTOPIA mode, a parity calculation is
performed over atmURxData[7:0] for each clock cycle of
atmUTxClk. Odd parity is used. In 16 bit UTOPIA mode, this signal
is the parity of atmURxData[15:0]. This signal is optional.
atmURxAddr[0]
atmURxAddr[1]
atmURxAddr[2]
atmURxAddr[3]
atmURxAddr[4]
ATM UTOPIA Receive
Address
E23
D24
C25
B26
E24
Receive ATM Cell Bus address. This address determines the source
channel of the Receive ATM cells output from the IMA subsystem
and also selects the channel sourcing the atmURxClAv signal.
®
28529-DSH-001-K
Mindspeed Technologies
50
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (11 of 18)
Pin Label
Signal Name
No.
I/O
Description
VDD18
Supply Voltage
(1.8 V)
E9
E10
E17
J5
Power supply connections. (1.8 V)
J22
K5
K10
K11
K16
K17
K22
L10
L17
T10
T17
U5
U10
U11
U16
U17
U22
V5
V22
AB9
AB10
AB17
AB18
®
28529-DSH-001-K
Mindspeed Technologies
51
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (12 of 18)
Pin Label
Signal Name
No.
I/O
Description
VDD33
Supply Voltage
(3.3 V)
C18
C24
E7
Power supply connections. (3.3 V)
E8
E11
E12
E15
E19
E20
G5
G22
H5
H22
K12
K15
L5
L22
M2
M5
M10
M17
M22
R17
R10
R22
T5
VDD33
(Continued)
Supply Voltage
(3.3 V)
(Continued)
T22
U12
U15
W5
Power supply connections. (3.3 V)
(Continued)
W22
Y5
Y22
AB7
AB8
AB11
AB12
AB15
AB16
AB19
AB20
AE3
U3
®
28529-DSH-001-K
Mindspeed Technologies
52
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (13 of 18)
Pin Label
Signal Name
No.
I/O
Description
VSS
Ground
A1
B2
Ground connections.
B12
D17
D23
E5
E6
E14
E21
E22
F5
F22
K13
K14
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
®
28529-DSH-001-K
Mindspeed Technologies
53
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (14 of 18)
Pin Label
Signal Name
No.
I/O
Description
VSS
Ground
N2
Ground connections.
N10
N11
N12
N13
N14
N15
N16
N17
N22
P5
P10
P11
P12
P13
P14
P15
P16
P17
R11
R12
R13
R14
R15
R16
R25
T11
T12
VSS
(Continued)
Ground
(Continued)
T13
T14
Ground connections.
(Continued)
T15
T16
U13
U14
AA5
AA22
AB5
AB6
AB13
AB21
AB22
AC24
AD3
AE15
VGG
Electrostatic Discharge
(ESD) Supply Voltage
AC23
D4
Provides ESD protection when interfacing with 5 V systems. If
using this device in a system with 5 V logic, this pin must be
connected to 5 V. If using 3.3 V system, connect to 3.3 V.
®
28529-DSH-001-K
Mindspeed Technologies
54
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (15 of 18)
Pin Label
Signal Name
No.
I/O
Description
Unused Inputs
A3
A7
Unused Inputs with internal pulldown
A8
A9
A10
A11
A15
A16
A17
A18
B3
B4
B5
B8
B9
B10
B11
B14
B15
B16
B17
B18
C1
C2
C6
C9
C10
C11
C14
C15
C16
C17
D2
D3
D6
D7
D9
D10
D11
D12
D14
D15
D16
E3
E4
F4
G1
H1
H2
H3
J1
J2
®
28529-DSH-001-K
Mindspeed Technologies
55
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (16 of 18)
Pin Label
Signal Name
No.
I/O
Description
Unused Input
J3
J4
Unused Inputs with Internal Pulldown
K1
K2
K3
K4
L2
L3
L4
M4
Y4
AA2
AA3
AA4
AB1
AB2
AB3
AB4
AC1
AC2
AC3
AC7
AC8
AC9
AC10
AC18
AC19
®
28529-DSH-001-K
Mindspeed Technologies
56
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (17 of 18)
Pin Label
Signal Name
No.
I/O
Description
Unused Input
AD1
AD2
AD6
AD7
AD8
AD9
AD18
AD19
AD20
AE1
Unused Inputs with Internal Pulldown
AE2
AE5
AE6
AE7
AE8
AE19
AE20
AE21
AF1
AF5
AF6
AF7
AF8
AF20
AF21
AF22
AF23
®
28529-DSH-001-K
Mindspeed Technologies
57
Mindspeed Proprietary and Confidential
Functional Description
Table 1-11. M2852x Pin Descriptions (18 of 18)
Pin Label
Signal Name
No.
I/O
Description
Unused I/O
A6
A13
A14
AC16
AC20
AD21
AE16
AE22
AF24
B7
Unused I/O with pulldown (outputs in tristate)
B13
C7
C8
Note: Leave unconnected.
Unused Outputs (tristate)
C13
Unused Outputs
A12
AC17
AC21
AD16
AD22
AE17
AE23
AF17
AF25
B6
C12
D13
Note: Leave unconnected.
D8
E13
Spare
A25
B1
Spare (unused) pins on the package. Reserved for future use and
should be left unconnected.
AA23
AB23
AC5
AC25
®
28529-DSH-001-K
Mindspeed Technologies
58
Mindspeed Proprietary and Confidential
Functional Description
1.5.3
Interleaved Highway Configuration
Four serial data streams can be combined together into one serial data stream using an Interleaved Highway
Interface. For more information on the operation of the Interleaved Highway, refer to Section 1.14.2.5.5. The
Interleaved Highway interface can be enabled on a per highway basis. When an Interleaved Highway is enabled
the pinout of the group of four muxed serial streams, see Table 1-12 for the grouping, changes to the pinout
desribed in Table 1-14, Table 1-15 and Table 1-16. Table 1-13 desribes the functionality of each of the interleaved
highway interface pins.
Table 1-12. Serial Stream Muxing into Interleaved Highway
Interleaved
Highway
Interleaved
Highway
Serial Stream
Serial Stream
0
1
2
3
0
1
4
5
6
7
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2
3
4
5
6
7
8
9
10
11
12
13
14
15
®
28529-DSH-001-K
Mindspeed Technologies
59
Mindspeed Proprietary and Confidential
Functional Description
Table 1-13. M28529 Interleaved Highway Pin Descriptions
Pin Label
Signal Name
I/O
Description
IHRxSync[x]
Interleaved Highway Receive Frame Sync Input
I/PD
When the Interleaved Highway interface is enabled, this
is the frame sync input.
IHRxClk[x]
IHRxInDo[x]
IHRxData[x]
IHTxSync[x]
IHTxClk[x]
Interleaved Highway Transmit Clock Input
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
O
When the Interleaved Highway interface is enabled, this
is the receive line clock input.
Interleaved Highway Receive Timeslot
Indicator Input
When the Interleaved Highway interface is enabled, this
is the receive timeslot indicator input.
Interleaved Highway Receive Data Input
When the Interleaved Highway interface is enabled, this
is the receive line data input.
Interleaved Highway Transmit Frame Sync
Input/Output
When the Interleaved Highway interface is enabled, this
is the frame sync.
Interleaved Highway Transmit Clock Input
When the Interleaved Highway interface is enabled, this
is the transmit line clock input.
IHTxInDo[x]
IHTxData[x]
Interleaved Highway Transmit Timeslot
Indicator Input
When the Interleaved Highway interface is enabled, this
is the transmit timeslot indicator input.
Interleaved Highway Transmit Data Output
When the Interleaved Highway interface is enabled, this
is the transmit line data output
Table 1-14. Interleaved Highway Port 0 - 3 Pinouts
Interleaved Highway 0 Interleaved Highway 1
Interleaved Highway 2
Interleaved Highway 3
Pin Label
No.
Pin Label
No.
Pin Label
No.
Pin Label
No.
IHRxSync[0]
B17
B18
A17
D15
A14
D13
A13
A15
IHRxSync[1]
C11
A11
B10
C10
C8
IHRxSync[2]
B4
B5
D6
C2
G4
H4
F3
IHRxSync[3]
H1
G1
K4
J1
IHRxClk[0]
IHRxInDo[0]
IHRxData[0]
IHTxSync[0]
IHTxData[0]
IHTxInDo[0]
IHTxClk[0]
IHRxClk[1]
IHRxInDo[1]
IHRxData[1]
IHTxSync[1]
IHTxData[1]
IHTxInDo[1]
IHTxClk[1]
IHRxClk[2]
IHRxInDo[2]
IHRxData[2]
IHTxSync[2]
IHTxData[2]
IHTxInDo[2]
IHTxClk[2]
IHRxClk[3]
IHRxInDo[3]
IHRxData[3]
IHTxSync[3]
IHTxData[3]
IHTxInDo[3]
IHTxClk[3]
L1
N4
M3
K1
D8
B7
C9
F4
®
28529-DSH-001-K
Mindspeed Technologies
60
Mindspeed Proprietary and Confidential
Functional Description
Table 1-15. Interleaved Highway Port 4 - 7 Pinouts
Interleaved Highway 4 Interleaved Highway 5
Interleaved Highway 6
Pin Label No.
Interleaved Highway 7
Pin Label
No.
Pin Label
No.
Pin Label
No.
IHRxSync[4]
Y4
IHRxSync[5]
AE6
AE5
IHRxSync[6]
AF12
AC12
AC13
AF13
AD15
AD16
AF16
AF15
IHRxSync[7]
AD18
AD17
AE19
AC18
AE22
AE23
AC20
AC19
IHRxClk[4]
AA2
AA3
AA4
AC4
AD5
AD4
AC3
IHRxClk[5]
IHRxInDo[5]
IHRxData[5]
IHTxSync[5]
IHTxData[5]
IHTxInDo[5]
IHTxClk[5]
IHRxClk[6]
IHRxInDo[6]
IHRxData[6]
IHTxSync[6]
IHTxData[6]
IHTxInDo[6]
IHTxClk[6]
IHRxClk[7]
IHRxInDo[7]
IHRxData[7]
IHTxSync[7]
IHTxData[7]
IHTxInDo[7]
IHTxClk[7]
IHRxInDo[4]
IHRxData[4]
IHTxSync[4]
IHTxData[4]
IHTxInDo[4]
IHTxClk[4]
AD7
AE7
AE9
AE10
AD10
AE8
General Note:
1. Interleaved Highway serial port 4-7 pins are no connects on the M28525.
The interleaved highway can be selected on a per group of 4 channel basis. When interleaved highway mode is
selected, the following serial mode pins, as identified in Table 1-16 become unused.
Table 1-16. No Connects Per Interleaved Highway Group (1 of 4)
Highway 0
A16
A18
B14
B15
B16
C14
C15
C16
C17
D14
D16
Input No Connects With Pulldown
B13
C13
Unused I/O (Pulled Down/Outputs tristate)
Note: Leave unconnected.
A12
C12
E13
Unused Outputs (tristate)
Note: Leave unconnected.
®
28529-DSH-001-K
Mindspeed Technologies
61
Mindspeed Proprietary and Confidential
Functional Description
Table 1-16. No Connects Per Interleaved Highway Group (2 of 4)
Highway 1
Highway 2
Highway 3
A7
A8
A9
A10
B8
B9
B11
D9
D10
D11
D12
Unused Input (Pulled Down)
A6
C7
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
A4
A5
B6
Unused Output (tristate)
Note: Leave unconnected.
A3
B3
C1
C6
D1
D2
D3
D7
E2
E3
E4
Unused Input (Pulled Down)
E1
F2
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
F1
G2
G3
Unused Output (tristate)
Note: Leave unconnected.
H2
H3
J2
Unused Input (Pulled Down)
J3
J4
K2
K3
L2
L3
L4
M4
M1
N5
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
N1
N3
P1
Unused Output (tristate)
Note: Leave unconnected.
®
28529-DSH-001-K
Mindspeed Technologies
62
Mindspeed Proprietary and Confidential
Functional Description
Table 1-16. No Connects Per Interleaved Highway Group (3 of 4)
Highway 4
Highway 5
Highway 6
AB1
AB2
AB3
AB4
AC1
AC2
AD1
AD2
AE1
AE2
AF1
Unused Input (Pulled Down)
AF2
AF3
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
AC6
AE4
AF4
Unused Output (tristate)
Note: Leave unconnected.
AC7
AC8
AC9
AC10
AD6
AD8
AD9
AF5
Unused Input (Pulled Down)
AF6
AF7
AF8
AC11
AF9
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
AD11
AE11
AF10
Unused Output (tristate)
Note: Leave unconnected.
AB14
AC14
AC15
AD12
AD13
AD14
AE12
AE13
AE14
AF11
AF14
Unused Input (Pulled Down)
AC16
AE16
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
AC17
AE17
AF17
Unused Output (tristate)
Note: Leave unconnected.
®
28529-DSH-001-K
Mindspeed Technologies
63
Mindspeed Proprietary and Confidential
Functional Description
Table 1-16. No Connects Per Interleaved Highway Group (4 of 4)
Highway 7
AD19
AD20
AE18
AE20
AE21
AF18
AF19
AF20
AF21
AF22
AF23
Unused Input (Pulled Down)
AD21
AF24
Unused I/O (Pulled down/Outputs tristate)
Note: Leave unconnected.
AC21
AD22
AF25
Unused Output (tristate)
Note: Leave unconnected.
®
28529-DSH-001-K
Mindspeed Technologies
64
Mindspeed Proprietary and Confidential
Functional Description
1.6
Stand Alone Cell Delineation
Figure 1-11 is an example of a non-IMA application. The M28529 is being used as a stand alone Cell Delineator.
Cell Delineation is performed internally and the M2852x interfaces directly to the framers. These framers could be
T1/E1 or DSL.
There may be applications that require the flexibility of the M28529 in a non-IMA mode.
This mode is also useful for troubleshoot during development since the IMA block is
bypassed. Configuration information is shown in Table 1-17.
NOTE:
Figure 1-11. Non-IMA Application
Table 1-17. Cell Delineation Configuration Information
ATMMux [7,6]
(ATMINTFC, 0xF03)
PhyIntFcSel
(Pin AD24)
Description
10
High
TC Block Direct; Device used as Stand-alone cell delineator with 32 serial ports; IMA block not
used.
®
28529-DSH-001-K
Mindspeed Technologies
65
Mindspeed Proprietary and Confidential
Functional Description
1.7
Source Loopbacks (UTOPIA-to-Serial Configuration Only)
Source loopback checks that the host (the ATM layer) is communicating with the PHY. It is enabled and disabled in
bit 5 of the PMODE register (0x04). When source loopback is enabled for a given port, all data transmitted by the
M2852x on that port is also looped back through the Receive Line Interface. Data from the framer interface is
ignored.
There are two different modes of source loopback, source loopback mode 0 and source loopback mode 1. The
loopbacks work in TC enabled modes.
1.7.1
Source Loopback Mode 0
During source loopback mode 0, the port is automatically placed in General Purpose mode and an internal clock
(IMA_SysClk/2 for IMA mode, atmUTxClk for TC Only mode) is used as the clock to loop back cells. As a result of
the automatic mode switch and clock used, the data on the Tx serial lines will be corrupted.
1.7.2
Source Loopback Mode 1
During source loopback mode 1, the port is not placed in General Purpose mode (the serial framing remains as
configured) and the SPTxCLK and SPTxSync device input signals are routed along with the SPTxDATA to the TC
receive port circuit.
Figure 1-12. Source Loopback Diagram (For simplicity the diagram shows the TC Block Only.)
UTOPIA
Level 2
Framer
(Line)
Interface
Interface
Host
atmUTxClk
Interface
Transmit
UTOPIA
Level 2
atmUTxClAv
atmUTxEnb*
atmUTxSOC
SPTxClk
4-cell
FIFO
ATMCell Transmitter
TC Transmit Port
SPTxSync
* See Note
atmUTxData[15:0]
atmUTxPrty
SPTxData
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
ATM Cell Receiver
4-cell
FIFO
TC Receive Port
Host
Cell Validation
VPI/VCI Screening
Cell
Alignment
atmURxSOC
atmURxData[15:0]
atmURxPrty
Interface
Receive
UTOPIA
Level 2
Loopback
Control
atmURxAddr[4:0]
This segment is replicated for ports 0-31
* SPTxData will be corrupted in in Source Loopback mode 0
®
28529-DSH-001-K
Mindspeed Technologies
66
Mindspeed Proprietary and Confidential
Functional Description
1.8
Far-End Line Loopback (Serial Configuration Only)
Far-End Line loopback verifies Line interface is communicating with the PHY. It is enabled by bit 4 of the PMODE
register (0x04). When line loopback is enabled for a given port, all data received by the M2852x on that port is
processed by the Receive Line Interface and transmitted out the line interface. Data from the Transmit UTOPIA bus
is ignored.
NOTE:
SPTxClk, SPRxClk, SPTxSync, and SPRxSync must be present for
the loopback mode to function properly for a given port.
Figure 1-13. Far-End Line Loopback (This only shows the TC Block.)
Framer
(Line)
UTOPIA
Level 2
Interface
Interface
IMA
Interface
Transmit
UTOPIA
Level 2
atmUTxClk
atmUTxClAv
atmUTxEnb*
atmUTxSOC
SPTxClk
SPTxSync
TC Transmit Port
4-cell
FIFO
ATM Cell Transmitter
atmUTxData[15:0]
atmUTxPrty
SPTxData
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
SPRxClk
4-cell
FIFO
ATM Cell Receiver
TC Receive Port
SPRxSync
SPRxData
SPRxHold
IMA
atmURxSOC
atmURxData[15:0]
atmURxPrty
Cell
Cell Validation
Loopback
Control
Interface
Receive
UTOPIA
Level 2
Alignment VPI/VCI Screening
This segment is replicated for Ports 0 - 7
atmURxAddr[4:0]
General Note:
Configuring a port for line loopback mode disables all UTOPIA signals for that port.
500027_058
®
28529-DSH-001-K
Mindspeed Technologies
67
Mindspeed Proprietary and Confidential
Functional Description
1.9
IMA Line Loopback
IMA line loopback is provided as shown in Figure 1-14. This loopback occurs in the PHY layer UTOPIA interface of
the IMA block. The loopback is functional both when the serial/interleaved (TC enabled) is selected and when the
PHY side UTOPIA interface (TC bypass) is selected. When this loopback is selected, incoming receive data
continues through the IMA processor and is looped back out of the transmit interface.
Figure 1-14. IMA Line Loopback
EXT RAM
INTERFACE
External Memory
Interface Pins
TC PORTS
Cell processor
Cell processor
Line interface 0
Line interface 1
IMA
Internal
512Kx8
SRAM
ATM-SIDE
INTERFACE
0
1
extmemsel pin
iDifferential Delay
memory interface
PHY-SIDE
INTERFACE
Rx Block and
Passthrough
Cell processor Line interface 30
Cell processor Line interface 31
IMA
Engine
Tx Block and
Passthrough
TC
Counters
TC Status
Registers
TC Control
Registers
OneSec
Micro
Clocks
Micro
Interface Pins
IMA clocks
JTAG
JTAG
INTERFACE
MICRO
INTERFACE
1.10
IMA System Loopbacks
IMA system loopback is provided as shown in Figure 1-15. This loopback occurs in the PHY layer UTOPIA
interface in the IMA block. When this loopback is selected, incoming transmit system data is looped back after IMA
processing and continues out the PHY side interface. The loopback is functional regardless of which PHY side
interface mode is selected. There are two different modes of system loopback, IMA System Loopback 0 and IMA
System loopback 1.
1.10.1
IMA System Loopback 0
During IMA System Loopback 0, data is looped back at the PHY Layer UL2 Interface. The TxClav signals from the
PHY (TC or External) are used for handshaking and data is passed through the TC Block to the serial interface (if
the TC block is enabled) or is routed to the PHY side UTOPIA Interface (if the TC block is disabled).
®
28529-DSH-001-K
Mindspeed Technologies
68
Mindspeed Proprietary and Confidential
Functional Description
1.10.2
IMA System Loopback 1
During IMA System loopback 1, data is looped back at the PHY Layer UL2 Interface, but the TxCLAV signals are
ignored from the PHY layer. Data is not passed through the TC Block during this mode.
Figure 1-15. IMA System Loopback
During IMA System Loopback 0 data will flow
through the TC block to the serial interface if
EXT RAM
INTERFACE
enabled.
External
Memory
Interface Pins
TC PORTS
Cell
processor
Line interface
0
Cell
processor
Line interface
1
IMA
Internal
512Kx8
SRAM
ATM-SIDE
INTERFACE
0
1
extmemsel
pin
iDifferential Delay
memory interface
PHY-SIDE
INTERFACE
Rx Block and Passthrough
Cell
processor
Line interface
30
IMA
Engine
Cell
processor
Line interface
31
Tx Block and Passthrough
T
CouCnter
s
TC
TC
Status
Control
Registers
Registers
OneSe
c
Micro
Clocks
Micro
Interface Pins
JTA
G
IMA clocks
Duing IMA System loopback 0, if
UTOPIA-UTOPIA mode is selected,
the TxClav signals will be used for
handshaking and data will flow to the
PHY side UTOPIA interface.
JTAG
INTERFACE
MICRO
INTERFACE
1.11
Reference Designs
Please contact Mindspeed for information on reference designs and schematic examples.
1.12
IMA Clocks
IMA frame rates must be locked to the PHY payload rates (the bandwidth reserved for ATM cells) used by those
PHY ports designated as IMA timing reference links. This applies to both the Transmit and Receive directions. IMA
frame rates can be derived from a number of sources:
•
•
IMA_SysClk
•
•
Fixed Divide-By-24 or
Programmable divider
IMA_RefClk
®
28529-DSH-001-K
Mindspeed Technologies
69
Mindspeed Proprietary and Confidential
Functional Description
•
•
Line rate clock input or
Programmable divider
•
•
SPRxClk or IHRxClk
PHY Line/Payload rate clock
Rx PHY side cell stream
PHY payload rate derived (synthesized) from cell transfer rate across PHY side UTOPIA interface
•
•
It should be noted that the IMA frame rates can not be directly derived from the SPTxClk[31:0] inputs.
In a typical application (see Case 1 in Table 1-18), the Tx direction is referenced from local clock sources whereas
the Rx direction is slaved to the FE Tx. It is also quite common (Case 2 in Table 1-18) for the Tx direction to be
slaved to the FE Tx, often using the same source as the Rx direction. In some rarer applications, (Case 3 in
Table 1-18) both the Tx and Rx directions are referenced from local clock sources.
Table 1-18. Reference Clock Configurations / Sources
Tx Direction
Possible Sources
Rx Direction
Case
Configuration
Configuration
Sources
1
Master / Internal
IMA_SysClk
IMA_RefClk
Slave / External
SPRxClk or IHRxClk
Rx Cell stream
(1)
IMA_SysClk or IMA_RefClk
2
Slave / External
Master / Internal
SPRxClk or IHRxClk
Rx Cell stream
IMA_SysClk or IMA_RefClk
Slave / External
Master / Internal
SPRxClk or IHRxClk
Rx Cell stream
IMA_SysClk or IMA_RefClk
(2)
3
IMA_SysClk
IMA_RefClk
IMA_SysClk
IMA_RefClk
Footnotes:
(1) These sources provide a “last resort” clock in case no valid timing can be derived from Rx side sources.
(2) This case assumes the FE Tx is loop timed to the NE Tx; this will limit applications. It is also applicable in loopback testing.
Internally the IMA engine generates a Transmit Data Cell Rate clock (Tx IDCR) to match the exact cell rate of each
group in the transmit side of the IMA device. The IMA engine also generates a Receive Data Cell Rate clock (Rx
IDCR) to match receive cell rate for each group and operates the Receive Cell Smoothing buffer. There is a Tx
IDCR and Rx IDCR for each of the 32 groups that the M28529 supports.
The M28529 also provides two clock outputs: Tx_TRL[1] and Tx_TRL[0]. These can be used to output one of the
reference clock inputs or generate an 8 KHz reference that is phase locked to IMA_SysClk or IMA_RefClk
(whichever is used as a timing reference).
Figure 1-16 shows the details of the M28529's IMA clock block from Figure 1-1. This block is responsible for
generating all clocks required by the IMA engine. It can be further divided into 8 sections, as shown in Table 1-19:
®
28529-DSH-001-K
Mindspeed Technologies
70
Mindspeed Proprietary and Confidential
Functional Description
Table 1-19. IMA Block Clock Sections
Clock Section
Description
Serial Port Synchronizer
IMA_SysClk Dividers
This block contains a transition detector and a synchronizer. It synchronizes the clocks from the TC block Serial ports to
the IMA_SysClk divided by 16 and the rate multiplier (RM). It handles all 32 internal serial ports independently. The rate
multiplier is configured to values 1, 2, or 4 based on the range of the link rate.
This block contains two dividers: a divide by 16, a divide by 24, and divide by rate multiplier (RM). The divide_16 is
used to synchronize external clocks to internal logic. The divide_24 allows the IMA_SysClk to be used to generate both
the Rx IDCR and the Tx IDCR clocks (provided that IMA_SysClk is 24 times the bit rate).
IMA_RefClk Synchronizer
This block contains a transition detector and a synchronizer. It synchronizes the IMA_RefClk to the IMA_SysClk divided
by 16 and the RM factor.
IDCR Source Mux
Rx IDCR Clock
This software controlled mux selects which clock sources are feed to the appropriate IDCR clock dividers.
This block divides the bit rate clock down to a link cell data rate clock based on the values of frame length (M), number
of links in the group (N), frame payload (P) and frame bit (F), then adjusts based on the rate multiplier (RM). (The 2048/
2049 factor results from the IMA standards requirement of inserting a stuff event every 2048 cells.) This block can
generate 16 independent Rx IDCR clock outputs (one per group).
Tx IDCR Clock
This block divides the bit rate clock down to a Link cell data rate clock based on the values of frame length (M), number
of links in the group (N), frame payload (P) and frame bit (F), then adjusts based on the rate multiplier (RM). (The 2048/
2049 factor results from the IMA standards requirement of inserting a stuff event every 2048 cells.) This block can
generate 16 independent Rx IDCR clock outputs (one per group).
Bit Rate Clock Generator
This block generates a clock that represents the link data rate. It can generate 16 independent Tx and 16 independent Rx
clocks. In normal operation, all parameters are configured automatically by the software driver. It contains the following
blocks:
• Pre-scaler—This block divides the selected input (either IMA_RefClk or IMA_SysClk) by the factor of Pnum divided
by Pden.
• Synchronizer—Synchronizes the Pre-Scaler output to the internal logic using the IMA_SysClk divided by 16 and the
RM factor.
• Numerically Controlled Oscillator—This clock circuit generates the link bit rate.
Digital Phase Locked Loop This block generates a bit rate clock that is phase locked to the PHY side RxClAv signal. It can monitor all 32 ports on
the bus. Any port can be selected as the group timing reference.
®
28529-DSH-001-K
Mindspeed Technologies
71
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-16. M28529 Clock Diagram
IDCR Clk Mux
Rx Mux
Note 1
Tx Mux
Note 1
®
28529-DSH-001-K
Mindspeed Technologies
72
Mindspeed Proprietary and Confidential
Functional Description
1.12.1
IMA Link Rates
In addition to supporting standard T1/E1 bit rates, the M2852x devices support fractional T1/E1 and DSL rates
from 64 kbps to more than 8.192 Mbps. The actual nominal link rate must be configured through software
parameters. Section 1.12.2.2 discusses the input clock requirements. When operating the device with only a single
link rate used for all IMA groups, any link rate within the specified range is possible. A reference clock synchronous
with that link rate must be provided to the device.
For multi-rate applications, internal timing generators (includes the synthesizers) within the device must be
supplied a reference clock with sufficient accuracy and resolution to generate the required bit rates. The following
relationship between link rate and IMA_SysClk frequency exists:
Table 1-20. Link Rate Resolution for Variable Rate Applications (direct serial clock)
IMA_SysClk/16 < Link Rate <
Link Rate < IMA_SysClk/16
Link Rate > IMA_SysClk/8
IMA_SysClk/8
Link Rate
n x 8 kbps
n x 16 kbps
n x 32 kbps
As an example, if IMA_SysClk is 49.152 MHz, the link rate boundaries occur at 3.072 Mbps and 6.144 Mbps. The
maximum IMA link rate is given by IMA_SysClk/4, or 12.288 Mbps.
When using the internal bit rate clock generator, the resolution boundaries and maximum link rate are a function of
the “intermediate” frequency (output of the Prescalar) selected. The “intermediate” frequency is a function of the
frequency of the input reference clock (IMA_SysClk or IMA_RefClk) and the resolution of the prescalar (8 bits).
This “intermediate” frequency (INT_FREQ) is limited to IMA_SysClk/16 due to internal synchronization. At this
limit, the values of Table 1-21 apply. But it is also likely that the “intermediate” frequency will be lower than
IMA_SysClk/16 and the following applies:
Table 1-21. Link Rate Resolution for Variable Rate Applications (internal bit rate generator)
Link Rate < INT_FREQ
INT_FREQ < Link Rate < INT_FREQ/2
Link Rate > INT_FREQ/2
Link Rate
n x 8 kbps
n x 16 kbps
n x 32 kbps
Returning to the example of IMA_SysClk = 49.152 MHz, if INT_FREQ = 2.56 MHz, then the rate boundaries occur
at 2.56 Mbps and 5.12 Mbps, with a maximum link rate of 10.24 Mbps.
1.12.2
Clock Input Requirements
The system designer must select the frequencies of IMA_SysClk and IMA_RefClk such that the IMA core can
process the aggregate cell bandwidth (BW), sample the serial clocks, and the IMA frame rates can be derived.
1.12.2.1
Aggregate Cell Bandwidth
The maximum aggregate cell bandwidth requirement (rule of thumb) is a function of the frequency of IMA_SysClk
and the number of active IMA groups. The following are empirically determined limits when operating with 1 or
more IMA groups:
•
32 IMA groups:
•
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (20 / 9).
•
16 IMA groups
•
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (24 / 9).
®
28529-DSH-001-K
Mindspeed Technologies
73
Mindspeed Proprietary and Confidential
Functional Description
•
•
1 IMA group
•
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (28 / 9).
If only pass-throughs are enabled, then the aggregate cell bandwidth limitation is:
•
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (16 / 5)
Table 1-22 list some examples.
Table 1-22. Maximum Aggregate Bandwidth Examples
IMA_SysClk
# ports
# groups
Maximum BW (Mbps)
49.152 MHz
1-32
1-32
1-32
1-32
1-32
1-32
1-32
1-32
0
1
157.3
152.9
131.1
109.2
211.2
205.3
176.0
146.7
≤ 16
≤ 32
0
66 MHz
1
≤ 16
≤ 32
As an example, setting IMA_SysClk = 49.152 MHz constrains the Maximum Aggregate BW to be less than 152.9
Mbps for configurations with at least 1 IMA group. For a 32 port application, depending on the number of active IMA
groups, this implies a maximum aggregate BW in the range of 109.2 - 152.9 Mbps with an average link BW in the
range of 3.41 - 4.78 Mbps.
As another example, for a 16 port application, with 16 IMA groups, the average link BW would be limited to 8.192
Mbps (131.1 Mbps / 16). This average link rate would increase if less than 16 IMA groups were active.
1.12.2.2
Serial Clock Sampling
IMA_SysClk is also used to sample the serial receive clocks (SPRxClk) and IMA_RefClk. These sampled signals
are used for IMA frame rate generation. When operating with the Interleaved Highway interface enabled, the 4x
input clock (IHRxClk) is first divided by 4 before being distributed to the IMA block where it is sampled. If the serial
interface is operating in fractional T1/E1 mode, either directly or using the Interleaved Highway interface, the
resulting “gated” clock being routed over to the IMA core is not used.
The requirements of the SPRxClk, IHRxClk, and IMA_RefClk inputs are summarized below:
®
28529-DSH-001-K
Mindspeed Technologies
74
Mindspeed Proprietary and Confidential
Functional Description
Table 1-23. IMA Serial Clock Requirements
Interface
Clock Period (1)
IMA Link Rate
Maximum (2)
Signal
Mode
Maximum
Minimum
SPRxClk
T1/E1/DSL
FT1/FE1
T1/E1
256 / IMA_SysClk
N/A
4 / IMA_SysClk
N/A
Min (4 / IMA_SysClk, INT_FREQ / 4)
INT_FREQ / 4
IHRxClk
N/A, f = 8.192 MHz
1.920 Mbps
N/A
N/A
2.048 Mbps
FT1/FE1
All
IMA_RefClk (3)
256 / IMA_SysClk
16 / IMA_SysClk
IMA_SysClk / 16
Footnotes:
(1) Clock period is shown since the sampling circuit is sensitive to the interval between rising edges of the clock signal.
(2) Limit is a function of whether bit rate generator is used. If not used, then IMA_SysClk caps the link rate. If used, the intermediate
frequency (INT_FREQ) determines the maximum link rate with the requirement that INT_FREQ ≤ IMA_SysClk / 16.
(3) IMA_RefClk used as a line rate reference; In this case, IMA_RefClk is not used as a reference for the internal bit rate generator.
1.12.2.3
Clock Generator Reference
The internal clock generators and synthesizers operate in the IMA_SysClk domain but are referenced from either
the IMA_SysClk or IMA_RefClk input. Due to internal synchronization circuitry, the following restriction applies to
the IMA_RefClk input when it is used as a reference for these generators:
Frequency of IMA_RefClk > Frequency of IMA_SysClk / 16
1.12.3
Summary Examples
The preceding sections listed many constraints on the IMA_SysClk and IMA_RefClk inputs. Table 1-24 provides
some simplified (and conservative) examples for these two clock signals.
®
28529-DSH-001-K
Mindspeed Technologies
75
Mindspeed Proprietary and Confidential
Functional Description
Table 1-24. IMA Reference Clock Summary Examples
PHY Interface
IMA_SysClk
Requirements
IMA_RefClk
Type
Mode
# Ports
Ref?(1)
Ref?
Requirements
T1/E1
Serial
≤ 32
Yes
T1: 37.056 MHz
E1: 49.152 MHz
Opt.
T1: 1.544 MHz
E1: 2.048 MHz
(2)
(3)
No
T1: ≥ 36.23 MHz (typical LIU)
Yes
N/A
T1: 1.544 or 1.536 MHz
E1: ≥ 48.06 MHz (typical LIU)
E1: 2.048 or 1.920 MHz
(4)
DSL
Serial
≤ 24
> 24
≤ 24
> 24
≤ 24
> 24
≤ 24
> 24
Yes
n x 8 kHz, ≥ 40.96 MHz
n x 8 kHz, ≥ 49.152 MHz
≥ 40.96 MHz
No
Yes
No
Yes
N/A
Yes
n x 8 kHz, ≥ 4.64 MHz
≥ 49.152 MHz
T1/E1/
DSL
UTOPIA
n x 8 kHz, ≥ 40.96 MHz
n x 8 kHz, ≥ 49.152 MHz
≥ 40.96 MHz
n x 8 kHz, ≥ 4.64 MHz
≥ 49.152 MHz
Footnotes:
(1) Indicates whether the clock signal is used as a timing reference.
(2) Frequency determined based on sampling SPRxCLk as described in Section 1.12.2.2.
(3) A line or payload rate clock signal may be used. A payload rate can only be used if all possible references (e.g., SPRxClk) are also payload
rate clocks.
(4) 40.96 MHz is selected as a minimum frequency for G.shdsl applications.
1.12.4
Typical Clock Configurations
1.12.4.1
Serial Mode (using internal TC)
Figure 1-17 and Figure 1-18 show simplified applications that utilize the serial interfaces and internal TC block of
the M28529 device. The block labeled “clock selection” in each figure may take on many forms depending on the
clock configuration / sources and specific capabilities of the LIU and Framer devices used in a given system
application.
1.12.4.1.1
T1/E1 Configurations
In the most common T1/E1 application (shown in Figure 1-17), T1/E1 line rate clocks and IMA_SysClk are used to
provide timing references. The M28529 device has internal dividers that generate the proper PHY payload rates
(1.536 Mbps / 1.920 Mbps) necessary for IMA frame generation. Since the line rate clocks are accessible within the
M28529 device and all facilities operate at the same nominal rate, although they may be asynchronous, no
programmable clock dividers or synthesizers tend to be used in these applications. Asynchronous facilities are
allowed in Independent Transmit Clock (ITC) mode and are accommodated using the IMA stuffing mechanism.
®
28529-DSH-001-K
Mindspeed Technologies
76
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-17. Typical T1/E1 Configurations
Clock
1x Clock
Source
Selection
1.544 MHz (T1)
or
1.544 MHz (T1)
or
2.048 MHz (E1)
2.048 MHz (E1)
Tx_TRL[1:0] IMA_RefClk
24x
Oscillator
SPRxClk[0]
SPTxClk[0]
T1/E1
32
LIU
Framer
IMA_SysClk
37.056 MHz (T1)
or
49.152 MHz (E1)
M28529
32
SPRxClk[31]
SPTxClk[31]
T1/E1
LIU
Framer
In the fractional T1/E1 application, the n x 64 kbps link rates are usually supported by relying on the programmable
dividers and clock synthesizers within the M28529 device rather than reliance on the serial clocks themselves. The
clock reference for these dividers and synthesizers is either IMA_SysClk or IMA_RefClk. Whichever input is being
used, it must be an integer multiple of 8 kHz. For IMA_SysClk, the same 24x frequency as shown in Figure 1-17
can be used but any frequency in the range of 33 - 66 MHz is permissible, subject to the restrictions discussed in
Section 1.12.2.
1.12.4.1.2
DSL Configurations
The DSL application is similar to the fractional T1/E1 in the sense that the serial clocks are not often used directly
as timing references. The link rates are usually set within the DSL transceiver as a programmable derivative of the
“system clock” provided to that device. In some cases, an 8 kHz Network Timing Reference (NTR) signal affects
the generated rate.
For the IMA frame rates to be locked when operating in the “Master / Internal” configuration, the M28529 and the
DSL transceivers must have clocks that are derived from the same source. Often, this is a simple matter of
connecting the DSL System Clock to the IMA_RefClk pin or using the IMA_SysClk signal as the source of the DSL
System Clock. The “Slave / External” configuration usually relies on the clock synthesizers.
®
28529-DSH-001-K
Mindspeed Technologies
77
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-18. Serial DSL Configurations
Local
DSL Clock
Oscillator
Clock
Selection
NTR Source
DSL System
Clock
8 kHz
NTR
Tx_TRL[0] IMA_RefClk
DSL
SPRxClk[0] IMA_SysClk
SPTxClk[0]
I/F
DSP
Framer
33 - 66 MHz
32
32
M28529
NTR
DSL
SPRxClk[31]
SPTxClk[31]
I/F
DSP
Framer
1.12.4.2
UTOPIA Mode
The UTOPIA mode applications are similar to the serial mode but the serial clocks are not typically used (or always
available). In UTOPIA mode, the M28529 device only has the SPRxClk[23:0] inputs available for those applications
that can take advantage of them. As noted, these aren’t typically used.
1.12.4.2.1
T1/E1 Configurations
The T1/E1 UTOPIA application is shown in Figure 1-19. It is similar to Figure 1-17 with the TC blocks external to
the M28529 device. Since the device does not provide 32 serial clocks, the IMA function most often is configured to
use its internal clock synthesizers when operating in the “Slave / External” configuration. This approach is used
when operating in fractional T1/E1 applications.
®
28529-DSH-001-K
Mindspeed Technologies
78
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-19. T1/E1 Configurations (UTOPIA Mode)
Clock
1x Clock
Source
Selection
1.544 MHz (T1)
or
1.544 MHz (T1)
or
2.048 MHz (E1)
2.048 MHz (E1)
Tx_TRL[1:0] IMA_RefClk
SPRxClk[0]
24x
Oscillator
T1/E1
LIU
LIU
Framer
Framer
TC
TC
IMA_SysClk
37.056 MHz (T1)
or
M28529
49.152 MHz (E1)
SPRxClk[23]
T1/E1
1.12.4.2.2
DSL Configurations
Since the serial clocks are not typically used as timing references when operating in DSL applications, the UTOPIA
mode configurations are similar to the Serial mode configurations. Figure 1-20 shows the DSL UTOPIA application.
Figure 1-20. DSL Configurations (UTOPIA Mode)
Local
DSL Clock
Oscillator
Clock
Selection
NTR Source
8 kHz
DSL System
Clock
NTR
Tx_TRL[0] IMA_RefClk
33 - 66 MHz
IMA_SysClk
PHY Rx UTOPIA
DSL
I/F
DSP
Framer
TC
M28529
32
32
NTR
DSL
I/F
DSP
Framer
TC
Phy Tx UTOPIA
®
28529-DSH-001-K
Mindspeed Technologies
79
Mindspeed Proprietary and Confidential
Functional Description
The solution for high port count and variable rate DSL applications is to use internal counters and frequency
synthesizers referenced from a common (n x y kHz) clock input with feedback from the cell available signal from the
PHY side UTOPIA bus.
For low port count, single rate applications that take advantage of the embedded ATM Cell Processor, the use of
receive bit clock inputs is the most straight-forward solution.
1.12.5
IMA Internal Timing Examples
T1/E1 Using Internal Serial Ports
1.12.5.1
1.12.5.1.1
Using IMA_SysClk as the Transmit Clock
Figure 1-21 illustrates T1/E1 with internal serial ports, using IMA_SysClk equal to 24 times the line rate. This is one
of the simplest implementations of IMA when a clock equal to 24 times the line rate is available. Several issues are
worth noting:
•
The IMA_RefClk input is unused and should be tied to ground. The M28529 is deriving all required clocks from
the Serial port clocks and the IMA_SysClk.
•
•
The IMA_SysClk is used to synchronize the SPRxClk inputs to internal logic (via the divide by 16 block).
The SPRxClk is being used to generate the Rx IDCR clock. Also note that the receive clock from any link within
a group could be used to generate the Rx IDCR for that group.
•
The IMA_SysClk is being used to derive the TX IDCR clock.
The device is configured using a software driver. The following code is an example of calls to the driver:
IMA_LINK_TYPE = IMA_DS1
IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE
IMA_DSL_REF_GENERATOR = IMA_INACTIVE
IMA_ALT_RX_TRL = IMA_INACTIVE
IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#)
IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#)
®
28529-DSH-001-K
Mindspeed Technologies
80
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-21. T1/E1 using Internal Serial ports; IMA_SysClk equals 24x line rate
TxClav Transition
up/down adjust
n*8kHz
Phase
NCO
Comparator
1
RM
RM
424
Transition
Detector
1
RM
SPRxClk 0
Synchronizer
ref
IMA_RefClk
NOT USED;
tie to ground
n*8kHz
NCO
Note 2
1
RM
Pre-Scaler
Synchronizer
ref
IMA_SysClk
24 x line rate
/16
/24
n*8kHz
NCO
Note 2
ref
Synchronizer
1
RM
Transition
Detector
General Notes:
1. SPRxCLK 1-31 are identical but not shown for clarity
2. RM - Rate Multiplier.
1.12.5.1.2
Using IMA_RefClk as the Transmit Clock
Figure 1-22 illustrates T1/E1 with internal serial ports, using IMA_RefClk. There are several important differences
from the first example:
•
In this case, IMA_SysClk is only used by internal logic. It must be greater than or equal to 22 times the line rate
to ensure that internal logic can keep up with the data.
•
•
Again, the SPRxClk is used to generate the RxIDCR clock.
The TX IDCR clocks are generated from the IMA_RefClk. Thus IMA_RefClk must equal 1.544, 1.536, 2.028, or
1.920 MHz depending of the frame format used.
The device is configured using a software driver. The following code is an example of calls to the driver:
®
28529-DSH-001-K
Mindspeed Technologies
81
Mindspeed Proprietary and Confidential
Functional Description
IMA_LINK_TYPE = IMA_DS1
IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE
IMA_DSL_REF_GENERATOR = IMA_INACTIVE
IMA_ALT_RX_TRL = IMA_INACTIVE
IMA_GRP_TX_TRL_SRC = IMA_REF_CLK1 (grp#)
IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#)
Figure 1-22. T1/E1 using Internal Serial ports; IMA_RefClk equals line rate
TxClav Transition
up/down adjust
n*8kHz
NCO
Phase
Comparator
1
RM
RM
424
IDCR Clk Mux
Transition
Detector
1
RM
SPRxClk 0
Synchronizer
rreeff
IMA_RefClk
n*8kHz
NCO
Note 2
1
RM
Pre-Scaler
Synchronizer
ref
IMA_SysClk
24 x line rate
/16
/24
n*8kHz
NCO
Note 2
ref
Synchronizer
1
RM
Transition
Detector
General Notes:
1. SPRxCLK 1-31 are identical but not shown for clarity
2. RM - Rate Multiplier.
1.12.5.2
DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces
Figure 1-23 illustrates the configuration most commonly used with applications that require more the TC block to be
external. Up to 32 links and 32 groups can be supported using external Cell Delineators. For the discussion below,
assume the link rates are less than 3.072 Mbps.
®
28529-DSH-001-K
Mindspeed Technologies
82
Mindspeed Proprietary and Confidential
Functional Description
•
The Rx IDCR clock is synthesized using the RxClAv input from the PHY side UTPOIA bus. This is performed
on a per group basis; that is, one link in each group is selected (via software) to provide the Rx IDCR for that
group.
•
•
IMA_SysClk must be greater than or equal to 40.96 MHz (less than 24 ports) and be greater than or equal to
49.152 MHz if there are more than 24 ports.
Either IMA_SysClk or IMA_RefClk can be used as the Tx IDCR clock:
•
•
IMA_SysClk may be used if it is an 8 kHz multiple of the bit rate.
IMA_RefClk may be used if it is an 8 kHz multiple of the bit rate and greater than or equal to 4.64 MHz.
The device is configured using a software driver. The following code is an example of calls to the driver:
IMA_LINK_TYPE = IMA_VAR_RATE
IMA_DSL_REF_CLK_FREQUENCY = 40960000
IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE
IMA_DSL_REF_GENERATOR = IMA_ACTIVE
IMA_ALT_RX_TRL = IMA_ACTIVE
IMA_GRP_LINK_BANDWIDTH = 2304 (grp#)
IMA_GRP_CLK_REF_FACTOR = IMA_NO_DIV (grp#)
IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#)
IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#)
®
28529-DSH-001-K
Mindspeed Technologies
83
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-23. DSL—UTOPIA-to-UTOPIA
TxClav Transition
up/down adjust
n*8kHz
NCO
Phase
Comparator
1
RM
RM
424
Transition
1
RM
SPRxClk 0
Detector
Synchronizer
ref
IMA_RefClk
n*8kHz
NCO
Note 2
1
RM
Pre-Scaler
Synchronizer
ref
IMA_SysClk
24 x line rate
/16
/24
n*8kHz
NCO
Note 2
ref
Synchronizer
1
RM
Transition
Detector
General Notes:
1. SPRxCLK 1-31 are identical but not shown for clarity
2. NCO - Numerically controlled oscillator; controlled by parameters in Register 816 and 817.
2. RM - Rate Multiplier.
1.13
UTOPIA Interfaces
The M2852x supports multi-PHY operation as described in the UTOPIA Level specification (AF-PHY-0039.000, see
www.atmforum.com). This standard allows up to 31 ports to be interfaced to both the ATM and PHY side interfaces.
The interfaces use either 8-bit or 16-bit wide data buses, and cell-level handshaking.
Each of the M2852x's UTOPIA blocks have two sections, transmit and receive. For the ATM interface, on the
transmit side, ATM cell data is placed in the transmit FIFOs where it can then be passed to the ATM cell processing
block. On the receive side of the UTOPIA interface, incoming cells are placed in the receive FIFO until sent. Both
FIFOs on the ATM side are 4 cells deep.
®
28529-DSH-001-K
Mindspeed Technologies
84
Mindspeed Proprietary and Confidential
Functional Description
With regard to IMA, each IMA group is considered one logical port and will only take up one UTOPIA address. For
example, a group with 8 T1 links could be assigned to address 0; the IMA engine handles the translation between
the ATM layer and the physical links. In addition, each pass-though connection also requires one address.
NOTE:
By convention, data being transferred from the PHY to the ATM layer
is considered received data, while data from the ATM layer to the
PHY is called transmitted data.
To provide maximum flexibility for system design the M28529 has 3 UTOPIA Level 2 interface modes. This allows
the M28529 to be used in either UTOPIA-to-UTOPIA or UTOPIA-to-Serial IMA applications or it can function as a
stand-alone cell delineator block. These interfaces are shown in Figure 1-26 and described below.
1. IMA direct—This interface allows the ATM layer to interface directly to the IMA engine. This would be the
normal mode for all IMA applications. It is controlled by registers in the IMA section.
2. TC block direct—This interface is selected when the IMA engine is disabled and the device is being used as a
stand-alone cell delineator. It may also be invoked during troubleshooting to verify serial port operation without
having to run the IMA drivers. It is configured by registers in the TC section.
3. PHY side UTOPIA—This interface is selected when the TC block is disabled and the designer wishes to
interface to a device via an UTOPIA interface. This allows the M28529 IMA engine to address up to 32 ports on
the line side.
1.13.1
General UTOPIA Operation
Three primary functions are performed by the UTOPIA controller: polling, selection, and data transfer. These
functions are basically the same for both the transmit and receive sides of the UTOPIA bus. The following example
describes the transmit functions. Refer to Figure 1-24.
The ATM layer UTOPIA controller polls the connected PHY ports by transmitting the port addresses on the
UTxAddr lines. If a port is ready to transfer data, it asserts UTxClAv. Note that the process of polling a port does
NOT result in that port being selected to transfer data! Polling allows the controller to determine which port is ready
for data; it must then select that port before sending data. It does so by reasserting the desired address and then
asserting UtxEnb*. The PHY will then be ready to transfer data on the UTxData lines. UTxEnb* is deasserted when
the transfer is completed. Polling can continue during the data transfer process but not during port selection. It
operates independently of the state of UTxEnb*.
To pause the data transfer, UTxEnb* can be deasserted. To continue the transfer, the controller must reselect the
port by transmitting its address one clock cycle before asserting UTxEnb*. The controller must ensure that the cell
transfer from this port has been completed, to avoid a start-of-cell error.
On the ATM side, the UTOPIA interface is a slave. On the PHY side, the UTOPIA interface is a master.
1.13.2
UTOPIA 8-bit and 16-bit Bus Widths (PHY and ATM)
The ATM side UTOPIA interface on the M2852x devices have two bus width options, 8-bit or 16-bit, depending on
the selection of AtmBusWidth, bit 5, of the ATMINTFC register (0xF03). The PHY side UTOPIA interface also has
two bus width options 8-bit or 16-bit, depending on the selection of PHYBusWidth, bit 5, of the PHYINTFC register
(0xF02).
The protocols and timing are the same in both modes, except that 8-bit mode uses only the lower half of the data
bus (TxData[7:0] and RxData[7:0]) and odd parity is only generated or checked over those bits. The ATM-Side
UTOPIA Level 2 interface operates up to 50 MHz in 16 bit mode (Note: 33 MHz for TC Mode Only) and 33 MHz in
8 bit mode. The PHY-Side UTOPIA interface operates at half the IMA_Sysclk rate (IMA_SysClk/2)
®
28529-DSH-001-K
Mindspeed Technologies
85
Mindspeed Proprietary and Confidential
Functional Description
In 8-bit mode, each ATM cell consists of 53 bytes. The first five bytes are used for header information. The
remaining bytes are used for payload.
In 16-bit mode, the cell consists of 54 bytes. The first five bytes contain header information. The sixth byte, UDF2,
is required to maintain alignment but is not read by the M2852x. The remaining bytes are used for payload.
1.13.3
UTOPIA Interface Blocks
1.13.3.1
IMA UTOPIA
This is the normal interface for IMA applications and is selected as shown in Table 1-25.
It is intended to interface to a single ATM Layer device and appear as a multi-port PHY device. Figure 1-24
illustrates the connections to/from the ATM Layer device. The number of “ports” or channels on the IMA Subsystem
is the sum of the number of configured IMA groups plus the number of pass-through facilities. The IMA M28529
requires a unique UTOPIA address for each channel (IMA group or pass-through). There are no restrictions placed
on the address assignment and not all 32 locations are normally used.
In IMA UTOPIA mode, the UTOPIA interface can operate with single Clav/Enb or Dual Clav/Enb handshaking. The
default configuration is for single Clav/Enb handshaking (See register 0xF03 ATMINTFC for more information).
When operated in single Clav/Enb mode, the UTOPIA bus address 0x1F can be configured as a valid port address
and not a null address, note this is nonstandard from the UTOPIA specification and must be supported by
connective devices.
When using dual Clav/Enb mode, Clav0/Enb0 are assigned to addresses 0x0 - 0xF while Clav1/Enb1are assigned
to addresses 0x10 - 0x1F. Note that only the first 4 bits[3:0] of the 5 bit address bus are used internally, bit 4 is
ignored. For example, if Clav is supposed to be active for addresses 0x1 and 0x11, polling with address 0x1 on the
address bus will cause Clav0 to be asserted and Clav1 to be asserted.
Dual Clav/Enb does not allow multiple M28529 devices to interface with a single ATM Layer
device on the ATM-side UTOPIA Interface. Multiple M28529 devices cannot share one
Utopia bus with an ATM-layer device.
NOTE:
If only one channel is programmed, (a single IMA group and no pass-through facilities), then the M28529 can be
compatible with UTOPIA Level 1 by fixing the address lines to a specific value and setting the IMA group’s ATM
address (through the software driver) to that value.
The M28529 provides numerous options to match non-standard UTOPIA controllers. See the
IMA_ATM_UTOPIA_BUS_CTL register, 0x813, for more information.
In single Clav mode, address 0x1F can be assigned as a valid port address to enable 32
unique addresses.
NOTE:
The behavior of Clav when a port is not selected can be set to either driven low or tri-state.
See the IMA_ATM_UTOPIA_BUS_CTL register, 0x813, bit 1.
®
28529-DSH-001-K
Mindspeed Technologies
86
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-24. ATM Layer UTOPIA Interface Connections
atmUTOPIA Tx data/
address bus
atmUTxClav_0
atmUTxEnb_0
ATM Layer
Device
PHY Layer
Utopia Bus
M28529
atmUTxClav_1
atmUTxEnb_1
Note: Only Transmit side drawn for Clarity
1.13.3.2
TC Block UTOPIA
This interface is selected when using the device as a stand-alone cell delineator. See Table 1-25 and Section 1.6. It
interfaces to the ATM layer as a normal UTOPIA Level 2 interface with the following enhancements.
UDF2 Programmability
The user can program the contents of the UDF2 byte when operating in 16-bit UTOPIA mode. By default, the
contents of the UDF2 byte on the receive interface will match the default value of the UTOPIA port address. This
can be changed by writing the desired value to the corresponding UDF2 control register, 0x0F. Bus width is
controlled by bit 5 of the ATMINTFC register.
Port Number Assignment
The UTOPIA address for each port is stored in bits 0–4 of the UTOP2 register (0x0E). The default for this value is
the port number. For example, the UTOP2 register for port 4 (0x10E [with the offset]) defaults to 04 hex. However,
the value can be changed to any value from 00–1E hex by programming the register to accommodate multiple
devices on the same UTOPIA bus. The value 1F hex is reserved for the null address. The UTOPIA address should
be changed only when the device or port is in the reset state.
HEC Override
In normal operation, the HEC is calculated by the TC layer and put in byte 5, UDF1. This may be overridden by
setting bit 7 of the CGEN register (0x08) to a 1. In this case, data inserted by the ATM layer into byte 5 is
transmitted unchanged by the device.
Table 1-25. Device Configuration Options
ATMMux [7,6]
(ATMINTFC, 0xF03)
PhyIntFcSel
(Pin AD24)
Description
01
01
10
Low
High
High
IMA UTOPIA using the PHY Side UTOPIA; UTOPIA-to-UTOPIA; TC block/serial ports not
used.
IMA UTOPIA using Internal TC block;
UTOPIA-to-Serial mode; 32 internal serial ports
TC only; Device used as Stand-alone cell delineator with 32 serial ports; IMA block not
used.
®
28529-DSH-001-K
Mindspeed Technologies
87
Mindspeed Proprietary and Confidential
Functional Description
In TC Block UTOPIA mode, both Single and Dual Clav/Enb modes are supported, however the Single Clav/Enb
mode only supports 31 addresses. UTOPIA address 0x1F is a null address. In dual Clav/Enb mode, the device can
respond as 32 unique phy devices (by sharing the same address but using different Clav/Enb’s), however address
0x1F is still a null address.
1.13.3.3
PHY-Side UTOPIA
An ATM forum compliant UTOPIA interface is provided for interfacing to PHY layer devices. Several unique features
should be noted:
1. It is only UTOPIA level 2.
2. This bus supports 8-bit and 16-bit wide data paths.
3. The UTOPIA interface has a second set of control lines (Dual Clav/Enb), which allow up to 32 ATM devices to
be connected to the bus. These can be connected as shown in Figure 1-25. This effectively provides two buses
with up to 16 devices each, all sharing common address and data lines but with separate control lines.
(Remember, UTOPIA uses address 0x1F as the null address thus limiting the bus to 31 ports. However, the
standard also allows for multiple ClAv and Enable lines.)
4. When using only a single Clav/Enb the device can be programmed to recognize null address 0x1F as a valid
address. Note that the TC block does not support 0x1F as an address. Thus when using the Utopia-Serial
configuration, dual Clav/Enb must be used if 32 ports are desired.
Figure 1-25. M28529 Multiple UTOPIA Control Lines
IMA Link
Number
1
CX28985
UTOPIA Port 0−7
8
UTOPIA data/
9
address bus
phyUTxClav_0
CX28985
UTOPIA Port 8−15
ATM Layer
phyUTxEnb_0
M28529
UTOPIA bus
phyUTxClav_1
phyUTxEnb_1
16
17
CX28985
UTOPIA Port 0−7
24
25
CX28985
UTOPIA Port 8−15
32
General Note:
Only the Transmit side is shown for clarity. The Receive side is identical.
500027_056
®
28529-DSH-001-K
Mindspeed Technologies
88
Mindspeed Proprietary and Confidential
Functional Description
1.13.4
Dual Clav/Enb Operation
The UTOPIA level 2 specification allows for 31 unique addresses 0-30 to be assigned to devices on the UTOPIA
bus. UTOPIA address 31 is a Null address. While both the ATM and PHY side Utopia support the null address
assigned as a valid address, many connecting devices may not support this. To alleviate this, the dual Clav/Enb
mode is available to support all 32 ports. When using Dual Clav/Enb, the UTOPIA port will respond to either Clav0/
Enb0 or Clav1/Enb1 depending on the port. For the ATM side, Clav0/Enb0 is assigned to port 0 - 15 and Clav1/
Enb1 is assigned to port 16-32. Enabling of dual Clav/Enb mode for the ATM side is set in the ATMMINTFC 0xF03
register. For the PHY side, assignment of ports to Clav/Enb is configurable in the IMA_MISC_CONFIG register
0x804.
1.14
Transmission Convergence Block
The M2852x’s ATM Transmission Convergence (TC) block is responsible for recovering cell alignment using the
HEC octet, performing detection/correction, and descrambling the payload octets. The resulting ATM cells are then
passed to the ATM layer via the UTOPIA interface. Simultaneously, the ATM transmitter block is receiving data from
the ATM layer, optionally inserting header fields, optionally calculating the HEC, and sending the cells to the
framers. If no data is being received from the ATM layer, the cell processor generates idle cells based on the data
programmed into the associated registers.
When operating in the UTOPIA-to-UTOPIA mode, the ATM Cell processor block is disabled.
NOTE:
1.14.1
ATM Cell Transmitter
The ATM cell transmitter controls the generation and formatting of 53-octet ATM cells that are sent to the Framer
(Line) Transmit Ports. This block formats an octet stream containing ATM data cells from the ATM layer device
when those cells are available. All 53 octets of the data cells may be obtained from the external data source and
formatted into the outgoing octet stream.
This block calculates the HEC octet in the outgoing cell from the header field. The calculated HEC octet can be
inserted in place of the incoming data octet by writing DisHEC (bit 7) in the CGEN register (0x08) to a logic 0. For
testing purposes, this HEC octet can be corrupted by XORing the calculated value with a specific error pattern
input set in the ERRPAT register (0x0B). This HEC error is achieved by writing ErrHEC (bit 4) in the CGEN register
(0x08) to a logic 1. The remaining 48-octet payload field of the outgoing cell is obtained from the external data
source. The payload can be scrambled.
When there is no data from the ATM layer device, the TC Block inserts idle cells automatically in the outgoing octet
stream. The 4-octet header field for these idle cells comes from the TXIDL1–4 registers (0x14–17). The HEC octet
is calculated and inserted automatically. The payload field is filled with the octet contained in the IDLPAY register
(0x0A).
In normal operation, the 4-octet header field in the outgoing cell is passed on from the ATM layer device. Header
patterns can be modified in the TXHDR1–4 registers (0x10–13) and inserted into outgoing cells in place of header
bytes received from the ATM layer. Whether the original header cells or replacement cells are sent is controlled by
bits 0–4 in the HDRFIELD (0x09) register.
1.14.1.1
HEC Generation
In normal operation, the M2852x calculates the HEC for the four header bytes of each cell coming from the ATM
layer. It then adds the HEC coset (55 hex, by ATM standards) and inserts the result in octet 5 of the outgoing cell.
HEC calculation can be disabled by setting bit 7 of CGEN (0x08) to a 1. When HEC is disabled, the M2852x leaves
the contents of the HEC field unchanged and transmits whatever data is placed in that field by the ATM layer.
®
28529-DSH-001-K
Mindspeed Technologies
89
Mindspeed Proprietary and Confidential
Functional Description
The HEC coset is used to maintain a value other than zero in the HEC field. If the first four bytes in the header are
zero, the HEC derived from these bytes is also zero. When this occurs and there are strings of zeros in the data,
the receiver cannot determine cell boundaries. Therefore, it is recommended that the value 55 hex be added to the
HEC before transmission. To enable the HEC coset on the transmit side, set bit 6 in register CGEN (0x08) to one.
To enable the receive HEC coset, set bit 5 in register CVAL (0x0C) to one.
1.14.2
ATM Cell Receiver
The ATM cell receiver performs cell delineation on incoming data cells by searching for the position of a valid HEC
field within the cell. The HEC coset can be either active or inactive; this is determined in bit 5 in the CVAL (0x0C)
register.
Figure 1-26. Details of the TC Block
MicroData[7:0]
MicroAddr[10:0]
Control Lines
MicroInt*
StatOut[0:1]
Microprocessor
Framer
(Line)
UTOPIA
Level 2
Interrupt Control
Interface
Interface
Interface
IMA
Status and Control
Transmit
UTOPIA
Level 2
atmUTxClk
atmUTxClAv
atmUTxEnb*
atmUTxSOC
SPTxClk
SPTxSync
TC Transmit Port
4-cell
FIFO
ATM Cell Transmitter
atmUTxData[15:0]
atmUTxPrty
SPTxData
atmUTxAddr[4:0]
atmURxClk
atmURxClAv
atmURxEnb*
SPRxClkI
SPRxSync
SPRxData
4-cell
FIFO
ATM Cell Receiver
TC Receive Port
IMA
atmURxSOC
atmURxData[15:0]
atmURxPrty
Cell
Cell Validation
Loopback
Control
Receive
UTOPIA
Level 2
Alignment VPI/VCI Screening
This segment is replicated for Ports 0 - 7
atmURxAddr[4:0]
JTAG Controller
One Second Interface
8kHzIn
TCK
TMS
TDO
OneSecIO
TRST*
TDI
500027_063
1.14.2.1
Cell Delineation
The ATM block receives octets from the framers and recovers ATM cells by means of cell delineation. Cell
delineation is achieved by aligning ATM cell boundaries using the HEC algorithm. Four consecutive bytes are
chosen and the HEC value is calculated. The result is compared with the value of the following byte. This “hunt” is
continued by shifting this four-byte window, one byte at a time, until the calculated HEC value equals the received
HEC value. When this occurs, a pre-sync state is declared and the next 48 bytes are assumed to be payload. The
ATM block calculates HEC on the four bytes following this payload, assuming that a new cell has begun. If seven
®
28529-DSH-001-K
Mindspeed Technologies
90
Mindspeed Proprietary and Confidential
Functional Description
consecutive header blocks are found, synchronization is declared. If any HEC calculation fails in the pre-sync state,
the process begins again (see Figure 1-27). Synchronization will be held until seven consecutive incorrect HECs
are received. At this time, the “hunt” state is reinitiated.
Figure 1-27. Cell Delineation Process
1 Correct HEC
Pre-Sync
1 Errored HEC
6 Correct HECs
Hunt
7 Errored HECs
Sync
500027_006
During the sync state of cell delineation, cells are passed to the UTOPIA interface if the HEC is valid. If a single-bit
error in the header is detected, the error is corrected (optionally), and the cell is passed to the UTOPIA interface. If
HEC checking is enabled and HEC correcting is disabled (bit 3 in the CVAL register [0x0C]), cells with single-bit
HEC errors are discarded. If a multi-bit error is detected, the cell is dropped. Once either type of error is noted, all
subsequent errored cells are dropped until a valid cell is received. This rule applies even for single-bit errors that
could be corrected. Once a valid cell is detected, the process begins again. (See Figure 1-28.)
When loss-of-cell delineation (LOCD) occurs, an interrupt is generated and the M2852x automatically enters the
“hunt” mode. However, the cell is still being scrambled by the far-end transmitter, leaving only the headers (or just
the HEC byte in Distributed Sample Scrambler [DSS]) unscrambled. This means that the only repetitive byte
patterns in the data stream that meet the cell delineation criteria are valid headers (or just the HEC bytes in DSS).
®
28529-DSH-001-K
Mindspeed Technologies
91
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-28. Header Error Check Process
Cell Delineation in Sync State
Errors Detected
(Drop Cell)
No Errors Detected
(Pass Cell)
No Errors Detected (Pass Cell)
Detection
Mode
Apparent Single-bit Error
(Correct Error and Pass Cell)
Correction
Mode
Apparent Multi-bit Error (Drop Cell)
500027_007
When the M2852x is in general purpose mode, a synchronization pulse from the framer interface is not always
available. In this mode, the M2852x performs a bit serial search to find byte and cell alignment. The M2852x
selects a starting window of 32 sequential bits and calculates the HEC over this window. This HEC is then
compared to the next eight incoming bits. If they do not match, the M2852x shifts the 32-bit window by 1 bit and
recalculates the HEC until a valid HEC position is found. Once byte-alignment is achieved, cell delineation is
performed.
1.14.2.2
Cell Delineation Control Modes
The M28529 contains two independent “HEC Check” state machines. The Cell Delineator (CD) State Machine is
used to find Cell Delineation and, conversely, to declare loss of cell delineation (LOCD). The other is the Cell Valid
(CV) State Machine, which is used to validate the cells to pass to the UTOPIA FIFOs.
These state machines are controlled by two register bits, (CVAL register, 0x0C), that allow the M28529 to be
programmed for special applications. Table 1-26 shows the control bits function.
®
28529-DSH-001-K
Mindspeed Technologies
92
Mindspeed Proprietary and Confidential
Functional Description
Table 1-26. Control Bit Functions
DisLOCD
DisHECChk
Description
Normal operation; used for standard ATM traffic.
0
0
Cells are output to the UTOPIA FIFO only after cell delineation is found. Only cells with valid HECs are
passed (this includes cells with single bit errors that have been corrected).
0
1
1
Ignore HEC Errors Mode; used for IMA applications.
The Cell Delineator state machine is active and looking for valid ATM cells. It will follow the ATM Forum’s
Cell Delineation process. However, since the Cell Valid State machine is turned off, the M28529 will pass
all cells, including those with HEC errors, to the UTOPIA FIFOs.
The M28529 will not transfer cells during LOCD.
0
1
The cell delineation function is disabled and every 53 bytes of incoming data is treated as a ‘cell’. How-
ever, since the CV machine is still active, only cells with valid HECs will be output. As a result, almost all
data will be dropped. Occasionally, random data will have what appears to be a valid HEC and will be out-
put. Mindspeed is not aware of any use for this mode.
1
Raw Data mode; allows the M28529 to be used as a generic ‘serial to parallel’ convertor.
All data received will be passed across the UTOPIA bus in blocks of 53 bytes. No attempt is made to find
ATM cells.
General Note:
1. The HEC Error Correction circuit is independent of the DisHECChk control bit. The M28529 will correct single bit errors even when the
DisHECChk is enabled (assuming that the EnHECCor bit is set to 1).
1.14.2.3
Cell Screening
The M2852x provides two optional types of cell screening. The first type, idle cell rejection, prevents idle cells from
being passed on. The second type, user traffic screening, compares incoming bits to the values in the receive cell
header registers. Cells are rejected or accepted based on the bit patterns of their headers.
Idle cell rejection is enabled in bit 6 of the CVAL register (0x0C). If this bit is set to 1, all incoming cells that match
the contents of the Receive Idle Cell Header Control Registers, RXIDL1–4 (0x20–23), are rejected. Individual bits
in the Receive Idle Cell Mask Control Registers, IDLMSK1–4 (0x24–27), can be set to 1 or Don’t Care, causing the
corresponding bits of the incoming cell to be treated as matching, regardless of their value. If idle cell rejection is
disabled, cells pass directly to user traffic screening.
User traffic cell screening is similar to idle cell screening in that the incoming cells are compared to the Receive
Cell Header Control Registers, RXHDR1–4 (0x18–1B). Individual bits in the Receive Cell Mask Control Registers,
RXMSK1–4 (0x1C–1F), can be set to 1 or Don’t Care, causing the corresponding bits of the incoming cell to be
treated as matching, regardless of their values. The RejHdr bit (bit 7) in the CVAL register (0x0C) determines
whether matching cells are rejected or accepted. If it is set to 0, matching cells are accepted. If it is set to 1,
matching cells are rejected. See Table 1-27 and Table 1-28.
®
28529-DSH-001-K
Mindspeed Technologies
93
Mindspeed Proprietary and Confidential
Functional Description
Table 1-27. Cell Screening—Matching
Receive Cell Mask Bit Receive Cell Header Bit
Incoming Bit
Result
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
Match
Fail
Fail
Match
Match
Table 1-28. Cell Screening—Accept/Reject Cell
Cell
Reject Header
Result
Match
Match
Fail
0
1
0
1
Accept Cell
Reject Cell
Reject Cell
Accept Cell
Fail
1.14.2.4
Cell Scrambler
The ATM standard requires cell scrambling to ensure that only valid headers are found in the cell delineation
process. Scrambling randomizes any repeated patterns or other data strings that could be mistaken for valid
headers. The M2852x supports two types of scrambling as defined by ITU-T I.432:
1. Self Synchronizing Scrambler (SSS)
2. Distributed Sample Scrambler (DSS). Typically, SSS is used and is, therefore, the M2852x’s default method.
However, xDSL in asynchronous format generally use DSS.
If both SSS and DSS are enabled, SSS overrides DSS.
NOTE:
1.14.2.4.1
SSS Scrambling
43
SSS scrambling uses the polynomial × + 1 to scramble the payload, leaving the five header bytes untouched. It
can be enabled in EnTxCellScr, bit 5, of the CGEN register (0x08).
Descrambling uses the same polynomial to recover the 48-byte cell payload. It can be enabled in EnRxCellScr, bit
4, of the CVAL register (0x0C).
1.14.2.4.2
DSS Scrambling
31
28
DSS scrambling uses the × + × + 1 polynomial to scramble the entire cell, except the HEC byte. HEC is
calculated after the first four bytes of the header have been scrambled. DSS scrambling is enabled in EnTxDSSScr,
bit 1, of the CGEN register (0x08).
Descrambling uses the first six bits of the HEC for alignment. Once alignment is found, all eight bits of the HEC are
sampled. Descrambling uses the same polynomial to recover the 48-byte cell payload. It is enabled in
EnRxDSSScr, bit 0, of the CGEN register (0x08). If DSS descrambling fails, the M2852x defaults to unscrambled
mode.
®
28529-DSH-001-K
Mindspeed Technologies
94
Mindspeed Proprietary and Confidential
Functional Description
DSS Scrambling is only supported in General Purpose Mode.
NOTE:
1.14.2.5
Framing Modes (UTOPIA-to-Serial Configuration)
The M2852x’s 32 serial ports can be individually configured for the major framing modes: T1/E1, fractional T1/E1
and DSL. A general purpose framing mode provides an interface to customized framers and each of the 32 ports
can be configured for a different mode. The M2852x also supports an Interleaved Highway mode where a
combination of four T1, E1, Fractional T1 or Fractional E1’s can be transported over a higher bandwith 8.192 MHz
Interface.
1.14.2.5.1
T1/E1 Interface
This describes the timing requirements of the M28529 when operating in T1 or E1 mode. Connection to a CN8370
T1/E1 framer is used as an example, as illustrated in Figure 1-29. The M28529 receives a T1/E1 data stream from
the external framer, ignores the T1/E1 overhead, extracts the ATM cells, and passes the ATM cells to the ATM layer
device. In the transmit direction, the M28529 inserts 0’s in the overhead bit locations and fills the rest of the frame
with ATM cells from the UTOPIA bus.
For the E1 mode, the ATM cells are mapped into time slots 1–15 and 17–31 as described in Recommendation
G.804. For the T1 mode, the ATM cells are mapped into time slots 1–24.
Figure 1-29. CN8370 Interface Diagram
CN8370
M28529
Tx Frame Marker
Serial Data
SPTxSync
TFSYNC
TPCMI
SPTxData
Transmit Framer
Rx Frame Marker
Serial Data
Clock
SPRxSync
RFSYNC
RPCMO
SPRxData
RSBCKI, TSBCKI
Receive Framer
SPTxClk, SPRxClk
Clock Source
The 8370 is a single port transceiver which is shown here for simplicity.
NOTE:
®
28529-DSH-001-K
Mindspeed Technologies
95
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-30. CN8370 Interface - T1 Timing Diagram
1.544 MHz Clock
Tx Framer Marker
TS24
TS1
LSB
0
F
MSB
Tx Serial Data
T1 Mod Count
192
Rx Framer Marker
TS1
TS24
LSB
0
F
MSB
Rx Serial Data
T1 Mod Count
192
General Notes:
In T1, ATM Cells are mapped into time slots 1-24
®
28529-DSH-001-K
Mindspeed Technologies
96
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-31. CN8370 Interface - E1 Timing Diagram
2.048 MHz Clock
Tx Framer Marker
TS0
TS31
LSB
0
MSB
255
Tx Serial Data
T1 Mod Count
Rx Framer Marker
TS0
TS31
LSB
0
MSB
255
Rx Serial Data
T1 Mod Count
General Notes:
In E1 mode, ATM Cells are mapped inot time slots 1-15 and 17-31 as described in recommendation G.804.
1.14.2.5.2
Fractional T1/E1 Interface
The purpose of the fractional T1/E1 logic is to gate off the serial clocks during inactive timeslots. The fractional T1/
E1 logic is enabled on a link-by-link basis when in serial mode or on all four links when the interleaved highway
mode is enabled.
Figure 1-32 shows an example of fractional T1 timing. In this mode, the clock frequency is 1.544 MHz and the sync
input is used to indicate active data timeslots. The clocks are gapped internally in the M28525/9 during inactive
timeslots. ATM cell bytes are continuously mapped into active timeslots.
®
28529-DSH-001-K
Mindspeed Technologies
97
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-32. Fractional T1 Timing.
sprxclk (1.544 MHz)
sprxsync
sprxdata
sptxclk (1.544 MHz)
sptxsync
TS24
TS24
F
TS1
TS2 (inactive)
TS3
TS3
sptxdata
TS2
Figure 1-33 shows an example of fractional E1 timing. In Fractional E1 mode, the clock frequency is 2.048 MHz,
and the sync inputs are used to indicate active data timeslots. The clocks are gapped internally in the M28525/9
during inactive timeslots. ATM cell bytes are continuously mapped into active timeslots.
Figure 1-33. Fractional E1 Timing.
sprxclk (2.048 MHz)
sprxsync
sprxdata
sptxclk (2.048 MHz)
sptxsync
TS31
TS31
TS0 (overhead)
TS1 (inactive)
TS2
TS3
TS3
sptxdata
TS1
To enable fractional T1/E1 on a link, the appropriate EnFrac bits must be set in the TC
Control Registers, (TCCTRL0-TCCTRL7). The PhyType[2:0] bits in the Port Mode Control
register for the link should also be configured to be in xDSL framing mode (PMODE[2:0] =
110). CGEN[3] (DSLSyncPol) must also be set to 1.
NOTE:
1.14.2.5.3
DSL Mode Interface
In DSL mode, the clock frequency can be up to 8.192 MHz. On the receive side, the sync input signals tell the TC
Port receiver to ignore the corresponding bits on the data bus. This can be used to mask out overhead bits. Other
than such overhead bits, the receive data stream should contain only serialized ATM cells. On the transmit side,
sync is an output and is used to indicate the start of cell – the MSB of the first byte of the cell. Only serialized ATM
data cells are present in the transmit data stream
The M2852x has a DSL mode interface as illustrated in Figure 1-34. This mode allows connection with framers that
require frame synchronization. The M2852x receives a data stream from the external framer, performs bit level cell
®
28529-DSH-001-K
Mindspeed Technologies
98
Mindspeed Proprietary and Confidential
Functional Description
delineation, and passes the ATM cells to the ATM layer device. In this mode, the framer must ensure that only ATM
cells are present in the receive data stream. The M2852x performs the inverse process on transmitted data.
Figure 1-34. DSL Mode
DSL Modem
TxData
M28529
SPTxData
Tx Serial Data
Tx Sync
TxSync
SPTxSync
SPRxSync
(1)
PORT X
Rx Sync
Rx Serial Data
RxData
SPRxData
Tx Clock
Rx Clock
TxClk
RxClk
SPTxClk
SPRxClk
Transparent CellTransport
Bit Clock
SPTxSync
MSB
Tx Serial Data
(1)
Rx Serial Data
OH
SPRxSync
General Notes:
1. RxData is ignored when SPRxSync is asserted based on it's programmable active level. This may be used to mask
overhead bits in the receive data stream. Polarity is shown as active low in above figure.
2. TxSync indicates the Start of Cell.
3. Tx and Rx are asynchronous.
500027_014
1.14.2.5.4
General Purpose Mode Interface
The M2852x has a general purpose mode interface as illustrated in Figure 1-35. This mode allows connection with
framers that do not provide frame synchronization. The M2852x receives a data stream from the external framer,
performs bit level cell delineation, and passes the ATM cells to the ATM layer device. In this mode, the framer must
ensure that only ATM cells are present in the receive data stream. The M2852x performs the inverse process on
transmitted data.
®
28529-DSH-001-K
Mindspeed Technologies
99
Mindspeed Proprietary and Confidential
Functional Description
In general purpose framing mode, there is no frame synchronization or overhead bit indicators – the sync inputs
should be held high. The receive data streams should contain only serialized ATM cells. The transmit data will only
contained serialized ATM cells.
Figure 1-35. General Purpose Mode
Bt8970
M28529
SPTxData
Tx Serial Data
+3.3 V
TSER
SPTxSync
SPRxSync
PORT X
Rx Serial Data
Clock
RSER
BClk
SPRxData
SPTxClk
SPRxClk
Transparent CellTransport
(1)
400 – 1168k clock
MSB
Tx Serial Data
Rx Serial Data
MSB
General Notes:
1. In general purpose mode, the SPTxSync and SPRxSync pins must be held in the active state (active state depends on
the sync polarity - TxSyncPol and RxSyncPol bits are set in the IOMODE register).
2. Diagram shows default values for TxClkPol and RxClkPol (IOMODE register).
500027_014a
1.14.2.5.5
Interleaved Highway Interface
The M2852x has interleaved highway interfaces (8-M28529, 4-M28525) as illustrated in Figure 1-36 and Figure 1-
37. Four serial data streams can be combined together into one serial data stream using an Interleaved Highway
interface. This interface is designed to communicate with Mindspeed's CX2839x framer devices, running in
internally multiplexed mode.
®
28529-DSH-001-K
Mindspeed Technologies
100
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-36. Interfacing Interleaved Highway to CX2839x (Frame Sync Provided by CX2389x)
RINDO
RFSYNC
RPCMO
RSBCKI
IHRxINDo
IHRxSync
IHRxData
IHRxClk
CX2839x
M28529
TXINDO
TFSYNC
TPCMI
IHTxInDo
IHTxSync
IHTxData
IHTxClk
TSBCKI
Note: Device Configured for Internally
Multiplexed Mode
8.152 MHz Receive Clock
8.152 MHzTransmit Clock
®
28529-DSH-001-K
Mindspeed Technologies
101
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-37. Interfacing Interleaved Highway to CX2839x (Frame Sync Externally Provided)
RINDO
RFSYNC
RPCMO
RSBCKI
IHRxINDo
IHRxSync
IHRxData
IHRxClk
CX2839x
M28529
TXINDO
TFSYNC
TPCMI
IHTxInDo
IHTxSync
IHTxData
IHTxClk
TSBCKI
Note: Device Configured for Internally
Multiplexed Mode
8.152 MHz Receive Clock
8.152 MHz Transmit Clock
Receive Frame Sync
Transmit Frame Sync
Each Interleaved highway interface carries four separate T1, E1, Fractional T1, or Fractional E1 style data streams
(32 8-bit timeslots per frame). The data streams are interleaved one timeslot at a time. T1 links are supported over
the Interleaved Highway interface, by mapping the 24 T1 timeslots (numbered 1-24) into the corresponding E1
timeslots. The remaining E1 timeslots, 0 and 25-31 are unused.
The interleaved highway mode can be selected on a per group of four link basis where the groups are as follows:
Interleaved highway 0: Serial streams 0-3
Interleaved highway 1: Serial streams 4-7
Interleaved highway 2: Serial streams 8-11
Interleaved highway 3: Serial streams 12-15
Interleaved highway 4: Serial streams 16-19
Interleaved highway 5: Serial streams 20-23
Interleaved highway 6: Serial streams 24-27
Interleaved highway 7: Serial streams 28-31
Input pins IHRxSync and IHTxSync are provided to indicate the first bit (MSB) of the first timeslot of the first data
stream, in the receive and transmit directions respectively. The streams are multiplexed in order of the lowest
numbered stream to highest number.
®
28529-DSH-001-K
Mindspeed Technologies
102
Mindspeed Proprietary and Confidential
Functional Description
Fractional T1/E1 is also supported over the Interleaved Highway interface. Two extra signals, IHRxInDo and
IHTxInDo, are used to indicate which timeslots are active on each of the data streams. These signals should be
high for active timeslots.
Active timeslots in each case are as follows (timeslot 0 is always inactive as it is used for overhead in E1 frames,
and has no corresponding timeslot in T1 frames):
•
•
•
•
Full T1: timeslots 1-24 are used.
Full E1: timeslots 1-15 and 17-31 are used.
Fractional T1: subset of timeslots 1-24 is used.
Fractional E1: subset of timeslots 1-15 and 17-31 are used.
The Fractional T1/E1 logic is automatically enabled when using the Interleaved Highway interface, to provide the
necessary internal clock gating. Figure 1-38 shows how the datastreams are combined on the interleave highway.
In this example time slots 31A and TS0B are inactive as indicated by IHRxInDo being low. If for example Figure 1-
38 represented Interleaved highway 5, the streams would be grouped as follows: A = Stream 20, B = Stream 21, C
= Stream 22, D = Stream 23.
Figure 1-38. Combined Datastreams on the Interleaved Highway
IHRxClk
IHRxData
IHRxInDo
IHRxSync
TS31A TS31B TS31C TS31D TS0A TS0B TS0C TS0D
Figure 1-39. Full T1 Interleaved Highway Frame
IHRxData
15
D
0
A
0
B
0
C
0
D
1
A
1
B
1
C
1
D
2
A
2
B
2
C
2
D
3
A
3
B
3
C
3
D
4
A
4
B
4
C
4
D
5
A
5
B
5
C
5
D
6
A
6
B
6
C
6
D
7
A
7
B
7
C
7
D
8
A
8
B
8
C
8
D
9
A
9
B
9
C
9
D
10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
IHRxInDo
IHRxSync
IHRxData
(Continued)
16 16 16 16 17 17 17 17 18 18 18 18 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23 23 23 23 24 24 24 24 25 25 25 25 26 26 26 26 27 27 27 27 28 28 28 28 29 29 29 29 30 30 30 30 31 31 31 31
A
B
C
D
A
B
A
A
B
A
C
D
A
B
C
D
A
B
C
D
A
B
C
D
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
C
D
A
B
C
A
B
C
D
IHRxInDo
(Continued)
IHRxSync
(Continued)
Note: Only the transmt frame structure is shown, but the receive frame structure is identical
®
28529-DSH-001-K
Mindspeed Technologies
103
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-40. Full E1 Interleaved Highway Frame
1
C
1
D
2
A
2
B
2
C
2
D
3
A
3
B
3
C
3
D
4
A
4
B
4
C
4
D
5
A
5
B
5
C
5
D
6
A
6
B
6
C
6
D
7
A
7
B
7
C
7
D
8
A
8
B
8
C
8
D
9
A
9
B
9
C
9
D
10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15
15
D
0
A
0
B
0
C
0
D
1
A
1
B
IHRxData
IHRxInDo
IHRxSync
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A B C
IHRxData
(Continued)
16 16 16 16 17 17
21
A
29 29
A B
D C
30
A
17 17 18 18 18 18 19 19 19 19 20 20 20 20
21 21 21 22 22 22 22 23 23 23 23 24 24 24 24 25 25 25 25 26 26 26 26 27 27 27 27 28 28 28 28
29 29 30 30 30
31 31 31 31
A B C D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
IHRxInDo
(Continued)
IHRxSync
(Continued)
Note: Only the transmt frame structure is shown, but the receive frame structure is identical
The TC Processors belonging to the Interleaved Highway group should be configured in
xDSL mode, by setting PhyType to 110 in the Port Mode Control Registers (PMODE[2:0])
0x04, as this is required when using the Fractional T1/E1 logic. Also, the IOMODE registers
0x05 should be set to their default values. This is because the clock polarities in Interleaved
Highway mode are controlled via the TCCTRL registers. Also the Internal sync inputs to the
TC processor are tied low (inactive state when IOMODE[6] and IOMODE[4] are set to
default values in xDSL mode) so that they have no effect
NOTE:
The T1/E1 streams must be locked to the 8.192 MHz clock rate.
NOTE:
Figure 1-41 is a block diagram showing how four serial links are combined.
®
28529-DSH-001-K
Mindspeed Technologies
104
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-41. Interleaved Highway Mux
Interleaved Highway Group
TC cell
processor
Line interface
n
TC cell
processor
Line interface
n+1
4 x 1
Mux
TC cell
processor
Line interface
n+2
Line interface
n+3
TC cell
processor
1.15
General Issues
1.15.1
Micro Interface
The microprocessor interface transfers control and status information in 8-bit data transfers between the external
microprocessor and M2852x by means of write and/or read access to internal registers. This interface allows the
microprocessor to configure the M2852x by writing various control registers. These control registers can also be
read for configuration confirmation. This interface also provides the ability to read the device’s current condition via
its status registers and counters. Summary status is available for rapid interrupt identification.
The microprocessor interface can operate in either an asynchronous mode or a synchronous mode. The
MSyncMode (pin AE24) determines which mode is active.
In the synchronous mode, the timing of these signals is synchronized to MicroClk, which is intended to be directly
driven by the external microprocessor.
The MicroClk is required for both modes. In asynchronous mode, a MicroClk frequency of
up to 66MHz, must be present but can be asynchronous to the other microprocessor
signals. In synchronous mode, MicroClk is limited to 25MHz.
NOTE:
1.15.1.1
Resets
There are four software controlled reset functions, two at the device level and two at the port level. The two levels
allow a user to reset either the entire M2852x with one command or only a port within the device. The two logic
resets allow the user to keep the device or port in a reset state while the control registers are being programmed.
When the reset bit is deasserted, all changes to the registers take place simultaneously.
®
28529-DSH-001-K
Mindspeed Technologies
105
Mindspeed Proprietary and Confidential
Functional Description
At the device level, the software-controlled DevMstRst, bit 7, in the GENCTRL register (0x0F00), restarts all device
functions and sets the control and status registers, including IMA, to their default values except this bit
(DevMstRst). The DevLgcRst, bit 6, in the GENCTRL register (0x0F00) restarts all device functions in the TC block
but leaves all control registers unaffected. During a device logic reset the IMA core is held in a complete reset
state.
If configuring the device for pass-through operation, a minimum delay of 25 uS for
IMA_Sysclk of 66 MHz or 33 uS for IMA_Sysclk of 50 MHz is required from the release of
device reset (DevMstRst) to the first access of the IMA_RX_TRANS_TABLE register or
IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
NOTE:
At the port level, the PrtMstRst, bit 7, in the PMODE register (0x04), restarts all port functions and sets the
registers for the associated port to their default values except this bit (PrtMstRst). The PrtLgcRst, bit 6, in the
PMODE register (0x04) restarts all functions but leaves the port control registers unaffected.
1.15.1.2
Counters (TC Block Only)
The M2852x counters record events within the TC block. Two types of events are recorded: error events, such as
Section BIP errors, and transmission events, such as transmitted ATM cells.
Counters comprised of more than one register must be accessed by reading the least significant byte (LSB) first.
This guarantees that the value contained in each component register accurately reflects the composite counter
value at the time the LSB was read, because the counter may be updated while the component registers are being
read.
Each counter is large enough to accommodate the maximum number of events that may occur within a one-second
interval. The counters are cleared after being read. Therefore, if the counters are read every second, the
application will receive an accurate recording of all events.
1.15.1.2.1
One-second Latching
The M2852x’s implementation of one-second latching ensures the integrity of the statistics being gathered by the
network management software. Internal statistics counters can be latched at one-second intervals, which are
synchronized to the OneSecIO pin (pin AE26). Therefore, the data read from the statistic counters represents the
same one second of real-time data, independent of network management software timing.
The M2852x implements one-second latching for both status signals and counter values. When the EnStatLat (bit
5) in the GENCTRL register (0xF00) is written to a logical 1, a read from any of the status registers returns the
state of the device at the time of the previous OneSecIO (pin AE26) assertion. When the EnCntrLat (bit 4) in the
GENCTRL register (0xF00) is written to a logical 1, a read from any of the counters returns the state of the device
at the time of the previous OneSecIO (pin AE26) assertion. Every second, the counter is read, moved to the latch,
and the counter is cleared. The latch is cleared when read.
Software can configure the OneSecIO pin as an output that equals the input from the 8kHzIn divided by 8000.
When configured as an input, status registers and counters may be latched on the rising edge of this input. See Bit
0 of the GENCTRL register (0xF00).
When latching is disabled and a counter is wider than one byte, the LSB should be read first
to retain the values of the other bytes for a subsequent read.
NOTE:
®
28529-DSH-001-K
Mindspeed Technologies
106
Mindspeed Proprietary and Confidential
Functional Description
1.15.1.2.2
Interrupts
The M2852x’s interrupt indications can be classified as either single- or dual-event; a single-event interrupt is
triggered by a status assertion; a dual-event interrupt is triggered by either a status assertion or deassertion. Both
types of interrupts are further described in the following examples.
Single-event interrupt: When a parity error occurs on the UTOPIA transmit data bus, an interrupt is generated on
ParErrInt, bit 7, in the TXCELLINT register (0x2C). This bit is cleared when read.
Dual-event interrupt: When LOCD occurs, bit 7 of the corresponding RXCELLINT register (0x0D) is set to 1. This
bit is cleared when the register is read. Once cell delineation is recovered, bit 7 is set to 1 again, generating
another interrupt.
All interrupt bits have a corresponding enable bit. This allows software to disable or mask interrupts as required.
The IMA block does not generate interrupts.
NOTE:
The M2852x uses three levels of interrupt indications. The first level consists of receive or transmit interrupt
indications, which correspond to specific events on a specific port. The second level summarizes first level
interrupts and indicates framer and one-second interrupts for each port. The third level indicates which port
generated an interrupt.
The first level interrupt indications are located in registers TXCELLINT and RXCELLINT for each port. Each
interrupt bit in these registers can be disabled in the corresponding ENCELLR or ENCELLT register, respectively.
The result is then ORed into the appropriate bit in the port’s SUMINT register.
The second level consists of summary interrupt indications, located in the SUMINT register. It also includes the
OneSecInt and the ExInt indications. Each interrupt bit in these registers can be disabled in the corresponding
ENSUMINT register. The result is then ORed into the appropriate bit in the SUMPORT register.
The third level contains the overall interrupt indications for each port in the SUMPORT register. These bits can be
disabled in the ENSUMPORT register. The result is ORed to the MicroInt* pin. The MicroInt* pin can be enabled or
disabled by setting the EnIntPin (bit 3) in the GENCTRL register (0x0F00).
Figure 1-42 illustrates the flow chart of the interrupt generation process and Figure 1-43 illustrates the registers
involved in the interrupt generation process.
®
28529-DSH-001-K
Mindspeed Technologies
107
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-42. Interrupt Indication Flow Chart
TXCELLINT or RXCELLINT Event Occurs
Return
Individual
Interrupt
Indication
Enabled
?
No
Yes
Set Individual Interrupt Indication Bit
SUMINT
No
Interrupt
Indication
Enabled
?
OneSecInt or ExInt Event Occurs
Yes
Set SUMINT Interrupt Indication Bit
SUMPORT
No
Port
Indication
Enabled
?
Yes
Set SUMPORT Interrupt Indication Bit
Interrupt
No
Pin
(MInt*)
Enabled
?
Yes
Set Interrupt Pin (MInt*)
500027_015
®
28529-DSH-001-K
Mindspeed Technologies
108
Mindspeed Proprietary and Confidential
Functional Description
Figure 1-43. Interrupt Indication Diagram (TC Block)
SUMPORT3 (0xF0B)
PortInt31
7
6
5
4
3
2
1
0
PortInt24
Input to Latch Enabled by
ENSUMPORT3 (0xF0C)
TXCELLINT (0x1EC)
ParErrInt
SOCErrInt
TxOvflInt
7
6
5
4
3
SUMINT (0x1C0)
MicroInt
RxOvflInt
CellSentInt
Resvd
Resvd
Resvd
Resvd
Resvd
7
6
5
4
3
2
1
0
Resvd
Resvd
Resvd
Resvd
TxCellInt
RxCellInt
2
1
0
RXCELLINT (0x1ED)
LOCDInt
HECDetInt
HECCorrInt
7
6
5
4
3
2
1
0
SUMPORT0 (0xF05)
7
6
5
4
3
2
1
0
Input to Latch Enabled by
ENSUMINT
Resvd
CellRcvInt
IdleRcvInt
NonMatchInt
NonZerGFCInt
Input to Latch Enabled by
ENSUMPORT0 (0xF06)
TXCELLINT (0x02C)
ParErrInt
7
6
5
4
3
SOCErrInt
TxOvflInt
RxOvflInt
CellSentInt
Resvd
SUMINT (0x000)
Resvd
Resvd
Resvd
Resvd
7
6
5
4
3
2
1
0
2
1
0
OneSecInt
Resvd
Resvd
Resvd
Resvd
TxCellInt
RxCellInt
Input to Latch Enabled by
ENONESECINT (0xF19)
RXCELLINT (0x02D)
LOCDInt
HECDetInt
HECCorrInt
7
6
5
4
3
Input to Latch Enabled by
ENSUMINT
Resvd
CellRcvInt
IdleRcvInt
NonMatchInt
NonZerGFCInt
2
1
0
®
28529-DSH-001-K
Mindspeed Technologies
109
Mindspeed Proprietary and Confidential
Functional Description
1.15.1.2.3
Interrupt Servicing
When an interrupt occurs on the MicroInt* pin (pin AA1), it could have been generated by any of 385 events. The
M2852x’s interrupt indication structure ensures that no more than a maximum of seven register reads are needed
to determine the source of an interrupt. The interrupt is traced back to its source using the following steps:
1. Read the SUMPORT0-3 registers and the ONESECINT register to see which port(s) shows an interrupt and/or
whether there was a one second interrupt.
2. Read the appropriate SUMINT register to see which bit(s) shows an interrupt.
•
•
•
Bit 0, RxCellInt, reflects activity in the RXCELLINT register.
Bit 1, TxCellInt, reflects activity in the TXCELLINT register.
Bits 2–7 are reserved.
3. If necessary, read the appropriate TXCELLINT or RXCELLINT register.
All Level 1 bits are cleared when the register is read. Once the register is read, ALL bits in that register are reset to
their default values. Therefore, interrupt service routines must be designed to handle multiple interrupts in the
same registers. In Level 2, OneSecInt and ExInt are cleared when the register is read. However, the TxCellInt and
RxCellInt bits are cleared only when the corresponding Level 1 register is read and cleared. Level 3 bits are cleared
when the entire corresponding Level 2 register has been read and cleared.
®
28529-DSH-001-K
Mindspeed Technologies
110
Mindspeed Proprietary and Confidential
2.0 Registers
2.1
Address Map
The M2852x registers control and observe the device’s operations. Table 2-1 lists the address ranges that
represent a device control and status range. The registers in each port range are replicated for the other ports.
Table 2-2 lists the device-level control and status registers. Table 2-3 lists the port-level control and status registers.
All registers are 8 bits wide. All control registers can be read to verify contents.
Control bits that do not have a documented function are reserved and must be written to a
logical 0.
NOTE:
Table 2-1.
Address Ranges (1 of 2)
Port Offset
Address Range (Hex)
Port Base Address
(Hex)
Description
0000–003F
0040–007F
0080–00BF
00C0–00FF
0100–013F
0140–017F
0180–01BF
01C0–01FF
0200-023F
0240-027F
0280-02BF
02C0-02FF
0300-033F
0340-037F
0380-03BF
03C0-03FF
0400-043F
0440-047F
0480-04BF
Port 0 Control and Status Registers
Port 1 Control and Status Registers
Port 2 Control and Status Registers
Port 3 Control and Status Registers
Port 4 Control and Status Registers
Port 5 Control and Status Registers
Port 6 Control and Status Registers
Port 7 Control and Status Registers
Port 8 Control and Status Registers
Port 9 Control and Status Registers
Port 10 Control and Status Registers
Port 11 Control and Status Registers
Port 12 Control and Status Registers
Port 13 Control and Status Registers
Port 14 Control and Status Registers
Port 15 Control and Status Registers
Port 16 Control and Status Registers
Port 17 Control and Status Registers
Port 18 Control and Status Registers
0000
0040
0080
00C0
0100
0140
0180
01C0
0200
0240
0280
02C0
0300
0340
0380
03C0
0400
0440
0480
®
28529-DSH-001-K
Mindspeed Technologies
111
Mindspeed Proprietary and Confidential
Registers
Table 2-1.
Address Ranges (2 of 2)
Port Offset
Address Range (Hex)
Port Base Address
(Hex)
Description
04C0-04FF
0500-053F
0540-057F
0580-05BF
05C0-05FF
0600-063F
0640-067F
0680-06BF
06C0-06FF
0700-073F
0740-077F
0780-07BF
07C0-07FF
0800-0EFF
0F00-0FFF
Port 19 Control and Status Registers
Port 20 Control and Status Registers
Port 21 Control and Status Registers
Port 22 Control and Status Registers
Port 23 Control and Status Registers
Port 24 Control and Status Registers
Port 25 Control and Status Registers
Port 26 Control and Status Registers
Port 27 Control and Status Registers
Port 28 Control and Status Registers
Port 29 Control and Status Registers
Port 30 Control and Status Registers
Port 31 Control and Status Registers
IMA Control and Status Registers
Device Control and Status Registers
04C0
0500
0540
0580
05C0
0600
0640
0680
06C0
0700
0740
0780
07C0
—
—
The device level registers in Table 2-2 provide control for the device’s major operating modes, as well as status and
control for summary interrupts.
Table 2-2.
Device Control and Status Registers (1 of 2)
OneSec
Latching
Page
Number
Address
Name
Type
Description
0x0F00
0x0F01
0x0F02
0x0F03
0x0F04
0x0F05
0x0F06
0x0F07
0x0F08
0x0F09
0x0F0A
0x0F0B
0x0F0C
0x0F0D
GENCTRL
R/W
R/W
R/W
R/W
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
General Device Control Register
page 179
page 179
page 180
page 180
page 180
page 181
page 181
page 182
page 182
page 183
page 183
page 184
page 184
PARTNUM
PHYINTFC
Part and Version Number
PHY-side Interface Control Register
ATMINTFC
STATOUT
ATM-side Interface Control Register
Output Status Control Register
SUMPORT0
ENSUMPORT0
SUMPORT1
ENSUMPORT1
SUMPORT2
ENSUMPORT2
SUMPORT3
ENSUMPORT3
—
R/W
R
Summary Interrupt Status Register (TC Ports 0-7)
Summary Interrupt Control Register (TC Ports 0-7)
Summary Interrupt Status Register (TC Ports 8-15)
Summary Interrupt Control Register (TC Ports 8-15)
Summary Interrupt Status Register (TC Ports 16-23)
Summary Interrupt Control Register (TC Ports 16-23)
Summary Interrupt Status Register (TC Ports 24-31)
Summary Interrupt Control Register (TC Ports 24-31)
Reserved, set register to all 0’s
R/W
R
R/W
R
R/W
R
®
28529-DSH-001-K
Mindspeed Technologies
112
Mindspeed Proprietary and Confidential
Registers
Table 2-2.
Device Control and Status Registers (2 of 2)
OneSec
Latching
Page
Number
Address
Name
Type
Description
0x0F0E
0x0F0F
0x0F10
0x0F11
0x0F12
0x0F13
0x0F14
0x0F15
0x0F16
0x0F17
0x0F18
0x0F19
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved, set register to all 0’s
SCRATCH
TCCTRL0
TCCTRL1
TCCTRL2
TCCTRL3
TCCTRL4
TCCTRL5
TCCTRL6
TCCTRL7
ONESECINT
ENONESECINT
Scratch Pad Register
page 184
page 185
page 185
page 186
page 186
page 187
page 187
page 188
page 188
page 188
page 189
TC Control Register for TC Ports 0-3
TC Control Register for TC Ports 4-7
TC Control Register for TC Ports 8-11
TC Control Register for TC Ports 12-15
TC Control Register for TC Ports 16-19
TC Control Register for TC Ports 20-23
TC Control Register for TC Ports 24-27
TC Control Register for TC Ports 28-31
One Second Interrupt Status Register
One Second Interrupt Control Register
The registers listed in Table 2-3 are replicated for each port. Two methods can be used to determine the exact
address of a specific register in a specific port. All numbers are in hexadecimal.
1. Add the port offset address to the port base address as shown in Table 2-1. For example:
For Port 3, IOMODE register 0xC0 (Port 3 base address) + 0x05 (port offset address) = 0xC5
2. Use the following formula:
0x40 (port register map size) × n (port number) + port offset address = exact register address
Table 2-3.
Port Control and Status Registers (1 of 3)
Port Offset
Address
One-second
Latching
Page
Number
Name
Type
Description
0x00
0x01
0x02
SUMINT
R
—
—
—
Summary Interrupt Indication Status Register
Summary Interrupt Control Register
Reserved, set to a logical 0
page 150
page 151
—
ENSUMINT
—
R/W
—
0x03
—
—
Reserved, set to a logical 0
—
—
PMODE
IOMODE
CGEN
0x04
0x05
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
Port Mode Control Register
page 152
page 153
page 154
page 155
page 155
page 156
page 156
page 157
page 157
Input/Output Mode Control Register
Cell Generation Control Register
Header Field Control Register
Transmit Idle Cell Payload Control Register
Error Pattern Control Register
Cell Validation Control Register
UTOPIA Control Register 1
HDRFIELD
IDLPAY
ERRPAT
CVAL
UTOP1
UTOP2
UTOPIA Control Register 2
®
28529-DSH-001-K
Mindspeed Technologies
113
Mindspeed Proprietary and Confidential
Registers
Table 2-3.
Port Control and Status Registers (2 of 3)
Port Offset
Address
One-second
Latching
Page
Number
Name
Type
Description (Continued)
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
UDF2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UDF2 Control Register
page 158
page 158
page 159
page 159
page 160
page 160
page 161
page 161
page 162
page 162
page 163
page 163
page 164
page 164
page 165
page 165
page 166
page 166
page 167
page 167
page 168
page 168
page 169
page 169
page 170
page 170
page 171
—
TXHDR1
TXHDR2
TXHDR3
TXHDR4
TXIDL1
Transmit Cell Header Control Register 1
Transmit Cell Header Control Register 2
Transmit Cell Header Control Register 3
Transmit Cell Header Control Register 4
Transmit Idle Cell Header Control Register 1
Transmit Idle Cell Header Control Register 2
Transmit Idle Cell Header Control Register 3
Transmit Idle Cell Header Control Register 4
Receive Cell Header Control Register 1
Receive Cell Header Control Register 2
Receive Cell Header Control Register 3
Receive Cell Header Control Register 4
Receive Cell Mask Control Register 1
Receive Cell Mask Control Register 2
Receive Cell Mask Control Register 3
Receive Cell Mask Control Register 4
Receive Idle Cell Header Control Register 1
Receive Idle Cell Header Control Register 2
Receive Idle Cell Header Control Register 3
Receive Idle Cell Header Control Register 4
Receive Idle Cell Mask Control Register 1
Receive Idle Cell Mask Control Register 2
Receive Idle Cell Mask Control Register 3
Receive Idle Cell Mask Control Register 4
Transmit Cell Interrupt Control Register
Receive Cell Interrupt Control Register
Reserved, set to a logical 0
TXIDL2
TXIDL3
TXIDL4
RXHDR1
RXHDR2
RXHDR3
RXHDR4
RXMSK1
RXMSK2
RXMSK3
RXMSK4
RXIDL1
RXIDL2
RXIDL3
RXIDL4
IDLMSK1
IDLMSK2
IDLMSK3
IDLMSK4
ENCELLT
ENCELLR
—
0x2B
—
—
Reserved, set to a logical 0
—
—
TXCELLINT
RXCELLINT
TXCELL
0x2C
0x2D
0x2E
0x2F
0x30
0x31
R
R
R
R
R
R
—
—
Transmit Cell Interrupt Indication Control Register
Receive Cell Interrupt Indication Control Register
Transmit Cell Status Control Register
Receive Cell Status Control Register
page 171
page 172
page 172
page 173
page 173
page 174
(1)
(1)
(2)
(2)
RXCELL
IDLCNTL
IDLCNTH
Idle Cell Receive Counter (low byte)
Idle Cell Receive Counter (high byte)
®
28529-DSH-001-K
Mindspeed Technologies
114
Mindspeed Proprietary and Confidential
Registers
Table 2-3.
Port Control and Status Registers (3 of 3)
Port Offset
Address
One-second
Latching
Page
Number
Name
Type
Description (Continued)
0x33
0x34
0x35
0x37
0x38
0x39
0x3B
0x3C
0x3D
0x3E
LOCDCNT
R
R
R
R
R
R
R
R
R
—
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
—
LOCD Event Counter
page 174
page 175
page 175
page 176
page 176
page 177
page 177
page 178
page 178
—
TXCNTL
Transmitted Cell Counter (low byte)
Transmitted Cell Counter (high byte)
Corrected HEC Error Counter
TXCNTH
CORRCNT
RXCNTL
RXCNTH
UNCCNT
NONCNTL
NONCNTH
Received Cell Counter (low byte)
Received Cell Counter (high byte)
Uncorrected HEC Error Counter
Non-Matching Cell Counter (low byte)
Non-Matching Cell Counter (high byte)
Reserved, set to a logical 0
—
—
0x3F
—
—
Reserved, set to a logical 0
—
Footnote:
(1) One-second latching is enabled by setting EnStatLat (bit 5) in the GENCTRL register (0xF00) to a logical 1.
(2) One-second latching is enabled by setting EnCntrLat (bit 4) in the MODE register (0xF00) to a logical 1.
Table 2-4 lists the control registers used for transmission of traffic.
Table 2-4.
Cell Transmit Registers
Port Offset
Address
Page
Number
Name
Description
0x08
0x09
0x0A
0x0B
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
CGEN
Cell Generation Control Register
Header Field Control Register
page 154
page 155
page 155
page 156
page 158
page 159
page 159
page 160
page 160
page 161
page 161
page 162
HDRFIELD
IDLPAY
ERRPAT
TXHDR1
TXHDR2
TXHDR3
TXHDR4
TXIDL1
TXIDL2
TXIDL3
TXIDL4
Transmit Idle Cell Payload Control Register
Error Pattern Control Register
Transmit Cell Header Control Register 1
Transmit Cell Header Control Register 2
Transmit Cell Header Control Register 3
Transmit Cell Header Control Register 4
Transmit Idle Cell Header Control Register 1
Transmit Idle Cell Header Control Register 2
Transmit Idle Cell Header Control Register 3
Transmit Idle Cell Header Control Register 4
Table 2-5 lists the control registers used for reception of traffic.
®
28529-DSH-001-K
Mindspeed Technologies
115
Mindspeed Proprietary and Confidential
Registers
Table 2-5.
Cell Receive Registers
Port Offset
Address
Page
Number
Name
Description
0x0C
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
CVAL
Cell Validation Control Register
page 156
page 162
page 163
page 163
page 164
page 164
page 165
page 165
page 166
page 166
page 167
page 167
page 168
page 168
page 169
page 169
page 170
RXHDR1
RXHDR2
RXHDR3
RXHDR4
RXMSK1
RXMSK2
RXMSK3
RXMSK4
RXIDL1
Receive Cell Header Control Register 1
Receive Cell Header Control Register 2
Receive Cell Header Control Register 3
Receive Cell Header Control Register 4
Receive Cell Mask Control Register 1
Receive Cell Mask Control Register 2
Receive Cell Mask Control Register 3
Receive Cell Mask Control Register 4
Receive Idle Cell Header Control Register 1
Receive Idle Cell Header Control Register 2
Receive Idle Cell Header Control Register 3
Receive Idle Cell Header Control Register 4
Receive Idle Cell Mask Control Register 1
Receive Idle Cell Mask Control Register 2
Receive Idle Cell Mask Control Register 3
Receive Idle Cell Mask Control Register 4
RXIDL2
RXIDL3
RXIDL4
IDLMSK1
IDLMSK2
IDLMSK3
IDLMSK4
Table 2-6 lists the control registers for the UTOPIA operations.
Table 2-6.
UTOPIA Registers
Port Offset
Address
Page
Number
Name
Description
0x0D
0x0E
UTOP1
UTOP2
UTOPIA Control Register 1
UTOPIA Control Register 2
page 157
page 157
®
28529-DSH-001-K
Mindspeed Technologies
116
Mindspeed Proprietary and Confidential
Registers
Table 2-7 and Table 2-8 list interrupt enables, interrupt indications, and status information.
Table 2-7.
Status and Interrupt Registers
Page
Number
Port Address
Name
Description
0xF05
0xF06
0xF07
0xF08
0xF09
0xF0A
0xF0B
0xF0C
SUMPORT0
Summary Port Interrupt Status Register 0
Summary Port Interrupt Control Register 0
page 181
page 181
page 182
page 182
page 183
page 183
page 184
page 184
ENSUMPORT0
SUMPORT1
Summary Port Interrupt Status Register 1
Summary Port Interrupt Control Register 1
Summary Port Interrupt Status Register 2
Summary Port Interrupt Control Register 2
Summary Port Interrupt Status Register 3
Summary Port Interrupt Control Register 3
ENSUMPORT1
SUMPORT2
ENSUMPORT2
SUMPORT3
ENSUMPORT3
Table 2-8.
Status and Interrupt Registers (Offset Registers)
Name Description
Port Offset
Address
Page
Number
0x00
0x01
0x28
0x29
0x2C
0x2D
0x2E
0x2F
SUMINT
Summary Interrupt Indication Status Register
Summary Interrupt Control Register
Transmit Cell Interrupt Control Register
Receive Cell Interrupt Control Register)
Transmit Cell Interrupt Indication Status Register
Receive Cell Interrupt Indication Status Register
Transmit Cell Status Register
page 150
page 151
page 170
page 171
page 171
page 172
page 172
page 173
ENSUMINT
ENCELLT
ENCELLR
TXCELLINT
RXCELLINT
TXCELL
RXCELL
Receive Cell Status Register
®
28529-DSH-001-K
Mindspeed Technologies
117
Mindspeed Proprietary and Confidential
Registers
Table 2-9 lists the M2852x’s counters. When the counters fill, they saturate and do not roll over. The counts have
been sized to ensure against saturation within a one-second interval. Therefore, when one-second latching is
enabled, the counters are read and cleared before they can saturate. All counters are cleared when read.
Table 2-9.
Counters
Port Offset
Address
Page
Number
Name
Description
0x30
0x31
0x33
0x34
0x35
0x37
0x38
0x39
0x3B
0x3C
0x3D
IDLCNTL
IDLCNTH
LOCDCNT
TXCNTL
Idle Cell Receive Counter [Low Byte]
Idle Cell Receive Counter [High Byte]
LOCD Event Counter
page 173
page 174
page 174
page 175
page 175
page 176
page 176
page 177
page 177
page 178
page 178
Transmitted Cell Counter [Low Byte]
Transmitted Cell Counter [High Byte]
Corrected HEC Error Counter
TXCNTH
CORRCNT
RXCNTL
RXCNTH
UNCCNT
NONCNTL
NONCNTH
Received Cell Counter [Low Byte]
Received Cell Counter [High Byte]
Uncorrected HEC Error Counter
Non-matching Cell Counter [Low Byte]
Non-matching Cell Counter [High Byte]
Table 2-10 lists IMA control and status information.
Table 2-10. IMA Control and Status Registers (1 of 33)
Page
Number
Address
Name
Description
0x800
0x801
0x802
0x803
0x804
0x805
0x806
0x807
0x808
0x809
0x80a
0x80b
0x80c
0x80e
0x80f
0x810
IMA_VER_1_CONFIG
IMA_VER_2_CONFIG
Device Version I
page 189
page 189
page 190
page 190
page 191
page 191
page 192
page 192
page 192
page 192
page 192
page 193
page 194
page 194
page 194
page 195
Device Version II
IMA_SUBSYS_CONFIG
IMA_MISC_STATUS
Configuration Control
Miscellaneous Status
Miscellaneous Control
Memory Test Address
Memory Test Address
Memory Test Control
Memory Test Data
IMA_MISC_CONFIG
IMA_MEM_LOW_TEST
IMA_MEM_HI_TEST
IMA_MEM_TEST_CTL
IMA_MEM_TEST_DATA
IMA_LNK_DIAG_CTL
IMA_LNK_DIFF_DEL
IMA_RCV_LNK_ANOMALIES
IMA_PHY_LOOPBACK
IMA_DIAG_XOR_BIT
IMA_DIAG
Link Diagnostic Control
Link Differential Delay
Receive Link Anomalies
IMA Phy Side UTOPIA Loopback
Address Diagnostic
Diagnostic Register
IMA_TIM_REF_MUX_CTL_ADDR
TRL Control Address
®
28529-DSH-001-K
Mindspeed Technologies
118
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (2 of 33)
Page
Number
Address
Name
Description (Continued)
0x811
0x812
0x813
0x814
0x815
0x816
0x817
0x818
0x819
0x81b
0x81c
0x81e
0x81f
0x91f
0xa1f
0xb1f
0xc1f
0xc9f
0xd1f
0xd9f
IMA_TIM_REF_MUX_CTL_DATA
IMA_RX_PERSIST_CONFIG
IMA_ATM_UTOPIA_BUS_CTL
IMA_DIFF_DELAY_ADDR
IMA_DIFF_DELAY_DATA
IMA_DSL_CLOCK_GEN_ADDR
IMA_DSL_CLOCK_GEN_DATA
IMA_RX_TRANS_TABLE
IMA_RX_ATM_TRANS_TABLE
IMA_TX_TRANS_TABLE
IMA_TX_ATM_TRANS_TABLE
IMA_LNK_SEM
TRL Control Data
page 196
page 197
page 197
page 198
page 198
page 199
page 200
page 201
page 202
page 203
page 203
page 230
page 204
page 204
page 205
page 206
page 206
page 207
page 207
page 208
Receive Persistence
ATM UTOPIA Control
Diff. Delay Control Address
Diff. Delay Control Data
DSL Clock Generator Control Address
DSL Clock Generator Control Data
Receive Translation Table Address
Receive Translation Table Internal Channel
Transmit Translation Table Address
Transmit Translation Table Internal Channel
Link Table Control
IMA_GRP_1TO4_SEM
Groups 1–4 Table Control
IMA_GRP_5TO8_SEM
Groups 5–8 Table Control
IMA_GRP_9TO12_SEM
IMA_GRP_13TO16_SEM
IMA_GRP_17TO20_SEM
IMA_GRP_21TO24_SEM
IMA_GRP_25TO28_SEM
IMA_GRP_29TO32_SEM
Groups 9–12 Table Control
Groups 13–16 Table Control
Groups 17–20 Table Control
Groups 21–24 Table Control
Groups 25–28 Table Control
Groups 29–32 Table Control
Transmit Groups 1–4 Configuration Tables
0x820
0x821
0x822
0x823
0x824
0x825
0x826
0x827
0x828
0x829
0x82a
0x82b
0x82c
0x82d
IMA_TX_GRP1_RX_TEST_PATTERN
IMA_TX_GRP1_CTL
Tx GRP 1 Rx Test Pattern
Tx GRP 1 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
IMA_TX_GRP1_FIRST_PHY_ADDR
IMA_TX_GRP1_ID
Tx GRP 1 First Link Address
Tx GRP 1 Tx Group ID
Tx GRP 1 Status / Control
Tx GRP 1 Timing Control
Tx GRP 1 Test Control
Tx GRP 1 Tx Test Pattern
Tx GRP 2 Rx Test Pattern
Tx GRP 2 Control
IMA_TX_GRP1_STAT_CTL
IMA_TX_GRP1_TIMING_INFO
IMA_TX_GRP1_TEST_CTL
IMA_TX_GRP1_TX_TEST_PATTERN
IMA_TX_GRP2_RX_TEST_PATTERN
IMA_TX_GRP2_CTL
IMA_TX_GRP2_FIRST_PHY_ADDR
IMA_TX_GRP2_ID
Tx GRP 2 First Link Address
Tx GRP 2 Tx Group ID
Tx GRP 2 Status / Control
Tx GRP 2 Timing Control
IMA_TX_GRP2_STAT_CTL
IMA_TX_GRP2_TIMING_INFO
®
28529-DSH-001-K
Mindspeed Technologies
119
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (3 of 33)
Page
Number
Address
Name
Description (Continued)
0x82e
0x82f
0x830
0x831
0x832
0x833
0x834
0x835
0x836
0x837
0x838
0x839
0x83a
0x83b
0x83c
0x83d
0x83e
0x83f
IMA_TX_GRP2_TEST_CTL
Tx GRP 2 Test Control
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
IMA_TX_GRP2_TX_TEST_PATTERN
IMA_TX_GRP3_RX_TEST_PATTERN
IMA_TX_GRP3_CTL
Tx GRP 2 Tx Test Pattern
Tx GRP 3 Rx Test Pattern
Tx GRP 3 Control
IMA_TX_GRP3_FIRST_PHY_ADDR
IMA_TX_GRP3_ID
Tx GRP 3 First Link Address
Tx GRP 3 Tx Group ID
Tx GRP 3 Status / Control
Tx GRP 3 Timing Control
Tx GRP 3 Test Control
Tx GRP 3 Tx Test Pattern
Tx GRP 4 Rx Test Pattern
Tx GRP 4 Control
IMA_TX_GRP3_STAT_CTL
IMA_TX_GRP3_TIMING_INFO
IMA_TX_GRP3_TEST_CTL
IMA_TX_GRP3_TX_TEST_PATTERN
IMA_TX_GRP4_RX_TEST_PATTERN
IMA_TX_GRP4_CTL
IMA_TX_GRP4_FIRST_PHY_ADDR
IMA_TX_GRP4_ID
Tx GRP 4 First Link Address
Tx GRP 4 Tx Group ID
Tx GRP 4 Status / Control
Tx GRP 4 Timing Control
Tx GRP 4 Test Control
Tx GRP 4 Tx Test Pattern
IMA_TX_GRP4_STAT_CTL
IMA_TX_GRP4_TIMING_INFO
IMA_TX_GRP4_TEST_CTL
IMA_TX_GRP4_TX_TEST_PATTERN
Tx UTOPIA Addresses 0 - 3 Cell Counters
0x840
0x841
0x842
0x843
0x844
0x845
0x846
0x847
IMA_TX_ATM0_CELL_COUNT_LSB
IMA_TX_ATM0_CELL_COUNT_MSB
IMA_TX_ATM1_CELL_COUNT_LSB
IMA_TX_ATM1_CELL_COUNT_MSB
IMA_TX_ATM2_CELL_COUNT_LSB
IMA_TX_ATM2_CELL_COUNT_MSB
IMA_TX_ATM3_CELL_COUNT_LSB
IMA_TX_ATM3_CELL_COUNT_MSB
Transmit UTOPIA Address 0x00 Cell Count LSBs
page 216
Transmit UTOPIA Address 0x00 Cell Count MSBs
Transmit UTOPIA Address 0x01 Cell Count LSBs
Transmit UTOPIA Address 0x01 Cell Count MSBs
Transmit UTOPIA Address 0x02 Cell Count LSBs
Transmit UTOPIA Address 0x02 Cell Count MSBs
Transmit UTOPIA Address 0x03 Cell Count LSBs
Transmit UTOPIA Address 0x03 Cell Count MSBs
Rx UTOPIA Addresses 0 - 3 Cell Counters
0x850
0x851
0x852
0x853
0x854
0x855
0x856
0x857
IMA_RX_ATM0_CELL_COUNT_LSB
IMA_RX_ATM0_CELL_COUNT_MSB
IMA_RX_ATM1_CELL_COUNT_LSB
IMA_RX_ATM1_CELL_COUNT_MSB
IMA_RX_ATM2_CELL_COUNT_LSB
IMA_RX_ATM2_CELL_COUNT_MSB
IMA_RX_ATM3_CELL_COUNT_LSB
IMA_RX_ATM3_CELL_COUNT_MSB
Receive UTOPIA Address 0x00 Cell Count LSBs
Receive UTOPIA Address 0x00 Cell Count MSBs
Receive UTOPIA Address 0x01 Cell Count LSBs
Receive UTOPIA Address 0x01 Cell Count MSBs
Receive UTOPIA Address 0x02 Cell Count LSBs
Receive UTOPIA Address 0x02 Cell Count MSBs
Receive UTOPIA Address 0x03 Cell Count LSBs
Receive UTOPIA Address 0x03 Cell Count MSBs
page 218
®
28529-DSH-001-K
Mindspeed Technologies
120
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (4 of 33)
Page
Number
Address
Name
Description (Continued)
Port 0–7 Control and Status
0x860
0x861
0x862
0x863
0x864
0x865
0x866
0x867
IMA_TX_LNK0_CTL
IMA_TX_LNK1_CTL
IMA_TX_LNK2_CTL
IMA_TX_LNK3_CTL
IMA_TX_LNK4_CTL
IMA_TX_LNK5_CTL
IMA_TX_LNK6_CTL
IMA_TX_LNK7_CTL
Tx Link 0 Control
Tx Link 1 Control
Tx Link 2 Control
Tx Link 3 Control
Tx Link 4 Control
Tx Link 5 Control
Tx Link 6 Control
Tx Link 7 Control
page 232
page 233
page 234
page 235
page 236
0x868
0x869
0x86a
0x86b
0x86c
0x86d
0x86e
0x86f
IMA_TX_LNK0_STATE
IMA_TX_LNK1_STATE
IMA_TX_LNK2_STATE
IMA_TX_LNK3_STATE
IMA_TX_LNK4_STATE
IMA_TX_LNK5_STATE
IMA_TX_LNK6_STATE
IMA_TX_LNK7_STATE
Tx Link 0 Status
Tx Link 1 Status
Tx Link 2 Status
Tx Link 3 Status
Tx Link 4 Status
Tx Link 5 Status
Tx Link 6 Status
Tx Link 7 Status
0x870
0x871
0x872
0x873
0x874
0x875
0x876
0x877
IMA_TX_LNK0_ID
IMA_TX_LNK1_ID
IMA_TX_LNK2_ID
IMA_TX_LNK3_ID
IMA_TX_LNK4_ID
IMA_TX_LNK5_ID
IMA_TX_LNK6_ID
IMA_TX_LNK7_ID
Tx Link 0 Assigned LID
Tx Link 1 Assigned LID
Tx Link 2 Assigned LID
Tx Link 3 Assigned LID
Tx Link 4 Assigned LID
Tx Link 5 Assigned LID
Tx Link 6 Assigned LID
Tx Link 7 Assigned LID
0x880
0x881
0x882
0x883
0x884
0x885
0x886
0x887
IMA_RX_LNK0_CTL
IMA_RX_LNK1_CTL
IMA_RX_LNK2_CTL
IMA_RX_LNK3_CTL
IMA_RX_LNK4_CTL
IMA_RX_LNK5_CTL
IMA_RX_LNK6_CTL
IMA_RX_LNK7_CTL
Rx Link 0 Control
Rx Link 1 Control
Rx Link 2 Control
Rx Link 3 Control
Rx Link 4 Control
Rx Link 5 Control
Rx Link 6 Control
Rx Link 7 Control
0x888
0x889
0x88a
0x88b
0x88c
0x88d
0x88e
0x88f
IMA_RX_LNK0_STATE
IMA_RX_LNK1_STATE
IMA_RX_LNK2_STATE
IMA_RX_LNK3_STATE
IMA_RX_LNK4_STATE
IMA_RX_LNK5_STATE
IMA_RX_LNK6_STATE
IMA_RX_LNK7_STATE
Rx Link 0 Status
Rx Link 1 Status
Rx Link 2 Status
Rx Link 3 Status
Rx Link 4 Status
Rx Link 5 Status
Rx Link 6 Status
Rx Link 7 Status
®
28529-DSH-001-K
Mindspeed Technologies
121
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (5 of 33)
Page
Number
Address
Name
Description (Continued)
0x890
0x891
0x892
0x893
0x894
0x895
0x896
0x897
IMA_RX_LNK0_DEFECT
Rx Link 0 Defects
Rx Link 1 Defects
Rx Link 2 Defects
Rx Link 3 Defects
Rx Link 4 Defects
Rx Link 5 Defects
Rx Link 6 Defects
Rx Link 7 Defects
page 237
page 238
page 239
page 240
page 241
page 242
IMA_RX_LNK1_DEFECT
IMA_RX_LNK2_DEFECT
IMA_RX_LNK3_DEFECT
IMA_RX_LNK4_DEFECT
IMA_RX_LNK5_DEFECT
IMA_RX_LNK6_DEFECT
IMA_RX_LNK7_DEFECT
0x898
0x899
0x89a
0x89b
0x89c
0x89d
0x89e
0x89f
IMA_FE_TX_LNK0_CFG
IMA_FE_TX_LNK1_CFG
IMA_FE_TX_LNK2_CFG
IMA_FE_TX_LNK3_CFG
IMA_FE_TX_LNK4_CFG
IMA_FE_TX_LNK5_CFG
IMA_FE_TX_LNK6_CFG
IMA_FE_TX_LNK7_CFG
FE Tx Link 0 Link Config
FE Tx Link 1 Link Config
FE Tx Link 2 Link Config
FE Tx Link 3 Link Config
FE Tx Link 4 Link Config
FE Tx Link 5 Link Config
FE Tx Link 6 Link Config
FE Tx Link 7 Link Config
0x8a0
0x8a1
0x8a2
0x8a3
0x8a4
0x8a5
0x8a6
0x8a7
IMA_FE_LNK0_STATE
IMA_FE_LNK1_STATE
IMA_FE_LNK2_STATE
IMA_FE_LNK3_STATE
IMA_FE_LNK4_STATE
IMA_FE_LNK5_STATE
IMA_FE_LNK6_STATE
IMA_FE_LNK7_STATE
Rx Link 0 FE Status
Rx Link 1 FE Status
Rx Link 2 FE Status
Rx Link 3 FE Status
Rx Link 4 FE Status
Rx Link 5 FE Status
Rx Link 6 FE Status
Rx Link 7 FE Status
0x8a8
0x8a9
0x8aa
0x8ab
0x8ac
0x8ad
0x8ae
0x8af
IMA_RX_LNK0_ID
IMA_RX_LNK1_ID
IMA_RX_LNK2_ID
IMA_RX_LNK3_ID
IMA_RX_LNK4_ID
IMA_RX_LNK5_ID
IMA_RX_LNK6_ID
IMA_RX_LNK7_ID
Rx Link 0 Assigned LID
Rx Link 1 Assigned LID
Rx Link 2 Assigned LID
Rx Link 3 Assigned LID
Rx Link 4 Assigned LID
Rx Link 5 Assigned LID
Rx Link 6 Assigned LID
Rx Link 7 Assigned LID
0x8b0
0x8b1
0x8b2
0x8b3
0x8b4
0x8b5
0x8b6
0x8b7
IMA_RX_LNK0_IV_CNT
IMA_RX_LNK1_IV_CNT
IMA_RX_LNK2_IV_CNT
IMA_RX_LNK3_IV_CNT
IMA_RX_LNK4_IV_CNT
IMA_RX_LNK5_IV_CNT
IMA_RX_LNK6_IV_CNT
IMA_RX_LNK7_IV_CNT
Rx Link 0 IV-IMA Counter
Rx Link 1 IV-IMA Counter
Rx Link 2 IV-IMA Counter
Rx Link 3 IV-IMA Counter
Rx Link 4 IV-IMA Counter
Rx Link 5 IV-IMA Counter
Rx Link 6 IV-IMA Counter
Rx Link 7 IV-IMA Counter
0x8b8
0x8b9
0x8ba
0x8bb
0x8bc
0x8bd
0x8be
0x8bf
IMA_RX_LNK0_OIF_CNT
IMA_RX_LNK1_OIF_CNT
IMA_RX_LNK2_OIF_CNT
IMA_RX_LNK3_OIF_CNT
IMA_RX_LNK4_OIF_CNT
IMA_RX_LNK5_OIF_CNT
IMA_RX_LNK6_OIF_CNT
IMA_RX_LNK7_OIF_CNT
Rx Link 0 OIF-IMA Counter
Rx Link 1 OIF-IMA Counter
Rx Link 2 OIF-IMA Counter
Rx Link 3 OIF-IMA Counter
Rx Link 4 OIF-IMA Counter
Rx Link 5 OIF-IMA Counter
Rx Link 6 OIF-IMA Counter
Rx Link 7 OIF-IMA Counter
®
28529-DSH-001-K
Mindspeed Technologies
122
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (6 of 33)
Page
Number
Address
Name
Description (Continued)
0x8c0
0x8c1
0x8c2
0x8c3
0x8c4
0x8c5
0x8c6
0x8c7
IMA_FE_TX_LNK0_GRP_ID
IMA_FE_TX_LNK1_GRP_ID
IMA_FE_TX_LNK2_GRP_ID
IMA_FE_TX_LNK3_GRP_ID
IMA_FE_TX_LNK4_GRP_ID
IMA_FE_TX_LNK5_GRP_ID
IMA_FE_TX_LNK6_GRP_ID
IMA_FE_TX_LNK7_GRP_ID
Rx Link 0 Captured GRP ID
page 243
Rx Link 1 Captured GRP ID
Rx Link 2 Captured GRP ID
Rx Link 3 Captured GRP ID
Rx Link 4 Captured GRP ID
Rx Link 5 Captured GRP ID
Rx Link 6 Captured GRP ID
Rx Link 7 Captured GRP ID
Receive Groups 1–4 Configuration Tables
0x8d0
0x8d1
0x8d2
0x8d3
0x8d4
0x8d5
0x8d6
0x8d7
0x8d8
0x8d9
0x8da
0x8db
0x8dc
0x8dd
0x8de
0x8df
IMA_RX_GRP1_CFG
Rx GRP 1 Configuration
Rx GRP 1 Control
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP1_CTL
IMA_RX_GRP1_FIRST_PHY_ADDR
IMA_RX_GRP1_ID
Rx GRP 1 First Link Address
Rx GRP 1 Rx Group ID
Rx GRP 2 Configuration
Rx GRP 2 Control
IMA_RX_GRP2_CFG
IMA_RX_GRP2_CTL
IMA_RX_GRP2_FIRST_PHY_ADDR
IMA_RX_GRP2_ID
Rx GRP 2 First Link Address
Rx GRP 2 Rx Group ID
Rx GRP 3 Configuration
Rx GRP 3 Control
IMA_RX_GRP3_CFG
IMA_RX_GRP3_CTL
IMA_RX_GRP3_FIRST_PHY_ADDR
IMA_RX_GRP3_ID
Rx GRP 3 First Link Address
Rx GRP 3 Rx Group ID
Rx GRP 4 Configuration
Rx GRP 4 Control
IMA_RX_GRP4_CFG
IMA_RX_GRP4_CTL
IMA_RX_GRP4_FIRST_PHY_ADDR
IMA_RX_GRP4_ID
Rx GRP 4 First Link Address
Rx GRP 4 Rx Group ID
Receive Groups 1–4 Far-End Status
0x8e0
0x8e2
0x8e3
0x8e4
0x8e5
0x8e6
0x8e7
0x8e8
0x8ea
0x8eb
0x8ec
IMA_RX_GRP1_RX_TEST_PATTERN
IMA_RX_GRP1_STAT_CTL_CHANGE
IMA_RX_GRP1_ACTUAL_GRP_ID
IMA_RX_GRP1_STAT_CTL
Rx GRP 1 Rx Test Pattern
Rx GRP 1 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
Rx GRP 1 Rx Group ID
Rx GRP 1 Status / Control
Rx GRP 1 Timing Control
Rx GRP 1 Test Control
Rx GRP 1 Tx Test Pattern
Rx GRP 2 Rx Test Pattern
Rx GRP 2 SCCI
IMA_RX_GRP1_TIMING_INFO
IMA_RX_GRP1_TEST_CTL
IMA_RX_GRP1_TX_TEST_PATTERN
IMA_RX_GRP2_RX_TEST_PATTERN
IMA_RX_GRP2_STAT_CTL_CHANGE
IMA_RX_GRP2_ACTUAL_GRP_ID
IMA_RX_GRP2_STAT_CTL
Rx GRP 2 Rx Group ID
Rx GRP 2 Status / Control
®
28529-DSH-001-K
Mindspeed Technologies
123
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (7 of 33)
Page
Number
Address
Name
Description (Continued)
0x8ed
0x8ee
0x8ef
0x8f0
0x8f2
0x8f3
0x8f4
0x8f5
0x8f6
0x8f7
0x8f8
0x8fa
0x8fb
0x8fc
0x8fd
0x8fe
0x8ff
IMA_RX_GRP2_TIMING_INFO
IMA_RX_GRP2_TEST_CTL
Rx GRP 2 Timing Control
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
Rx GRP 2 Test Control
Rx GRP 2 Tx Test Pattern
Rx GRP 3 Rx Test Pattern
Rx GRP 3 SCCI
IMA_RX_GRP2_TX_TEST_PATTERN
IMA_RX_GRP3_RX_TEST_PATTERN
IMA_RX_GRP3_STAT_CTL_CHANGE
IMA_RX_GRP3_ACTUAL_GRP_ID
IMA_RX_GRP3_STAT_CTL
Rx GRP 3 Rx Group ID
Rx GRP 3 Status / Control
Rx GRP 3 Timing Control
Rx GRP 3 Test Control
Rx GRP 3 Tx Test Pattern
Rx GRP 4 Rx Test Pattern
Rx GRP 4 SCCI
IMA_RX_GRP3_TIMING_INFO
IMA_RX_GRP3_TEST_CTL
IMA_RX_GRP3_TX_TEST_PATTERN
IMA_RX_GRP4_RX_TEST_PATTERN
IMA_RX_GRP4_STAT_CTL_CHANGE
IMA_RX_GRP4_ACTUAL_GRP_ID
IMA_RX_GRP4_STAT_CTL
Rx GRP 4 Rx Group ID
Rx GRP 4 Status / Control
Rx GRP 4 Timing Control
Rx GRP 4 Test Control
Rx GRP 4 Tx Test Pattern
IMA_RX_GRP4_TIMING_INFO
IMA_RX_GRP4_TEST_CTL
IMA_RX_GRP4_TX_TEST_PATTERN
Transmit Groups 5–8 Configuration Tables
0x920
0x921
0x922
0x923
0x924
0x925
0x926
0x927
0x928
0x929
0x92a
0x92b
0x92c
0x92d
0x92e
0x92f
0x930
IMA_TX_GRP5_RX_TEST_PATTERN
IMA_TX_GRP5_CTL
Tx GRP 5 Rx Test Pattern
Tx GRP 5 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
IMA_TX_GRP5_FIRST_PHY_ADDR
IMA_TX_GRP5_ID
Tx GRP 5 First Link Address
Tx GRP 5 Tx Group ID
Tx GRP 5 Status / Control
Tx GRP 5 Timing Control
Tx GRP 5 Test Control
Tx GRP 5 Tx Test Pattern
Tx GRP 6 Rx Test Pattern
Tx GRP 6 Control
IMA_TX_GRP5_STAT_CTL
IMA_TX_GRP5_TIMING_INFO
IMA_TX_GRP5_TEST_CTL
IMA_TX_GRP5_TX_TEST_PATTERN
IMA_TX_GRP6_RX_TEST_PATTERN
IMA_TX_GRP6_CTL
IMA_TX_GRP6_FIRST_PHY_ADDR
IMA_TX_GRP6_ID
Tx GRP 6 First Link Address
Tx GRP 6 Tx Group ID
Tx GRP 6 Status / Control
Tx GRP 6 Timing Control
Tx GRP 6 Test Control
Tx GRP 6 Tx Test Pattern
Tx GRP 7 Rx Test Pattern
IMA_TX_GRP6_STAT_CTL
IMA_TX_GRP6_TIMING_INFO
IMA_TX_GRP6_TEST_CTL
IMA_TX_GRP6_TX_TEST_PATTERN
IMA_TX_GRP7_RX_TEST_PATTERN
®
28529-DSH-001-K
Mindspeed Technologies
124
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (8 of 33)
Page
Number
Address
Name
Description (Continued)
0x931
0x932
0x933
0x934
0x935
0x936
0x937
0x938
0x939
0x93a
0x93b
0x93c
0x93d
0x93e
0x93f
IMA_TX_GRP7_CTL
Tx GRP 7 Control
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
IMA_TX_GRP7_FIRST_PHY_ADDR
IMA_TX_GRP7_ID
Tx GRP 7 First Link Address
Tx GRP 7 Tx Group ID
Tx GRP 7 Status / Control
Tx GRP 7 Timing Control
Tx GRP 7 Test Control
Tx GRP 7 Tx Test Pattern
Tx GRP 8 Rx Test Pattern
Tx GRP 8 Control
IMA_TX_GRP7_STAT_CTL
IMA_TX_GRP7_TIMING_INFO
IMA_TX_GRP7_TEST_CTL
IMA_TX_GRP7_TX_TEST_PATTERN
IMA_TX_GRP8_RX_TEST_PATTERN
IMA_TX_GRP8_CTL
IMA_TX_GRP8_FIRST_PHY_ADDR
IMA_TX_GRP8_ID
Tx GRP 8 First Link Address
Tx GRP 8 Tx Group ID
Tx GRP 8 Status / Control
Tx GRP 8 Timing Control
Tx GRP 8 Test Control
Tx GRP 8 Tx Test Pattern
IMA_TX_GRP8_STAT_CTL
IMA_TX_GRP8_TIMING_INFO
IMA_TX_GRP8_TEST_CTL
IMA_TX_GRP8_TX_TEST_PATTERN
Tx UTOPIA Addresses 4 - 7 Cell Counters
0x940
0x941
0x942
0x943
0x944
0x945
0x946
0x947
IMA_TX_ATM4_CELL_COUNT_LSB
IMA_TX_ATM4_CELL_COUNT_MSB
IMA_TX_ATM5_CELL_COUNT_LSB
IMA_TX_ATM5_CELL_COUNT_MSB
IMA_TX_ATM6_CELL_COUNT_LSB
IMA_TX_ATM6_CELL_COUNT_MSB
IMA_TX_ATM7_CELL_COUNT_LSB
IMA_TX_ATM7_CELL_COUNT_MSB
Transmit UTOPIA Address 0x04 Cell Count LSBs
page 216
Transmit UTOPIA Address 0x04 Cell Count MSBs
Transmit UTOPIA Address 0x05 Cell Count LSBs
Transmit UTOPIA Address 0x05 Cell Count MSBs
Transmit UTOPIA Address 0x06 Cell Count LSBs
Transmit UTOPIA Address 0x06 Cell Count MSBs
Transmit UTOPIA Address 0x07 Cell Count LSBs
Transmit UTOPIA Address 0x07 Cell Count MSBs
Rx UTOPIA Addresses 4 - 7 Cell Counters
0x950
0x951
0x952
0x953
0x954
0x955
0x956
0x957
IMA_RX_ATM4_CELL_COUNT_LSB
IMA_RX_ATM4_CELL_COUNT_MSB
IMA_RX_ATM5_CELL_COUNT_LSB
IMA_RX_ATM5_CELL_COUNT_MSB
IMA_RX_ATM6_CELL_COUNT_LSB
IMA_RX_ATM6_CELL_COUNT_MSB
IMA_RX_ATM7_CELL_COUNT_LSB
IMA_RX_ATM7_CELL_COUNT_MSB
Receive UTOPIA Address 0x04 Cell Count LSBs
Receive UTOPIA Address 0x04 Cell Count MSBs
Receive UTOPIA Address 0x05 Cell Count LSBs
Receive UTOPIA Address 0x05 Cell Count MSBs
Receive UTOPIA Address 0x06 Cell Count LSBs
Receive UTOPIA Address 0x06 Cell Count MSBs
Receive UTOPIA Address 0x07 Cell Count LSBs
Receive UTOPIA Address 0x07 Cell Count MSBs
page 218
®
28529-DSH-001-K
Mindspeed Technologies
125
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (9 of 33)
Page
Number
Address
Name
Description (Continued)
Port 8–15 Control and Status
0x960
0x961
0x962
0x963
0x964
0x965
0x966
0x967
IMA_TX_LNK8_CTL
IMA_TX_LNK9_CTL
IMA_TX_LNK10_CTL
IMA_TX_LNK11_CTL
IMA_TX_LNK12_CTL
IMA_TX_LNK13_CTL
IMA_TX_LNK14_CTL
IMA_TX_LNK15_CTL
Tx Link 8 Control
Tx Link 9 Control
Tx Link 10 Control
Tx Link 11 Control
Tx Link 12 Control
Tx Link 13 Control
Tx Link 14 Control
Tx Link 15 Control
page 232
page 233
page 234
page 235
page 236
0x968
0x969
0x96a
0x96b
0x96c
0x96d
0x96e
0x96f
IMA_TX_LNK8_STATE
IMA_TX_LNK9_STATE
Tx Link 8 Status
Tx Link 9 Status
Tx Link 10 Status
Tx Link 11 Status
Tx Link 12 Status
Tx Link 13 Status
Tx Link 14 Status
Tx Link 15 Status
IMA_TX_LNK10_STATE
IMA_TX_LNK11_STATE
IMA_TX_LNK12_STATE
IMA_TX_LNK13_STATE
IMA_TX_LNK14_STATE
IMA_TX_LNK15_STATE
0x970
0x971
0x972
0x973
0x974
0x975
0x976
0x977
IMA_TX_LNK8_ID
IMA_TX_LNK9_ID
IMA_TX_LNK10_ID
IMA_TX_LNK11_ID
IMA_TX_LNK12_ID
IMA_TX_LNK13_ID
IMA_TX_LNK14_ID
IMA_TX_LNK15_ID
Tx Link 8 Assigned LID
Tx Link 9 Assigned LID
Tx Link 10 Assigned LID
Tx Link 11 Assigned LID
Tx Link 12 Assigned LID
Tx Link 13 Assigned LID
Tx Link 14 Assigned LID
Tx Link 15 Assigned LID
0x980
0x981
0x982
0x983
0x984
0x985
0x986
0x987
IMA_RX_LNK8_CTL
IMA_RX_LNK9_CTL
IMA_RX_LNK10_CTL
IMA_RX_LNK11_CTL
IMA_RX_LNK12_CTL
IMA_RX_LNK13_CTL
IMA_RX_LNK14_CTL
IMA_RX_LNK15_CTL
Rx Link 8 Control
Rx Link 9 Control
Rx Link 10 Control
Rx Link 11 Control
Rx Link 12 Control
Rx Link 13 Control
Rx Link 14 Control
Rx Link 15 Control
0x988
0x989
0x98a
0x98b
0x98c
0x98d
0x98e
0x98f
IMA_RX_LNK8_STATE
IMA_RX_LNK9_STATE
IMA_RX_LNK10_STATE
IMA_RX_LNK11_STATE
IMA_RX_LNK12_STATE
IMA_RX_LNK13_STATE
IMA_RX_LNK14_STATE
IMA_RX_LNK15_STATE
Rx Link 8 Status
Rx Link 9 Status
Rx Link 10 Status
Rx Link 11 Status
Rx Link 12 Status
Rx Link 13 Status
Rx Link 14 Status
Rx Link 15 Status
®
28529-DSH-001-K
Mindspeed Technologies
126
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (10 of 33)
Page
Number
Address
Name
Description (Continued)
0x990
0x991
0x992
0x993
0x994
0x995
0x996
0x997
IMA_RX_LNK8_DEFECT
Rx Link 8 Defects
Rx Link 9 Defects
Rx Link 10 Defects
Rx Link 11 Defects
Rx Link 12 Defects
Rx Link 13 Defects
Rx Link 14 Defects
Rx Link 15 Defects
page 237
page 238
page 239
page 240
page 241
page 242
IMA_RX_LNK9_DEFECT
IMA_RX_LNK10_DEFECT
IMA_RX_LNK11_DEFECT
IMA_RX_LNK12_DEFECT
IMA_RX_LNK13_DEFECT
IMA_RX_LNK14_DEFECT
IMA_RX_LNK15_DEFECT
0x998
0x999
0x99a
0x99b
0x99c
0x99d
0x99e
0x99f
IMA_FE_TX_LNK8_CFG
IMA_FE_TX_LNK9_CFG
IMA_FE_TX_LNK10_CFG
IMA_FE_TX_LNK11_CFG
IMA_FE_TX_LNK12_CFG
IMA_FE_TX_LNK13_CFG
IMA_FE_TX_LNK14_CFG
IMA_FE_TX_LNK15_CFG
FE Tx Link 8 Link Config
FE Tx Link 9 Link Config
FE Tx Link 10 Link Config
FE Tx Link 11 Link Config
FE Tx Link 12 Link Config
FE Tx Link 13 Link Config
FE Tx Link 14 Link Config
FE Tx Link 15 Link Config
0x9a0
0x9a1
0x9a2
0x9a3
0x9a4
0x9a5
0x9a6
0x9a7
IMA_FE_LNK8_STATE
IMA_FE_LNK9_STATE
IMA_FE_LNK10_STATE
IMA_FE_LNK11_STATE
IMA_FE_LNK12_STATE
IMA_FE_LNK13_STATE
IMA_FE_LNK14_STATE
IMA_FE_LNK15_STATE
Rx Link 8 FE Status
Rx Link 9 FE Status
Rx Link 10 FE Status
Rx Link 11 FE Status
Rx Link 12 FE Status
Rx Link 13 FE Status
Rx Link 14 FE Status
Rx Link 15 FE Status
0x9a8
0x9a9
0x9aa
0x9ab
0x9ac
0x9ad
0x9ae
0x9af
IMA_RX_LNK8_ID
IMA_RX_LNK9_ID
IMA_RX_LNK10_ID
IMA_RX_LNK11_ID
IMA_RX_LNK12_ID
IMA_RX_LNK13_ID
IMA_RX_LNK14_ID
IMA_RX_LNK15_ID
Rx Link 8 Assigned LID
Rx Link 9 Assigned LID
Rx Link 10 Assigned LID
Rx Link 11 Assigned LID
Rx Link 12 Assigned LID
Rx Link 13 Assigned LID
Rx Link 14 Assigned LID
Rx Link 15 Assigned LID
0x9b0
0x9b1
0x9b2
0x9b3
0x9b4
0x9b5
0x9b6
0x9b7
IMA_RX_LNK8_IV_CNT
IMA_RX_LNK9_IV_CNT
IMA_RX_LNK10_IV_CNT
IMA_RX_LNK11_IV_CNT
IMA_RX_LNK12_IV_CNT
IMA_RX_LNK13_IV_CNT
IMA_RX_LNK14_IV_CNT
IMA_RX_LNK15_IV_CNT
Rx Link 8 IV-IMA Counter
Rx Link 9 IV-IMA Counter
Rx Link 10 IV-IMA Counter
Rx Link 11 IV-IMA Counter
Rx Link 12 IV-IMA Counter
Rx Link 13 IV-IMA Counter
Rx Link 14 IV-IMA Counter
Rx Link 15 IV-IMA Counter
0x9b8
0x9b9
0x9ba
0x9bb
0x9bc
0x9bd
0x9be
0x9bf
IMA_RX_LNK8_OIF_CNT
IMA_RX_LNK9_OIF_CNT
IMA_RX_LNK10_OIF_CNT
IMA_RX_LNK11_OIF_CNT
IMA_RX_LNK12_OIF_CNT
IMA_RX_LNK13_OIF_CNT
IMA_RX_LNK14_OIF_CNT
IMA_RX_LNK15_OIF_CNT
Rx Link 8 OIF-IMA Counter
Rx Link 9 OIF-IMA Counter
Rx Link 10 OIF-IMA Counter
Rx Link 11 OIF-IMA Counter
Rx Link 12 OIF-IMA Counter
Rx Link 13 OIF-IMA Counter
Rx Link 14 OIF-IMA Counter
Rx Link 15 OIF-IMA Counter
®
28529-DSH-001-K
Mindspeed Technologies
127
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (11 of 33)
Page
Number
Address
Name
Description (Continued)
0x9c0
0x9c1
0x9c2
0x9c3
0x9c4
0x9c5
0x9c6
0x9c7
IMA_FE_TX_LNK8_GRP_ID
IMA_FE_TX_LNK9_GRP_ID
IMA_FE_TX_LNK10_GRP_ID
IMA_FE_TX_LNK11_GRP_ID
IMA_FE_TX_LNK12_GRP_ID
IMA_FE_TX_LNK13_GRP_ID
IMA_FE_TX_LNK14_GRP_ID
IMA_FE_TX_LNK15_GRP_ID
Rx Link 8 Captured GRP ID
page 243
Rx Link 9 Captured GRP ID
Rx Link 10 Captured GRP ID
Rx Link 11 Captured GRP ID
Rx Link 12 Captured GRP ID
Rx Link 13 Captured GRP ID
Rx Link 14 Captured GRP ID
Rx Link 15 Captured GRP ID
Receive Groups 5–8 Configuration Tables
0x9d0
0x9d1
0x9d2
0x9d3
0x9d4
0x9d5
0x9d6
0x9d7
0x9d8
0x9d9
0x9da
0x9db
0x9dc
0x9dd
0x9de
0x9df
IMA_RX_GRP5_CFG
Rx GRP 5 Configuration
Rx GRP 5 Control
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP5_CTL
IMA_RX_GRP5_FIRST_PHY_ADDR
IMA_RX_GRP5_ID
Rx GRP 5 First Link Address
Rx GRP 5 Rx Group ID
Rx GRP 6 Configuration
Rx GRP 6 Control
IMA_RX_GRP6_CFG
IMA_RX_GRP6_CTL
IMA_RX_GRP6_FIRST_PHY_ADDR
IMA_RX_GRP6_ID
Rx GRP 6 First Link Address
Rx GRP 6 Rx Group ID
Rx GRP 7 Configuration
Rx GRP 7 Control
IMA_RX_GRP7_CFG
IMA_RX_GRP7_CTL
IMA_RX_GRP7_FIRST_PHY_ADDR
IMA_RX_GRP7_ID
Rx GRP 7 First Link Address
Rx GRP 7 Rx Group ID
Rx GRP 8 Configuration
Rx GRP 8 Control
IMA_RX_GRP8_CFG
IMA_RX_GRP8_CTL
IMA_RX_GRP8_FIRST_PHY_ADDR
IMA_RX_GRP8_ID
Rx GRP 8 First Link Address
Rx GRP 8 Rx Group ID
Receive Groups 5–8 Far-End Status
0x9e0
0x9e2
0x9e3
0x9e4
0x9e5
0x9e6
0x9e7
0x9e8
0x9ea
0x9eb
0x9ec
IMA_RX_GRP5_RX_TEST_PATTERN
IMA_RX_GRP5_STAT_CTL_CHANGE
IMA_RX_GRP5_ACTUAL_GRP_ID
IMA_RX_GRP5_STAT_CTL
Rx GRP 5 Rx Test Pattern
Rx GRP 5 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
Rx GRP 5 Rx Group ID
Rx GRP 5 Status / Control
Rx GRP 5 Timing Control
Rx GRP 5 Test Control
Rx GRP 5 Tx Test Pattern
Rx GRP 6 Rx Test Pattern
Rx GRP 6 SCCI
IMA_RX_GRP5_TIMING_INFO
IMA_RX_GRP5_TEST_CTL
IMA_RX_GRP5_TX_TEST_PATTERN
IMA_RX_GRP6_RX_TEST_PATTERN
IMA_RX_GRP6_STAT_CTL_CHANGE
IMA_RX_GRP6_ACTUAL_GRP_ID
IMA_RX_GRP6_STAT_CTL
Rx GRP 6 Rx Group ID
Rx GRP 6 Status / Control
®
28529-DSH-001-K
Mindspeed Technologies
128
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (12 of 33)
Page
Number
Address
Name
Description (Continued)
0x9ed
0x9ee
0x9ef
0x9f0
0x9f2
0x9f3
0x9f4
0x9f5
0x9f6
0x9f7
0x9f8
0x9fa
0x9fb
0x9fc
0x9fd
0x9fe
0x9ff
IMA_RX_GRP6_TIMING_INFO
IMA_RX_GRP6_TEST_CTL
Rx GRP 6 Timing Control
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
Rx GRP 6 Test Control
Rx GRP 6 Tx Test Pattern
Rx GRP 7 Rx Test Pattern
Rx GRP 7 SCCI
IMA_RX_GRP6_TX_TEST_PATTERN
IMA_RX_GRP7_RX_TEST_PATTERN
IMA_RX_GRP7_STAT_CTL_CHANGE
IMA_RX_GRP7_ACTUAL_GRP_ID
IMA_RX_GRP7_STAT_CTL
Rx GRP 7 Rx Group ID
Rx GRP 7 Status / Control
Rx GRP 7 Timing Control
Rx GRP 7 Test Control
Rx GRP 7 Tx Test Pattern
Rx GRP 8 Rx Test Pattern
Rx GRP 8 SCCI
IMA_RX_GRP7_TIMING_INFO
IMA_RX_GRP7_TEST_CTL
IMA_RX_GRP7_TX_TEST_PATTERN
IMA_RX_GRP8_RX_TEST_PATTERN
IMA_RX_GRP8_STAT_CTL_CHANGE
IMA_RX_GRP8_ACTUAL_GRP_ID
IMA_RX_GRP8_STAT_CTL
Rx GRP 8 Rx Group ID
Rx GRP 8 Status / Control
Rx GRP 8 Timing Control
Rx GRP 8 Test Control
Rx GRP 8 Tx Test Pattern
IMA_RX_GRP8_TIMING_INFO
IMA_RX_GRP8_TEST_CTL
IMA_RX_GRP8_TX_TEST_PATTERN
Transmit Groups 9–12 Configuration Tables
0xa20
0xa21
0xa22
0xa23
0xa24
0xa25
0xa26
0xa27
0xa28
0xa29
0xa2a
0xa2b
0xa2c
0xa2d
0xa2e
0xa2f
0xa30
IMA_TX_GRP9_RX_TEST_PATTERN
IMA_TX_GRP9_CTL
Tx GRP 9 Rx Test Pattern
Tx GRP 9 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
IMA_TX_GRP9_FIRST_PHY_ADDR
IMA_TX_GRP9_ID
Tx GRP 9 First Link Address
Tx GRP 9 Tx Group ID
Tx GRP 9 Status / Control
Tx GRP 9 Timing Control
Tx GRP 9 Test Control
Tx GRP 9 Tx Test Pattern
IMA_TX_GRP9_STAT_CTL
IMA_TX_GRP9_TIMING_INFO
IMA_TX_GRP9_TEST_CTL
IMA_TX_GRP9_TX_TEST_PATTERN
IMA_TX_GRP10_RX_TEST_PATTERN
IMA_TX_GRP10_CTL
Tx GRP 10 Rx Test Pattern
Tx GRP 10 Control
IMA_TX_GRP10_FIRST_PHY_ADDR
IMA_TX_GRP10_ID
Tx GRP 10 First Link Address
Tx GRP 10 Tx Group ID
Tx GRP 10 Status / Control
Tx GRP 10 Timing Control
Tx GRP 10 Test Control
Tx GRP 10 Tx Test Pattern
Tx GRP 11 Rx Test Pattern
IMA_TX_GRP10_STAT_CTL
IMA_TX_GRP10_TIMING_INFO
IMA_TX_GRP10_TEST_CTL
IMA_TX_GRP10_TX_TEST_PATTERN
IMA_TX_GRP11_RX_TEST_PATTERN
®
28529-DSH-001-K
Mindspeed Technologies
129
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (13 of 33)
Page
Number
Address
Name
Description (Continued)
0xa31
0xa32
0xa33
0xa34
0xa35
0xa36
0xa37
0xa38
0xa39
0xa3a
0xa3b
0xa3c
0xa3d
0xa3e
0xa3f
IMA_TX_GRP11_CTL
Tx GRP 11 Control
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
IMA_TX_GRP11_FIRST_PHY_ADDR
IMA_TX_GRP11_ID
Tx GRP 11 First Link Address
Tx GRP 11 Tx Group ID
Tx GRP 11 Status / Control
Tx GRP 11 Timing Control
Tx GRP 11 Test Control
Tx GRP 11 Tx Test Pattern
Tx GRP 12 Rx Test Pattern
Tx GRP 12 Control
IMA_TX_GRP11_STAT_CTL
IMA_TX_GRP11_TIMING_INFO
IMA_TX_GRP11_TEST_CTL
IMA_TX_GRP11_TX_TEST_PATTERN
IMA_TX_GRP12_RX_TEST_PATTERN
IMA_TX_GRP12_CTL
IMA_TX_GRP12_FIRST_PHY_ADDR
IMA_TX_GRP12_ID
Tx GRP 12 First Link Address
Tx GRP 12 Tx Group ID
Tx GRP 12 Status / Control
Tx GRP 12 Timing Control
Tx GRP 12 Test Control
Tx GRP 12 Tx Test Pattern
IMA_TX_GRP12_STAT_CTL
IMA_TX_GRP12_TIMING_INFO
IMA_TX_GRP12_TEST_CTL
IMA_TX_GRP12_TX_TEST_PATTERN
Tx UTOPIA Addresses 8 - 11 Cell Counters
0xa40
0xa41
0xa42
0xa43
0xa44
0xa45
0xa46
0xa47
IMA_TX_ATM8_CELL_COUNT_LSB
IMA_TX_ATM8_CELL_COUNT_MSB
IMA_TX_ATM9_CELL_COUNT_LSB
IMA_TX_ATM9_CELL_COUNT_MSB
IMA_TX_ATM10_CELL_COUNT_LSB
IMA_TX_ATM10_CELL_COUNT_MSB
IMA_TX_ATM11_CELL_COUNT_LSB
IMA_TX_ATM11_CELL_COUNT_MSB
Transmit UTOPIA Address 0x08 Cell Count LSBs
page 216
Transmit UTOPIA Address 0x08 Cell Count MSBs
Transmit UTOPIA Address 0x09 Cell Count LSBs
Transmit UTOPIA Address 0x09 Cell Count MSBs
Transmit UTOPIA Address 0x0A Cell Count LSBs
Transmit UTOPIA Address 0x0A Cell Count MSBs
Transmit UTOPIA Address 0x0B Cell Count LSBs
Transmit UTOPIA Address 0x0B Cell Count MSBs
Rx UTOPIA Addresses 8 - 11 Cell Counters
0xa50
0xa51
0xa52
0xa53
0xa54
0xa55
0xa56
0xa57
IMA_RX_ATM8_CELL_COUNT_LSB
IMA_RX_ATM8_CELL_COUNT_MSB
IMA_RX_ATM9_CELL_COUNT_LSB
IMA_RX_ATM9_CELL_COUNT_MSB
IMA_RX_ATM10_CELL_COUNT_LSB
IMA_RX_ATM10_CELL_COUNT_MSB
IMA_RX_ATM11_CELL_COUNT_LSB
IMA_RX_ATM11_CELL_COUNT_MSB
Receive UTOPIA Address 0x08 Cell Count LSBs
Receive UTOPIA Address 0x08 Cell Count MSBs
Receive UTOPIA Address 0x09 Cell Count LSBs
Receive UTOPIA Address 0x09 Cell Count MSBs
Receive UTOPIA Address 0x0A Cell Count LSBs
Receive UTOPIA Address 0x0A Cell Count MSBs
Receive UTOPIA Address 0x0B Cell Count LSBs
Receive UTOPIA Address 0x0B Cell Count MSBs
page 218
®
28529-DSH-001-K
Mindspeed Technologies
130
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (14 of 33)
Page
Number
Address
Name
Description (Continued)
Port 16–23 Control and Status
0xa60
0xa61
0xa62
0xa63
0xa64
0xa65
0xa66
0xa67
IMA_TX_LNK16_CTL
IMA_TX_LNK17_CTL
IMA_TX_LNK18_CTL
IMA_TX_LNK19_CTL
IMA_TX_LNK20_CTL
IMA_TX_LNK21_CTL
IMA_TX_LNK22_CTL
IMA_TX_LNK23_CTL
Tx Link 16 Control
Tx Link 17 Control
Tx Link 18 Control
Tx Link 19 Control
Tx Link 20 Control
Tx Link 21 Control
Tx Link 22 Control
Tx Link 23 Control
page 232
page 233
page 234
page 235
page 236
0xa68
0xa69
0xa6a
0xa6b
0xa6c
0xa6d
0xa6e
0xa6f
IMA_TX_LNK16_STATE
IMA_TX_LNK17_STATE
IMA_TX_LNK18_STATE
IMA_TX_LNK19_STATE
IMA_TX_LNK20_STATE
IMA_TX_LNK21_STATE
IMA_TX_LNK22_STATE
IMA_TX_LNK23_STATE
Tx Link 16 Status
Tx Link 17 Status
Tx Link 18 Status
Tx Link 19 Status
Tx Link 20 Status
Tx Link 21 Status
Tx Link 22 Status
Tx Link 23 Status
0xa70
0xa71
0xa72
0xa73
0xa74
0xa75
0xa76
0xa77
IMA_TX_LNK16_ID
IMA_TX_LNK17_ID
IMA_TX_LNK18_ID
IMA_TX_LNK19_ID
IMA_TX_LNK20_ID
IMA_TX_LNK21_ID
IMA_TX_LNK22_ID
IMA_TX_LNK23_ID
Tx Link 16 Assigned LID
Tx Link 17 Assigned LID
Tx Link 18 Assigned LID
Tx Link 19 Assigned LID
Tx Link 20 Assigned LID
Tx Link 21 Assigned LID
Tx Link 22 Assigned LID
Tx Link 23 Assigned LID
0xa80
0xa81
0xa82
0xa83
0xa84
0xa85
0xa86
0xa87
IMA_RX_LNK16_CTL
IMA_RX_LNK17_CTL
IMA_RX_LNK18_CTL
IMA_RX_LNK19_CTL
IMA_RX_LNK20_CTL
IMA_RX_LNK21_CTL
IMA_RX_LNK22_CTL
IMA_RX_LNK23_CTL
Rx Link 16 Control
Rx Link 17 Control
Rx Link 18 Control
Rx Link 19 Control
Rx Link 20 Control
Rx Link 21 Control
Rx Link 22 Control
Rx Link 23 Control
0xa88
0xa89
0xa8a
0xa8b
0xa8c
0xa8d
0xa8e
0xa8f
IMA_RX_LNK16_STATE
IMA_RX_LNK17_STATE
IMA_RX_LNK18_STATE
IMA_RX_LNK19_STATE
IMA_RX_LNK20_STATE
IMA_RX_LNK21_STATE
IMA_RX_LNK22_STATE
IMA_RX_LNK23_STATE
Rx Link 16 Status
Rx Link 17 Status
Rx Link 18 Status
Rx Link 19 Status
Rx Link 20 Status
Rx Link 21 Status
Rx Link 22 Status
Rx Link 23 Status
®
28529-DSH-001-K
Mindspeed Technologies
131
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (15 of 33)
Page
Number
Address
Name
Description (Continued)
0xa90
0xa91
0xa92
0xa93
0xa94
0xa95
0xa96
0xa97
IMA_RX_LNK16_DEFECT
Rx Link 16 Defects
Rx Link 17 Defects
Rx Link 18 Defects
Rx Link 19 Defects
Rx Link 20 Defects
Rx Link 21 Defects
Rx Link 22 Defects
Rx Link 23 Defects
page 237
page 238
page 239
page 240
page 241
page 242
IMA_RX_LNK17_DEFECT
IMA_RX_LNK18_DEFECT
IMA_RX_LNK19_DEFECT
IMA_RX_LNK20_DEFECT
IMA_RX_LNK21_DEFECT
IMA_RX_LNK22_DEFECT
IMA_RX_LNK23_DEFECT
0xa98
0xa99
0xa9a
0xa9b
0xa9c
0xa9d
0xa9e
0xa9f
IMA_FE_TX_LNK16_CFG
IMA_FE_TX_LNK17_CFG
IMA_FE_TX_LNK18_CFG
IMA_FE_TX_LNK19_CFG
IMA_FE_TX_LNK20_CFG
IMA_FE_TX_LNK21_CFG
IMA_FE_TX_LNK22_CFG
IMA_FE_TX_LNK23_CFG
FE Tx Link 16 Link Config
FE Tx Link 17 Link Config
FE Tx Link 18 Link Config
FE Tx Link 19 Link Config
FE Tx Link 20 Link Config
FE Tx Link 21 Link Config
FE Tx Link 22 Link Config
FE Tx Link 23 Link Config
0xaa0
0xaa1
0xaa2
0xaa3
0xaa4
0xaa5
0xaa6
0xaa7
IMA_FE_LNK16_STATE
IMA_FE_LNK17_STATE
IMA_FE_LNK18_STATE
IMA_FE_LNK19_STATE
IMA_FE_LNK20_STATE
IMA_FE_LNK21_STATE
IMA_FE_LNK22_STATE
IMA_FE_LNK23_STATE
Rx Link 16 FE Status
Rx Link 17 FE Status
Rx Link 18 FE Status
Rx Link 19 FE Status
Rx Link 20 FE Status
Rx Link 21 FE Status
Rx Link 22 FE Status
Rx Link 23 FE Status
0xaa8
0xaa9
0xaaa
0xaab
0xaac
0xaad
0xaae
0xaaf
IMA_RX_LNK16_ID
IMA_RX_LNK17_ID
IMA_RX_LNK18_ID
IMA_RX_LNK19_ID
IMA_RX_LNK20_ID
IMA_RX_LNK21_ID
IMA_RX_LNK22_ID
IMA_RX_LNK23_ID
Rx Link 16 Assigned LID
Rx Link 17 Assigned LID
Rx Link 18 Assigned LID
Rx Link 19 Assigned LID
Rx Link 20 Assigned LID
Rx Link 21 Assigned LID
Rx Link 22 Assigned LID
Rx Link 23 Assigned LID
0xab0
0xab1
0xab2
0xab3
0xab4
0xab5
0xab6
0xab7
IMA_RX_LNK16_IV_CNT
IMA_RX_LNK17_IV_CNT
IMA_RX_LNK18_IV_CNT
IMA_RX_LNK19_IV_CNT
IMA_RX_LNK20_IV_CNT
IMA_RX_LNK21_IV_CNT
IMA_RX_LNK22_IV_CNT
IMA_RX_LNK23_IV_CNT
Rx Link 16 IV-IMA Counter
Rx Link 17 IV-IMA Counter
Rx Link 18 IV-IMA Counter
Rx Link 19 IV-IMA Counter
Rx Link 20 IV-IMA Counter
Rx Link 21 IV-IMA Counter
Rx Link 22 IV-IMA Counter
Rx Link 23 IV-IMA Counter
0xab8
0xab9
0xaba
0xabb
0xabc
0xabd
0xabe
0xabf
IMA_RX_LNK16_OIF_CNT
IMA_RX_LNK17_OIF_CNT
IMA_RX_LNK18_OIF_CNT
IMA_RX_LNK19_OIF_CNT
IMA_RX_LNK20_OIF_CNT
IMA_RX_LNK21_OIF_CNT
IMA_RX_LNK22_OIF_CNT
IMA_RX_LNK23_OIF_CNT
Rx Link 16 OIF-IMA Counter
Rx Link 17 OIF-IMA Counter
Rx Link 18 OIF-IMA Counter
Rx Link 19 OIF-IMA Counter
Rx Link 20 OIF-IMA Counter
Rx Link 21 OIF-IMA Counter
Rx Link 22 OIF-IMA Counter
Rx Link 23 OIF-IMA Counter
®
28529-DSH-001-K
Mindspeed Technologies
132
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (16 of 33)
Page
Number
Address
Name
Description (Continued)
0xac0
0xac1
0xac2
0xac3
0xac4
0xac5
0xac6
0xac7
IMA_FE_TX_LNK16_GRP_ID
IMA_FE_TX_LNK17_GRP_ID
IMA_FE_TX_LNK18_GRP_ID
IMA_FE_TX_LNK19_GRP_ID
IMA_FE_TX_LNK20_GRP_ID
IMA_FE_TX_LNK21_GRP_ID
IMA_FE_TX_LNK22_GRP_ID
IMA_FE_TX_LNK23_GRP_ID
Rx Link 16 Captured GRP ID
page 243
Rx Link 17 Captured GRP ID
Rx Link 18 Captured GRP ID
Rx Link 19 Captured GRP ID
Rx Link 20 Captured GRP ID
Rx Link 21 Captured GRP ID
Rx Link 22 Captured GRP ID
Rx Link 23 Captured GRP ID
Receive Groups 9–12 Configuration Tables
0xad0
0xad1
0xad2
0xad3
0xad4
0xad5
0xad6
0xad7
0xad8
0xad9
0xada
0xadb
0xadc
0xadd
0xade
0xadf
IMA_RX_GRP9_CFG
Rx GRP 9 Configuration
Rx GRP 9 Control
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP9_CTL
IMA_RX_GRP9_FIRST_PHY_ADDR
IMA_RX_GRP9_ID
Rx GRP 9 First Link Address
Rx GRP 9 Rx Group ID
Rx GRP 10 Configuration
Rx GRP 10 Control
IMA_RX_GRP10_CFG
IMA_RX_GRP10_CTL
IMA_RX_GRP10_FIRST_PHY_ADDR
IMA_RX_GRP10_ID
Rx GRP 10 First Link Address
Rx GRP 10 Rx Group ID
Rx GRP 11 Configuration
Rx GRP 11 Control
IMA_RX_GRP11_CFG
IMA_RX_GRP11_CTL
IMA_RX_GRP11_FIRST_PHY_ADDR
IMA_RX_GRP11_ID
Rx GRP 11 First Link Address
Rx GRP 11 Rx Group ID
Rx GRP 12 Configuration
Rx GRP 12 Control
IMA_RX_GRP12_CFG
IMA_RX_GRP12_CTL
IMA_RX_GRP12_FIRST_PHY_ADDR
IMA_RX_GRP12_ID
Rx GRP 12 First Link Address
Rx GRP 12 Rx Group ID
Receive Groups 9–12 Far-End Status
0xae0
0xae2
0xae3
0xae4
0xae5
0xae6
0xae7
0xae8
0xaea
0xaeb
0xaec
IMA_RX_GRP9_RX_TEST_PATTERN
IMA_RX_GRP9_STAT_CTL_CHANGE
IMA_RX_GRP9_ACTUAL_GRP_ID
IMA_RX_GRP9_STAT_CTL
Rx GRP 9 Rx Test Pattern
Rx GRP 9 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
Rx GRP 9 Rx Group ID
Rx GRP 9 Status / Control
Rx GRP 9 Timing Control
Rx GRP 9 Test Control
Rx GRP 9 Tx Test Pattern
IMA_RX_GRP9_TIMING_INFO
IMA_RX_GRP9_TEST_CTL
IMA_RX_GRP9_TX_TEST_PATTERN
IMA_RX_GRP10_RX_TEST_PATTERN
IMA_RX_GRP10_STAT_CTL_CHANGE
IMA_RX_GRP10_ACTUAL_GRP_ID
IMA_RX_GRP10_STAT_CTL
Rx GRP 10 Rx Test Pattern
Rx GRP 10 SCCI
Rx GRP 10 Rx Group ID
Rx GRP 10 Status / Control
®
28529-DSH-001-K
Mindspeed Technologies
133
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (17 of 33)
Page
Number
Address
Name
Description (Continued)
0xaed
0xaee
0xaef
0xaf0
0xaf2
0xaf3
0xaf4
0xaf5
0xaf6
0xaf7
0xaf8
0xafa
0xafb
0xafc
0xafd
0xafe
0xaff
IMA_RX_GRP10_TIMING_INFO
IMA_RX_GRP10_TEST_CTL
Rx GRP 10 Timing Control
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
Rx GRP 10 Test Control
Rx GRP 10 Tx Test Pattern
Rx GRP 11 Rx Test Pattern
Rx GRP 11 SCCI
IMA_RX_GRP10_TX_TEST_PATTERN
IMA_RX_GRP11_RX_TEST_PATTERN
IMA_RX_GRP11_STAT_CTL_CHANGE
IMA_RX_GRP11_ACTUAL_GRP_ID
IMA_RX_GRP11_STAT_CTL
Rx GRP 11 Rx Group ID
Rx GRP 11 Status / Control
Rx GRP 11 Timing Control
Rx GRP 11 Test Control
Rx GRP 11 Tx Test Pattern
Rx GRP 12 Rx Test Pattern
Rx GRP 12 SCCI
IMA_RX_GRP11_TIMING_INFO
IMA_RX_GRP11_TEST_CTL
IMA_RX_GRP11_TX_TEST_PATTERN
IMA_RX_GRP12_RX_TEST_PATTERN
IMA_RX_GRP12_STAT_CTL_CHANGE
IMA_RX_GRP12_ACTUAL_GRP_ID
IMA_RX_GRP12_STAT_CTL
Rx GRP 12 Rx Group ID
Rx GRP 12 Status / Control
Rx GRP 12 Timing Control
Rx GRP 12 Test Control
Rx GRP 12 Tx Test Pattern
IMA_RX_GRP12_TIMING_INFO
IMA_RX_GRP12_TEST_CTL
IMA_RX_GRP12_TX_TEST_PATTERN
Transmit Groups 13–16 Configuration Tables
0xb20
0xb21
0xb22
0xb23
0xb24
0xb25
0xb26
0xb27
0xb28
0xb29
0xb2a
0xb2b
0xb2c
0xb2d
0xb2e
0xb2f
0xb30
IMA_TX_GRP13_RX_TEST_PATTERN
Tx GRP 13 Rx Test Pattern
Tx GRP 13 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
IMA_TX_GRP13_CTL
IMA_TX_GRP13_FIRST_PHY_ADDR
IMA_TX_GRP13_ID
Tx GRP 13 First Link Address
Tx GRP 13 Tx Group ID
Tx GRP 13 Status / Control
Tx GRP 13 Timing Control
Tx GRP 13 Test Control
Tx GRP 13 Tx Test Pattern
Tx GRP 14 Rx Test Pattern
Tx GRP 14 Control
IMA_TX_GRP13_STAT_CTL
IMA_TX_GRP13_TIMING_INFO
IMA_TX_GRP13_TEST_CTL
IMA_TX_GRP13_TX_TEST_PATTERN
IMA_TX_GRP14_RX_TEST_PATTERN
IMA_TX_GRP14_CTL
IMA_TX_GRP14_FIRST_PHY_ADDR
IMA_TX_GRP14_ID
Tx GRP 14 First Link Address
Tx GRP 14 Tx Group ID
Tx GRP 14 Status / Control
Tx GRP 14 Timing Control
Tx GRP 14 Test Control
Tx GRP 14 Tx Test Pattern
Tx GRP 15 Rx Test Pattern
IMA_TX_GRP14_STAT_CTL
IMA_TX_GRP14_TIMING_INFO
IMA_TX_GRP14_TEST_CTL
IMA_TX_GRP14_TX_TEST_PATTERN
IMA_TX_GRP15_RX_TEST_PATTERN
®
28529-DSH-001-K
Mindspeed Technologies
134
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (18 of 33)
Page
Number
Address
Name
Description (Continued)
0xb31
0xb32
0xb33
0xb34
0xb35
0xb36
0xb37
0xb38
0xb39
0xb3a
0xb3b
0xb3c
0xb3d
0xb3e
0xb3f
IMA_TX_GRP15_CTL
Tx GRP 15 Control
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
IMA_TX_GRP15_FIRST_PHY_ADDR
IMA_TX_GRP15_ID
Tx GRP 15 First Link Address
Tx GRP 15 Tx Group ID
Tx GRP 15 Status / Control
Tx GRP 15 Timing Control
Tx GRP 15 Test Control
Tx GRP 15 Tx Test Pattern
Tx GRP 16 Rx Test Pattern
Tx GRP 16 Control
IMA_TX_GRP15_STAT_CTL
IMA_TX_GRP15_TIMING_INFO
IMA_TX_GRP15_TEST_CTL
IMA_TX_GRP15_TX_TEST_PATTERN
IMA_TX_GRP16_RX_TEST_PATTERN
IMA_TX_GRP16_CTL
IMA_TX_GRP16_FIRST_PHY_ADDR
IMA_TX_GRP16_ID
Tx GRP 16 First Link Address
Tx GRP 16 Tx Group ID
Tx GRP 16 Status / Control
Tx GRP 16 Timing Control
Tx GRP 16 Test Control
Tx GRP 16 Tx Test Pattern
IMA_TX_GRP16_STAT_CTL
IMA_TX_GRP16_TIMING_INFO
IMA_TX_GRP16_TEST_CTL
IMA_TX_GRP16_TX_TEST_PATTERN
Tx UTOPIA Addresses 12 - 15 Cell Counters
0xb40
0xb41
0xb42
0xb43
0xb44
0xb45
0xb46
0xb47
IMA_TX_ATM12_CELL_COUNT_LSB
IMA_TX_ATM12_CELL_COUNT_MSB
IMA_TX_ATM13_CELL_COUNT_LSB
IMA_TX_ATM13_CELL_COUNT_MSB
IMA_TX_ATM14_CELL_COUNT_LSB
IMA_TX_ATM14_CELL_COUNT_MSB
IMA_TX_ATM15_CELL_COUNT_LSB
IMA_TX_ATM15_CELL_COUNT_MSB
Transmit UTOPIA Address 0x0C Cell Count LSBs
page 216
Transmit UTOPIA Address 0x0C Cell Count MSBs
Transmit UTOPIA Address 0x0D Cell Count LSBs
Transmit UTOPIA Address 0x0D Cell Count MSBs
Transmit UTOPIA Address 0x0E Cell Count LSBs
Transmit UTOPIA Address 0x0E Cell Count MSBs
Transmit UTOPIA Address 0x0F Cell Count LSBs
Transmit UTOPIA Address 0x0F Cell Count MSBs
Rx UTOPIA Addresses 12 - 15 Cell Counters
0xb50
0xb51
0xb52
0xb53
0xb54
0xb55
0xb56
0xb57
IMA_RX_ATM12_CELL_COUNT_LSB
IMA_RX_ATM12_CELL_COUNT_MSB
IMA_RX_ATM13_CELL_COUNT_LSB
IMA_RX_ATM13_CELL_COUNT_MSB
IMA_RX_ATM14_CELL_COUNT_LSB
IMA_RX_ATM14_CELL_COUNT_MSB
IMA_RX_ATM15_CELL_COUNT_LSB
IMA_RX_ATM15_CELL_COUNT_MSB
Receive UTOPIA Address 0x0C Cell Count LSBs
Receive UTOPIA Address 0x0C Cell Count MSBs
Receive UTOPIA Address 0x0D Cell Count LSBs
Receive UTOPIA Address 0x0D Cell Count MSBs
Receive UTOPIA Address 0x0E Cell Count LSBs
Receive UTOPIA Address 0x0E Cell Count MSBs
Receive UTOPIA Address 0x0F Cell Count LSBs
Receive UTOPIA Address 0x0F Cell Count MSBs
page 218
®
28529-DSH-001-K
Mindspeed Technologies
135
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (19 of 33)
Page
Number
Address
Name
Description (Continued)
Port 24–31 Control and Status
0xb60
0xb61
0xb62
0xb63
0xb64
0xb65
0xb66
0xb67
IMA_TX_LNK24_CTL
IMA_TX_LNK25_CTL
IMA_TX_LNK26_CTL
IMA_TX_LNK27_CTL
IMA_TX_LNK28_CTL
IMA_TX_LNK29_CTL
IMA_TX_LNK30_CTL
IMA_TX_LNK31_CTL
Tx Link 24 Control
Tx Link 25 Control
Tx Link 26 Control
Tx Link 27 Control
Tx Link 28 Control
Tx Link 29 Control
Tx Link 30 Control
Tx Link 31 Control
page 232
page 233
page 234
page 235
page 236
0xb68
0xb69
0xb6a
0xb6b
0xb6c
0xb6d
0xb6e
0xb6f
IMA_TX_LNK24_STATE
IMA_TX_LNK25_STATE
IMA_TX_LNK26_STATE
IMA_TX_LNK27_STATE
IMA_TX_LNK28_STATE
IMA_TX_LNK29_STATE
IMA_TX_LNK30_STATE
IMA_TX_LNK31_STATE
Tx Link 24 Status
Tx Link 25 Status
Tx Link 26 Status
Tx Link 27 Status
Tx Link 28 Status
Tx Link 29 Status
Tx Link 30 Status
Tx Link 31 Status
0xb70
0xb71
0xb72
0xb73
0xb74
0xb75
0xb76
0xb77
IMA_TX_LNK24_ID
IMA_TX_LNK25_ID
IMA_TX_LNK26_ID
IMA_TX_LNK27_ID
IMA_TX_LNK28_ID
IMA_TX_LNK29_ID
IMA_TX_LNK30_ID
IMA_TX_LNK31_ID
Tx Link 24 Assigned LID
Tx Link 25 Assigned LID
Tx Link 26 Assigned LID
Tx Link 27 Assigned LID
Tx Link 28 Assigned LID
Tx Link 29 Assigned LID
Tx Link 30 Assigned LID
Tx Link 31 Assigned LID
0xb80
0xb81
0xb82
0xb83
0xb84
0xb85
0xb86
0xb87
IMA_RX_LNK24_CTL
IMA_RX_LNK25_CTL
IMA_RX_LNK26_CTL
IMA_RX_LNK27_CTL
IMA_RX_LNK28_CTL
IMA_RX_LNK29_CTL
IMA_RX_LNK30_CTL
IMA_RX_LNK31_CTL
Rx Link 24 Control
Rx Link 25 Control
Rx Link 26 Control
Rx Link 27 Control
Rx Link 28 Control
Rx Link 29 Control
Rx Link 30 Control
Rx Link 31 Control
0xb88
0xb89
0xb8a
0xb8b
0xb8c
0xb8d
0xb8e
0xb8f
IMA_RX_LNK24_STATE
IMA_RX_LNK25_STATE
IMA_RX_LNK26_STATE
IMA_RX_LNK27_STATE
IMA_RX_LNK28_STATE
IMA_RX_LNK29_STATE
IMA_RX_LNK30_STATE
IMA_RX_LNK31_STATE
Rx Link 24 Status
Rx Link 25 Status
Rx Link 26 Status
Rx Link 27 Status
Rx Link 28 Status
Rx Link 29 Status
Rx Link 30 Status
Rx Link 31 Status
®
28529-DSH-001-K
Mindspeed Technologies
136
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (20 of 33)
Page
Number
Address
Name
Description (Continued)
0xb90
0xb91
0xb92
0xb93
0xb94
0xb95
0xb96
0xb97
IMA_RX_LNK24_DEFECT
Rx Link 24 Defects
Rx Link 25 Defects
Rx Link 26 Defects
Rx Link 27 Defects
Rx Link 28 Defects
Rx Link 29 Defects
Rx Link 30 Defects
Rx Link 31 Defects
page 237
page 238
page 239
page 240
page 241
page 242
IMA_RX_LNK25_DEFECT
IMA_RX_LNK26_DEFECT
IMA_RX_LNK27_DEFECT
IMA_RX_LNK28_DEFECT
IMA_RX_LNK29_DEFECT
IMA_RX_LNK30_DEFECT
IMA_RX_LNK31_DEFECT
0xb98
0xb99
0xb9a
0xb9b
0xb9c
0xb9d
0xb9e
0xb9f
IMA_FE_TX_LNK24_CFG
IMA_FE_TX_LNK25_CFG
IMA_FE_TX_LNK26_CFG
IMA_FE_TX_LNK27_CFG
IMA_FE_TX_LNK28_CFG
IMA_FE_TX_LNK29_CFG
IMA_FE_TX_LNK30_CFG
IMA_FE_TX_LNK31_CFG
FE Tx Link 24 Link Config
FE Tx Link 25 Link Config
FE Tx Link 26 Link Config
FE Tx Link 27 Link Config
FE Tx Link 28 Link Config
FE Tx Link 29 Link Config
FE Tx Link 30 Link Config
FE Tx Link 31 Link Config
0xba0
0xba1
0xba2
0xba3
0xba4
0xba5
0xba6
0xba7
IMA_FE_LNK24_STATE
IMA_FE_LNK25_STATE
IMA_FE_LNK26_STATE
IMA_FE_LNK27_STATE
IMA_FE_LNK28_STATE
IMA_FE_LNK29_STATE
IMA_FE_LNK30_STATE
IMA_FE_LNK31_STATE
Rx Link 24 FE Status
Rx Link 25 FE Status
Rx Link 26 FE Status
Rx Link 27 FE Status
Rx Link 28 FE Status
Rx Link 29 FE Status
Rx Link 30 FE Status
Rx Link 31 FE Status
0xba8
0xba9
0xbaa
0xbab
0xbac
0xbad
0xbae
0xbaf
IMA_RX_LNK24_ID
IMA_RX_LNK25_ID
IMA_RX_LNK26_ID
IMA_RX_LNK27_ID
IMA_RX_LNK28_ID
IMA_RX_LNK29_ID
IMA_RX_LNK30_ID
IMA_RX_LNK31_ID
Rx Link 24 Assigned LID
Rx Link 25 Assigned LID
Rx Link 26 Assigned LID
Rx Link 27 Assigned LID
Rx Link 28 Assigned LID
Rx Link 29 Assigned LID
Rx Link 30 Assigned LID
Rx Link 31 Assigned LID
0xbb0
0xbb1
0xbb2
0xbb3
0xbb4
0xbb5
0xbb6
0xbb7
IMA_RX_LNK24_IV_CNT
IMA_RX_LNK25_IV_CNT
IMA_RX_LNK26_IV_CNT
IMA_RX_LNK27_IV_CNT
IMA_RX_LNK28_IV_CNT
IMA_RX_LNK29_IV_CNT
IMA_RX_LNK30_IV_CNT
IMA_RX_LNK31_IV_CNT
Rx Link 24 IV-IMA Counter
Rx Link 25 IV-IMA Counter
Rx Link 26 IV-IMA Counter
Rx Link 27 IV-IMA Counter
Rx Link 28 IV-IMA Counter
Rx Link 29 IV-IMA Counter
Rx Link 30 IV-IMA Counter
Rx Link 31 IV-IMA Counter
0xbb8
0xbb9
0xbba
0xbbb
0xbbc
0xbbd
0xbbe
0xbbf
IMA_RX_LNK24_OIF_CNT
IMA_RX_LNK25_OIF_CNT
IMA_RX_LNK26_OIF_CNT
IMA_RX_LNK27_OIF_CNT
IMA_RX_LNK28_OIF_CNT
IMA_RX_LNK29_OIF_CNT
IMA_RX_LNK30_OIF_CNT
IMA_RX_LNK31_OIF_CNT
Rx Link 24 OIF-IMA Counter
Rx Link 25 OIF-IMA Counter
Rx Link 26 OIF-IMA Counter
Rx Link 27 OIF-IMA Counter
Rx Link 28 OIF-IMA Counter
Rx Link 29 OIF-IMA Counter
Rx Link 30 OIF-IMA Counter
Rx Link 31 OIF-IMA Counter
®
28529-DSH-001-K
Mindspeed Technologies
137
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (21 of 33)
Page
Number
Address
Name
Description (Continued)
0xbc0
0xbc1
0xbc2
0xbc3
0xbc4
0xbc5
0xbc6
0xbc7
IMA_FE_TX_LNK24_GRP_ID
IMA_FE_TX_LNK25_GRP_ID
IMA_FE_TX_LNK26_GRP_ID
IMA_FE_TX_LNK27_GRP_ID
IMA_FE_TX_LNK28_GRP_ID
IMA_FE_TX_LNK29_GRP_ID
IMA_FE_TX_LNK30_GRP_ID
IMA_FE_TX_LNK31_GRP_ID
Rx Link 24 Captured GRP ID
page 243
Rx Link 25 Captured GRP ID
Rx Link 26 Captured GRP ID
Rx Link 27 Captured GRP ID
Rx Link 28 Captured GRP ID
Rx Link 29 Captured GRP ID
Rx Link 30 Captured GRP ID
Rx Link 31 Captured GRP ID
Receive Groups 13–16 Configuration Tables
0xbd0
0xbd1
0xbd2
0xbd3
0xbd4
0xbd5
0xbd6
0xbd7
0xbd8
0xbd9
0xbda
0xbdb
0xbdc
0xbdd
0xbde
0xbdf
IMA_RX_GRP13_CFG
Rx GRP 13 Configuration
Rx GRP 13 Control
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP13_CTL
IMA_RX_GRP13_FIRST_PHY_ADDR
IMA_RX_GRP13_ID
Rx GRP 13 First Link Address
Rx GRP 13 Rx Group ID
Rx GRP 14 Configuration
Rx GRP 14 Control
IMA_RX_GRP14_CFG
IMA_RX_GRP14_CTL
IMA_RX_GRP14_FIRST_PHY_ADDR
IMA_RX_GRP14_ID
Rx GRP 14 First Link Address
Rx GRP 14 Rx Group ID
Rx GRP 15 Configuration
Rx GRP 15 Control
IMA_RX_GRP15_CFG
IMA_RX_GRP15_CTL
IMA_RX_GRP15_FIRST_PHY_ADDR
IMA_RX_GRP15_ID
Rx GRP 15 First Link Address
Rx GRP 15 Rx Group ID
Rx GRP 16 Configuration
Rx GRP 16 Control
IMA_RX_GRP16_CFG
IMA_RX_GRP16_CTL
IMA_RX_GRP16_FIRST_PHY_ADDR
IMA_RX_GRP16_ID
Rx GRP 16 First Link Address
Rx GRP 16 Rx Group ID
Receive Groups 13–16 Far-End Status
0xbe0
0xbe2
0xbe3
0xbe4
0xbe5
0xbe6
0xbe7
0xbe8
0xbea
0xbeb
0xbec
IMA_RX_GRP13_RX_TEST_PATTERN
IMA_RX_GRP13_STAT_CTL_CHANGE
IMA_RX_GRP13_ACTUAL_GRP_ID
IMA_RX_GRP13_STAT_CTL
Rx GRP 13 Rx Test Pattern
Rx GRP 13 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
Rx GRP 13 Rx Group ID
Rx GRP 13 Status / Control
Rx GRP 13 Timing Control
Rx GRP 13 Test Control
Rx GRP 13 Tx Test Pattern
Rx GRP 14 Rx Test Pattern
Rx GRP 14 SCCI
IMA_RX_GRP13_TIMING_INFO
IMA_RX_GRP13_TEST_CTL
IMA_RX_GRP13_TX_TEST_PATTERN
IMA_RX_GRP14_RX_TEST_PATTERN
IMA_RX_GRP14_STAT_CTL_CHANGE
IMA_RX_GRP14_ACTUAL_GRP_ID
IMA_RX_GRP14_STAT_CTL
Rx GRP 14 Rx Group ID
Rx GRP 14 Status / Control
®
28529-DSH-001-K
Mindspeed Technologies
138
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (22 of 33)
Page
Number
Address
Name
Description (Continued)
0xbed
0xbee
0xbef
0xbf0
0xbf2
0xbf3
0xbf4
0xbf5
0xbf6
0xbf7
0xbf8
0xbfa
0xbfb
0xbfc
0xbfd
0xbfe
0xbff
IMA_RX_GRP14_TIMING_INFO
IMA_RX_GRP14_TEST_CTL
Rx GRP 14 Timing Control
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
Rx GRP 14 Test Control
Rx GRP 14 Tx Test Pattern
Rx GRP 15 Rx Test Pattern
Rx GRP 15 SCCI
IMA_RX_GRP14_TX_TEST_PATTERN
IMA_RX_GRP15_RX_TEST_PATTERN
IMA_RX_GRP15_STAT_CTL_CHANGE
IMA_RX_GRP15_ACTUAL_GRP_ID
IMA_RX_GRP15_STAT_CTL
Rx GRP 15 Rx Group ID
Rx GRP 15 Status / Control
Rx GRP 15 Timing Control
Rx GRP 15 Test Control
Rx GRP 15 Tx Test Pattern
Rx GRP 16 Rx Test Pattern
Rx GRP 16 SCCI
IMA_RX_GRP15_TIMING_INFO
IMA_RX_GRP15_TEST_CTL
IMA_RX_GRP15_TX_TEST_PATTERN
IMA_RX_GRP16_RX_TEST_PATTERN
IMA_RX_GRP16_STAT_CTL_CHANGE
IMA_RX_GRP16_ACTUAL_GRP_ID
IMA_RX_GRP12_STAT_CTL
Rx GRP 16 Rx Group ID
Rx GRP 16 Status / Control
Rx GRP 16 Timing Control
Rx GRP 16 Test Control
Rx GRP 16 Tx Test Pattern
IMA_RX_GRP16_TIMING_INFO
IMA_RX_GRP16_TEST_CTL
IMA_RX_GRP16_TX_TEST_PATTERN
Transmit Groups 17–20 Configuration Tables
0xc20
0xc21
0xc22
0xc23
0xc24
0xc25
0xc26
0xc27
0xc28
0xc29
0xc2a
0xc2b
0xc2c
0xc2d
0xc2e
0xc2f
0xc30
IMA_TX_GRP17_RX_TEST_PATTERN
Tx GRP 17 Rx Test Pattern
Tx GRP 17 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
IMA_TX_GRP17_CTL
IMA_TX_GRP17_FIRST_PHY_ADDR
IMA_TX_GRP17_ID
Tx GRP 17 First Link Address
Tx GRP 17 Tx Group ID
Tx GRP 17 Status / Control
Tx GRP 17 Timing Control
Tx GRP 17 Test Control
Tx GRP 17 Tx Test Pattern
Tx GRP 18 Rx Test Pattern
Tx GRP 18 Control
IMA_TX_GRP17_STAT_CTL
IMA_TX_GRP17_TIMING_INFO
IMA_TX_GRP17_TEST_CTL
IMA_TX_GRP17_TX_TEST_PATTERN
IMA_TX_GRP18_RX_TEST_PATTERN
IMA_TX_GRP18_CTL
IMA_TX_GRP18_FIRST_PHY_ADDR
IMA_TX_GRP18_ID
Tx GRP 18 First Link Address
Tx GRP 18 Tx Group ID
Tx GRP 18 Status / Control
Tx GRP 18 Timing Control
Tx GRP 18 Test Control
Tx GRP 18 Tx Test Pattern
Tx GRP 19 Rx Test Pattern
IMA_TX_GRP18_STAT_CTL
IMA_TX_GRP18_TIMING_INFO
IMA_TX_GRP18_TEST_CTL
IMA_TX_GRP18_TX_TEST_PATTERN
IMA_TX_GRP19_RX_TEST_PATTERN
®
28529-DSH-001-K
Mindspeed Technologies
139
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (23 of 33)
Page
Number
Address
Name
Description (Continued)
0xc31
0xc32
0xc33
0xc34
0xc35
0xc36
0xc37
0xc38
0xc39
0xc3a
0xc3b
0xc3c
0xc3d
0xc3e
0xc3f
IMA_TX_GRP19_CTL
Tx GRP 19 Control
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
IMA_TX_GRP19_FIRST_PHY_ADDR
IMA_TX_GRP19_ID
Tx GRP 19 First Link Address
Tx GRP 19 Tx Group ID
Tx GRP 19 Status / Control
Tx GRP 19 Timing Control
Tx GRP 19 Test Control
Tx GRP 19 Tx Test Pattern
Tx GRP 20 Rx Test Pattern
Tx GRP 20 Control
IMA_TX_GRP19_STAT_CTL
IMA_TX_GRP19_TIMING_INFO
IMA_TX_GRP19_TEST_CTL
IMA_TX_GRP19_TX_TEST_PATTERN
IMA_TX_GRP20_RX_TEST_PATTERN
IMA_TX_GRP20_CTL
IMA_TX_GRP20_FIRST_PHY_ADDR
IMA_TX_GRP20_ID
Tx GRP 20 First Link Address
Tx GRP 20 Tx Group ID
Tx GRP 20 Status / Control
Tx GRP 20 Timing Control
Tx GRP 20 Test Control
Tx GRP 20 Tx Test Pattern
IMA_TX_GRP20_STAT_CTL
IMA_TX_GRP20_TIMING_INFO
IMA_TX_GRP20_TEST_CTL
IMA_TX_GRP20_TX_TEST_PATTERN
Tx UTOPIA Addresses 16 - 19 Cell Counters
0xc40
0xc41
0xc42
0xc43
0xc44
0xc45
0xc46
0xc47
IMA_TX_ATM16_CELL_COUNT_LSB
IMA_TX_ATM16_CELL_COUNT_MSB
IMA_TX_ATM17_CELL_COUNT_LSB
IMA_TX_ATM17_CELL_COUNT_MSB
IMA_TX_ATM18_CELL_COUNT_LSB
IMA_TX_ATM18_CELL_COUNT_MSB
IMA_TX_ATM19_CELL_COUNT_LSB
IMA_TX_ATM19_CELL_COUNT_MSB
Transmit UTOPIA Address 0x10 Cell Count LSBs
page 216
Transmit UTOPIA Address 0x10 Cell Count MSBs
Transmit UTOPIA Address 0x11 Cell Count LSBs
Transmit UTOPIA Address 0x11 Cell Count MSBs
Transmit UTOPIA Address 0x12 Cell Count LSBs
Transmit UTOPIA Address 0x12 Cell Count MSBs
Transmit UTOPIA Address 0x13 Cell Count LSBs
Transmit UTOPIA Address 0x13 Cell Count MSBs
Rx UTOPIA Addresses 16 - 19 Cell Counters
0xc48
0xc49
0xc4a
0xc4b
0xc4c
0xc4d
0xc4e
0xc4f
IMA_RX_ATM16_CELL_COUNT_LSB
IMA_RX_ATM16_CELL_COUNT_MSB
IMA_RX_ATM17_CELL_COUNT_LSB
IMA_RX_ATM17_CELL_COUNT_MSB
IMA_RX_ATM18_CELL_COUNT_LSB
IMA_RX_ATM18_CELL_COUNT_MSB
IMA_RX_ATM19_CELL_COUNT_LSB
IMA_RX_ATM19_CELL_COUNT_MSB
Receive UTOPIA Address 0x10 Cell Count LSBs
Receive UTOPIA Address 0x10 Cell Count MSBs
Receive UTOPIA Address 0x11 Cell Count LSBs
Receive UTOPIA Address 0x11 Cell Count MSBs
Receive UTOPIA Address 0x12 Cell Count LSBs
Receive UTOPIA Address 0x12 Cell Count MSBs
Receive UTOPIA Address 0x13 Cell Count LSBs
Receive UTOPIA Address 0x13 Cell Count MSBs
page 218
Receive Groups 17–20 Configuration Tables
0xc50
0xc51
0xc52
0xc53
0xc54
IMA_RX_GRP17_CFG
Rx GRP 17 Configuration
Rx GRP 17 Control
page 220
page 221
page 222
page 223
page 220
IMA_RX_GRP17_CTL
IMA_RX_GRP17_FIRST_PHY_ADDR
IMA_RX_GRP17_ID
Rx GRP 17 First Link Address
Rx GRP 17 Rx Group ID
Rx GRP 18 Configuration
IMA_RX_GRP18_CFG
®
28529-DSH-001-K
Mindspeed Technologies
140
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (24 of 33)
Page
Number
Address
Name
Description (Continued)
0xc55
0xc56
0xc57
0xc58
0xc59
0xc5a
0xc5b
0xc5c
0xc5d
0xc5e
0xc5f
IMA_RX_GRP18_CTL
Rx GRP 18 Control
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP18_FIRST_PHY_ADDR
IMA_RX_GRP18_ID
Rx GRP 18 First Link Address
Rx GRP 18 Rx Group ID
Rx GRP 19 Configuration
Rx GRP 19 Control
IMA_RX_GRP19_CFG
IMA_RX_GRP19_CTL
IMA_RX_GRP19_FIRST_PHY_ADDR
IMA_RX_GRP19_ID
Rx GRP 19 First Link Address
Rx GRP 19 Rx Group ID
Rx GRP 20 Configuration
Rx GRP 20 Control
IMA_RX_GRP20_CFG
IMA_RX_GRP20_CTL
IMA_RX_GRP20_FIRST_PHY_ADDR
IMA_RX_GRP20_ID
Rx GRP 20 First Link Address
Rx GRP 20 Rx Group ID
Receive Groups 17–20 Far-End Status
0xc60
0xc62
0xc63
0xc64
0xc65
0xc66
0xc67
0xc68
0xc6a
0xc6b
0xc6c
0xc6d
0xc6e
0xc6f
0xc70
0xc72
0xc73
0xc74
0xc75
0xc76
0xc77
0xc78
0xc7a
IMA_RX_GRP17_RX_TEST_PATTERN
IMA_RX_GRP17_STAT_CTL_CHANGE
IMA_RX_GRP17_ACTUAL_GRP_ID
IMA_RX_GRP17_STAT_CTL
Rx GRP 17 Rx Test Pattern
Rx GRP 17 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
Rx GRP 17 Rx Group ID
Rx GRP 17 Status / Control
Rx GRP 17 Timing Control
Rx GRP 17 Test Control
Rx GRP 17 Tx Test Pattern
Rx GRP 18 Rx Test Pattern
Rx GRP 18 SCCI
IMA_RX_GRP17_TIMING_INFO
IMA_RX_GRP17_TEST_CTL
IMA_RX_GRP17_TX_TEST_PATTERN
IMA_RX_GRP18_RX_TEST_PATTERN
IMA_RX_GRP18_STAT_CTL_CHANGE
IMA_RX_GRP18_ACTUAL_GRP_ID
IMA_RX_GRP18_STAT_CTL
Rx GRP 18 Rx Group ID
Rx GRP 18 Status / Control
Rx GRP 18 Timing Control
Rx GRP 18 Test Control
Rx GRP 18 Tx Test Pattern
Rx GRP 19 Rx Test Pattern
Rx GRP 19 SCCI
IMA_RX_GRP18_TIMING_INFO
IMA_RX_GRP18_TEST_CTL
IMA_RX_GRP18_TX_TEST_PATTERN
IMA_RX_GRP19_RX_TEST_PATTERN
IMA_RX_GRP19_STAT_CTL_CHANGE
IMA_RX_GRP19_ACTUAL_GRP_ID
IMA_RX_GRP19_STAT_CTL
Rx GRP 19 Rx Group ID
Rx GRP 19 Status / Control
Rx GRP 19 Timing Control
Rx GRP 19 Test Control
Rx GRP 19 Tx Test Pattern
Rx GRP 20 Rx Test Pattern
Rx GRP 20 SCCI
IMA_RX_GRP19_TIMING_INFO
IMA_RX_GRP19_TEST_CTL
IMA_RX_GRP19_TX_TEST_PATTERN
IMA_RX_GRP20_RX_TEST_PATTERN
IMA_RX_GRP20_STAT_CTL_CHANGE
®
28529-DSH-001-K
Mindspeed Technologies
141
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (25 of 33)
Page
Number
Address
Name
Description (Continued)
0xc7b
0xc7c
0xc7d
0xc7e
0xc7f
IMA_RX_GRP20_ACTUAL_GRP_ID
IMA_RX_GRP20_STAT_CTL
Rx GRP 20 Rx Group ID
page 226
page 227
page 228
page 229
page 230
Rx GRP 20 Status / Control
Rx GRP 20 Timing Control
Rx GRP 20 Test Control
Rx GRP 20 Tx Test Pattern
IMA_RX_GRP20_TIMING_INFO
IMA_RX_GRP20_TEST_CTL
IMA_RX_GRP20_TX_TEST_PATTERN
Transmit Groups 21–24 Configuration Tables
0xca0
0xca1
0xca2
0xca3
0xca4
0xca5
0xca6
0xca7
0xca8
0xca9
0xcaa
0xcab
0xcac
0xcad
0xcae
0xcaf
IMA_TX_GRP21_RX_TEST_PATTERN
Tx GRP 21 Rx Test Pattern
Tx GRP 21 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
IMA_TX_GRP21_CTL
IMA_TX_GRP21_FIRST_PHY_ADDR
IMA_TX_GRP21_ID
Tx GRP 21 First Link Address
Tx GRP 21 Tx Group ID
Tx GRP 21 Status / Control
Tx GRP 21 Timing Control
Tx GRP 21 Test Control
Tx GRP 21 Tx Test Pattern
Tx GRP 22 Rx Test Pattern
Tx GRP 22 Control
IMA_TX_GRP21_STAT_CTL
IMA_TX_GRP21_TIMING_INFO
IMA_TX_GRP21_TEST_CTL
IMA_TX_GRP21_TX_TEST_PATTERN
IMA_TX_GRP22_RX_TEST_PATTERN
IMA_TX_GRP22_CTL
IMA_TX_GRP22_FIRST_PHY_ADDR
IMA_TX_GRP22_ID
Tx GRP 22 First Link Address
Tx GRP 22 Tx Group ID
Tx GRP 22 Status / Control
Tx GRP 22 Timing Control
Tx GRP 22 Test Control
Tx GRP 22 Tx Test Pattern
Tx GRP 23 Rx Test Pattern
Tx GRP 23 Control
IMA_TX_GRP22_STAT_CTL
IMA_TX_GRP22_TIMING_INFO
IMA_TX_GRP22_TEST_CTL
IMA_TX_GRP22_TX_TEST_PATTERN
IMA_TX_GRP23_RX_TEST_PATTERN
IMA_TX_GRP23_CTL
0xcb0
0xcb1
0xcb2
0xcb3
0xcb4
0xcb5
0xcb6
0xcb7
0xcb8
0xcb9
0xcba
0xcbb
0xcbc
IMA_TX_GRP23_FIRST_PHY_ADDR
IMA_TX_GRP23_ID
Tx GRP 23 First Link Address
Tx GRP 23 Tx Group ID
Tx GRP 23 Status / Control
Tx GRP 23 Timing Control
Tx GRP 23 Test Control
Tx GRP 23 Tx Test Pattern
Tx GRP 24 Rx Test Pattern
Tx GRP 24 Control
IMA_TX_GRP23_STAT_CTL
IMA_TX_GRP23_TIMING_INFO
IMA_TX_GRP23_TEST_CTL
IMA_TX_GRP23_TX_TEST_PATTERN
IMA_TX_GRP24_RX_TEST_PATTERN
IMA_TX_GRP24_CTL
IMA_TX_GRP24_FIRST_PHY_ADDR
IMA_TX_GRP24_ID
Tx GRP 24 First Link Address
Tx GRP 24 Tx Group ID
Tx GRP 24 Status / Control
IMA_TX_GRP24_STAT_CTL
®
28529-DSH-001-K
Mindspeed Technologies
142
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (26 of 33)
Page
Number
Address
Name
Description (Continued)
0xcbd
0xcbe
0xcbf
IMA_TX_GRP24_TIMING_INFO
IMA_TX_GRP24_TEST_CTL
Tx GRP 24 Timing Control
page 213
page 214
page 215
Tx GRP 24 Test Control
IMA_TX_GRP24_TX_TEST_PATTERN
Tx GRP 24 Tx Test Pattern
Tx UTOPIA Addresses 20 - 23 Cell Counters
0xcc0
0xcc1
0xcc2
0xcc3
0xcc4
0xcc5
0xcc6
0xcc7
IMA_TX_ATM20_CELL_COUNT_LSB
IMA_TX_ATM20_CELL_COUNT_MSB
IMA_TX_ATM21_CELL_COUNT_LSB
IMA_TX_ATM21_CELL_COUNT_MSB
IMA_TX_ATM22_CELL_COUNT_LSB
IMA_TX_ATM22_CELL_COUNT_MSB
IMA_TX_ATM23_CELL_COUNT_LSB
IMA_TX_ATM23_CELL_COUNT_MSB
Transmit UTOPIA Address 0x14 Cell Count LSBs
page 216
Transmit UTOPIA Address 0x14 Cell Count MSBs
Transmit UTOPIA Address 0x15 Cell Count LSBs
Transmit UTOPIA Address 0x15 Cell Count MSBs
Transmit UTOPIA Address 0x16 Cell Count LSBs
Transmit UTOPIA Address 0x16 Cell Count MSBs
Transmit UTOPIA Address 0x17 Cell Count LSBs
Transmit UTOPIA Address 0x17 Cell Count MSBs
Rx UTOPIA Addresses 20 - 23 Cell Counters
0xcc8
0xcc9
0xcca
0xccb
0xccc
0xccd
0xcce
0xccf
IMA_RX_ATM20_CELL_COUNT_LSB
IMA_RX_ATM20_CELL_COUNT_MSB
IMA_RX_ATM21_CELL_COUNT_LSB
IMA_RX_ATM21_CELL_COUNT_MSB
IMA_RX_ATM22_CELL_COUNT_LSB
IMA_RX_ATM22_CELL_COUNT_MSB
IMA_RX_ATM23_CELL_COUNT_LSB
IMA_RX_ATM23_CELL_COUNT_MSB
Receive UTOPIA Address 0x14 Cell Count LSBs
Receive UTOPIA Address 0x14 Cell Count MSBs
Receive UTOPIA Address 0x15 Cell Count LSBs
Receive UTOPIA Address 0x15 Cell Count MSBs
Receive UTOPIA Address 0x16 Cell Count LSBs
Receive UTOPIA Address 0x16 Cell Count MSBs
Receive UTOPIA Address 0x17 Cell Count LSBs
Receive UTOPIA Address 0x17 Cell Count MSBs
page 218
Receive Groups 21–24 Configuration Tables
0xcd0
0xcd1
0xcd2
0xcd3
0xcd4
0xcd5
0xcd6
0xcd7
0xcd8
0xcd9
0xcda
0xcdb
0xcdc
0xcdd
0xcde
0xcdf
IMA_RX_GRP21_CFG
Rx GRP 21 Configuration
Rx GRP 21 Control
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP21_CTL
IMA_RX_GRP21_FIRST_PHY_ADDR
IMA_RX_GRP21_ID
Rx GRP 21 First Link Address
Rx GRP 21 Rx Group ID
Rx GRP 22 Configuration
Rx GRP 22 Control
IMA_RX_GRP22_CFG
IMA_RX_GRP22_CTL
IMA_RX_GRP22_FIRST_PHY_ADDR
IMA_RX_GRP22_ID
Rx GRP 22 First Link Address
Rx GRP 22 Rx Group ID
Rx GRP 23 Configuration
Rx GRP 23 Control
IMA_RX_GRP23_CFG
IMA_RX_GRP23_CTL
IMA_RX_GRP23_FIRST_PHY_ADDR
IMA_RX_GRP23_ID
Rx GRP 23 First Link Address
Rx GRP 23 Rx Group ID
Rx GRP 24 Configuration
Rx GRP 24 Control
IMA_RX_GRP24_CFG
IMA_RX_GRP24_CTL
IMA_RX_GRP24_FIRST_PHY_ADDR
IMA_RX_GRP24_ID
Rx GRP 24 First Link Address
Rx GRP 24 Rx Group ID
®
28529-DSH-001-K
Mindspeed Technologies
143
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (27 of 33)
Page
Number
Address
Name
Description (Continued)
Receive Groups 21–24 Far-End Status
0xce0
0xce2
0xce3
0xce4
0xce5
0xce6
0xce7
0xce8
0xcea
0xceb
0xcec
0xced
0xcee
0xcef
0xcf0
0xcf2
0xcf3
0xcf4
0xcf5
0xcf6
0xcf7
0xcf8
0xcfa
0xcfb
0xcfc
0xcfd
0xcfe
0xcff
IMA_RX_GRP21_RX_TEST_PATTERN
IMA_RX_GRP21_STAT_CTL_CHANGE
IMA_RX_GRP21_ACTUAL_GRP_ID
IMA_RX_GRP21_STAT_CTL
Rx GRP 21 Rx Test Pattern
Rx GRP 21 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
Rx GRP 21 Rx Group ID
Rx GRP 21 Status / Control
Rx GRP 21 Timing Control
Rx GRP 21 Test Control
Rx GRP 21 Tx Test Pattern
Rx GRP 22 Rx Test Pattern
Rx GRP 22 SCCI
IMA_RX_GRP21_TIMING_INFO
IMA_RX_GRP21_TEST_CTL
IMA_RX_GRP21_TX_TEST_PATTERN
IMA_RX_GRP22_RX_TEST_PATTERN
IMA_RX_GRP22_STAT_CTL_CHANGE
IMA_RX_GRP22_ACTUAL_GRP_ID
IMA_RX_GRP22_STAT_CTL
Rx GRP 22 Rx Group ID
Rx GRP 22 Status / Control
Rx GRP 22 Timing Control
Rx GRP 22 Test Control
Rx GRP 22 Tx Test Pattern
Rx GRP 23 Rx Test Pattern
Rx GRP 23 SCCI
IMA_RX_GRP22_TIMING_INFO
IMA_RX_GRP22_TEST_CTL
IMA_RX_GRP22_TX_TEST_PATTERN
IMA_RX_GRP23_RX_TEST_PATTERN
IMA_RX_GRP23_STAT_CTL_CHANGE
IMA_RX_GRP23_ACTUAL_GRP_ID
IMA_RX_GRP23_STAT_CTL
Rx GRP 23 Rx Group ID
Rx GRP 23 Status / Control
Rx GRP 23 Timing Control
Rx GRP 23 Test Control
Rx GRP 23 Tx Test Pattern
Rx GRP 24 Rx Test Pattern
Rx GRP 24 SCCI
IMA_RX_GRP23_TIMING_INFO
IMA_RX_GRP23_TEST_CTL
IMA_RX_GRP23_TX_TEST_PATTERN
IMA_RX_GRP24_RX_TEST_PATTERN
IMA_RX_GRP24_STAT_CTL_CHANGE
IMA_RX_GRP24_ACTUAL_GRP_ID
IMA_RX_GRP24_STAT_CTL
Rx GRP 24 Rx Group ID
Rx GRP 24 Status / Control
Rx GRP 24 Timing Control
Rx GRP 24 Test Control
Rx GRP 24 Tx Test Pattern
IMA_RX_GRP24_TIMING_INFO
IMA_RX_GRP24_TEST_CTL
IMA_RX_GRP24_TX_TEST_PATTERN
Transmit Groups 25–28 Configuration Tables
0xd20
0xd21
0xd22
0xd23
0xd24
IMA_TX_GRP25_RX_TEST_PATTERN
Tx GRP 25 Rx Test Pattern
Tx GRP 25 Control
page 208
page 209
page 210
page 211
page 212
IMA_TX_GRP25_CTL
IMA_TX_GRP25_FIRST_PHY_ADDR
IMA_TX_GRP25_ID
Tx GRP 25 First Link Address
Tx GRP 25 Tx Group ID
Tx GRP 25 Status / Control
IMA_TX_GRP25_STAT_CTL
®
28529-DSH-001-K
Mindspeed Technologies
144
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (28 of 33)
Page
Number
Address
Name
Description (Continued)
0xd25
0xd26
0xd27
0xd28
0xd29
0xd2a
0xd2b
0xd2c
0xd2d
0xd2e
0xd2f
0xd30
0xd31
0xd32
0xd33
0xd34
0xd35
0xd36
0xd37
0xd38
0xd39
0xd3a
0xd3b
0xd3c
0xd3d
0xd3e
0xd3f
IMA_TX_GRP25_TIMING_INFO
IMA_TX_GRP25_TEST_CTL
IMA_TX_GRP25_TX_TEST_PATTERN
IMA_TX_GRP26_RX_TEST_PATTERN
IMA_TX_GRP26_CTL
Tx GRP 25 Timing Control
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
Tx GRP 25 Test Control
Tx GRP 25 Tx Test Pattern
Tx GRP 26 Rx Test Pattern
Tx GRP 26 Control
IMA_TX_GRP26_FIRST_PHY_ADDR
IMA_TX_GRP26_ID
Tx GRP 26 First Link Address
Tx GRP 26 Tx Group ID
Tx GRP 26 Status / Control
Tx GRP 26 Timing Control
Tx GRP 26 Test Control
Tx GRP 26 Tx Test Pattern
Tx GRP 27 Rx Test Pattern
Tx GRP 27 Control
IMA_TX_GRP26_STAT_CTL
IMA_TX_GRP26_TIMING_INFO
IMA_TX_GRP26_TEST_CTL
IMA_TX_GRP26_TX_TEST_PATTERN
IMA_TX_GRP27_RX_TEST_PATTERN
IMA_TX_GRP27_CTL
IMA_TX_GRP27_FIRST_PHY_ADDR
IMA_TX_GRP27_ID
Tx GRP 27 First Link Address
Tx GRP 27 Tx Group ID
Tx GRP 27 Status / Control
Tx GRP 27 Timing Control
Tx GRP 27 Test Control
Tx GRP 27 Tx Test Pattern
Tx GRP 28 Rx Test Pattern
Tx GRP 28 Control
IMA_TX_GRP27_STAT_CTL
IMA_TX_GRP27_TIMING_INFO
IMA_TX_GRP27_TEST_CTL
IMA_TX_GRP27_TX_TEST_PATTERN
IMA_TX_GRP28_RX_TEST_PATTERN
IMA_TX_GRP28_CTL
IMA_TX_GRP28_FIRST_PHY_ADDR
IMA_TX_GRP28_ID
Tx GRP 28 First Link Address
Tx GRP 28 Tx Group ID
Tx GRP 28 Status / Control
Tx GRP 28 Timing Control
Tx GRP 28 Test Control
Tx GRP 28 Tx Test Pattern
IMA_TX_GRP28_STAT_CTL
IMA_TX_GRP28_TIMING_INFO
IMA_TX_GRP28_TEST_CTL
IMA_TX_GRP28_TX_TEST_PATTERN
Tx UTOPIA Addresses 24 - 27 Cell Counters
0xd40
0xd41
0xd42
0xd43
0xd44
0xd45
0xd46
0xd47
IMA_TX_ATM24_CELL_COUNT_LSB
IMA_TX_ATM24_CELL_COUNT_MSB
IMA_TX_ATM25_CELL_COUNT_LSB
IMA_TX_ATM25_CELL_COUNT_MSB
IMA_TX_ATM26_CELL_COUNT_LSB
IMA_TX_ATM26_CELL_COUNT_MSB
IMA_TX_ATM27_CELL_COUNT_LSB
IMA_TX_ATM27_CELL_COUNT_MSB
Transmit UTOPIA Address 0x18 Cell Count LSBs
page 216
Transmit UTOPIA Address 0x18 Cell Count MSBs
Transmit UTOPIA Address 0x19 Cell Count LSBs
Transmit UTOPIA Address 0x19 Cell Count MSBs
Transmit UTOPIA Address 0x1A Cell Count LSBs
Transmit UTOPIA Address 0x1A Cell Count MSBs
Transmit UTOPIA Address 0x1B Cell Count LSBs
Transmit UTOPIA Address 0x1B Cell Count MSBs
®
28529-DSH-001-K
Mindspeed Technologies
145
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (29 of 33)
Page
Number
Address
Name
Description (Continued)
Rx UTOPIA Addresses 24 - 27 Cell Counters
0xd48
0xd49
0xd4a
0xd4b
0xd4c
0xd4d
0xd4e
0xd4f
IMA_RX_ATM24_CELL_COUNT_LSB
IMA_RX_ATM24_CELL_COUNT_MSB
IMA_RX_ATM25_CELL_COUNT_LSB
IMA_RX_ATM25_CELL_COUNT_MSB
IMA_RX_ATM26_CELL_COUNT_LSB
IMA_RX_ATM26_CELL_COUNT_MSB
IMA_RX_ATM27_CELL_COUNT_LSB
IMA_RX_ATM27_CELL_COUNT_MSB
Receive UTOPIA Address 0x18 Cell Count LSBs
Receive UTOPIA Address 0x18 Cell Count MSBs
Receive UTOPIA Address 0x19 Cell Count LSBs
Receive UTOPIA Address 0x19 Cell Count MSBs
Receive UTOPIA Address 0x1A Cell Count LSBs
Receive UTOPIA Address 0x1A Cell Count MSBs
Receive UTOPIA Address 0x1B Cell Count LSBs
Receive UTOPIA Address 0x1B Cell Count MSBs
page 218
Receive Groups 25–28 Configuration Tables
0xd50
0xd51
0xd52
0xd53
0xd54
0xd55
0xd56
0xd57
0xd58
0xd59
0xd5a
0xd5b
0xd5c
0xd5d
0xd5e
0xd5f
IMA_RX_GRP25_CFG
Rx GRP 25 Configuration
Rx GRP 25 Control
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
IMA_RX_GRP25_CTL
IMA_RX_GRP25_FIRST_PHY_ADDR
IMA_RX_GRP25_ID
Rx GRP 25 First Link Address
Rx GRP 25 Rx Group ID
Rx GRP 26 Configuration
Rx GRP 26 Control
IMA_RX_GRP26_CFG
IMA_RX_GRP26_CTL
IMA_RX_GRP26_FIRST_PHY_ADDR
IMA_RX_GRP26_ID
Rx GRP 26 First Link Address
Rx GRP 26 Rx Group ID
Rx GRP 27 Configuration
Rx GRP 27 Control
IMA_RX_GRP27_CFG
IMA_RX_GRP27_CTL
IMA_RX_GRP27_FIRST_PHY_ADDR
IMA_RX_GRP27_ID
Rx GRP 27 First Link Address
Rx GRP 27 Rx Group ID
Rx GRP 28 Configuration
Rx GRP 28 Control
IMA_RX_GRP28_CFG
IMA_RX_GRP28_CTL
IMA_RX_GRP28_FIRST_PHY_ADDR
IMA_RX_GRP28_ID
Rx GRP 28 First Link Address
Rx GRP 28 Rx Group ID
Receive Groups 25–28 Far-End Status
0xd60
0xd62
0xd63
0xd64
0xd65
0xd66
0xd67
0xd68
0xd6a
0xd6b
IMA_RX_GRP25_RX_TEST_PATTERN
IMA_RX_GRP25_STAT_CTL_CHANGE
IMA_RX_GRP25_ACTUAL_GRP_ID
IMA_RX_GRP25_STAT_CTL
Rx GRP 25 Rx Test Pattern
Rx GRP 25 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
Rx GRP 25 Rx Group ID
Rx GRP 25 Status / Control
Rx GRP 25 Timing Control
Rx GRP 25 Test Control
Rx GRP 25 Tx Test Pattern
Rx GRP 26 Rx Test Pattern
Rx GRP 26 SCCI
IMA_RX_GRP25_TIMING_INFO
IMA_RX_GRP25_TEST_CTL
IMA_RX_GRP25_TX_TEST_PATTERN
IMA_RX_GRP26_RX_TEST_PATTERN
IMA_RX_GRP26_STAT_CTL_CHANGE
IMA_RX_GRP26_ACTUAL_GRP_ID
Rx GRP 26 Rx Group ID
®
28529-DSH-001-K
Mindspeed Technologies
146
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (30 of 33)
Page
Number
Address
Name
Description (Continued)
0xd6c
0xd6d
0xd6e
0xd6f
0xd70
0xd72
0xd73
0xd74
0xd75
0xd76
0xd77
0xd78
0xd7a
0xd7b
0xd7c
0xd7d
0xd7e
0xd7f
IMA_RX_GRP26_STAT_CTL
Rx GRP 26 Status / Control
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
IMA_RX_GRP26_TIMING_INFO
IMA_RX_GRP26_TEST_CTL
Rx GRP 26 Timing Control
Rx GRP 26 Test Control
Rx GRP 26 Tx Test Pattern
Rx GRP 27 Rx Test Pattern
Rx GRP 27 SCCI
IMA_RX_GRP26_TX_TEST_PATTERN
IMA_RX_GRP27_RX_TEST_PATTERN
IMA_RX_GRP27_STAT_CTL_CHANGE
IMA_RX_GRP27_ACTUAL_GRP_ID
IMA_RX_GRP27_STAT_CTL
Rx GRP 27 Rx Group ID
Rx GRP 27 Status / Control
Rx GRP 27 Timing Control
Rx GRP 27 Test Control
Rx GRP 27 Tx Test Pattern
Rx GRP 28 Rx Test Pattern
Rx GRP 28 SCCI
IMA_RX_GRP27_TIMING_INFO
IMA_RX_GRP27_TEST_CTL
IMA_RX_GRP27_TX_TEST_PATTERN
IMA_RX_GRP28_RX_TEST_PATTERN
IMA_RX_GRP28_STAT_CTL_CHANGE
IMA_RX_GRP28_ACTUAL_GRP_ID
IMA_RX_GRP28_STAT_CTL
Rx GRP 28 Rx Group ID
Rx GRP 28 Status / Control
Rx GRP 28 Timing Control
Rx GRP 28 Test Control
Rx GRP 28 Tx Test Pattern
IMA_RX_GRP28_TIMING_INFO
IMA_RX_GRP28_TEST_CTL
IMA_RX_GRP28_TX_TEST_PATTERN
Transmit Groups 29–32 Configuration Tables
0xda0
0xda1
0xda2
0xda3
0xda4
0xda5
0xda6
0xda7
0xda8
0xda9
0xdaa
0xdab
0xdac
0xdad
0xdae
0xdaf
IMA_TX_GRP29_RX_TEST_PATTERN
Tx GRP 29 Rx Test Pattern
Tx GRP 29 Control
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
IMA_TX_GRP29_CTL
IMA_TX_GRP29_FIRST_PHY_ADDR
IMA_TX_GRP29_ID
Tx GRP 29 First Link Address
Tx GRP 29 Tx Group ID
Tx GRP 29 Status / Control
Tx GRP 29 Timing Control
Tx GRP 29 Test Control
Tx GRP 29 Tx Test Pattern
Tx GRP 30 Rx Test Pattern
Tx GRP 30 Control
IMA_TX_GRP29_STAT_CTL
IMA_TX_GRP29_TIMING_INFO
IMA_TX_GRP29_TEST_CTL
IMA_TX_GRP29_TX_TEST_PATTERN
IMA_TX_GRP30_RX_TEST_PATTERN
IMA_TX_GRP30_CTL
IMA_TX_GRP30_FIRST_PHY_ADDR
IMA_TX_GRP30_ID
Tx GRP 30 First Link Address
Tx GRP 30 Tx Group ID
Tx GRP 30 Status / Control
Tx GRP 30 Timing Control
Tx GRP 30 Test Control
Tx GRP 30 Tx Test Pattern
IMA_TX_GRP30_STAT_CTL
IMA_TX_GRP30_TIMING_INFO
IMA_TX_GRP30_TEST_CTL
IMA_TX_GRP30_TX_TEST_PATTERN
®
28529-DSH-001-K
Mindspeed Technologies
147
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (31 of 33)
Page
Number
Address
Name
Description (Continued)
0xdb0
0xdb1
0xdb2
0xdb3
0xdb4
0xdb5
0xdb6
0xdb7
0xdb8
0xdb9
0xdba
0xdbb
0xdbc
0xdbd
0xdbe
0xdbf
IMA_TX_GRP31_RX_TEST_PATTERN
IMA_TX_GRP31_CTL
Tx GRP 31 Rx Test Pattern
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
page 208
page 209
page 210
page 211
page 212
page 213
page 214
page 215
Tx GRP 31 Control
IMA_TX_GRP31_FIRST_PHY_ADDR
IMA_TX_GRP31_ID
Tx GRP 31 First Link Address
Tx GRP 31 Tx Group ID
Tx GRP 31 Status / Control
Tx GRP 31 Timing Control
Tx GRP 31 Test Control
Tx GRP 31 Tx Test Pattern
Tx GRP 32 Rx Test Pattern
Tx GRP 32 Control
IMA_TX_GRP31_STAT_CTL
IMA_TX_GRP31_TIMING_INFO
IMA_TX_GRP31_TEST_CTL
IMA_TX_GRP31_TX_TEST_PATTERN
IMA_TX_GRP32_RX_TEST_PATTERN
IMA_TX_GRP32_CTL
IMA_TX_GRP32_FIRST_PHY_ADDR
IMA_TX_GRP32_ID
Tx GRP 32 First Link Address
Tx GRP 32 Tx Group ID
Tx GRP 32 Status / Control
Tx GRP 32 Timing Control
Tx GRP 32 Test Control
Tx GRP 32 Tx Test Pattern
IMA_TX_GRP32_STAT_CTL
IMA_TX_GRP32_TIMING_INFO
IMA_TX_GRP32_TEST_CTL
IMA_TX_GRP32_TX_TEST_PATTERN
Tx UTOPIA Addresses 28 - 31 Cell Counters
0xdc0
0xdc1
0xdc2
0xdc3
0xdc4
0xdc5
0xdc6
0xdc7
IMA_TX_ATM28_CELL_COUNT_LSB
IMA_TX_ATM28_CELL_COUNT_MSB
IMA_TX_ATM29_CELL_COUNT_LSB
IMA_TX_ATM29_CELL_COUNT_MSB
IMA_TX_ATM30_CELL_COUNT_LSB
IMA_TX_ATM30_CELL_COUNT_MSB
IMA_TX_ATM31_CELL_COUNT_LSB
IMA_TX_ATM31_CELL_COUNT_MSB
Transmit UTOPIA Address 0x1C Cell Count LSBs
page 216
Transmit UTOPIA Address 0x1C Cell Count MSBs
Transmit UTOPIA Address 0x1D Cell Count LSBs
Transmit UTOPIA Address 0x1D Cell Count MSBs
Transmit UTOPIA Address 0x1E Cell Count LSBs
Transmit UTOPIA Address 0x1E Cell Count MSBs
Transmit UTOPIA Address 0x1F Cell Count LSBs
Transmit UTOPIA Address 0x1F Cell Count MSBs
Rx UTOPIA Addresses 28 - 31 Cell Counters
0xdc8
0xdc9
0xdca
0xdcb
0xdcc
0xdcd
0xdce
0xdcf
IMA_RX_ATM28_CELL_COUNT_LSB
IMA_RX_ATM28_CELL_COUNT_MSB
IMA_RX_ATM29_CELL_COUNT_LSB
IMA_RX_ATM29_CELL_COUNT_MSB
IMA_RX_ATM30_CELL_COUNT_LSB
IMA_RX_ATM30_CELL_COUNT_MSB
IMA_RX_ATM31_CELL_COUNT_LSB
IMA_RX_ATM31_CELL_COUNT_MSB
Receive UTOPIA Address 0x1C Cell Count LSBs
Receive UTOPIA Address 0x1C Cell Count MSBs
Receive UTOPIA Address 0x1D Cell Count LSBs
Receive UTOPIA Address 0x1D Cell Count MSBs
Receive UTOPIA Address 0x1E Cell Count LSBs
Receive UTOPIA Address 0x1E Cell Count MSBs
Receive UTOPIA Address 0x1F Cell Count LSBs
Receive UTOPIA Address 0x1F Cell Count MSBs
page 218
Receive Groups 29–32 Configuration Tables
0xdd0
0xdd1
0xdd2
0xdd3
IMA_RX_GRP29_CFG
Rx GRP 29 Configuration
Rx GRP 29 Control
page 220
page 221
page 222
page 223
IMA_RX_GRP29_CTL
IMA_RX_GRP29_FIRST_PHY_ADDR
IMA_RX_GRP29_ID
Rx GRP 29 First Link Address
Rx GRP 29 Rx Group ID
®
28529-DSH-001-K
Mindspeed Technologies
148
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (32 of 33)
Page
Number
Address
Name
Description (Continued)
0xdd4
0xdd5
0xdd6
0xdd7
0xdd8
0xdd9
0xdda
0xddb
0xddc
0xddd
0xdde
0xddf
IMA_RX_GRP30_CFG
IMA_RX_GRP30_CTL
Rx GRP 30 Configuration
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
page 220
page 221
page 222
page 223
Rx GRP 30 Control
IMA_RX_GRP30_FIRST_PHY_ADDR
IMA_RX_GRP30_ID
Rx GRP 30 First Link Address
Rx GRP 30 Rx Group ID
Rx GRP 31 Configuration
Rx GRP 31 Control
IMA_RX_GRP31_CFG
IMA_RX_GRP31_CTL
IMA_RX_GRP31_FIRST_PHY_ADDR
IMA_RX_GRP31_ID
Rx GRP 31 First Link Address
Rx GRP 31 Rx Group ID
Rx GRP 32 Configuration
Rx GRP 32 Control
IMA_RX_GRP32_CFG
IMA_RX_GRP32_CTL
IMA_RX_GRP32_FIRST_PHY_ADDR
IMA_RX_GRP32_ID
Rx GRP 32 First Link Address
Rx GRP 32 Rx Group ID
Receive Groups 29–32 Far-End Status
0xde0
0xde2
0xde3
0xde4
0xde5
0xde6
0xde7
0xde8
0xdea
0xdeb
0xdec
0xded
0xdee
0xdef
0xdf0
0xdf2
0xdf3
0xdf4
0xdf5
0xdf6
0xdf7
0xdf8
IMA_RX_GRP29_RX_TEST_PATTERN
IMA_RX_GRP29_STAT_CTL_CHANGE
IMA_RX_GRP29_ACTUAL_GRP_ID
IMA_RX_GRP29_STAT_CTL
Rx GRP 29 Rx Test Pattern
Rx GRP 29 SCCI
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
page 225
page 226
page 227
page 228
page 229
page 230
page 224
Rx GRP 29 Rx Group ID
Rx GRP 29 Status / Control
Rx GRP 29 Timing Control
Rx GRP 29 Test Control
Rx GRP 29 Tx Test Pattern
Rx GRP 30 Rx Test Pattern
Rx GRP 30 SCCI
IMA_RX_GRP29_TIMING_INFO
IMA_RX_GRP29_TEST_CTL
IMA_RX_GRP29_TX_TEST_PATTERN
IMA_RX_GRP30_RX_TEST_PATTERN
IMA_RX_GRP30_STAT_CTL_CHANGE
IMA_RX_GRP30_ACTUAL_GRP_ID
IMA_RX_GRP30_STAT_CTL
Rx GRP 30 Rx Group ID
Rx GRP 30 Status / Control
Rx GRP 30 Timing Control
Rx GRP 30 Test Control
Rx GRP 30 Tx Test Pattern
Rx GRP 31 Rx Test Pattern
Rx GRP 31 SCCI
IMA_RX_GRP30_TIMING_INFO
IMA_RX_GRP30_TEST_CTL
IMA_RX_GRP30_TX_TEST_PATTERN
IMA_RX_GRP31_RX_TEST_PATTERN
IMA_RX_GRP31_STAT_CTL_CHANGE
IMA_RX_GRP31_ACTUAL_GRP_ID
IMA_RX_GRP31_STAT_CTL
Rx GRP 31 Rx Group ID
Rx GRP 31 Status / Control
Rx GRP 31 Timing Control
Rx GRP 31 Test Control
Rx GRP 31 Tx Test Pattern
Rx GRP 32 Rx Test Pattern
IMA_RX_GRP31_TIMING_INFO
IMA_RX_GRP31_TEST_CTL
IMA_RX_GRP31_TX_TEST_PATTERN
IMA_RX_GRP32_RX_TEST_PATTERN
®
28529-DSH-001-K
Mindspeed Technologies
149
Mindspeed Proprietary and Confidential
Registers
Table 2-10. IMA Control and Status Registers (33 of 33)
Page
Number
Address
Name
Description (Continued)
0xdfa
0xdfb
0xdfc
0xdfd
0xdfe
0xdff
IMA_RX_GRP32_STAT_CTL_CHANGE
IMA_RX_GRP32_ACTUAL_GRP_ID
IMA_RX_GRP32_STAT_CTL
Rx GRP 32 SCCI
page 225
page 226
page 227
page 228
page 229
page 230
Rx GRP 32 Rx Group ID
Rx GRP 32 Status / Control
Rx GRP 32 Timing Control
Rx GRP 32 Test Control
Rx GRP 32 Tx Test Pattern
IMA_RX_GRP32_TIMING_INFO
IMA_RX_GRP32_TEST_CTL
IMA_RX_GRP32_TX_TEST_PATTERN
ATM Cell Capture Registers
0xe00-
0xe2F
CELL_CAP_PAYLDn
Cell Capture Payload Contents Registers
page 244
0xe30
0xe31
0xe32
CAP_FAC
Capture Facility Register
Capture Control Register
Capture Status Register
page 244
page 244
page 245
CAP_CNTL
CAP_STAT
2.2
TC Registers
2.2.1
0x00—SUMINT (Summary Interrupt Indication Status Register)
The SUMINT register indicates the one-second interrupts, external framer interrupts, and port summary interrupts.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
—
—
—
—
—
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0
Reserved, set to a logical 0.
0
0
0
0
—
(1)
—
TxCellInt
When a logical 1 is read, this bit indicates a Transmit Cell Interrupt. This interrupt is a summary
interrupt and signifies that an interrupt indication occurred in the TxCellInt register (0x2C).
(1)
0
—
RxCellInt
When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a summary
interrupt and signifies that an interrupt indication occurred in the RxCellInt register (0x2D).
Footnote:
(1) This bit is a summary indication of any interrupt events that occurred in the indicated registers. This bit is a pointer to the next interrupt
indication register to be read. This bit will be cleared when the interrupt bits in the corresponding interrupt indication registers are read
and automatically cleared.
®
28529-DSH-001-K
Mindspeed Technologies
150
Mindspeed Proprietary and Confidential
Registers
2.2.2
0x01—ENSUMINT (Summary Interrupt Control Register)
The ENSUMINT register controls which of the interrupts listed in the SUMINT register (0x00) appear in the
SUMPORT register and on the MicroInt* (pin AA1), provided the corresponding ENSUMPORT bit is enabled and
EnIntPin (bit 3) in the GENCTRL register (0xF00) is enabled.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
—
—
—
—
—
—
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
EnTxCellInt
When written to a logical 1, this bit enables the transmit cell interrupts located in the TxCellInt
register (0x2C). These interrupts appear can on the MicroInt* pin (pin AA1), provided that
EnPortInt in the ENSUMPORT0-3 register (0x0F06, 0x0F08, 0x0F0A, 0x0F0C) is enabled for this
port and EnIntPin (bit 3) in the GENCTRL register (0x0F00) is enabled.
0
0
EnRxCellInt
When written to a logical 1, this bit enables the receive cell interrupts located in the RxCellInt
register (0x2D). These interrupts can appear on the MicroInt* pin (pin AA1), provided that
EnPortInt in the ENSUMPORT0-3 register (0x0F06, 0x0F08, 0x0F0A, 0x0F0C) is enabled for this
port and EnIntPin (bit 3) in the GENCTRL register (0x0F00) is enabled.
®
28529-DSH-001-K
Mindspeed Technologies
151
Mindspeed Proprietary and Confidential
Registers
2.2.3
0x04—PMODE (Port Mode Control Register)
The PMODE register controls the port-level software resets, source loopback, and physical layer interface mode.
Bit
Default
Name
Description
7
0
PrtMstRst
When written to a logical 1, this bit initiates a Port Master Reset. All internal state machines
associated with this port are reset and all control registers for this port, except this one, assume
their default values. Only bits 0–6 in this register are overwritten with their default values.
6
5
0
0
PrtLgcRst
When written to a logical 1, this bit initiates a Port Logic Reset. All internal state machines
associated with this port are reset but all registers (0x00–0x3F) listed as “Type: W/R” in Table 2-
3 are unaltered. Output signals for this port are three-state during Port Logic Reset.
(1)
SrcLoop
When written to a logical 1, this bit enables a source loopback. The line transmit clock and data
outputs are connected to the line receive clock and data inputs. Refer to Figure 1-12. During
Source loopback mode 0, the device is automatically configured for General Purpose mode
(ignoring the contents of the PhyType[2:0] bits).
(1)
4
3
0
0
FeLnLoop
Enables Far-end line loopback. In this mode, the receive data is processed by the TC block and
looped back at the UTOPIA interface to the transmit side. Refer to Figure 1-13.
(1)
SrcLoopMode
When source loopback is enabled (when SrcLoop is written to a logic 1), this bit select between
the two types of source loopback as follows:
0 - Source Loopback 0 selected
1 - Source Loopback 1 selected
(1)
2
1
0
0
0
0
PhyType[2]
These bits determine the Physical Layer Interface Mode:
(1)
PhyType[1]
000—T1 mode
001—E1 mode
010—Reserved
011—Reserved
100—Reserved
101—General Purpose
110—DSL Mode
111—Power Down
(1)
PhyType[0]
In General Purpose Mode, the SPRxSync and SPTxSync pins are ignored. (However,
good design practice would have them tied high.)
Footnote:
(1) These bits should only be changed when the device or port logic reset is asserted.
®
28529-DSH-001-K
Mindspeed Technologies
152
Mindspeed Proprietary and Confidential
Registers
2.2.4
0x05—IOMODE (Input/Output Mode Control Register)
The IOMODE register controls the line interface signal polarities and status outputs.
Bit
Default
Name
Description
7
6
0
0
—
Reserved, set to 0.
(1)
RxSyncPol
This bit determines the Receiver Synchronization input Polarity. When written to a logical 1, the
active level on the SPRxSync input is high. When written to a logical 0, the active level is low.
(1)
5
0
RxClkPol
This bit determines the Receiver Clock Input Polarity. When written to a logical 1, the active edge
on the SPRxClk input is the falling edge. When written to a logical 0, the active edge is the rising
edge.
(1)
4
3
0
0
TxSyncPol
This bit determines the Transmitter Synchronization input Polarity. When written to a logical 1,
the active level on the SPTxSync input is high. When written to a logical 0, the active level is low.
(1)
TxClkPol
This bit determines the Transmitter Clock Input Polarity. When written to a logical 1, the active
edge on the SPTxClk input is the falling edge. When written to a logical 0, the active edge is the
rising edge.
(1)
2
0
TxDatShft
This bit when set to a logical 1 shifts the serial Tx data by 1/2 a cycle. This results in the Tx data
being output a 1/2 SPTxClk cycle later than when the Tx inputs are sampled. This feature is
disabled when set to 0.
1
0
0
—
—
Reserved, set to 0.
Reserved, set to 0.
0
Footnote:
(1) These bits should only be changed when the device or port logic reset is asserted.
®
28529-DSH-001-K
Mindspeed Technologies
153
Mindspeed Proprietary and Confidential
Registers
2.2.5
0x08—CGEN (Cell Generation Control Register)
The CGEN register controls the device’s cell generation functions.
Bit
Default
Name
Description
7
0
DisHEC
When written to a logical 1, this bit disables internal generation of the HEC field. When disabled,
the HEC field from the UTOPIA interface remains unchanged in the transmitted cell. When
written to a logical 0, HEC is internally calculated and inserted in the transmitted cell.
6
5
4
1
1
0
EnTxCos
When written to a logical 1, this bit enables the Transmit HEC Coset. When written to a logical 0,
the HEC Coset is disabled.
EnTxCellScr
ErrHEC
When written to a logical 1, this bit enables the Transmit Cell Scrambler. When written to a
logical 0, the Transmit Cell Scrambler is disabled.
When written to a logical 1, this bit causes the ERRPAT register to be XORed with the calculated
HEC byte for one transmit cell. These bits are cleared automatically by internal circuitry after the
indicated error insertion has taken place. Clearing takes precedence over a simultaneous write
operation to this register.
3
0
DSLSyncPol
This bit controls the polarity of the sync pulse in DSL mode. Set to 1 for active high and to 0 for
active low.
2
1
0
0
—
Reserved, write to a logical 0.
EnTxDSSScr
When written to a logical 1, this bit enables the Transmit DSS Scrambler. When written to a
logical 0, the Transmit DSS Scrambler is disabled.
0
0
EnRxDSSScr
When written to a logical 1, this bit enables the Receive DSS Scrambler. When written to a
logical 0, the Receive DSS Scrambler is disabled.
®
28529-DSH-001-K
Mindspeed Technologies
154
Mindspeed Proprietary and Confidential
Registers
2.2.6
0x09—HDRFIELD (Header Field Control Register)
The HDRFIELD register controls the header insertion elements.
Bit
Default
Name
Description
7
6
5
4
0
0
0
0
—
—
—
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
InsGFC
InsVPI
InsVCI
InsPT
When written to a logical 1, this bit inserts a Generic Flow Control (GFC) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the GFC field is not changed prior
to transmission.
3
2
1
0
0
0
0
0
When written to a logical 1, this bit inserts a Virtual Path Identifier (VPI) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the VPI field is not changed prior
to transmission.
When written to a logical 1, this bit inserts a Virtual Channel Identifier (VCI) field in the outgoing
header from the TXHDR registers. When written to a logical 0, the VCI field is not changed prior
to transmission.
When written to a logical 1, this bit inserts a Payload Type (PT) field in the outgoing header from
the TXHDR registers. When written to a logical 0, the PT field is not changed prior to
transmission.
InsCLP
When written to a logical 1, this bit inserts a Cell Loss Priority (CLP) bit in the outgoing header
from the TXHDR registers. When written to a logical 0, the CLP field is not changed prior to
transmission.
2.2.7
0x0A—IDLPAY (Transmit Idle Cell Payload Control Register)
The IDLPAY register contains the transmit idle cell payload.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
1
1
0
1
0
1
0
IdlPay[7]
IdlPay[6]
IdlPay[5]
IdlPay[4]
IdlPay[3]
IdlPay[2]
IdlPay[1]
IdlPay[0]
These bits hold the Transmit Idle Cell Payload values for outgoing idle cells.
®
28529-DSH-001-K
Mindspeed Technologies
155
Mindspeed Proprietary and Confidential
Registers
2.2.8
0x0B—ERRPAT (Error Pattern Control Register)
The ERRPAT register provides the error pattern for the HEC error insertion function. ErrHEC (bit 4) in the CGEN
register (0x08) enables this function. Each bit in the error pattern register is XORed with the corresponding bit of
the calculated HEC byte to be errored.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ErrPat[7]
ErrPat[6]
ErrPat[5]
ErrPat[4]
ErrPat[3]
ErrPat[2]
ErrPat[1]
ErrPat[0]
Error pattern bit 7.
Error pattern bit 6.
Error pattern bit 5.
Error pattern bit 4.
Error pattern bit 3.
Error pattern bit 2.
Error pattern bit 1.
Error pattern bit 0.
2.2.9
0x0C—CVAL (Cell Validation Control Register)
The CVAL register controls the validation of incoming cells.
Bit
Default
Name
Description
7
0
RejHdr
When written to a logical 1, this bit enables the Rejection of certain Header cells. When enabled,
cells with headers matching the RXHDRx/RXMSKx definition are rejected and all others are
accepted. When written to a logical 0, cells with matching headers are accepted and cells with
non-matching headers are rejected.
6
1
DelIdle
When written to a logical 1, this bit enables the Deletion of Idle Cells. When enabled, cells
matching the RXIDL/IDLMSK definition are deleted from the received cell stream. When written
to a logical 0, idle cells are included in the received stream.
5
4
3
2
1
1
1
0
0
0
EnRxCos
When written to a logical 1, this bit enables the Receive HEC Coset. When written to a logical 0,
the HEC Coset is disabled.
EnRxCellScr
EnHECCorr
DisHECChk
DisCellRcvr
When written to a logical 1, this bit enables the Receive Cell Scrambler. When written to a logical
0, the Receive Cell Scrambler is disabled.
When written to a logical 1, this bit enables HEC Correction. When written to a logical 0, HEC
Correction is disabled.
When written to a logical 1, this bit disables HEC Checking. When written to a logical 0, HEC
checking is performed as a cell validation criterion. See Table 1-26.
When written to a logical 1, this bit disables the Cell Receiver. When disabled, all cell reception is
disabled on the next cell boundary. When written to a logical 0, cell reception begins or resumes
on the next cell boundary.
0
0
DisLOCD
When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled, cells are
passed even if cell delineation has not been found. When written to a logical 0, cells are passed
only while cell alignment has been achieved. See Table 1-26.
®
28529-DSH-001-K
Mindspeed Technologies
156
Mindspeed Proprietary and Confidential
Registers
2.2.10
0x0D—UTOP1 (UTOPIA Control Register 1)
The UTOP1 register controls the UTOPIA resets.
Bit
Default
Name
Description
7
0
TxReset
RxReset
When written to a logical 1, this bit resets the transmit FIFO pointers. This reset should only be
used as a test function because it can create short cells.
6
0
When written to a logical 1, this bit resets the receive FIFO pointers. This reset should only be
used as a test function because it can create short cells.
5
4
3
2
1
0
0
0
0
0
0
0
—
—
—
—
—
—
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
Reserved, write to a logical 0.
2.2.11
0x0E—UTOP2 (UTOPIA Control Register 2) (TC Block)
The UTOP2 register contains the multi-PHY address value for the port.
Bit
Default
Name
Description
7
0
0
—
—
Reserved, write to a logical 0.
Reserved, write to a logical 0.
6
(1)
5
1
UtopDis
When written to a logical 1, this bit disables UTOPIA outputs for this port.
(1)
4
0
MphyAddr[4]—MSB
These bits are the Multi-PHY Device Address. Each M2852x port should have a unique address.
These bits correspond to the URxAddr and UTxAddr pins. When the pin matches the bit values,
the port is accessed. This port ignores any transactions meant for another port or PHY device.
(1)
3
(2)
(2)
(2)
(2)
MphyAddr[3]
(1)
2
MphyAddr[2]
(1)
1
MphyAddr[1]
(1)
0
MphyAddr[0]—LSB
Footnote:
(1) These bits should only be changed when the device or port logic reset is asserted.
(2) The default for these bits is the port number for each port. (0000—Port 0, 0001—Port 1, 0010—Port 2, 0011—Port 3, 0100—Port 4,
0101—Port 5, 0110—Port 6, 0111—Port 7, 1000—Port 8, 1001—Port 9, 1010—Port 10, 1011—Port 11, 1100—Port 12, 1101—Port
13, 1110—Port 14, 1111—Port 15, 0000—Port 16, 0001—Port 17, 0010—Port 18, 0011—Port 19, 0100—Port 20, 0101—Port 21,
0110—Port 22, 0111—Port 23, 1000—Port 24, 1001—Port 25, 1010—Port 26, 1011—Port 27, 1100—Port 28, 1101—Port 29,
1110—Port 30, 1111—Port 31)
®
28529-DSH-001-K
Mindspeed Technologies
157
Mindspeed Proprietary and Confidential
Registers
2.2.12
0x0F—UDF2 (UDF2 Control Register)
The contents of the UDF2 register are inserted into the UDF2 byte on the UTOPIA receive bus when operating in
16-bit UTOPIA mode.
Bit
Default
Name
Description
7
0
0
UDF2[7]
UDF2[6]
UDF2[5]
UDF2[4]
UDF2[3]
UDF2[2]
UDF2[1]
UDF2[0]
The contents of this register are output over the UTOPIA receive bus when operating in UTOPIA
16-bit mode. The default matches the port address.
6
5
0
4
0
3
(1)
(1)
(1)
(1)
2
1
0
Footnote:
(1) The default for these bits is the port number for each port. (0000—Port 0, 0001—Port 1, 0010—Port 2, 0011—Port 3, 0100—Port 4,
0101—Port 5, 0110—Port 6, 0111—Port 7, 1000—Port 8, 1001—Port 9, 1010—Port 10, 1011—Port 11, 1100—Port 12, 1101—Port
13, 1110—Port 14, 1111—Port 15, 0000—Port 16, 0001—Port 17, 0010—Port 18, 0011—Port 19, 0100—Port 20, 0101—Port 21,
0110—Port 22, 0111—Port 23, 1000—Port 24, 1001—Port 25, 1010—Port 26, 1011—Port 27, 1100—Port 28, 1101—Port 29,
1110—Port 30, 1111—Port 31)
2.2.13
0x10—TXHDR1 (Transmit Cell Header Control Register 1)
The TXHDR1 register contains the first byte of the Transmit Cell Header. It controls the header value that is
inserted in the transmitted cell. This header consists of 32 bits divided among four registers (TXHDR1–4).
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxHdr1[7]
These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion of the bits
is controlled by the HDRFIELD register (0x09).
TxHdr1[6]
TxHdr1[5]
TxHdr1[4]
TxHdr1[3]
TxHdr1[2]
TxHdr1[1]
TxHdr1[0]
GFC/VPI bits
(for UNI they are GFC bits, for NNI they are VPI bits)
VPI bits
®
28529-DSH-001-K
Mindspeed Technologies
158
Mindspeed Proprietary and Confidential
Registers
2.2.14
0x11—TXHDR2 (Transmit Cell Header Control Register 2)
The TXHDR2 register contains the second byte of the Transmit Cell Header. (See 0x10—TXHDR1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxHdr2[7]
These bits hold the Transmit Header values for Octet 2 of the outgoing cell. Insertion of the bits
is controlled by the HDRFIELD register (0x09).
TxHdr2[6]
TxHdr2[5]
TxHdr2[4]
TxHdr2[3]
TxHdr2[2]
TxHdr2[1]
TxHdr2[0]
VPI bits
VCI bits
2.2.15
0x12—TXHDR3 (Transmit Cell Header Control Register 3)
The TXHDR3 register contains the third byte of the Transmit Cell Header. (See 0x10—TXHDR1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxHdr3[7]
These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion of the bits
is controlled by the HDRFIELD register (0x09).
TxHdr3[6]
TxHdr3[5]
TxHdr3[4]
TxHdr3[3]
TxHdr3[2]
TxHdr3[1]
TxHdr3[0]
VCI bits
®
28529-DSH-001-K
Mindspeed Technologies
159
Mindspeed Proprietary and Confidential
Registers
2.2.16
0x13—TXHDR4 (Transmit Cell Header Control Register 4)
The TXHDR4 register contains the fourth byte of the Transmit Cell Header. (See 0x10—TXHDR1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxHdr4[7]
These bits hold the Transmit Header values for Octet 4 of the outgoing cell. Insertion of the bits
is controlled by the HDRFIELD register (0x09).
TxHdr4[6]
TxHdr4[5]
TxHdr4[4]
TxHdr4[3]
TxHdr4[2]
TxHdr4[1]
TxHdr4[0]
VCI bits
Payload-type bits
Cell Loss Priority bit
2.2.17
0x14—TXIDL1 (Transmit Idle Cell Header Control Register 1)
The TXIDL1 register contains the first byte of the Transmit Idle Cell Header. It controls the header value that is
inserted in the transmitted idle cells. This header consists of 32 bits divided among four registers.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxIdl1[7]
TxIdl1[6]
TxIdl1[5]
TxIdl1[4]
TxIdl1[3]
TxIdl1[2]
TxIdl1[1]
TxIdl1[0]
These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell.
GFC/VPI bits
(for UNI they are GFC bits, for NNI the are VPI bits)
VPI bits
®
28529-DSH-001-K
Mindspeed Technologies
160
Mindspeed Proprietary and Confidential
Registers
2.2.18
0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2)
The TXIDL2 register contains the second byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxIdl2[7]
TxIdl2[6]
TxIdl2[5]
TxIdl2[4]
TxIdl2[3]
TxIdl2[2]
TxIdl2[1]
TxIdl2[0]
These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell.
VPI bits
VCI bits
2.2.19
0x16—TXIDL3 (Transmit Idle Cell Header Control Register 3)
The TXIDL3 register contains the third byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
TxIdl3[7]
TxIdl3[6]
TxIdl3[5]
TxIdl3[4]
TxIdl3[3]
TxIdl3[2]
TxIdl3[1]
TxIdl3[0]
These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell.
VCI bits
®
28529-DSH-001-K
Mindspeed Technologies
161
Mindspeed Proprietary and Confidential
Registers
2.2.20
0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4)
The TXIDL4 register contains the fourth byte of the Transmit Idle Cell Header. (See 0x14—TXIDL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
TxIdl4[7]
TxIdl4[6]
TxIdl4[5]
TxIdl4[4]
TxIdl4[3]
TxIdl4[2]
TxIdl4[1]
TxIdl4[0]
These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell.
VCI bits
Payload-type bits
Cell Loss Priority bit
2.2.21
0x18—RXHDR1 (Receive Cell Header Control Register 1)
The RXHDR1 register contains the first byte of the Receive Cell Header. The header values direct ATM cells to the
UTOPIA port if an incoming ATM cell header matches the value in the header register. Receive Header Mask
Registers further qualify ATM cell reception. This header consists of 32 bits divided among four registers.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxHdr1[7]
These bits hold the Receive Header values for Octet 1 of the incoming cell.
RxHdr1[6]
RxHdr1[5]
RxHdr1[4]
RxHdr1[3]
RxHdr1[2]
RxHdr1[1]
RxHdr1[0]
®
28529-DSH-001-K
Mindspeed Technologies
162
Mindspeed Proprietary and Confidential
Registers
2.2.22
0x19—RXHDR2 (Receive Cell Header Control Register 2)
The RXHDR2 register contains the second byte of the Receive Cell Header. (See 0x18—RXHDR1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxHdr2[7]
These bits hold the Receive Header values for Octet 2 of the incoming cell.
RxHdr2[6]
RxHdr2[5]
RxHdr2[4]
RxHdr2[3]
RxHdr2[2]
RxHdr2[1]
RxHdr2[0]
2.2.23
0x1A—RXHDR3 (Receive Cell Header Control Register 3)
The RXHDR3 register contains the third byte of the Receive Cell Header. (See 0x18—RXHDR1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxHdr3[7]
These bits hold the Receive Header values for Octet 3 of the incoming cell.
RxHdr3[6]
RxHdr3[5]
RxHdr3[4]
RxHdr3[3]
RxHdr3[2]
RxHdr3[1]
RxHdr3[0]
®
28529-DSH-001-K
Mindspeed Technologies
163
Mindspeed Proprietary and Confidential
Registers
2.2.24
0x1B—RXHDR4 (Receive Cell Header Control Register 4)
The RXHDR4 register contains the fourth byte of the Receive Cell Header. (See 0x18—RXHDR1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxHdr4[7]
These bits hold the Receive Header values for Octet 4 of the incoming cell.
RxHdr4[6]
RxHdr4[5]
RxHdr4[4]
RxHdr4[3]
RxHdr4[2]
RxHdr4[1]
RxHdr4[0]
2.2.25
0x1C—RXMSK1 (Receive Cell Mask Control Register 1)
The RXMSK1 register contains the first byte of the Receive Cell Mask. It modifies ATM cell screening, which
compares the Receive Cell Header Registers to the incoming cells. Setting a bit in the Mask Register causes the
corresponding bit in the received ATM cell header to be disregarded for screening. For example, setting RXMSK1
bit 0 to 1 causes ATM cells to be accepted with either 1 or 0 in the octet 1, bit 0 position. Combinations of Receive
Header Mask bits can select groups of ATM VPI/VCIs for reception. This mask consists of 32 bits divided among
four registers.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
RxMsk1[7]
These bits hold the Receive Header Mask for Octet 1 of the incoming cell.
RxMsk1[6]
RxMsk1[5]
RxMsk1[4]
RxMsk1[3]
RxMsk1[2]
RxMsk1[1]
RxMsk1[0]
®
28529-DSH-001-K
Mindspeed Technologies
164
Mindspeed Proprietary and Confidential
Registers
2.2.26
0x1D—RXMSK2 (Receive Cell Mask Control Register 2)
The RXMSK2 register contains the second byte of the Receive Cell Mask. (See 0x1D—RXMSK1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
RxMsk2[7]
These bits hold the Receive Header Mask for Octet 2 of the incoming cell.
RxMsk2[6]
RxMsk2[5]
RxMsk2[4]
RxMsk2[3]
RxMsk2[2]
RxMsk2[1]
RxMsk2[0]
2.2.27
0x1E—RXMSK3 (Receive Cell Mask Control Register 3)
The RXMSK3 register contains the third byte of the Receive Cell Mask. (See 0x1D—RXMSK1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
RxMsk3[7]
These bits hold the Receive Header Mask for Octet 3 of the incoming cell.
RxMsk3[6]
RxMsk3[5]
RxMsk3[4]
RxMsk3[3]
RxMsk3[2]
RxMsk3[1]
RxMsk3[0]
®
28529-DSH-001-K
Mindspeed Technologies
165
Mindspeed Proprietary and Confidential
Registers
2.2.28
0x1F—RXMSK4 (Receive Cell Mask Control Register 4)
The RXMSK4 register contains the fourth byte of the Receive Cell Mask. (See 0x1D—RXMSK1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
RxMsk4[7]
These bits hold the Receive Header Mask for Octet 4 of the incoming cell.
RxMsk4[6]
RxMsk4[5]
RxMsk4[4]
RxMsk4[3]
RxMsk4[2]
RxMsk4[1]
RxMsk4[0]
2.2.29
0x20—RXIDL1 (Receive Idle Cell Header Control Register 1)
The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines ATM idle cells for the cell
receiver. Idle cells are discarded from the received stream if register CVAL (0x0C) bit 6 is set to 1. This header
consists of 32 bits divided among four registers.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxIdl1[7]
These bits hold the Receive Idle cell header for Octet 1 of the incoming cell.
RxIdl1[6]
RxIdl1[5]
RxIdl1[4]
RxIdl1[3]
RxIdl1[2]
RxIdl1[1]
RxIdl1[0]
®
28529-DSH-001-K
Mindspeed Technologies
166
Mindspeed Proprietary and Confidential
Registers
2.2.30
0x21—RXIDL2 (Receive Idle Cell Header Control Register 2)
The RXIDL2 register contains the second byte of the Receive Idle Cell Header. (See 0x20—RXIDL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxIdl2[7]
These bits hold the Receive Idle cell header for Octet 2 of the incoming cell.
RxIdl2[6]
RxIdl2[5]
RxIdl2[4]
RxIdl2[3]
RxIdl2[2]
RxIdl2[1]
RxIdl2[0]
2.2.31
0x22—RXIDL3 (Receive Idle Cell Header Control Register 3)
The RXIDL3 register contains the third byte of the Receive Idle Cell Header. (See 0x20—RXIDL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
RxIdl3[7]
These bits hold the Receive Idle cell header for Octet 3 of the incoming cell.
RxIdl3[6]
RxIdl3[5]
RxIdl3[4]
RxIdl3[3]
RxIdl3[2]
RxIdl3[1]
RxIdl3[0]
®
28529-DSH-001-K
Mindspeed Technologies
167
Mindspeed Proprietary and Confidential
Registers
2.2.32
0x23—RXIDL4 (Receive Idle Cell Header Control Register 4)
The RXIDL4 register contains the fourth byte of the Receive Idle Cell Header. (See 0x20—RXIDL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
RxIdl4[7]
These bits hold the Receive Idle cell header for Octet 4 of the incoming cell.
RxIdl4[6]
RxIdl4[5]
RxIdl4[4]
RxIdl4[3]
RxIdl4[2]
RxIdl4[1]
RxIdl4[0]
2.2.33
0x24—IDLMSK1 (Receive Idle Cell Mask Control Register 1)
The IDLMSK1 register contains the first byte of the Receive Idle Cell Mask. It modifies ATM cell screening, which
compares the Receive Idle Cell Header Registers to the incoming cells. Setting a bit in the Mask Register causes
the corresponding bit in the received ATM idle cell header to be disregarded for screening. For example, setting
IDLMSK1 bit 0 to 1 causes cells to be accepted as ATM idle cells with either 1 or 0 in the octet 1, bit 0 position. This
header consists of 32 bits divided among four registers.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
IdlMsk1[7]
These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell.
IdlMsk1[6]
IdlMsk1[5]
IdlMsk1[4]
IdlMsk1[3]
IdlMsk1[2]
IdlMsk1[1]
IdlMsk1[0]
®
28529-DSH-001-K
Mindspeed Technologies
168
Mindspeed Proprietary and Confidential
Registers
2.2.34
0x25—IDLMSK2 (Receive Idle Cell Mask Control Register 2)
The IDLMSK2 register contains the second byte of the Receive Idle Cell Mask. (See 0x24—RXMSKL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
IdlMsk2[7]
These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell.
IdlMsk2[6]
IdlMsk2[5]
IdlMsk2[4]
IdlMsk2[3]
IdlMsk2[2]
IdlMsk2[1]
IdlMsk2[0]
2.2.35
0x26—IDLMSK3 (Receive Idle Cell Mask Control Register 3)
The IDLMSK3 register contains the third byte of the Receive Idle Cell Mask. (See 0x24—RXMSKL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
IdlMsk3[7]
These bits hold the Receive Idle cell header mask for Octet 3 of the incoming cell.
IdlMsk3[6]
IdlMsk3[5]
IdlMsk3[4]
IdlMsk3[3]
IdlMsk3[2]
IdlMsk3[1]
IdlMsk3[0]
®
28529-DSH-001-K
Mindspeed Technologies
169
Mindspeed Proprietary and Confidential
Registers
2.2.36
0x27—IDLMSK4 (Receive Idle Cell Mask Control Register 4)
The IDLMSK4 register contains the fourth byte of the Receive Idle Cell Mask. (See 0x24—RXMSKL1.)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
IdlMsk4[7]
These bits hold the Receive Idle cell header mask for Octet 4 of the incoming cell.
IdlMsk4[6]
IdlMsk4[5]
IdlMsk4[4]
IdlMsk4[3]
IdlMsk4[2]
IdlMsk4[1]
IdlMsk4[0]
2.2.37
0x28—ENCELLT (Transmit Cell Interrupt Control Register)
The ENCELLT register controls which of the interrupts listed in the TxCellInt register (0x2C) appear on the
MicroInt* pin (pin AA1), provided that both EnTxCellInt (bit 1) in the ENSUMINT register (0x01) and EnPortInt bit in
the appropriate ENSUMPORTn (n= 0 - 3) register (0xF06, 0xF08, 0xF0A or 0xF0C) for this port are enabled, and
EnIntPin (bit 3) in the GENCTRL register (0xF00) is enabled.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
0
EnParErrInt
When written to a logical 1, this bit enables the Parity Error Interrupt.
When written to a logical 1, this bit enables the Start of Cell Error Interrupt.
When written to a logical 1, this bit enables the Transmit FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt.
When written to a logical 1, this bit enables the Cell Sent Interrupt.
Reserved for factory test, ignore.
EnSOCErrInt
EnTxOvflInt
EnRxOvflInt
EnCellSentInt
—
—
Reserved, set to a logical 0.
—
Reserved, set to a logical 0.
®
28529-DSH-001-K
Mindspeed Technologies
170
Mindspeed Proprietary and Confidential
Registers
2.2.38
0x29—ENCELLR (Receive Cell Interrupt Control Register)
The ENCELLR register controls which of the interrupts listed in the RxCellInt register (0x2D) appear on the
MicroInt* pin (pin AA1), provided that both EnRxCellInt (bit 0) in the ENSUMINT register (0x01) and EnPortInt bit in
the appropriate ENSUMPORTn (n= 0 - 3) register (0xF06, 0xF08, 0xF0A or 0xF0C) for this port are enabled, and
EnIntPin (bit 3) in the GENCTRL register (0xF00) is enabled.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
EnLOCDInt
When written to a logical 1, this bit enables a Loss of Cell Delineation Interrupt.
When written to a logical 1, this bit enables a HEC Error Detected Interrupt.
When written to a logical 1, this bit enables a HEC Error Corrected Interrupt.
Reserved, write to a logical 0.
EnHECDetInt
EnHECCorrInt
—
EnCellRcvdInt
EnIdleRcvdInt
EnNonMatchInt
EnNonZerGFCInt
When written to a logical 1, this bit enables a Cell Received Interrupt.
When written to a logical 1, this bit enables an Idle Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-matching Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-zero GFC Received Interrupt.
2.2.39
0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register)
The TXCELLINT register indicates that a change of status has occurred within the transmit status signals.
Bit
Default
Name
(1)
Description
7
—
—
—
—
—
—
0
ParErrInt
When a logical 1 is read, this bit indicates that a Parity Error occurred.
When a logical 1 is read, this bit indicates that a Start of Cell Error occurred.
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a cell has been sent.
Reserved for factory test, ignore.
(1)
6
SOCErrInt
(1)
5
TxOvflInt
RxOvflInt
(1)
4
(1)
3
CellSentInt
2
—
—
—
1
Reserved, set to a logical 0.
0
0
Reserved, write to a logical 0.
Footnote:
(1) Single event—A 0 to 1 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has been
enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
®
28529-DSH-001-K
Mindspeed Technologies
171
Mindspeed Proprietary and Confidential
Registers
2.2.40
0x2D—RXCELLINT (Receive Cell Interrupt Indication Status Register)
The RXCELLINT register indicates that a change of status has occurred within the receive status signals.
Bit
Default
Name
(2)
Description
7
—
—
—
—
—
—
—
—
LOCDInt
When a logical 1 is read, this bit indicates that a Loss of Cell Delineation has occurred.
When a logical 1 is read, this bit indicates that a HEC Error was detected.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
Reserved, write to a logical 0.
(1)
6
HECDetInt
HECCorrInt
(1)
5
4
—
(1)
3
CellRcvdInt
When a logical 1 is read, this bit indicates that a cell has been received.
When a logical 1 is read, this bit indicates that an Idle Cell has been received.
When a logical 1 is read, this bit indicates that a Non-matching Cell has been received.
When a logic 1 is read, this bit indicates that a Non-zero GFC has been received.
(1)
2
IdleRcvdInt
(1)
1
NonMatchInt
(1)
0
NonZerGFCInt
Footnote:
(1) Single event—A 0 to 1 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has been
enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
(2) Dual event—Either a 0 to 1 or a 1 to 0 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt
has been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
2.2.41
0x2E—TXCELL (Transmit Cell Status Register)
The TXCELL register contains status for the cell transmitter. This register is cleared on read. Bits 1-7 are read-
only.
Bit
Default
Name
Description
(1)
7
—
ParErr
When a logical 1 is read, this bit indicates that a parity error was received on the transmit
UTOPIA input data octet.
(1)
6
5
4
—
—
—
SOCErr
When a logical 1 is read, this bit indicates that a Start of Cell Error was received on the UTxSOC
pin (pin TBD).
(1)
TxOvfl
RxOvfl
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow condition occurred in
the transmit UTOPIA FIFO.
(1)
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow condition occurred in the
receive UTOPIA FIFO.
(1)
3
—
—
0
CellSent
When a logical 1 is read, this bit indicates that a non-idle cell was formatted and transmitted.
Reserved for factory test, ignore.
2
—
—
—
1
Reserved, set to a logical 0.
0
0
Reserved, set to a logical 0.
Footnote:
(1) This status indicates an event that occurred since the register was last read.
®
28529-DSH-001-K
Mindspeed Technologies
172
Mindspeed Proprietary and Confidential
Registers
2.2.42
0x2F—RXCELL (Receive Cell Status Register)
The RXCELL register contains status for the cell receiver. This register is cleared on read.
Bit
Default
Name
Description
(2)
7
6
5
4
3
2
—
—
—
—
—
—
LOCD
When a logical 1 is read, this bit indicates a Loss of Cell Delineation.
(1)
HECDet
When a logical 1 is read, this bit indicates that an uncorrected HEC Error was detected.
When a logical 1 is read, this bit indicates that a HEC Error was corrected.
Reserved, ignore this bit.
(1)
HECCorr
—
CellRcvd
IdleRcvd
When logical 1 is read, this bit indicates that a valid cell was received.
(1)
(1)
When a logical 1 is read, this bit indicates that a cell with a header matching the receive idle cell
header value and mask criteria was received.
1
—
—
NonMatch
When a logical 1 is read, this bit indicates that a cell has been rejected by the cell screening
function.
(1)
0
NonZerGFC
When a logical 1 is read, this bit indicates that a cell with a Non-zero GFC field in the header was
received.
Footnote:
(1) This status indicates an event that occurred since the register was last read.
(2) This status reflects the current state of the circuit.
2.2.43
0x30—IDLCNTL (Idle Cell Receive Counter [Low Byte])
The IDLCNTL counter tracks the number of received idle cells. This byte of the counter should be read first. The
counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
IdleCnt[7]
Received cell counter bit 7.
Received cell counter bit 6.
Received cell counter bit 5.
Received cell counter bit 4.
Received cell counter bit 3.
Received cell counter bit 2.
Received cell counter bit 1.
Received cell counter bit 0 (LSB).
IdleCnt[6]
IdleCnt[5]
IdleCnt[4]
IdleCnt[3]
IdleCnt[2]
IdleCnt[1]
IdleCnt[0]
®
28529-DSH-001-K
Mindspeed Technologies
173
Mindspeed Proprietary and Confidential
Registers
2.2.44
0x31—IDLCNTH (Idle Cell Receive Counter [High Byte])
The IDLCNTH counter tracks the number of received cells. The counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
IdleCnt[15]
Received cell counter bit 15.
Received cell counter bit 14.
Received cell counter bit 13.
Received cell counter bit 12.
Received cell counter bit 11.
Received cell counter bit 10.
Received cell counter bit 9.
Received cell counter bit 8.
IdleCnt[14]
IdleCnt[13]
IdleCnt[12]
IdleCnt[11]
IdleCnt[10]
IdleCnt[9]
IdleCnt[8]
2.2.45
0x33—LOCDCNT (LOCD Event Counter)
This counter tracks the number of times that cell delineation was lost. Note that the LOCD interrupt is a dual event
interrupt and is set when cell delineation is lost or regained. Thus the number of LOCD events will not match the
number of LOCD interrupts.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
LOCDCnt[7]
LOCD Event counter bit 7 (MSB).
LOCD Event counter bit 6.
LOCD Event counter bit 5.
LOCD Event counter bit 4.
LOCD Event counter bit 3.
LOCD Event counter bit 2.
LOCD Event counter bit 1.
LOCD Event counter bit 0 (LSB).
LOCDCnt[6]
LOCDCnt[5]
LOCDCnt[4]
LOCDCnt[3]
LOCDCnt[2]
LOCDCnt[1]
LOCDCnt[0]
®
28529-DSH-001-K
Mindspeed Technologies
174
Mindspeed Proprietary and Confidential
Registers
2.2.46
0x34—TXCNTL (Transmitted Cell Counter [Low Byte])
The TXCNTL counter tracks the number of transmitted cells. This byte of the counter should be read first. The
counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
TxCnt[7]
TxCnt[6]
TxCnt[5]
TxCnt[4]
TxCnt[3]
TxCnt[2]
TxCnt[1]
TxCnt[0]
Transmitted cell counter bit 7.
Transmitted cell counter bit 6.
Transmitted cell counter bit 5.
Transmitted cell counter bit 4.
Transmitted cell counter bit 3.
Transmitted cell counter bit 2.
Transmitted cell counter bit 1.
Transmitted cell counter bit 0 (LSB).
2.2.47
0x35—TXCNTH (Transmitted Cell Counter [High Byte])
The TXCNTH counter tracks the number of transmitted cells. The counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
TxCnt[15]
Transmitted cell counter bit 15.
Transmitted cell counter bit 14.
Transmitted cell counter bit 13.
Transmitted cell counter bit 12.
Transmitted cell counter bit 11.
Transmitted cell counter bit 10.
Transmitted cell counter bit 9.
Transmitted cell counter bit 8.
TxCnt[14]
TxCnt[13]
TxCnt[12]
TxCnt[11]
TxCnt[10]
TxCnt[9]
TxCnt[8]
®
28529-DSH-001-K
Mindspeed Technologies
175
Mindspeed Proprietary and Confidential
Registers
2.2.48
0x37—CORRCNT (Corrected HEC Error Counter)
The CORRCNT counter tracks the number of corrected HEC errors. The counter is cleared on read 0x38—
RXCNTL (Received Cell Counter [Low Byte]).
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
CorrCnt[7]
Corrected HEC Error counter bit 7 (MSB).
Corrected HEC Error counter bit 6.
Corrected HEC Error counter bit 5.
Corrected HEC Error counter bit 4.
Corrected HEC Error counter bit 3.
Corrected HEC Error counter bit 2.
Corrected HEC Error counter bit 1.
Corrected HEC Error counter bit 0 (LSB).
CorrCnt[6]
CorrCnt[5]
CorrCnt[4]
CorrCnt[3]
CorrCnt[2]
CorrCnt[1]
CorrCnt[0]
2.2.49
0x38—RXCNTL (Received Cell Counter [Low Byte])
The RXCNTL counter tracks the number of received cells. This byte of the counter should be read first. The counter
is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
RxCnt[7]
RxCnt[6]
RxCnt[5]
RxCnt[4]
RxCnt[3]
RxCnt[2]
RxCnt[1]
RxCnt[0]
Received cell counter bit 7.
Received cell counter bit 6.
Received cell counter bit 5.
Received cell counter bit 4.
Received cell counter bit 3.
Received cell counter bit 2.
Received cell counter bit 1.
Received cell counter bit 0 (LSB).
®
28529-DSH-001-K
Mindspeed Technologies
176
Mindspeed Proprietary and Confidential
Registers
2.2.50
0x39—RXCNTH (Received Cell Counter [High Byte])
The RXCNTH register tracks the number of received cells. The counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
RxCnt[15]
Received cell counter bit 15.
Received cell counter bit 14.
Received cell counter bit 13.
Received cell counter bit 12.
Received cell counter bit 11.
Received cell counter bit 10.
Received cell counter bit 9.
Received cell counter bit 8.
RxCnt[14]
RxCnt[13]
RxCnt[12]
RxCnt[11]
RxCnt[10]
RxCnt[9]
RxCnt[8]
2.2.51
0x3B—UNCCNT (Uncorrected HEC Error Counter)
The UNCCNT counter tracks the number of uncorrected HEC errors. The counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
UncCnt[7]
Uncorrected HEC Error counter bit 7 (MSB).
UncCnt[6]
UncCnt[5]
UncCnt[4]
UncCnt[3]
UncCnt[2]
UncCnt[1]
UncCnt[0]
Uncorrected HEC Error counter bit 6.
Uncorrected HEC Error counter bit 5.
Uncorrected HEC Error counter bit 4.
Uncorrected HEC Error counter bit 3.
Uncorrected HEC Error counter bit 2.
Uncorrected HEC Error counter bit 1.
Uncorrected HEC Error counter bit 0 (LSB).
®
28529-DSH-001-K
Mindspeed Technologies
177
Mindspeed Proprietary and Confidential
Registers
2.2.52
0x3C—NONCNTL (Non-matching Cell Counter [Low Byte])
The NONCNTL counter tracks the number of non-matching cells. This byte of the counter should be read first. The
counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
NonCnt[7]
Non-matching cell counter bit 7.
Non-matching cell counter bit 6.
Non-matching cell counter bit 5.
Non-matching cell counter bit 4.
Non-matching cell counter bit 3.
Non-matching cell counter bit 2.
Non-matching cell counter bit 1.
Non-matching cell counter bit 0 (LSB).
NonCnt[6]
NonCnt[5]
NonCnt[4]
NonCnt[3]
NonCnt[2]
NonCnt[1]
NonCnt[0]
2.2.53
0x3D—NONCNTH (Non-matching Cell Counter [High Byte])
The NONCNTH counter tracks the number of non-matching cells. The counter is cleared on read.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
NonCnt[15]
Non-matching cell counter bit 15 (MSB).
Non-matching cell counter bit 14.
Non-matching cell counter bit 13.
Non-matching cell counter bit 12.
Non-matching cell counter bit 11.
Non-matching cell counter bit 10.
Non-matching cell counter bit 9.
Non-matching cell counter bit 8.
NonCnt[14]
NonCnt[13]
NonCnt[12]
NonCnt[11]
NonCnt[10]
NonCnt[9]
NonCnt[8]
®
28529-DSH-001-K
Mindspeed Technologies
178
Mindspeed Proprietary and Confidential
Registers
2.3
General Control Registers
2.3.1
0xF00—GENCTRL (General Device Control Register)
Bit
Default
Name
Description
7
0
DevMstRst
Device master reset. When set high, all internal state machines in the TC block are held in reset
and all registers (except this bit) assume their default values. If configuring the device for
pass-through operation, a minimum delay of 25 uS for IMA_Sysclk of 66 MHz or 33uS for
IMA_Sysclk of 50 MHz is required from the release of device reset to the first access of the
IMA_RX_TRANS_TABLE register or IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
6
5
0
0
DevLgcRst
EnStatLat
Device logic reset. When set high, all internal state machines in the TC block are held in reset
but register values are unaffected.
When set to 1, the one-second status latching is enabled. The value of the status bits are the
events which occurred between the last two one-second events. Any events occurring after the
last one-second event is not reflected when the status register is read. Those events are
reflected in the status register upon the next one-second event. When a status register is read,
the status is cleared and is not updated until the next one-second event.
When set to 0, the one-second status latching is disabled. The value of a status register is the
events occurred since the last read of the status register.
4
0
EnCntrLat
EnIntPin
When set to 1, the one-second counter latching is enabled. The value of the counter is the
number of events counted between the last two one-second events. Any events occurring after
the last one-second event is not reflected when the counter is read. Those events are reflected
in the counter upon the next one-second event. When a counter is read, the count is cleared
and is not updated until the next one-second event.
When set to 0, the one-second counter latching is disabled. The value of a counter is the
number of events counted since the last read of the counter.
3
2–1
0
0
00
0
Enables the MicroInt* output pin.
Reserved, set to zero.
—
OneSecOut
When set to 1, the OneSecIO pin is configured as an output. The pin provides a one-second
event pulse. The one-second event is generated internally of the device. The event occurs after
the device has counted 8000 periods of a 8 KHz clock.
When set to 0, the OneSecIO pin is configured as an input. The one-second event must be
generated externally, by pulsing the OneSecIO pin for low-high-low.
2.3.2
0xF01—PARTNUM (Part and Version Number Register)
Bit
Default
Name
Description
7–4
pppp
PartNum[3:0]
Part number controlled by bondout:
16 TC Port version - 0101
32 TC Port version - 1001
3–0
0000
Version[3:0]
Version number of the device. Number starts at “0000” for the initial version
®
28529-DSH-001-K
Mindspeed Technologies
179
Mindspeed Proprietary and Confidential
Registers
2.3.3
0xF02—PHYINTFC (PHY-side Interface Control Register)
Bit
Default
Name
Description
7
6
5
0
—
1
—
PHYIntSelPin
PHYBusWidth
Reserved, set to 0.
This bit reflects the level of the external PhyIntFcSel pin (read only)
When set to 0, the PHY-side UTOPIA interface is set to 16-bit mode.
When set to 1, the PHY-side UTOPIA interface is set to 8-bit mode.
4–0
00000
—
Reserved, set to zero.
2.3.4
0xF03—ATMINTFC (ATM-side Interface Control Register)
Bit
Default
Name
Description
7–6
00
ATMmux[1:0]
Controls the ATM-side UTOPIA interface mux.
00 – External interface is placed in Tristate mode.
01 – UTOPIA level 2 interface to IMA32 block is enabled.
10 – UTOPIA level 2 interface to TC block is enabled.
11 – External interface is placed in Tristate mode.
5
4
0
0
ATMBusWidth
DualClavEnb
When set to 0, the 16-bit UTOPIA bus is enabled
When set to 1, the 8-bit UTOPIA bus is enabled.
When set to 1, Dual Clav/Enb mode on the interface is enabled. When set to 0, single clav/enb
is enabled. For single Clav mode, UrxEnb[1] and UtxEnB[1] are not used but must be pulled
up.
3-0
0000
—
Reserved, set to zero.
2.3.5
0xF04—STATOUT (Output Status Control Register)
Bit
Default
Name
Description
7–2
1–0
000000
00
—
Reserved, set to zero.
StatOut[1:0]
The value written into these bits will be asserted on the StatOut[1:0] output pins.
®
28529-DSH-001-K
Mindspeed Technologies
180
Mindspeed Proprietary and Confidential
Registers
2.3.6
0xF05—SUMPORT0 (Summary Port Interrupt Status Register for TC ports
0-7)
Bit
Default
Name
Description
1
7
0
0
0
0
0
0
0
0
PortInt[7]
This bit is a summary indicator of the interrupts from the Port 7 SUMINT register (0x1C0).
This bit is a summary indicator of the interrupts from the Port 6 SUMINT register (0x180).
This bit is a summary indicator of the interrupts from the Port 5 SUMINT register (0x140).
This bit is a summary indicator of the interrupts from the Port 4 SUMINT register (0x100).
This bit is a summary indicator of the interrupts from the Port 3 SUMINT register (0x0C0).
This bit is a summary indicator of the interrupts from the Port 2 SUMINT register (0x080).
This bit is a summary indicator of the interrupts from the Port 1 SUMINT register (0x040).
This bit is a summary indicator of the interrupts from the Port 0 SUMINT register (0x000).
1
1
1
1
1
1
1
6
PortInt[6]
PortInt[5]
PortInt[4]
PortInt[3]
PortInt[2]
PortInt[1]
PortInt[0]
5
4
3
2
1
0
Footnote:
(1) This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bit in the corresponding
interrupt indication register is read and automatically cleared.
2.3.7
0xF06—ENSUMPORT0 (Summary Port Interrupt Control Register for TC
Ports 0-7)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
EnPortInt[7]
When set, this bit enables PortInt[7] to appear on the MicroInt* output.
When set, this bit enables PortInt[6] to appear on the MicroInt* output.
When set, this bit enables PortInt[5] to appear on the MicroInt* output.
When set, this bit enables PortInt[4] to appear on the MicroInt* output.
When set, this bit enables PortInt[3] to appear on the MicroInt* output.
When set, this bit enables PortInt[2] to appear on the MicroInt* output.
When set, this bit enables PortInt[1] to appear on the MicroInt* output.
When set, this bit enables PortInt[0] to appear on the MicroInt* output.
EnPortInt[6]
EnPortInt[5]
EnPortInt[4]
EnPortInt[3]
EnPortInt[2]
EnPortInt[1]
EnPortInt[0]
®
28529-DSH-001-K
Mindspeed Technologies
181
Mindspeed Proprietary and Confidential
Registers
2.3.8
0xF07—SUMPORT1 (Summary Port Interrupt Status Register for TC ports
8-15)
Bit
Default
Name
Description
1
7
0
0
0
0
0
0
0
0
PortInt[15]
This bit is a summary indicator of the interrupts from the Port 15 SUMINT register (0x3C0).
This bit is a summary indicator of the interrupts from the Port 14 SUMINT register (0x380).
This bit is a summary indicator of the interrupts from the Port 13 SUMINT register (0x340).
This bit is a summary indicator of the interrupts from the Port 12 SUMINT register (0x300).
This bit is a summary indicator of the interrupts from the Port 11 SUMINT register (0x2C0).
This bit is a summary indicator of the interrupts from the Port 10 SUMINT register (0x280).
This bit is a summary indicator of the interrupts from the Port 9 SUMINT register (0x240).
This bit is a summary indicator of the interrupts from the Port 8 SUMINT register (0x200).
1
1
1
1
1
6
PortInt[14]
PortInt[13]
PortInt[12]
PortInt[11]
PortInt[10]
5
4
3
2
1
1
0
PortInt[9]
1
PortInt[8]
Footnote:
(1) This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bit in the corresponding
interrupt indication register is read and automatically cleared.
2.3.9
0xF08—ENSUMPORT1 (Summary Port Interrupt Control Register for TC
Ports 8-15)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
EnPortInt[15]
EnPortInt[14]
EnPortInt[13]
EnPortInt[12]
EnPortInt[11]
EnPortInt[10]
EnPortInt[9]
EnPortInt[8]
When set, this bit enables PortInt[15] to appear on the MicroInt* output.
When set, this bit enables PortInt[14] to appear on the MicroInt* output.
When set, this bit enables PortInt[13] to appear on the MicroInt* output.
When set, this bit enables PortInt[12] to appear on the MicroInt* output.
When set, this bit enables PortInt[11] to appear on the MicroInt* output.
When set, this bit enables PortInt[10] to appear on the MicroInt* output.
When set, this bit enables PortInt[9] to appear on the MicroInt* output.
When set, this bit enables PortInt[8] to appear on the MicroInt* output.
®
28529-DSH-001-K
Mindspeed Technologies
182
Mindspeed Proprietary and Confidential
Registers
2.3.10
0xF09—SUMPORT2 (Summary Port Interrupt Status Register for TC ports
16-23)
Bit
Default
Name
Description
1
7
0
0
0
0
0
0
0
0
PortInt[23]
This bit is a summary indicator of the interrupts from the Port 23 SUMINT register (0x5C0).
This bit is a summary indicator of the interrupts from the Port 22 SUMINT register (0x580).
This bit is a summary indicator of the interrupts from the Port 21 SUMINT register (0x540).
This bit is a summary indicator of the interrupts from the Port 20 SUMINT register (0x500).
This bit is a summary indicator of the interrupts from the Port 19 SUMINT register (0x4C0).
This bit is a summary indicator of the interrupts from the Port 18 SUMINT register (0x480).
This bit is a summary indicator of the interrupts from the Port 17 SUMINT register (0x440).
This bit is a summary indicator of the interrupts from the Port 16 SUMINT register (0x400).
1
1
1
1
1
1
1
6
PortInt[22]
PortInt[21]
PortInt[20]
PortInt[19]
PortInt[18]
PortInt[17]
PortInt[16]
5
4
3
2
1
0
Footnote:
(1) This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bit in the corresponding
interrupt indication register is read and automatically cleared.
2.3.11
0xF0A—ENSUMPORT2 (Summary Port Interrupt Control Register for TC
Ports 16-23)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
EnPortInt[23]
EnPortInt[22]
EnPortInt[21]
EnPortInt[20]
EnPortInt[19]
EnPortInt[18]
EnPortInt[17]
EnPortInt[16]
When set, this bit enables PortInt[23] to appear on the MicroInt* output.
When set, this bit enables PortInt[22] to appear on the MicroInt* output.
When set, this bit enables PortInt[21] to appear on the MicroInt* output.
When set, this bit enables PortInt[20] to appear on the MicroInt* output.
When set, this bit enables PortInt[19] to appear on the MicroInt* output.
When set, this bit enables PortInt[18] to appear on the MicroInt* output.
When set, this bit enables PortInt[17] to appear on the MicroInt* output.
When set, this bit enables PortInt[16] to appear on the MicroInt* output.
®
28529-DSH-001-K
Mindspeed Technologies
183
Mindspeed Proprietary and Confidential
Registers
2.3.12
0xF0B—SUMPORT3 (Summary Port Interrupt Status Register for TC ports
24-31)
Bit
Default
Name
Description
1
7
0
0
0
0
0
0
0
0
PortInt[31]
This bit is a summary indicator of the interrupts from the Port 31 SUMINT register (0x7C0).
This bit is a summary indicator of the interrupts from the Port 30 SUMINT register (0x780).
This bit is a summary indicator of the interrupts from the Port 29 SUMINT register (0x740).
This bit is a summary indicator of the interrupts from the Port 28 SUMINT register (0x700).
This bit is a summary indicator of the interrupts from the Port 27 SUMINT register (0x6C0).
This bit is a summary indicator of the interrupts from the Port 26 SUMINT register (0x680).
This bit is a summary indicator of the interrupts from the Port 25 SUMINT register (0x640).
This bit is a summary indicator of the interrupts from the Port 24 SUMINT register (0x600).
1
1
1
1
1
1
1
6
PortInt[30]
PortInt[29]
PortInt[28]
PortInt[27]
PortInt[26]
PortInt[25]
PortInt[24]
5
4
3
2
1
0
Footnote:
(1) This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bit in the corresponding
interrupt indication register is read and automatically cleared.
2.3.13
0xF0C—ENSUMPORT3 (Summary Port Interrupt Control Register for TC
Ports 24-31)
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
EnPortInt[31]
EnPortInt[30]
EnPortInt[29]
EnPortInt[28]
EnPortInt[27]
EnPortInt[26]
EnPortInt[25]
EnPortInt[24]
When set, this bit enables PortInt[31] to appear on the MicroInt* output.
When set, this bit enables PortInt[30] to appear on the MicroInt* output.
When set, this bit enables PortInt[29] to appear on the MicroInt* output.
When set, this bit enables PortInt[28] to appear on the MicroInt* output.
When set, this bit enables PortInt[27] to appear on the MicroInt* output.
When set, this bit enables PortInt[26] to appear on the MicroInt* output.
When set, this bit enables PortInt[25] to appear on the MicroInt* output.
When set, this bit enables PortInt[24] to appear on the MicroInt* output.
2.3.14
0xF0F—SCRATCH (Scratch Pad Register)
Bit
Default
Name
Description
7-0
00000000 Scratch
These bits can be written and read by the system. These bits are not used for any purpose
inside the device.
®
28529-DSH-001-K
Mindspeed Technologies
184
Mindspeed Proprietary and Confidential
Registers
2.3.15
0xF10—TCCTRL0 (TC Control Register for TC ports 0-3)
Bit
Default
Name
Description
7
0
IhTxDatShft0
When set to 1, the Tx data on the Interleaved Highway Data Bus 0 will be output 1/2 IHTxClk0
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol0
IhRxClkPol0
Interleaved Highway Bus 0 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk0, set to 1 for
falling edge.
Interleaved Highway Bus 0 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk0, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH0
When set, this bit enables interleaved highway interface for TC Ports 0-3.
When set, this bit enables fractional T1/E1 logic for TC port 3.
When set, this bit enables fractional T1/E1 logic for TC port 2.
When set, this bit enables fractional T1/E1 logic for TC port 1.
When set, this bit enables fractional T1/E1 logic for TC port 0.
EnFrac[3]
EnFrac[2]
EnFrac[1]
EnFrac[0]
2.3.16
0xF11—TCCTRL1 (TC Control Register for TC ports 4-7)
Bit
Default
Name
Description
7
0
IhTxDatShft1
When set to 1, the Tx data on the Interleaved Highway Data Bus 1 will be output 1/2 IHTxClk1
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol1
IhRxClkPol1
Interleaved Highway Bus 1 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk1, set to 1 for
falling edge.
Interleaved Highway Bus 1 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk1, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH1
When set, this bit enables interleaved highway interface for TC Ports 4-7.
When set, this bit enables fractional T1/E1 logic for TC port 7.
When set, this bit enables fractional T1/E1 logic for TC port 6.
When set, this bit enables fractional T1/E1 logic for TC port 5.
When set, this bit enables fractional T1/E1 logic for TC port 4.
EnFrac[7]
EnFrac[6]
EnFrac[5]
EnFrac[4]
®
28529-DSH-001-K
Mindspeed Technologies
185
Mindspeed Proprietary and Confidential
Registers
2.3.17
0xF12—TCCTRL2 (TC Control Register for TC ports 8-11)
Bit
Default
Name
Description
7
0
IhTxDatShft2
When set to 1, the Tx data on the Interleaved Highway Data Bus 2 will be output 1/2 IHTxClk2
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol2
IhRxClkPol2
Interleaved Highway Bus 2 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk2, set to 1 for
falling edge.
Interleaved Highway Bus 2 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk2, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH2
When set, this bit enables interleaved highway interface for TC Ports 8-11.
When set, this bit enables fractional T1/E1 logic for TC port 11.
When set, this bit enables fractional T1/E1 logic for TC port 10.
When set, this bit enables fractional T1/E1 logic for TC port 9.
When set, this bit enables fractional T1/E1 logic for TC port 8.
EnFrac[11]
EnFrac[10]
EnFrac[9]
EnFrac[8]
2.3.18
0xF13—TCCTRL3 (TC Control Register for TC ports 12-15)
Bit
Default
Name
Description
7
0
IhTxDatShft3
When set to 1, the Tx data on the Interleaved Highway Data Bus 3 will be output 1/2 IHTxClk3
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol3
IhRxClkPol3
Interleaved Highway Bus 3 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk3, set to 1 for
falling edge.
Interleaved Highway Bus 3 Rx Clock Polarity. Set to 0 for rising edge of IHTxClk3, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH3
When set, this bit enables interleaved highway interface for TC Ports 12-15.
When set, this bit enables fractional T1/E1 logic for TC port 15.
When set, this bit enables fractional T1/E1 logic for TC port 14.
When set, this bit enables fractional T1/E1 logic for TC port 13.
When set, this bit enables fractional T1/E1 logic for TC port 12.
EnFrac[15]
EnFrac[14]
EnFrac[13]
EnFrac[12]
®
28529-DSH-001-K
Mindspeed Technologies
186
Mindspeed Proprietary and Confidential
Registers
2.3.19
0xF14—TCCTRL4 (TC Control Register for TC ports 16-19)
Bit
Default
Name
Description
7
0
IhTxDatShft4
When set to 1, the Tx data on the Interleaved Highway Data Bus 4 will be output 1/2 IHTxClk4
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol4
IhRxClkPol4
Interleaved Highway Bus 4 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk4, set to 1 for
falling edge.
Interleaved Highway Bus 4 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk4, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH4
When set, this bit enables interleaved highway interface for TC Ports 16-19.
When set, this bit enables fractional T1/E1 logic for TC port 19.
When set, this bit enables fractional T1/E1 logic for TC port 18.
When set, this bit enables fractional T1/E1 logic for TC port 17.
When set, this bit enables fractional T1/E1 logic for TC port 16.
EnFrac[19]
EnFrac[18]
EnFrac[17]
EnFrac[16]
2.3.20
0xF15—TCCTRL5 (TC Control Register for TC ports 20-23)
Bit
Default
Name
Description
7
0
IhTxDatShft5
When set to 1, the Tx data on the Interleaved Highway Data Bus 5 will be output 1/2 IHTxClk5
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol5
IhRxClkPol5
Interleaved Highway Bus 5 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk5, set to 1 for
falling edge.
Interleaved Highway Bus 5 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk5, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH5
When set, this bit enables interleaved highway interface for TC Ports 20-23.
When set, this bit enables fractional T1/E1 logic for TC port 23.
When set, this bit enables fractional T1/E1 logic for TC port 22.
When set, this bit enables fractional T1/E1 logic for TC port 21.
When set, this bit enables fractional T1/E1 logic for TC port 20.
EnFrac[23]
EnFrac[22]
EnFrac[21]
EnFrac[20]
®
28529-DSH-001-K
Mindspeed Technologies
187
Mindspeed Proprietary and Confidential
Registers
2.3.21
0xF16—TCCTRL6 (TC Control Register for TC ports 24-27)
Bit
Default
Name
Description
7
0
IhTxDatShft6
When set to 1, the Tx data on the Interleaved Highway Data Bus 6 will be output 1/2 IHTxClk6
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol6
IhRxClkPol6
Interleaved Highway Bus 6 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk6, set to 1 for
falling edge.
Interleaved Highway Bus 6 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk6, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH6
When set, this bit enables interleaved highway interface for TC Ports 24-27.
When set, this bit enables fractional T1/E1 logic for TC port 27.
When set, this bit enables fractional T1/E1 logic for TC port 26.
When set, this bit enables fractional T1/E1 logic for TC port 25.
When set, this bit enables fractional T1/E1 logic for TC port 24.
EnFrac[27]
EnFrac[26]
EnFrac[25]
EnFrac[24]
2.3.22
0xF17—TCCTRL7 (TC Control Register for TC ports 28-31)
Bit
Default
Name
Description
7
0
IhTxDatShft7
When set to 1, the Tx data on the Interleaved Highway Data Bus 7 will be output 1/2 IHTxClk7
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
6
5
0
0
IhTxClkPol7
IhRxClkPol7
Interleaved Highway Bus 7 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk7, set to 1 for
falling edge.
Interleaved Highway Bus 7 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk7, set to 1 for
falling edge.
4
3
2
1
0
0
0
0
0
0
EnIH7
When set, this bit enables interleaved highway interface for TC Ports 28-31.
When set, this bit enables fractional T1/E1 logic for TC port 31.
When set, this bit enables fractional T1/E1 logic for TC port 30.
When set, this bit enables fractional T1/E1 logic for TC port 29.
When set, this bit enables fractional T1/E1 logic for TC port 28.
EnFrac[31]
EnFrac[30]
EnFrac[29]
EnFrac[28]
2.3.23
0xF18—ONESECINT (One Second Interrupt Status Register)
Bit
Default
Name
Description
7-1
0
0000000
0
-
Reserved, set to zero
OneSecInt
This bit is the indicator of the one second interrupt
®
28529-DSH-001-K
Mindspeed Technologies
188
Mindspeed Proprietary and Confidential
Registers
2.3.24
0xF19—ONESECINT (One Second Interrupt Control Register)
Bit
Default
Name
Description
7-1
0
0000000
1
-
Reserved, set to zero
When set, this bit enables OneSecInt to appear on the Microint* output pin.
EnOneSecInt
2.4
IMA Subsystem Registers
The IMA Subsystem layer contains configuration and status information that is common to all IMA groups.
2.4.1
0x800—IMA_VER_1_CONFIG (IMA Type and Version Code I)
The IMA_Version I and II registers contain the type and revision level of the IMA core. Read-only.
Bit
Default
Name
Description
7–4
IMA Core Type I
0xa = M28529, 32 ports 32 IMA groups
0xb = M28525, 16 ports 16 IMA groups
3
1
IMA Core Type II
Version Code I
1 = Internal memory present
2–0
0x4 = M2852x family major revision level
2.4.2
0x801—IMA_VER_2_CONFIG (IMA Version Codes II and III)
This register is read-only.
Bit
Default
Name
Description
7–4
Version Code II
4 bit code:
0x4 = M2852x-12
3–0
Version Code III
4 bit code:
0x0 = M2852x-12
®
28529-DSH-001-K
Mindspeed Technologies
189
Mindspeed Proprietary and Confidential
Registers
2.4.3
0x802—IMA_SUBSYS_CONFIG (IMA Configuration Control)
This register contains some of the basic IMA Subsystem configuration.
Bit
Default
Name
Description
7–6
0
Link Type
Sets default link type for all IMA groups. Not used with variable rate facilities
0 = T1
1 = E1
2 = Alternate T1 (1.544 Mbps payload)
3 = Alternate E1 (1.984 Mbps payload)
5–4
0
SRAM size
0 = 25 ms (E1 mode)
1 = 50 ms
2 = 100 ms
3 = 200 ms
3
0
0
Number of SRAMs
Number of Ports
0 = 1 SRAM, Set to 0 for all M2852x devices
2–0
This field indicates the range of valid PHY addresses.
0: addresses 0x00–0x03 are valid
1: addresses 0x00–0x07 are valid
2: addresses 0x00–0x0B are valid
3: addresses 0x00–0x0F are valid
4: addresses 0x00–0x13 are valid
5: addresses 0x00–0x17 are valid
6: addresses 0x00–0x1B are valid
7: addresses 0x00–0x1F are valid
This field has different ranges depending on Product type:
M28525: Range: 0–3
M28529: Range: 0–7
2.4.4
0x803—IMA_MISC_STATUS (IMA Miscellaneous Status)
This register contains miscellaneous status information for the IMA Subsystem. Read-only.
Bit
Default
Name
Description
7
6
5
4
—
—
—
—
—
Reserved
Reserved
Reserved
—
—
ATM Data Width
This bit indicates whether the ATM UTOPIA bus is operating in 16 bit (high) or 8 bit (low) data
mode.
3
2
—
—
IMA_RefClk Error
This bit is set high if a transition detector for IMA_RefClk detects a bad signal. This bit is active
high and is reset upon reading this address.
Tx ATM Parity Error
This bit indicates that a parity error has been detected on the Transmit ATM side UTOPIA bus.
This bit is active high and is reset upon reading this address.
1
0
—
—
—
Reserved.
Rx PHY Parity Error
This bit indicates that a parity error has been detected on the Receive PHY side cell bus. This bit
is active high and is reset upon reading this address.
®
28529-DSH-001-K
Mindspeed Technologies
190
Mindspeed Proprietary and Confidential
Registers
2.4.5
0x804—IMA_MISC_CONFIG (IMA Miscellaneous Control)
This register contains some of the basic IMA Subsystem configuration.
Bit
Default
Name
Description
7
6
—
0
—
Reserved. Set to 0
Alternate GTSM Mode
1 = When the GTSM is down, ATMUTxClAv for that group is controlled as if all configured
links in the group are Active.
0 = When the GTSM is down, ATMUTxClAv for that group is inactive.
5–4
0
PHY Size
This two bit field determines the use of the PHY side ClAv and Enb* signals. When using
Utopia-to-Serial mode, PHY Size should be set to 16 ports per Clav and En*. Thus for
M28525, PHY Size should be 2 while for M28529, PHY Size should be 1.
0 = ClAv and En* for every 4 PHY addresses (support 8 ports total)
(Ports 0-3 assigned to Clav0/Enb0*)
(Ports 4-7 assigned to Clav1/En1*)
1 = ClAv and En* for every 16 PHY addresses (support 32 ports total)
(Ports 0-15 assigned to Clav0/Enb0*)
(Ports 16-31 assigned to Clav1/Enb1*)
2 = ClAv and En* for all PHY addresses (support 32 ports total)
(Ports 0-31 assigned to Clav0/Enb0*)
For Utopia-to-Utopia mode, PhyUrxEna[1] and PhyUtxEna[1] should be pull
high when PHY Size is set to 2.
3 = ClAv and En* for every 8 PHY addresses (support 16 ports total)
(Ports 0-7 assigned to Clav0/Enb0*)
(Ports 8-15 assigned to Clav1/Enb1*)
3
2
1
0
0
0
0
0
Enable External HEC
Checker
1 = Bit 7 of the HEC Byte is a HEC error flag
0 = Use the HEC Error checker within the IMA block
Check ATMUTxAddr[4] and 0 = mask bits (don’t care)
ATMURxAddr[4]
1 = Check ATMUTxAddr[4] and TMURxAddr[4] for correct value
Check ATMUTxAddr[3] and 0 = mask bits (don’t care)
ATMURxAddr[3]
1 = Check ATMUTxAddr[3] and ATMURxAddr[3] for correct value
Check ATMUTxAddr[2] and 0 = mask bits (don’t care)
ATMURxAddr[2]
1 = Check ATMUTxAddr[2] and ATMURxAddr[2] for correct value
2.4.6
0x805—IMA_MEM_LOW_TEST (IMA Memory Test Address (Bits 0–7))
Registers 0x805—0x808 are used to perform memory diagnostic tests on the internal or external differential delay
SRAM.
Bit
Default
Name
Description
7–0
0x00
Memory Test Address
This field contains the least significant bits of the memory test address for the selected memory
component. Range: 0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
191
Mindspeed Proprietary and Confidential
Registers
2.4.7
0x806—IMA_MEM_HI_TEST (IMA Memory Test Address (Bits 8–15))
Bit
Default
Name
Description
7–0
0x00
Memory Test Address
This field contains the middle significant bits of the memory test address for the selected
memory component. Range: 0x00–0xFF
2.4.8
0x807—IMA_MEM_TEST_CTL (IMA Memory Test Control / Address MSBs)
Bit
Default
Name
Description
7
0
Memory Test Address
Bit 20
This field contains the most significant bit of the memory test address for the selected memory
component.
6–4
3–0
0
0
RAM Test Access
0 = no test selected, normal operation
1 = SRAM Test
2–7 = Reserved
Memory Test Address
Bits 19–16
This field contains the most significant bits of the memory test address for the selected memory
component. Range: 0x00–0x0F
2.4.9
0x808—IMA_MEM_TEST_DATA (IMA Memory Test Data)
Bit
Default
Name
Description
7–0
0x00
Memory Test Data
This field contains the data to be written or read from the memory test address for the selected
memory component. Range: 0x00–0xFF
2.4.10
0x809—IMA_LNK_DIAG_CTL (IMA Link Diagnostic Control Register)
This register is used to specify a port number for observation of link differential delay and anomalies. The contents
of this register are used to report the link information via registers 0x809–0x80B. Bit 5 of this register is read-only.
Bit
Default
Name
Description
7
6
5
—
—
—
—
—
Reserved. Set to 0
Reserved. Set to 0
Link Delay Write
Counter
This field contains the most significant bit of the SRAM write counter for the diagnostic link
(selected using the field below).
4–0
0x00
Link Diagnostic PHY
Address
This field contains the PHY Cell Bus Address of the port for which a diagnostic measurement is
to be performed. Range: 0x00–0x1F
2.4.11
0x80A—IMA_LNK_DIFF_DEL (IMA Link Differential Delay Write Counter)
This register, along with bit 5 of address 0x809, reports the value of the SRAM write phase at the time when the
read phase is 0. This phase information is used to calculate the link differential delay.
®
28529-DSH-001-K
Mindspeed Technologies
192
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description
7–0
—
Link Delay Write
Counter
This field contains a snapshot of 8 of the least significant bits of the SRAM write counter for the
diagnostic link (selected using address 0x809).
All others (Range: 0x00–0xFF)
Delay Window = 0 (see register 0x815): Value = Cell_count >> 1
Delay Window = 1–3 (see register 0x815): Value = Cell_count
Delay Window = 4 (see register 0x815): Value = Cell_count >> 2
2.4.12
0x80B—IMA_RCV_LNK_ANOMALIES (IMA Receive Link Anomalies)
These anomalies are for the diagnostic link selected using address 0x809. The bits in this register are read-only
and are cleared upon read.
Bit
Default
Name
Description
7
—
ICP-ERR Anomaly
1 = ICP-ERR anomaly was active sometime since the last time this register was read
0 = ICP-ERR defect was inactive
6
5
4
3
2
1
0
—
—
—
—
—
—
—
ICP-INV Anomaly—
Unexpected IMA Label
1 = Unexpected IMA Label condition of the ICP-INV anomaly was active sometime since the last
time this register was read
0 = Unexpected IMA Label condition was inactive
ICP-INV Anomaly—
Unexpected LID
1 = Unexpected LID condition of the ICP-INV anomaly was active sometime since the last time
this register was read
0 = Unexpected LID condition was inactive
ICP-INV Anomaly—
Unexpected IMA ID
1 = Unexpected IMA ID condition of the ICP-INV anomaly was active sometime since the last
time this register was read
0 = Unexpected IMA ID condition was inactive
ICP-INV Anomaly—
Unexpected M
1 = Unexpected M condition of the ICP-INV anomaly was active sometime since the last time
this register was read
0 = Unexpected M condition was inactive
ICP-INV Anomaly—
Unexpected IMA Frame since the last time this register was read
Number
1 = Unexpected IMA Frame Number condition of the ICP-INV anomaly was active sometime
0 = Unexpected IMA Frame Number condition was inactive
ICP-INV Anomaly—
Unexpected IMA Cell
Offset
1 = Unexpected IMA Cell Offset condition of the ICP-INV anomaly was active sometime since the
last time this register was read
0 = Unexpected IMA Cell Offset condition was inactive
ICP-MIS Anomaly
1 = ICP-MIS anomaly was active sometime since the last time this register was read
0 = ICP-MIS defect was inactive
®
28529-DSH-001-K
Mindspeed Technologies
193
Mindspeed Proprietary and Confidential
Registers
2.4.13
0x80C—IMA _PHY_LOOPBACK (IMA Phy Side UTOPIA Loopback)
This register controls the UTOPIA loopbacks on the PHY side of the IMA block.
Bit
Default
Name
Description
7-3
2
—
—
—
Reserved. Set to 0
Loopback Enable
0 = PHY side loopback disabled.
1 = PHY side loopback enabled per bits 1:0 of this register.
1-0
—
Loopback Type(s)
0 = IMA System Loopback 0 -- uses TxClav signal(s) from PHY (TC or external)
1 = IMA System Loopback 1 -- ignores TxClav signal(s) from PHY layer
2 = IMA Line Loopback -- ignores TxClav signal(s) from PHY layer
3 = Not Defined
2.4.14
0x80E—IMA_DIAG_XOR_BIT (IMA Diagnostic Bit)
This register provides a single bit that can be used by a diagnostic test routine to verify the connectivity of the
microprocessor address lines to the IMA device. This bit is read-only.
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Address Diagnostic Bit Exclusive OR of address bits from previous IMA core Read access. The number of bits in the
exclusive OR operation is 11.
2.4.15
0x80F—IMA_DIAG (IMA Diagnostic Register)
This register provides an isolated 8 bit storage register that can be used by a diagnostic test routine to verify the
connectivity of the microprocessor data lines to the IMA device.
Bit
Default
Name
Description
7–0
0x00
Data Diagnostic Register An 8 bit register that can be written and read by the processor. The register is not used within
the IMA Block.
®
28529-DSH-001-K
Mindspeed Technologies
194
Mindspeed Proprietary and Confidential
Registers
2.4.16
0x810—IMA_TIM_REF_MUX_CTL_ADDR (IMA Timing Reference
Multiplexer Control Address)
This register is used in conjunction with 0x811 to configure various timing elements within the IMA core. Register
0x810 and 0x811 are an indirect register pair in that a particular timing element is selected using register 0x810
and the configuration for that timing element is programmed using register 0x811.
Bit
Default
Name
Description
7–6
0
Multiplexer Type
0 = Set timing reference for a Rx IMA Group
1 = Set timing reference for a Tx IMA Group
2 = Set timing source for Tx_TRL Outputs
3 = Set the Clock Divisor for an IMA group
5
—
0
—
Reserved. Set to 0.
4–0
Multiplexer ID
For Multiplexer Type = 0, Multiplexer Type = 1, and Multiplexer Type = 3:
M28525: 0–0xF: IMA Group 1–16
M28529: 0–0x1F: IMA Group 1–32
For Multiplexer Type = 2:
0–1: Tx_TRL[0]–Tx_TRL[1] output
®
28529-DSH-001-K
Mindspeed Technologies
195
Mindspeed Proprietary and Confidential
Registers
2.4.17
0x811—IMA_TIM_REF_MUX_CTL_DATA (IMA Timing Reference
Multiplexer Control Data)
Bit
Default
Name
Description
7
6
—
—
—
—
Reserved. Set to 0.
Reserved. Set to 0.
For Multiplexer Type 0 and 1
5–0
5–0
0x00
0x00
Timing Source
Timing Source
0x00–0x1F: Select timing from a Receive Port (see register 0x816)
M28525: 0–0xF: Port 0–15
M28529: 0–0x1F: Port 0–31
0x20: Use IMA_SysClk/24 or DSL generator output as source (see register 0x816)
0x21: Use IMA_RefClk as source
For Multiplexer Type 2
0x00–0x1F: Select timing from a Receive Port (see register 0x816)
M28525: 0–0xF: Port 0–15
M28529: 0–0x1F: Port 0–31
0x20: IMA_SysClk/24
0x21: IMA_RefClk
0x22: 8 kHz
For Multiplexer Type 3
5
4
—
—
—
—
Reserved. Set to 0.
Reserved. Set to 0.
3–0
0x0
Clock Divisor
This field contains the clock divider multiplier for the group. The IMA group number is set by
writing to the Multiplexer ID field in address 0x810.
0 = Based on Link Type field in address 0x002
1 = 1/1
2 = 192/193
3 = 15/16
®
28529-DSH-001-K
Mindspeed Technologies
196
Mindspeed Proprietary and Confidential
Registers
2.4.18
0x812—IMA_RX_PERSIST_CONFIG (IMA Receive Persistence
Configuration)
Bit
Default
Name
Description
7
6
0
0
—
Reserved. Set to 0.
(1)
Alpha Value
0: α = 1
1: α = 2
(2)
5–3
2–0
0
0
Beta Value
0: β = 1
1: β = 2
2: β = 3
3: β = 4
4: β = 5
(3)
Gamma Value
0: γ = 1
1: γ = 2
2: γ = 3
3: γ = 4
4: γ = 5
Footnote:
(1) The Alpha Value is the number of consecutive invalid ICP cells needed for the link to leave the IMA Sync state.
(2) The Beta Value is the number of consecutive errored ICP cells needed for the link to leave the IMA Sync state.
(3) The Gamma Value is the number of consecutive valid ICP cells needed for the link to enter the IMA Sync state.
2.4.19
0x813—IMA_ATM_UTOPIA_BUS_CTL (IMA ATM UTOPIA Bus Control)
This register configures the operation of the ATM side UTOPIA bus and the sample time of PhyUTxClAv for an IMA
group.
Bit
Default
Name
Description
7
6
—
0
—
Reserved. Set to 0.
ATM Address Mode
0 = UTOPIA Level 2 (multiple addresses)
1 = UTOPIA Level 1 (single fixed address, no address latching)
5
4
0
0
—
Reserved. Set to 0.
ATMURxClAv Mode
0 = ATMURxClAv is set active for selected channel during cell transfer
1 = ATMURxClAv is set inactive for selected channel during cell transfer
3
0
ATMUTxClAv Last 4
Bytes/Words Mode
0 = ATMUTxClAv is forced inactive/active (based on the state of bit 2) during last 4 bytes/words
for selected channel during cell transfer
1 = ATMUTxClAv reflects true cell available status during last 4 bytes/words for selected channel
during cell transfer
2
1
0
0
0
0
ATMUTxClAv Mode
0 = ATMUTxClAv is set inactive for selected channel during cell transfer
1 = ATMUTxClAv is set active for selected channel during cell transfer
ClAv Three-state Disable 0 = ATMURxClAv and ATMUTxClAv threestate when not selected
1 = ATMURxClAv and ATMUTxClAv do not threestate
PHYUTxClAv Sample
Time
0 = For an IMA group, sample PhyUTxClAv during an ICP cell to determine SICP rate
1 = For an IMA group, delay sampling PhyUTxClAv until >5 payload byte periods after an ICP
transfer
®
28529-DSH-001-K
Mindspeed Technologies
197
Mindspeed Proprietary and Confidential
Registers
2.4.20
0x814—IMA_DIFF_DELAY_ADDR (IMA Differential Delay Control Address)
This register is used in conjunction with 0x815 to configure the differential delay operation of the IMA core. Register
0x814 and 0x815 are an indirect register pair in that a particular IMA group is selected using register 0x814 and the
configuration for that IMA group is programmed using register 0x815.
Bit
Default
Name
Description
7
6
—
0
—
Reserved. Set to 0.
Control Type
0 = Set Delay Threshold for an IMA group
1 = Set Delay Window for an IMA group
5
—
—
Reserved. Set to 0.
4–0
0x0
Group Number
M28525: 0–0xF: IMA Group 1–16
M28529: 0–0x1F: IMA Group 1–32
2.4.21
0x815—IMA_DIFF_DELAY_DATA (IMA Differential Delay Control Data)
Bit
Default
Name
Description
For Control Type = 0
7–0
0x00
Differential Delay
Threshold
This field contains the cell offset that corresponds to differential delay threshold setting for the
group.
Delay Window = 0, 5: Value = 255–(Cell_count >> 1)
Delay Window = 1–3, 6–7: Value = 255–Cell_count
Delay Window = 4: Value = 255–(Cell_count >> 2)
For Control Type = 1
7
6
—
—
—
—
—
—
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
—
5
—
4
—
—
3
2–0
Delay Window
This field contains the number of IMA frames (assuming M=128) that are examined when
setting the differential delay buffer. This field is set based on the facility payload rate.
0 = 8 frames (1024 cells), for payload rates ≥ 1024 kbps
1 = 4 frames (512 cells), for 1024 kbps > payload rates ≥ 512 kbps
2 = 2 frames (256 cells), for 512 kbps > payload rates ≥ 256 kbps
3 = 1 frame (128 cells), for payload rates < 256 kbps
4 = 16 frames (2048 cells), for payload rates ≥ 1024 kbps
5 = 8 frames (1024 cells), for 1024 kbps > payload rates ≥ 512 kbps
6 = 4 frames (512 cells), for 512 kbps > payload rates ≥ 256 kbps
7 = 2 frame (256 cells), for payload rates < 256 kbps
®
28529-DSH-001-K
Mindspeed Technologies
198
Mindspeed Proprietary and Confidential
Registers
2.4.22
0x816—IMA_DSL_CLOCK_GEN_ADDR (IMA DSL Clock Generator Control)
This register is used in conjunction with 0x817 to configure the operation of the DSL Clock Generator in the IMA
core. Register 0x816 and 0x817 are an indirect register pair in that a particular clock generator element is selected
using register 0x816 and the configuration for that element is programmed using register 0x817.
The overall operation of the clock generators are governed by the following equations:
•
•
•
•
Prescaler Factor = Prescaler Numerator / (Prescaler Terminal Count + 1)
Intermediate Frequency = Reference Clock Frequency * Prescaler Factor
Reference Denominator = 257 + Reference Clock Divisor
8 kHz = Intermediate Frequency / (Reference Denominator)
Link Payload Rate = 8 kbps * (Multiplier Factor) * (Rate Multiplier)
A further constraint is:
•
(Maximum Link Payload Rate) / (Rate Multiplier) ≤ Intermediate Frequency ≤ IMA_SysClk/16
In a typical G.shdsl application, Intermediate Frequency is set to 2.56 MHz, Rate Multiplier = 1, and the Reference
Denominator is set to 320. Other settings are possible as long as the above equations and constraints are met.
Bit
Default
Name
Description
7–5
0
Control Type
0 = Basic Setup
1 = Pre-scaler and Reference Divisor Setup
2 = Tx IMA Group Factor LSBs
3 = Tx IMA Group Factor MSB
4 = Rx IMA Group Factor LSBs
5 = Rx IMA Group Factor MSB
6 = Rx Timing Synthesizer Factor LSBs
7 = Rx Timing Synthesizer Factor MSB
For Control Type = 0
Reserved. Set to 0.
4–0
—
—
—
For Control Type = 1
Reserved. Set to 0.
4-2
1-0
—
—
Sub Type
0 = Pre-scaler Terminal Count
1 = Pre-scalar Numerator
2 = Reference Divisor
3 = Reserved
For Control Type = 2, 3, 4, 5
4–0
4–0
0x0
Group Number
Port Number
M28525: 0–0xF: IMA Group 1–16
M28529: 0–0x1F: IMA Group 1–32
For Control Type = 6, 7
0x00
M28525: 0–0xF: Port 0–15
M28529: 0–0x1F: Port 0–31
®
28529-DSH-001-K
Mindspeed Technologies
199
Mindspeed Proprietary and Confidential
Registers
2.4.23
0x817—IMA_DSL_CLOCK_GEN_DATA (IMA_DSL Clock Generator Data)
This register is used in conjunction with 0x816 to configure the operation of the DSL Clock Generator in the IMA
core. Register 0x816 and 0x817 are an indirect register pair in that a particular clock generator element is selected
using register 0x816 and the configuration for that element is programmed using register 0x817.
Bit
Default
Name
Description
For Control Type = 0
7
6
—
0
—
Reserved. Set to 0.
EnRxSyn
Enable Rx Timing Synthesizers
0 = Use SPRxClk inputs
1 = Use synthesizers instead of SPRxClk inputs
5
0
DSLClkGen
Substitute DSL clock generator
0 = Use IMA_SysClk/24 in IMA group clock and Tx_TRL selectors
1 = Use DSL Clock generator outputs when Timing Source is set to 0x20 in register
0x811.
4
0
IMA_ClkSel
0 = Use IMA_SysClk as input to DSL Clock Generators
1 = Use IMA_RefClk as input to DSL Clock Generators
3–0
—
—
Reserved. Set to 0.
For Control Type = 1/Sub-type = 0
7–0
0x00
Pre-scaler Terminal
Count
This field contains the terminal count of the pre-scaler clock divider. The pre-scaler denominator
is the value of this field plus 1.
For Control Type = 1/Sub-type = 1
This field contains the numerator for the pre-scaler.
For Control Type = 1/Sub-type = 2
7–0
7-0
0x00
0x00
Pre-scaler Numerator
Reference Clock Divisor This field contains 8 of the 9 bits of the terminal count for the reference clock divisor. The
reference clock divisor counts from 0 to the terminal count which is given by the value of this
field plus 257. As an example if the value of this register is 63 decimal, then the reference clock
divisor will be 320.
For Control Type = 2, 4
7–0
0x00
Group Clock Multiplier
Factor (lsbs)
This register contains the 8 lsbs of the payload bandwidth for the ports used in the IMA group.
The contents of this register are multiplied by 8kbps and the Rate Multiplier in order to obtain
the bandwidth.
For Control Type = 3, 5
7-6
5-4
—
0
—
Reserved. Set to 0.
Rate Multiplier
Scale factor used to generate link rates > Intermediate Frequency
0 = Multiply rate by 1 (typically used by link rates < 3.072 Mbps)
1 = Multiply rate by 2 (typically used by 3.072 < link rates < 6.144 Mbps)
2 = Multiply rate by 4 (typically used by link rates > 6.144 Mbps)
3 = Not defined.
3-1
0
—
0
—
Reserved. Set to 0.
Group Clock Multiplier
Factor (msb)
This register contains the msb of the payload bandwidth for the ports used in the IMA group.
The contents of this register are multiplied by 2048kbps and the Rate Multiplier in order to
obtain the bandwidth.
®
28529-DSH-001-K
Mindspeed Technologies
200
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description (Continued)
For Control Type = 6
7–0
0x00
Port Clock Multiplier
Factor (lsbs)
This register contains the 8 lsbs of the payload bandwidth for the specific port of the Rx Timing
clock synthesizer. The contents of this register are multiplied by 8kbps and the Rate Multiplier in
order to obtain the bandwidth.
For Control Type = 7
7–6
5-4
—
0
—
Reserved. Set to 0.
Rate Multiplier
Scale factor used to generate link rates > Intermediate Frequency
0 = Multiply rate by 1 (typically used by link rates < 3.072 Mbps)
1 = Multiply rate by 2 (typically used by 3.072 < link rates < 6.144 Mbps)
2 = Multiply rate by 4 (typically used by link rates > 6.144 Mbps)
3 = Not defined.
3–1
0
—
0
—
Reserved. Set to 0.
Port Clock Multiplier
Factor (msb)
This register contains the msb of the payload bandwidth for the specific port of the Rx Timing
clock synthesizer. The contents of this register are multiplied by 2048kbps and the Rate
Multiplier in order to obtain the bandwidth.
2.4.24
0x818—IMA_RX_TRANS_TABLE (IMA Receive Translation Table Address)
This register is used in conjunction with 0x819 for configure the translation between the ATM side UTOPIA
addresses and the internal channels (bypass ports and IMA groups) associated with the IMA core. Register 0x818
and 0x819 are an indirect register pair in that a address is selected using register 0x818 and the configuration for
that address is programmed using register 0x819.
Bit
Default
Name
Description
7
0
Translation Type
0 = the value in bits 5–0 enables ATM address –> IMA internal channel translations
1 = the value in bits 5–0 enables IMA internal channel –> ATM address translations
6
—
—
Don’t care. Ignore.
For Translation Type = 0
Don’t care. Ignore.
5
—
—
4–0
0x00
ATM UTOPIA Address
For Type 0, this field contains the ATM Side UTOPIA address.
Range: 0x00–0x1F
For Translation Type = 1
5–0
0x00
Internal IMA Channel
For Type 1, this field contains the IMA internal channel address.
Range 0x00–0x1F: Receive Port
M28525: 0–0xF: Port 0–15
M28529: 0–0x1F: Port 0–31
Range 0x20–0x3F: IMA Group
M28525: 0x20–0x2F: IMA Group 1–16
M28529: 0x20–0x3F: IMA Group 1–32
®
28529-DSH-001-K
Mindspeed Technologies
201
Mindspeed Proprietary and Confidential
Registers
2.4.25
0x819—IMA_RX_ATM_TRANS_TABLE (IMA Receive ATM Translation
Table Internal Channel)
This register is used in conjunction with 0x818 for configure the translation between the ATM side UTOPIA
addresses and the internal channels (bypass ports and IMA groups) associated with the IMA core. Register 0x818
and 0x819 are an indirect register pair in that an address is selected using register 0x818 and the configuration for
that address is programmed using register 0x819.
Bit
Default
Name
Description
For Translation Type = 0
7
6
—
1
—
Don’t care. Ignore.
Internal IMA Channel
1=ATM address is not assigned to this device
0=ATM address is assigned to this device
5-0
7
—
0
—
Don’t care. Ignore.
For Translation Type = 1
Channel Active
1 = Internal Channel Active
0 = Internal Channel Inactive
6
5
—
—
—
—
Don’t care. Ignore.
Don’t care. Ignore.
4–0
0x00
ATM UTOPIA Address
This field contains the mapping for the Internal IMA channel set in register 0x818.
Range: 0x00–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
202
Mindspeed Proprietary and Confidential
Registers
2.4.26
0x81B—IMA_TX_TRANS_TABLE (IMA Transmit Translation Table Address)
This register is used in conjunction with 0x81C for configure the translation between the ATM side UTOPIA
addresses and the internal channels (bypass ports and IMA groups) associated with the IMA core. Register 0x81B
and 0x81C are an indirect register pair in that a address is selected using register 0x81B and the configuration for
that address is programmed using register 0x81C.
Bit
Default
Name
Description
7
0
Translation Type
0 = the value in bits 5–0 enables ATM address –> IMA internal channel translations
1 = the value in bits 5–0 enables IMA internal channel –> ATM address translations
6
—
—
Don’t care. Ignore.
For Translation Type = 0
Don’t care. Ignore.
5
—
—
4–0
0x00
ATM UTOPIA Address
For Type 0, this field contains the ATM Side UTOPIA address.
Range: 0x00–0x1F
For Translation Type = 1
5–0
0x00
Internal IMA Channel
For Type 1, this field contains the IMA internal channel address.
Range 0x00–0x1F: Transmit Port
M28525: 0–0xF: Port 0–15
M28529: 0–0x1F: Port 0–31
Range 0x20–0x3F: IMA Group
M28525: 0x20–0x2F: IMA Group 1–16
M28529: 0x20–0x3F: IMA Group 1–32
2.4.27
0x81C—IMA_TX_ATM_TRANS_TABLE (Transmit ATM Translation Table
Internal Channel)
This register is used in conjunction with 0x81B for configure the translation between the ATM side UTOPIA
addresses and the internal channels (bypass ports and IMA groups) associated with the IMA core. Register 0x81B
and 0x81C are an indirect register pair in that a address is selected using register 0x81B and the configuration for
that address is programmed using register 0x81C.
Bit
Default
Name
Description
For Translation Type = 0
7
6
—
1
—
Don’t care. Ignore.
Internal IMA Channel
1=ATM address is not assigned to this device
0=ATM address is assigned to this device
5-0
—
—
Don’t care. Ignore
®
28529-DSH-001-K
Mindspeed Technologies
203
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description
For Translation Type = 1
7
0
Channel Active
1 = Internal Channel Active
0 = Internal Channel Inactive
6
5
—
—
—
—
Don’t care. Ignore.
Don’t care. Ignore.
4–0
0x00
ATM UTOPIA Address
This field contains the mapping for the Internal IMA channel set in register 0x81B.
Range: 0x00–0x1F
2.5
IMA Group
The IMA Group layer contains configuration and status information that is associated with IMA groups.
2.5.1
0x81F—IMA_GRP_1TO4_SEM (Group Table Control I)
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 4
addresses 0x8DC–0x8DF
addresses 0x8D8–0x8DB
addresses 0x8D4–0x8D7
addresses 0x8D0–0x8D3
addresses 0x838–0x83F
addresses 0x830–0x837
addresses 0x828–0x82F
addresses 0x820–0x827
Update Enable for Receive group 3
Update Enable for Receive group 2
Update Enable for Receive group 1
Update Enable for Transmit group 4
Update Enable for Transmit group 3
Update Enable for Transmit group 2
Update Enable for Transmit group 1
2.5.2
0x91F—IMA_GRP_5TO8_SEM (Group Table Control II)
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
®
28529-DSH-001-K
Mindspeed Technologies
204
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 8
Update Enable for Receive group 7
Update Enable for Receive group 6
Update Enable for Receive group 5
Update Enable for Transmit group 8
Update Enable for Transmit group 7
Update Enable for Transmit group 6
Update Enable for Transmit group 5
addresses 0x9DC–0x9DF
addresses 0x9D8–0x9DB
addresses 0x9D4–0x9D7
addresses 0x9D0–0x9D3
addresses 0x938–0x93F
addresses 0x930–0x937
addresses 0x928–0x92F
addresses 0x920–0x927
2.5.3
0xA1F—IMA_GRP_9TO12_SEM (Group Table Control III)
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 12
Update Enable for Receive group 11
Update Enable for Receive group 10
Update Enable for Receive group 9
Update Enable for Transmit group 12
Update Enable for Transmit group 11
Update Enable for Transmit group 10
Update Enable for Transmit group 9
addresses 0xADC–0xADF
addresses 0xAD8–0xADB
addresses 0xAD4–0xAD7
addresses 0xAD0–0xAD3
addresses 0xA38–0xA3F
addresses 0xA30–0xA37
addresses 0xA28–0xA2F
addresses 0xA20–0xA27
®
28529-DSH-001-K
Mindspeed Technologies
205
Mindspeed Proprietary and Confidential
Registers
2.5.4
0xB1F—IMA_GRP_13TO16_SEM (Group Table Control IV)
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 16
Update Enable for Receive group 15
Update Enable for Receive group 14
Update Enable for Receive group 13
Update Enable for Transmit group 16
Update Enable for Transmit group 15
Update Enable for Transmit group 14
Update Enable for Transmit group 13
addresses 0xBDC–0xBDF
addresses 0xBD8–0xBDB
addresses 0xBD4–0xBD7
addresses 0xBD0–0xBD3
addresses 0xB38–0xB3F
addresses 0xB30–0xB37
addresses 0xB28–0xB2F
addresses 0xB20–0xB27
2.5.5
0xC1F—IMA_GRP_17TO20_SEM (Group Table Control V (M28529 Only))
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 20
Update Enable for Receive group 19
Update Enable for Receive group 18
Update Enable for Receive group 17
Update Enable for Transmit group 20
Update Enable for Transmit group 19
Update Enable for Transmit group 18
Update Enable for Transmit group 17
addresses 0xC5C–0xC5F (Not defined for M28525)
addresses 0xC58–0xC5B (Not defined for M28525)
addresses 0xC54–0xC57 (Not defined for M28525)
addresses 0xC50–0xC53 (Not defined for M28525)
addresses 0xC38–0xC3F (Not defined for M28525)
addresses 0xC30–0xC37 (Not defined for M28525)
addresses 0xC28–0xC2F (Not defined for M28525)
addresses 0xC20–0xC27 (Not defined for M28525)
®
28529-DSH-001-K
Mindspeed Technologies
206
Mindspeed Proprietary and Confidential
Registers
2.5.6
0xC9F—IMA_GRP_21TO24_SEM (Group Table Control V (M28529 Only))
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 24
Update Enable for Receive group 23
Update Enable for Receive group 22
Update Enable for Receive group 21
Update Enable for Transmit group 24
Update Enable for Transmit group 23
Update Enable for Transmit group 22
Update Enable for Transmit group 21
addresses 0xCDC–0xCDF (Not defined for M28525)
addresses 0xCD8–0xCDB (Not defined for M28525)
addresses 0xCD4–0xCD7 (Not defined for M28525)
addresses 0xCD0–0xCD3 (Not defined for M28525)
addresses 0xCB8–0xCBF (Not defined for M28525)
addresses 0xCB0–0xCB7 (Not defined for M28525)
addresses 0xCA8–0xCAF (Not defined for M28525)
addresses 0xCA0–0xCA7 (Not defined for M28525)
2.5.7
0xD1F—IMA_GRP_25TO28_SEM (Group Table Control V (M28529 Only))
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 28
Update Enable for Receive group 27
Update Enable for Receive group 26
Update Enable for Receive group 25
Update Enable for Transmit group 28
Update Enable for Transmit group 27
Update Enable for Transmit group 26
Update Enable for Transmit group 25
addresses 0xD5C–0xD5F (Not defined for M28525)
addresses 0xD58–0xD5B (Not defined for M28525)
addresses 0xD54–0xD57 (Not defined for M28525)
addresses 0xD50–0xD53 (Not defined for M28525)
addresses 0xD38–0xD3F (Not defined for M28525)
addresses 0xD30–0xD37 (Not defined for M28525)
addresses 0xD28–0xD2F (Not defined for M28525)
addresses 0xD20–0xD27 (Not defined for M28525)
®
28529-DSH-001-K
Mindspeed Technologies
207
Mindspeed Proprietary and Confidential
Registers
2.5.8
0xD9F—IMA_GRP_29TO32_SEM (Group Table Control V (M28529 Only))
For the following bits, 1 = the group table is being updated, 0 = the group table is not being updated. The update
enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After
writing to all 8 elements, the update enable is reset to 0. The group tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Update Enable for Receive group 32
Update Enable for Receive group 31
Update Enable for Receive group 30
Update Enable for Receive group 29
Update Enable for Transmit group 32
Update Enable for Transmit group 31
Update Enable for Transmit group 30
Update Enable for Transmit group 29
addresses 0xDDC–0xDDF (Not defined for M28525)
addresses 0xDD8–0xDDB (Not defined for M28525)
addresses 0xDD4–0xDD7 (Not defined for M28525)
addresses 0xDD0–0xDD3 (Not defined for M28525)
addresses 0xDB8–0xDBF (Not defined for M28525)
addresses 0xDB0–0xDB7 (Not defined for M28525)
addresses 0xDA8–0xDAF (Not defined for M28525)
addresses 0xDA0–0xDA7 (Not defined for M28525)
2.5.9
IMA_TX_GRPn_RX_TEST_PATTERN (Transmit Group Rx Test Pattern)
This register contains the value of the Rx Test Pattern field for the transmitted ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x820 0x828 0x830 0x838 0x920 0x928 0x930 0x938 0xA20 0xA28 0xA30 0xA38 0xB20 0xB28 0xB30 0xB38
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC20 0xC28 0xC30 0xC38 0xCA
0
0xCA
8
0xCB
0
0xCB
8
0xD2
0
0xD2
8
0xD3
0
0xD3
8
0xDA
0
0xDA
8
0xDB
0
0xDB
8
M28525 -- Not Applicable
M28529
®
28529-DSH-001-K
Mindspeed Technologies
208
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description
7–0
0x00
Rx Test Pattern
In support of the Test Pattern Procedure, this field is set equal to the value acquired from the
Receive side test link. See address 0x8E7. When the Test Pattern Procedure is inactive, the Rx
Test Pattern field should be set to 0xFF.
Range: 0x00–0xFF
2.5.10
IMA_TX_GRPn_CTL (Transmit Group Control Register)
This register, in conjunction with the IMA_TX_GRPn_FIRST_PHY_ADDR register, controls the operation of the
Transmit IMA group.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x821 0x829 0x831 0x839 0x921 0x929 0x931 0x939 0xA21 0xA29 0xA31 0xA39 0xB21 0xB29 0xB31 0xB39
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC21 0xC29 0xC31 0xC39 0xCA
1
0xCA
9
0xCB
1
0xCB
9
0xD2
1
0xD2
9
0xD3
1
0xD3
9
0xDA
1
0xDA
9
0xDB
1
0xDB
9
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
0
Group Enable
1 = Group is established and a round-robin is created
0 = Group is not established
6
0
SW Timeout Expired
1 = certain LSM transitions (Unusable → Usable, Usable → Active) are allowed
0 = certain LSM transitions (Unusable → Usable, Usable → Active) are blocked
5
—
—
Reserved. Set to 0.
4–0
0x0
Group Size
Sets the number of configured links within group.
Range: 0x0–0x1F (1–32 links in group)
®
28529-DSH-001-K
Mindspeed Technologies
209
Mindspeed Proprietary and Confidential
Registers
2.5.11
IMA_TX_GRPn_FIRST_PHY_ADDR (Transmit First PHY Address)
This register, in conjunction with the IMA_TX_GRPn_CTL register, controls the operation of the Transmit IMA
group.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x82
2
0x82A
0x83
2
0x83A
0x92
2
0x92A
0x93
2
0x93A 0xA2 0xA2A 0xA3 0xA3A 0xB2 0xB2A 0xB3 0xB3A
2
2
2
2
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC22 0xC2 0xC32 0xC3
0xCA
2
0xCA
A
0xCB
2
0xCB
A
0xD2
2
0xD2
A
0xD3
2
0xD3
A
0xDA
2
0xDA
A
0xDB
2
0xDB
A
A
A
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
6
—
0
—
Reserved. Set to 0.
Group Inhibit
1 = Group is inhibited from carrying traffic
0 = Group is not inhibited
5
0x0
Tx IMA Version
IMA OAM Label value
1 = IMA v1.1
0 = IMA v1.0
4–0
0x00
Link PHY Address
This field contains the PHY port address of the Transmit link with the lowest LID in the group.
M28525: Range: 0–0xF
M28529: Range: 0–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
210
Mindspeed Proprietary and Confidential
Registers
2.5.12
IMA_TX_GRPn_ID (Transmit Group ID)
This register contains the value of the IMA Group ID field for the transmitted ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x82 0x82B 0x83 0x83B 0x923 0x92B 0x933 0x93B 0xA2 0xA2B 0xA3 0xA3B 0xB2 0xB2B 0xB3 0xB3B
3
3
3
3
3
3
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC23 0xC2 0xC33 0xC3
0xCA
3
0xCA
B
0xCB
3
0xCB
B
0xD2
3
0xD2
B
0xD3
3
0xD3
B
0xDA
3
0xDA
B
0xDB
3
0xDB
B
B
B
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–0
0x00
Tx Group ID
This field contains the Transmit Group ID sent in the Transmit ICP cells of all links within the
group. Range: 0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
211
Mindspeed Proprietary and Confidential
Registers
2.5.13
IMA_TX_GRPn_STAT_CTL (Transmit Group Status and Control)
This register contains the value of the Group Status and Control field for the transmitted ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x824 0x82C 0x834 0x83C 0x924 0x92C 0x934 0x93C 0xA2 0xA2C 0xA3 0xA3C 0xB2 0xB2C 0xB3 0xB3C
4
4
4
4
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC2
4
0xC2
C
0xC3
4
0xC3
C
0xCA
4
0xCA
C
0xCB
4
0xCB
C
0xD2
4
0xD2
C
0xD3
4
0xD3 0xDA 0xDA 0xDB 0xDB
C
4
C
4
C
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–4
0x00
Group State
0 = Start-up
1 = Start-up-Ack
2 = Config-Abort–Unsupported M
3 = Config-Abort–Incompatible Symmetry
4 = Config-Abort–Unsupported IMA Version
5–7 = Reserved for other Config-Abort states
8 = Insufficient Links
9 = Blocked
0xA = Operational
0xB–F = reserved
3–2
1–0
0
0
Group Symmetry
Frame Length (M)
0 = Symmetrical configuration and operation
1 = Symmetrical configuration and asymmetrical operation
2 = Asymmetrical configuration and operation
3 = Alternate symmetrical configuration and operation
0 = M is 32
1 = M is 64
2 = M is 128
3 = M is 256
®
28529-DSH-001-K
Mindspeed Technologies
212
Mindspeed Proprietary and Confidential
Registers
2.5.14
IMA_TX_GRPn_TIMING_INFO (Transmit Timing Information)
This register contains the value of the Transmit Timing Information field for the transmitted ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x82 0x82D 0x83 0x83D 0x92 0x92D 0x93 0x93D 0xA2 0xA2D 0xA3 0xA3D 0xB2 0xB2D 0xB3 0xB3D
5
5
5
5
5
5
5
5
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC25 0xC2 0xC35 0xC3
0xCA
5
0xCA
D
0xCB
5
0xCB
D
0xD2
5
0xD2
D
0xD3
5
0xD3
D
0xDA
5
0xDA
D
0xDB
5
0xDB
D
D
D
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
6
5
0
0
0
Unused: Set to 0.
Unused: Set to 0.
Tx Clock Mode
0 = Independent Transmit Clock (ITC)
1 = Common Transmit Clock (CTC)
4–0
0
Timing Reference Link This field contains the LID of the Transmit TRL. Range: 0x0–0x1F
ID
®
28529-DSH-001-K
Mindspeed Technologies
213
Mindspeed Proprietary and Confidential
Registers
2.5.15
IMA_TX_GRPn_TEST_CTL (Transmit Test Control)
This register contains the value of the Tx Test Control field for the transmitted ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x826 0x82E 0x836 0x83E 0x926 0x92E 0x936 0x93E 0xA2 0xA2E 0xA3 0xA3E 0xB2 0xB2E 0xB3 0xB3E
6
6
6
6
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC26 0xC2E 0xC36 0xC3E 0xCA
6
0xCA
E
0xCB
6
0xCB
E
0xD2
6
0xD2
E
0xD3
6
0xD3
E
0xDA
6
0xDA
E
0xDB
6
0xDB
E
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
6
5
0
0
0
Unused: Set to 0.
Unused: Set to 0.
Test Link Command
Test Link ID
0 = Inactive
1 = Active
4–0
0
This field contains the LID of the Transmit Test Link. Range: 0x0–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
214
Mindspeed Proprietary and Confidential
Registers
2.5.16
IMA_TX_GRPn_TX_TEST_PATTERN (Transmit Group Tx Test Pattern)
This register contains the value of the Tx Test Pattern field for the transmitted ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x827 0x82F 0x837 0x83F 0x927 0x92F 0x937 0x93F 0xA27 0xA2F 0xA37 0xA3F 0xB27 0xB2F 0xB37 0xB3F
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC27 0xC2F 0xC37 0xC3F 0xCA 0xCAF 0xCB 0xCBF 0xD2 0xD2F 0xD3 0xD3F 0xDA
0xDA
F
0xDB
7
0xDB
F
7
7
7
M28525 -- Not Applicable
M28529
7
7
Bit
Default
Name
Description
7–0
0x0
Tx Test Pattern
If the Test Link Command is set to Active, the Tx Test Pattern is sent in the ICP cell of the
Transmit Test Link. For other links and when the Test Link Command is Inactive, the Tx Test
Pattern in the Transmit ICP cells will automatically be set to 0x00. Range: 0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
215
Mindspeed Proprietary and Confidential
Registers
2.5.17
IMA_TX_ATMn_CELL_COUNT_LSB (Transmit Cell Count LSBs)
This register contains the least significant bits of a 16 bit count of the number of ATM layer cells transmitted over
the Transmit ATM side UTOPIA bus for a particular UTOPIA address. The register is read only.
Tx UTOPIA Address 0 - 15
n=0
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15
0x840 0x842 0x844 0x846 0x940 0x942 0x944 0x946 0xA40 0xA42 0xA44 0xA46 0xB40 0xB42 0xB44 0xB46
M28525
M28529
Tx UTOPIA Address 16–31
n=16 n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31
0xC40 0xC42 0xC44 0xC46 0xCC
0
0xCC
2
0xCC
4
0xCC
6
0xD4
0
0xD4
2
0xD4
4
0xD4
6
0xDC
0
0xDC
2
0xDC
4
0xDC
6
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7-0
0
Transmit Cell Count LSBs
Transmit Cell Count: This field contains the least significant bits of a 16-bit count of the
number of ATM layer cells transmitted over the specific UTOPIA address. A write
operation with data = 0x01 to the first address (0x840 for Address 0, 0x842 for Address
1, etc.) transfers the state of all 16 bits of the counter to registers that are accessible to
the microprocessor bus and clears the state of the counter, The first address should be
read first. The second address (0x841 for Address 0, 0x843 for Address 1, etc.) is read
next. A write operation with data = 0x00 to the first address of each group returns back to
the raw counters.
®
28529-DSH-001-K
Mindspeed Technologies
216
Mindspeed Proprietary and Confidential
Registers
2.5.18
IMA_TX_ATMn_CELL_COUNT_MSB (Transmit Cell Count MSBs)
This register contains the most significant bits of a 16 bit count of the number of ATM layer cells transmitted over
the Transmit ATM side UTOPIA bus for a particular UTOPIA address. The register is read only.
Tx UTOPIA Address 0 - 15
n=0
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15
0x841 0x843 0x845 0x847 0x941 0x943 0x945 0x947 0xA41 0xA43 0xA45 0xA47 0xB41 0xB43 0xB45 0xB47
M28525
M28529
Tx UTOPIA Address 16–31
n=16 n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31
0xC41 0xC43 0xC45 0xC47 0xCC
1
0xCC
3
0xCC
5
0xCC
7
0xD4
1
0xD4
3
0xD4
5
0xD4
7
0xDC
1
0xDC
3
0xDC
5
0xDC
7
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7-0
0
Transmit Cell Count MSBs
Transmit Cell Count: This field contains the most significant bits of a 16 bit count of the
number of ATM layer cells transmitted over the specific UTOPIA address. A write
operation with data = 0x01 to the first address (0x840 for Address 0, 0x842 for Address
1, etc.) transfers the state of all 16 bits of the counter to registers that are accessible to
the microprocessor bus and clears the counter. A read operation should then be
performed to read the previous state of the counter. The first address should be read
first. The second address (0x841 for Address 0, 0x843 for Address 1, etc.) is read next. A
write operation with data = 0x00 to the first address of each group returns back to the
raw counters.
®
28529-DSH-001-K
Mindspeed Technologies
217
Mindspeed Proprietary and Confidential
Registers
2.5.19
IMA_RX_ATMn_CELL_COUNT_LSB (Receive Cell Count LSBs)
This register contains the least significant bits of a 16 bit count of the number of ATM layer cells received over the
Receive ATM side UTOPIA bus for a particular UTOPIA address. The register is read only.
Rx UTOPIA Address 0 - 15
n=0
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15
0x850 0x852 0x854 0x856 0x950 0x952 0x954 0x956 0xA50 0xA52 0xA54 0xA56 0xB50 0xB52 0xB54 0xB56
M28525
M28529
Rx UTOPIA Address 16–31
n=16 n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31
0xC48 0xC4
A
0xC4 0xC4E 0xCC
0xCC
A
0xCC
C
0xCC
E
0xD4
8
0xD4
A
0xD4
C
0xD4
E
0xDC
8
0xDC
A
0xDC
C
0xDC
E
C
8
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7-0
0
Receive Cell Count LSBs
Receive Cell Count: This field contains the least significant bits of a 16 bit count of the
number of ATM layer cells received over the specific UTOPIA address. A write operation
with data = 0x01 to the first address (0x850 for Address 0, 0x852 for Address 1, etc.)
transfers the state of all 16 bits of the counter to registers that are accessible to the
microprocessor bus and clears the counter. A read operation should then be performed to
read the previous state of the counter. The first address should be read first. The second
address (0x851 for Address 0, 0x853 for Address 1, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw counters.
®
28529-DSH-001-K
Mindspeed Technologies
218
Mindspeed Proprietary and Confidential
Registers
2.5.20
IMA_RX_ATMn_CELL_COUNT_MSB (Receive Cell Count MSBs)
This register contains the most significant bits of a 16 bit count of the number of ATM layer cells received over the
Receive ATM side UTOPIA bus for a particular UTOPIA address. The register is read only.
Rx UTOPIA Address 0 - 15
n=0
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15
0x851 0x853 0x855 0x857 0x951 0x953 0x955 0x957 0xA51 0xA53 0xA55 0xA57 0xB51 0xB53 0xB55 0xB57
M28525
M28529
Rx UTOPIA Address 16–31
n=16 n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31
0xC49 0xC4
B
0xC4 0xC4F 0xCC
0xCC
B
0xCC 0xCCF 0xD4
0xD4
B
0xD4 0xD4F 0xDC
0xDC
B
0xDC
D
0xDC
F
D
9
D
9
D
9
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7-0
0
Receive Cell Count MSBs
Receive Cell Count: This field contains the most significant bits of a 16 bit count of the
number of ATM layer cells received over the specific UTOPIA address. A write operation
with data = 0x01 to the first address (0x850 for Address 0, 0x852 for Address 1, etc.)
transfers the state of all 16 bits of the counter to registers that are accessible to the
microprocessor bus and clears the counter. A read operation should then be performed to
read the previous state of the counter. The first address should be read first. The second
address (0x851 for Address 0, 0x853 for Address 1, etc.) is read next. A write operation
with data = 0x00 to the first address of each group returns back to the raw counters.
®
28529-DSH-001-K
Mindspeed Technologies
219
Mindspeed Proprietary and Confidential
Registers
2.5.21
IMA_RX_GRPn_CFG (Receive Group Status and Control)
This register, in conjunction with the IMA_RX_GRPn_CTL and IMA_RX_GRPn_FIRST_PHY_ADDR registers,
controls the operation of the Receive IMA group.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8D
0
0x8D
4
0x8D
8
0x8D
C
0x9D
0
0x9D
4
0x9D
8
0x9D
C
0xAD
0
0xAD
4
0xAD
8
0xAD
C
0xBD
0
0xBD
4
0xBD
8
0xBD
C
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC50 0xC54 0xC58 0xC5
C
0xCD
0
0xCD
4
0xCD
8
0xCD
C
0xD5
0
0xD5
4
0xD5
8
0xD5
C
0xDD
0
0xDD
4
0xDD
8
0xDD
C
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
0
Check Group ID
1 = The receive group ID is compared with the expected Group ID as part of link framing
0 = the receive group ID is ignored
6
0
Acquire Frame Length 1 = The frame length and IMA version acquired from the received link is used as part of link framing
0 = The frame length and IMA version from the received link is compared against the expected
frame length and IMA version as part of link framing
5–4
3–2
0
0
Maximum Differential Reserved. Set to 0.
Delay
Group Symmetry
0 = Symmetrical configuration and operation
1 = Symmetrical configuration and asymmetrical operation
2 = Asymmetrical configuration and operation
3 = Alternate symmetrical configuration and operation
1–0
0
Frame Length (M)
0 = M is 32
1 = M is 64
2 = M is 128
3 = M is 256
®
28529-DSH-001-K
Mindspeed Technologies
220
Mindspeed Proprietary and Confidential
Registers
2.5.22
IMA_RX_GRPn_CTL (Receive Group Control Register)
This register, in conjunction with the IMA_RX_GRPn_CFG and IMA_RX_GRPn_FIRST_PHY_ADDR registers,
controls the operation of the Receive IMA group.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8D
1
0x8D
5
0x8D 0x8DD 0x9D
0x9D
5
0x9D 0x9DD 0xAD
0xAD
5
0xAD
9
0xAD
D
0xBD
1
0xBD
5
0xBD
9
0xBD
D
9
1
9
1
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC5
1
0xC5
5
0xC5
9
0xC5
D
0xCD
1
0xCD
5
0xCD
9
0xCD
D
0xD5
1
0xD5
5
0xD5
9
0xD5
D
0xDD
1
0xDD
5
0xDD
9
0xDD
D
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
0
Group Enable
1 = Group is established and a round-robin is created
0 = Group is not established
6
0
SW Timeout Expired
1 = certain LSM transitions (Usable → Active) are allowed
0 = certain LSM transitions (Usable → Active) are blocked
5
—
—
Reserved. Set to 0.
4–0
0x0
Group Size
Sets the number of configured links within group.
Range: 0x0–0x1F (1–32 links in group)
®
28529-DSH-001-K
Mindspeed Technologies
221
Mindspeed Proprietary and Confidential
Registers
2.5.23
IMA_RX_GRPn_FIRST_PHY_ADDR (Receive First PHY Address)
This register, in conjunction with the IMA_RX_GRPn_CTL and IMA_RX_GRPn_CFG registers, controls the
operation of the Receive IMA group.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8D
2
0x8D 0x8DA 0x8DE 0x9D
0x9D 0x9DA 0x9DE 0xAD
0xAD 0xADA 0xAD
0xBD
2
0xBD 0xBDA 0xBD
6
2
6
2
6
E
6
E
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC5
2
0xC5
6
0xC5 0xC5E 0xCD
0xCD
6
0xCD
A
0xCD
E
0xD5
2
0xD5
6
0xD5 0xD5E 0xDD
0xDD
6
0xDD
A
0xDD
E
A
2
A
2
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
0
Resync Group
1 = Enables the link differential delay synchronization process
0 = Disables the link differential delay synchronization process
6
0
Drain Buffer
This bit is used by the software driver to reset the differential delay in T1/E1 mode:
1 = Allows the differential delay buffer to drain excess cell buffering.
0 = Normal delay buffering.
5
0
Rx IMA Version
IMA OAM Label value
1 = IMA v1.1
0 = IMA v1.0
4–0
0x00
Link PHY Address
This field contains the PHY port address of the Receive link with the lowest LID in the group.
M28525: Range: 0–0xF
M28529: Range: 0–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
222
Mindspeed Proprietary and Confidential
Registers
2.5.24
IMA_RX_GRPn_ID (Expected Receive Group ID)
This register contains the value of the Expected IMA Group ID field for the received ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8D
3
0x8D 0x8DB 0x8DF 0x9D
0x9D 0x9DB 0x9DF 0xAD
0xAD
7
0xAD
B
0xAD
F
0xBD
3
0xBD
7
0xBD
B
0xBD
F
7
3
7
3
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC5
3
0xC5
7
0xC5 0xC5F 0xCD
0xCD
7
0xCD 0xCDF 0xD5
0xD5
7
0xD5 0xD5F 0xDD
0xDD
7
0xDD 0xDDF
B
B
3
B
3
B
3
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–0
0x00
Expected Rx Group ID This field contains the Group ID expected in the Receive ICP cells of all links in this group. Range:
0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
223
Mindspeed Proprietary and Confidential
Registers
2.5.25
IMA_RX_GRPn_RX_TEST_PATTERN (Receive Group Rx Test Pattern)
This read-only register contains the value of the Rx Test Pattern field acquired from the received ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E0 0x8E8 0x8F0 0x8F8 0x9E0 0x9E8 0x9F0 0x9F8 0xAE0 0xAE8 0xAF0 0xAF8 0xBE0 0xBE8 0xBF0 0xBF8
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6
0
0xC6
8
0xC7 0xC78 0xCE0 0xCE8 0xCF0 0xCF8 0xD6
0xD6 0xD70 0xD78 0xDE0 0xDE8 0xDF0 0xDF8
8
0
0
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–0
—
Rx Test Pattern
This field reflects the value of the Rx Test Pattern byte acquired from the Receive side test link.
Range: 0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
224
Mindspeed Proprietary and Confidential
Registers
2.5.26
IMA_RX_GRPn_STAT_CTL_CHANGE (Receive Group Status & Control
Change Indication)
This read-only register contains the value of the Status and Control Indication field acquired from the received ICP
cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E2 0x8EA
0x8F
2
0x8FA 0x9E2 0x9EA
0x9F
2
0x9FA
0xAE
2
0xAEA 0xAF 0xAFA 0xBE
0xBEA 0xBF 0xBFA
2
2
2
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6
2
0xC6
A
0xC7 0xC7A 0xCE2 0xCEA 0xCF2 0xCFA 0xD6
0xD6 0xD72 0xD7 0xDE2 0xDE 0xDF2 0xDFA
2
2
A
A
A
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–0
—
Rx SCCI
This field reflects the value of the Status & Change Control Indication byte acquired from the
Receive ICP cells of the monitored link. Range: 0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
225
Mindspeed Proprietary and Confidential
Registers
2.5.27
IMA_RX_GRPn_ACTUAL_GRP_ID (Actual Receive Group ID)
This read-only register contains the value of the IMA ID field acquired from the received ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E3 0x8EB
0x8F
3
0x8FB 0x9E3 0x9EB 0x9F
3
0x9FB 0xAE3 0xAEB 0xAF 0xAFB 0xBE3 0xBEB 0xBF 0xBFB
3
3
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6
3
0xC6
B
0xC7 0xC7B 0xCE3 0xCEB 0xCF3 0xCFB 0xD6
0xD6 0xD73 0xD7 0xDE3 0xDE 0xDF3 0xDFB
3
3
B
B
B
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–0
—
Actual Rx Group ID
This field contains the Group ID acquired from the Receive ICP cells of the monitored link. Range:
0x00–0xFF
®
28529-DSH-001-K
Mindspeed Technologies
226
Mindspeed Proprietary and Confidential
Registers
2.5.28
IMA_RX_GRPn_STAT_CTL (Receive Group Status and Control)
This read-only register contains the value of the Group Status and Control field acquired from the received ICP
cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E4 0x8EC
0x8F
4
0x8FC 0x9E4 0x9EC 0x9F
4
0x9FC 0xAE4 0xAEC 0xAF 0xAFC 0xBE4 0xBEC 0xBF 0xBFC
4
4
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6
4
0xC6
C
0xC7 0xC7C 0xCE4 0xCEC 0xCF4 0xCFC 0xD6
0xD6 0xD74 0xD7 0xDE4 0xDE 0xDF4 0xDFC
4
4
C
C
C
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7–4
—
Group State
0 = Start-up
1 = Start-up-Ack
2 = Config-Abort–Unsupported M
3 = Config-Abort–Incompatible Symmetry
4 = Config-Abort–Unsupported IMA Version
5–7 = Reserved for other Config-Abort states
8 = Insufficient Links
9 = Blocked
0xA = Operational
0xB–F = reserved
3–2
1–0
—
—
Group Symmetry
Frame Length (M)
0 = Symmetrical configuration and operation
1 = Symmetrical configuration and asymmetrical operation
2 = Asymmetrical configuration and operation
0 = M is 32
1 = M is 64
2 = M is 128
3 = M is 256
®
28529-DSH-001-K
Mindspeed Technologies
227
Mindspeed Proprietary and Confidential
Registers
2.5.29
IMA_RX_GRPn_TIMING_INFO (Receive Timing Information)
This read-only register contains the value of the Transmit Timing Information field acquired from the received ICP
cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E5 0x8ED
0x8F 0x8FD 0x9E5 0x9ED
5
0x9F 0x9FD 0xAE 0xAED 0xAF 0xAFD 0xBE 0xBED 0xBF 0xBFD
5
5
5
5
5
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6
5
0xC6
D
0xC7
5
0xC7 0xCE5 0xCE
0xCF5 0xCFD 0xD6
5
0xD6
D
0xD7
5
0xD7
D
0xDE
5
0xDE 0xDF5 0xDFD
D
D
D
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
6
5
—
—
—
—
—
Unused
Unused
Rx Clock Mode
0 = Independent Transmit Clock (ITC)
1 = Common Transmit Clock (CTC)
4–0
—
Timing Reference Link This field contains the LID of the Receive TRL. Range: 0x0–0x1F
ID
®
28529-DSH-001-K
Mindspeed Technologies
228
Mindspeed Proprietary and Confidential
Registers
2.5.30
IMA_RX_GRPn_TEST_CTL (Receive Test Control)
This read-only register contains the value of the Tx Test Control field acquired from the received ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E6 0x8EE 0x8F6 0x8FE 0x9E6 0x9EE 0x9F6 0x9FE 0xAE6 0xAEE
0xAF 0xAFE 0xBE6 0xBEE 0xBF 0xBFE
6
6
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6 0xC6E 0xC7 0xC7E 0xCE6 0xCEE 0xCF6 0xCFE 0xD6
0xD6
E
0xD7
6
0xD7
E
0xDE
6
0xDE 0xDF6 0xDFE
E
6
6
6
M28525 -- Not Applicable
M28529
Bit
Default
Name
Description
7
6
5
—
—
—
—
—
Unused
Unused
Test Link Command
0 = Inactive
1 = Active
4–0
—
Test Link ID
This field contains the LID of the Receive Test Link. Range: 0x0–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
229
Mindspeed Proprietary and Confidential
Registers
2.5.31
IMA_RX_GRPn_TX_TEST_PATTERN (Receive Group Tx Test Pattern)
This read-only register contains the value of the Tx Test Pattern field acquired from the received ICP cells.
Group 1–16 Address
n=1
n=2
n=3
n=4
n=5
n=6
n=7
n=8
n=9
n=10 n=11 n=12 n=13 n=14 n=15 n=16
0x8E7 0x8EF 0x8F7 0x8FF 0x9E7 0x9EF 0x9F7 0x9FF 0xAE7 0xAEF 0xAF7 0xAFF 0xBE7 0xBEF 0xBF7 0xBFF
M28525
M28529
Group 17–32 Address
n=17 n=18 n=19 n=20 n=21 n=22 n=23 n=24 n=25 n=26 n=27 n=28 n=29 n=30 n=31 n=32
0xC6 0xC6F 0xC7 0xC7F 0xCE7 0xCEF 0xCF7 0xCFF 0xD6 0xD6F 0xD7 0xD7F 0xDE 0xDEF 0xDF7 0xDFF
7
7
7
M28525 -- Not Applicable
M28529
7
7
Bit
Default
Name
Description
7–0
—
Tx Test Pattern
If the Test Link Command is set to Active, the Tx Test Pattern is accessed from the ICP cell of the
Transmit Test Link. This register should be read multiple times (debounced) to ensure receipt of a
valid test pattern. Range: 0x00–0xFF
2.6
IMA Link Registers
The IMA Link layer contains configuration and status information that is associated with IMA groups or pass-
through facilities.
2.6.1
0x81E—IMA_LNK_SEM (Link Table Control Register)
For the following bits, 1 = the link table is being updated, 0 = the link table is not being updated. The update enable
must be set to 1 prior to writing the link table. All elements of the link table must be re-written. After writing to all 8
elements, the update enable is reset to 0. The link tables are described below.
This register cannot be read back.
NOTE:
Bit
Default
Name
Description
7
0
Update Enable for Receive
addresses 0xB80–0xB87, 0xBA8–0xBAF
facilities 24–31
(Not defined for M28525)
6
0
Update Enable for Receive
facilities 16–23
addresses 0xA80–0xA87, 0xAA8–0xAAF
(Not defined for M28525)
®
28529-DSH-001-K
Mindspeed Technologies
230
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description
5
0
Update Enable for Receive
facilities 8–15
addresses 0x980–0x987, 0x9A8–0x9AF
(Not defined for M28525)
4
3
2
1
0
0
0
0
0
0
Update Enable for Receive
facilities 0–7
addresses 0x880–0x887, 0x8A8–0x8AF
(Not defined for M28525)
Update Enable for Transmit
facilities 24–31
addresses 0xB60–0xB67, 0xB70–0xB77
(Not defined for M28525)
Update Enable for Transmit
facilities 16–23
addresses 0xA60–0xA67, 0xA70–0xA77
(Not defined for M28525)
Update Enable for Transmit
facilities 8–15
addresses 0x960–0x967, 0x970–0x977
(Not defined for M28525)
Update Enable for Transmit
facilities 0–7
addresses 0x860–0x867, 0x870–0x877
®
28529-DSH-001-K
Mindspeed Technologies
231
Mindspeed Proprietary and Confidential
Registers
2.6.2
IMA_TX_LNKn_CTL (Transmit Link Control Register)
This register, in conjunction with IMA_TX_LNKn_ID register, configures the IMA link attributes for the Transmit port.
Hex Address
n
Address
n
Address
0
1
0x860
0x861
0x862
0x863
0x864
0x865
0x866
0x867
0x960
0x961
0x962
0x963
0x964
0x965
0x966
0x967
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA60
0xA61
0xA62
0xA63
0xA64
0xA65
0xA66
0xA67
0xB60
0xB61
0xB62
0xB63
0xB64
0xB65
0xB66
0xB67
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7
0
0
0
0
Link Assigned
1 = Facility is part of IMA Group
0 = Facility is a bypass channel (pass-through or unassigned)
6
5
Link Inhibit
Link Fault
1 = Link is blocked from use
0 = Link is not inhibited
1 = Link Fault Failure is active
0 = Link Fault Failure is inactive
4–0
Next Link PHY Address This field contains the PHY address of the next link in the IMA Group. If the link is a pass-
through facility, this field is ignored but is recommended to be set to the PHY address of the
pass-through facility (i.e., set to 0 for PHY address 0, set to 1 for PHY address 1, etc.).
M28525: Range: 0–0x0F
M28529: Range: 0–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
232
Mindspeed Proprietary and Confidential
Registers
2.6.3
IMA_TX_LNKn_STATE (Transmit Link Status Register)
This read-only register provides state and status information for the Transmit link.
Hex Address
n
Address
n
Address
0
1
0x868
0x869
0x86A
0x86B
0x86C
0x86D
0x86E
0x86F
0x968
0x969
0x96A
0x96B
0x96C
0x96D
0x96E
0x96F
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA68
0xA69
0xA6A
0xA6B
0xA6C
0xA6D
0xA6E
0xA6F
0xB68
0xB69
0xB6A
0xB6B
0xB6C
0xB6D
0xB6E
0xB6F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7–6
—
Tx-Stuff-IMA Counter
This field contains a count of the number of Near-End Transmit cell stuffing events. Upon a read
of this address, the contents of the counter is transferred to a register that is accessible to the
microprocessor bus and the counter is cleared.
5
4
3
—
—
—
—
—
Reserved.
Reserved.
Waiting for SW Timer
1 = a transition of the Transmit LSM is waiting for an enable from software
0 = no transition of the LSM is waiting for software
2–0
—
NE Tx LSM State
0 = Not In Group
1 = Unusable—no reason given
2 = Unusable—Fault
3 = Unusable—Mis-connected
4 = Unusable—Blocked
5 = Unusable—Failed
6 = Usable
7 = Active
®
28529-DSH-001-K
Mindspeed Technologies
233
Mindspeed Proprietary and Confidential
Registers
2.6.4
IMA_TX_LNKn_ID (Transmit Link ID Register)
This register, in conjunction with IMA_TX_LNKn_CTL register, configures the IMA link attributes for the Transmit
port.
Hex Address
n
Address
n
Address
0
1
0x870
0x871
0x872
0x873
0x874
0x875
0x876
0x877
0x970
0x971
0x972
0x973
0x974
0x975
0x976
0x977
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA70
0xA71
0xA72
0xA73
0xA74
0xA75
0xA76
0xA77
0xB70
0xB71
0xB72
0xB73
0xB74
0xB75
0xB76
0xB77
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7
6
5
—
—
0
—
—
Reserved. Set to 0
Reserved. Set to 0
Link Misconnect
1 = Link Misconnect Failure is active
0 = Link Misconnect Failure is inactive
4–0
0x00
Link ID
This field contains the Transmit Link ID assigned to this facility.
Range: 0x00–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
234
Mindspeed Proprietary and Confidential
Registers
2.6.5
IMA_RX_LNKn_CTL (Receive Link Control Register)
This register, in conjunction with IMA_RX_LNKn_ID register, configures the IMA link attributes for the Receive port.
Hex Address
n
Address
n
Address
0
1
0x880
0x881
0x882
0x883
0x884
0x885
0x886
0x887
0x980
0x981
0x982
0x983
0x984
0x985
0x986
0x987
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA80
0xA81
0xA82
0xA83
0xA84
0xA85
0xA86
0xA87
0xB80
0xB81
0xB82
0xB83
0xB84
0xB85
0xB86
0xB87
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7
0
Link Assigned
1 = Facility is part of IMA Group
0 = Facility is a bypass channel (pass-through or unassigned)
6–5
4–0
0
Link State
0 = Link is not inhibited
1 = Link Fault Failure is active
2 = Link is blocked from use
3 = Rx Failed condition
0
Next Link PHY Address This field contains the PHY address of the next link in the IMA Group. If the link is a pass-
through facility, this field is ignored but is recommended to be set to the PHY address of the
pass-through facility (i.e., set to 0 for PHY address 0, set to 1 for PHY address 1, etc.).
M28525: Range: 0–F
M28529: Range: 0–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
235
Mindspeed Proprietary and Confidential
Registers
2.6.6
IMA_RX_LNKn_STATE (Receive Link Status Register)
This read-only register provides state and status information for the Receive link.
Hex Address
n
Address
n
Address
0
1
0x888
0x889
0x88A
0x88B
0x88C
0x88D
0x88E
0x88F
0x988
0x989
0x98A
0x98B
0x98C
0x98D
0x98E
0x98F
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA88
0xA89
0xA8A
0xA8B
0xA8C
0xA8D
0xA8E
0xA8F
0xB88
0xB89
0xB8A
0xB8B
0xB8C
0xB8D
0xB8E
0xB8F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7–6
—
Rx-Stuff-IMA Counter
This field contains a count of the number of Near-End Receive cell stuffing events. Upon a read
of this address, the contents of the counter is transferred to a register that is accessible to the
microprocessor bus and the counter is cleared.
5
4
3
—
—
—
—
—
Reserved.
Reserved.
Waiting for SW Timer
1 = a transition of the Receive LSM is waiting for an enable from software
0 = no transition of the LSM is waiting for software
2–0
—
NE Rx LSM State
0 = Not In Group
1 = Unusable—no reason given
2 = Unusable—Fault
3 = Unusable—Mis-connected
4 = Unusable—Blocked
5 = Unusable—Failed
6 = Usable
7 = Active
®
28529-DSH-001-K
Mindspeed Technologies
236
Mindspeed Proprietary and Confidential
Registers
2.6.7
IMA_RX_LNKn_DEFECT (Receive Link Defects Register)
This register provides state and status information for the Receive link. This register is primarily read-only except
for bit 1 which is read/write.
Hex Address
n
Address
n
Address
0
1
0x890
0x891
0x892
0x893
0x894
0x895
0x896
0x897
0x990
0x991
0x992
0x993
0x994
0x995
0x996
0x997
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA90
0xA91
0xA92
0xA93
0xA94
0xA95
0xA96
0xA97
0xB90
0xB91
0xB92
0xB93
0xB94
0xB95
0xB96
0xB97
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7
—
—
—
—
—
—
0
∆ (LIF Defect)
1 = The LIF defect has changed state since the last time this register was read
0 = The LIF defect has not changed state
6
5
4
3
2
1
0
LIF Defect
1 = The LIF defect is currently active
0 = The LIF defect is inactive
∆ (LODS Defect)
LODS Defect
∆ (RDI Defect)
RDI Defect
1 = The LODS defect has changed state since the last time this register was read
0 = The LODS defect has not changed state
1 = The LODS defect is currently active
0 = The LODS defect is inactive
1 = The RDI defect has changed state since the last time this register was read
0 = The RDI defect has not changed state
1 = The RDI defect is currently active
0 = The RDI defect is inactive
PHY Defect
1 = A PHY defect is active
0 = All PHY defects are inactive
—
Rx_TRL Error
This bit is set high if the transition detector for the Rx_TRL input detects a bad signal. This bit is
active high and is reset upon reading this address.
®
28529-DSH-001-K
Mindspeed Technologies
237
Mindspeed Proprietary and Confidential
Registers
2.6.8
IMA_FE_TX_LNKn_CFG (FE Transmit Configuration Register)
This read-only register provides Far-End Transmit configuration information for the Receive link.
Hex Address
n
Address
n
Address
0
1
0x898
0x899
0x89A
0x89B
0x89C
0x89D
0x89E
0x89F
0x998
0x999
0x99A
0x99B
0x99C
0x99D
0x99E
0x99F
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xA98
0xA99
0xA9A
0xA9B
0xA9C
0xA9D
0xA9E
0xA9F
0xB98
0xB99
0xB9A
0xB9B
0xB9C
0xB9D
0xB9E
0xB9F
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7–6
—
Frame Length (M)
This field contains the contents of the frame length field for the ICP cell arriving on this facility.
0 = M is 32
1 = M is 64
2 = M is 128
3 = M is 256
5
—
—
IMA Version
Link ID
(IMA OAM Label value)
1 = IMA v1.1
0 = IMA v1.0
4–0
This field contains the contents of the Link ID field for the ICP cell arriving on this facility. Range:
0x0–0x1F.
The value in this register is undefined when there is no valid IMA cell stream present on the
link. The value in this register is also undefined for a maximum of two seconds following
the creation of a group containing this link.
NOTE:
®
28529-DSH-001-K
Mindspeed Technologies
238
Mindspeed Proprietary and Confidential
Registers
2.6.9
IMA_FE_LNKn_STATE (FE Link Status Register)
This read-only register provides Far-End link status information for the facility.
Hex Address
n
Address
n
Address
0
1
0x8A0
0x8A1
0x8A2
0x8A3
0x8A4
0x8A5
0x8A6
0x8A7
0x9A0
0x9A1
0x9A2
0x9A3
0x9A4
0x9A5
0x9A6
0x9A7
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xAA0
0xAA1
0xAA2
0xAA3
0xAA4
0xAA5
0xAA6
0xAA7
0xBA0
0xBA1
0xBA2
0xBA3
0xBA4
0xBA5
0xBA6
0xBA7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7–5
—
FE Tx LSM State
0 = Not In Group
1 = Unusable—No reason given
2 = Unusable—Fault
3 = Unusable—Mis-connected
4 = Unusable—Blocked
5 = Unusable—Failed
6 = Usable
7 = Active
4–2
—
FE Rx LSM State
0 = Not In Group
1 = Unusable—No reason given
2 = Unusable—Fault
3 = Unusable—Mis-connected
4 = Unusable—Blocked
5 = Unusable—Failed
6 = Usable
7 = Active
®
28529-DSH-001-K
Mindspeed Technologies
239
Mindspeed Proprietary and Confidential
Registers
Bit
Default
Name
Description (Continued)
1–0
—
FE Rx Defect Indicator
0 = No Defects
1 = Physical link defect
2 = LIF defect
3 = LODS defect
2.6.10
IMA_RX_LNKn_ID (Receive Link ID Register)
This register, in conjunction with IMA_RX_LNKn_CTL register, configures the IMA link attributes for the Receive
port.
Hex Address
n
Address
n
Address
0
1
0x8A8
0x8A9
0x8AA
0x8AB
0x8AC
0x8AD
0x8AE
0x8AF
0x9A8
0x9A9
0x9AA
0x9AB
0x9AC
0x9AD
0x9AE
0x9AF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xAA8
0xAA9
0xAAA
0xAAB
0xAAC
0xAAD
0xAAE
0xAAF
0xBA8
0xBA9
0xBAA
0xBAB
0xBAC
0xBAD
0xBAE
0xBAF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7
6
5
—
—
0
—
—
Reserved. Set to 0
Reserved. Set to 0
Link Misconnect
1 = Link Misconnect Failure is active
0 = Link Misconnect Failure is inactive
4–0
0
Link ID
This field contains the Receive Link ID assigned to this facility.
Range: 0x00–0x1F
®
28529-DSH-001-K
Mindspeed Technologies
240
Mindspeed Proprietary and Confidential
Registers
2.6.11
IMA_RX_LNKn_IV_CNT (IMA Violation Counter Register)
This read-only register contains a count of the IV-IMA Anomalies for the Receive link.
Hex Address
n
Address
n
Address
0
1
0x8B0
0x8B1
0x8B2
0x8B3
0x8B4
0x8B5
0x8B6
0x8B7
0x9B0
0x9B1
0x9B2
0x9B3
0x9B4
0x9B5
0x9B6
0x9B7
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xAB0
0xAB1
0xAB2
0xAB3
0xAB4
0xAB5
0xAB6
0xAB7
0xBB0
0xBB1
0xBB2
0xBB3
0xBB4
0xBB5
0xBB6
0xBB7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7–0
—
IV-IMA Counter
This field contains a count of the ICP-ERR, ICP-INV, and ICP-MIS anomalies. Writing a 0x01 to
address 0x8B0 will freeze the value of all the IV-IMA and OIF-IMA counters in the defined
registers. The internal counters are cleared by this action. After all the registers have been read,
writing a 0x00 to address 0x8B0 will release the “freeze” and the defined registers will reflect the
current anomaly count.
®
28529-DSH-001-K
Mindspeed Technologies
241
Mindspeed Proprietary and Confidential
Registers
2.6.12
IMA_RX_LNKn_OIF_CNT (Out-of-IMA Frame Counter Register)
This read-only register contains a count of the OIF-IMA Anomalies for the Receive link.
Hex Address
n
Address
n
Address
0
1
0x8B8
0x8B9
0x8BA
0x8BB
0x8BC
0x8BD
0x8BE
0x8BF
0x9B8
0x9B9
0x9BA
0x9BB
0x9BC
0x9BD
0x9BE
0x9BF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xAB8
0xAB9
0xABA
0xABB
0xABC
0xABD
0xABE
0xABF
0xBB8
0xBB9
0xBBA
0xBBB
0xBBC
0xBBD
0xBBE
0xBBF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7
6
—
—
—
—
—
—
Reserved.
Reserved.
Reserved.
Reserved.
—
5
—
—
4
3–0
OIF-IMA Counter
This field contains a count of the OIF anomalies. Writing a 0x01 to address 0x8B0 will freeze the
value of all the IV-IMA and OIF-IMA counters in the defined registers. The internal counters are
cleared by this action. After all the registers have been read, writing a 0x00 to address 0x8B0 will
release the “freeze” and the defined registers will reflect the current anomaly count.
®
28529-DSH-001-K
Mindspeed Technologies
242
Mindspeed Proprietary and Confidential
Registers
2.6.13
IMA_FE_TX_LNKn_GRP_ID (FE Transmit Group ID Register)
This read-only register contains the value of the IMA ID field acquired from the received ICP for the Receive link.
Hex Address
n
Address
n
Address
0
1
0x8C0
0x8C1
0x8C2
0x8C3
0x8C4
0x8C5
0x8C6
0x8C7
0x9C0
0x9C1
0x9C2
0x9C3
0x9C4
0x9C5
0x9C6
0x9C7
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xAC0
0xAC1
0xAC2
0xAC3
0xAC4
0xAC5
0xAC6
0xAC7
0xBC0
0xBC1
0xBC2
0xBC3
0xBC4
0xBC5
0xBC6
0xBC7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Default
Name
Description
7–0
—
Actual Rx Group ID
This field contains the value of the Group ID field from the ICP cells for this facility. Range:
0x00–0xFF
The value in this register is undefined when there is no valid IMA cell stream present on the
link. The value in this register is also undefined for a maximum of two seconds following
the creation of a group containing this link.
NOTE:
®
28529-DSH-001-K
Mindspeed Technologies
243
Mindspeed Proprietary and Confidential
Registers
2.7
ATM Cell Capture Registers
The ATM Cell Capture registers allow an ATM cell to be captured from a facility for diagnostic purposes.
When a facility is configured to be part of an IMA Group, a valid cell stream must be present
on the input port or the values contained in these registers are undefined. The values in
these registers are also undefined for a maximum of two seconds following the creation of
a group containing the specified facility in 0xE30. If the facility is configured for
passthrough mode, the above restrictions do not apply.
NOTE:
2.7.1
0xE00-0xE2F—CELL_CAP_PAYLDn (Capture Payload Contents Register)
These registers hold the 48 byte payload contents of a captured ATM Cell. These registers are read-only.
Bit
Default
Name
Description
7-0
0
ATMPLDn
Contains one byte of the 48 byte payload contents of a captured ATM Cell. The first byte is stored
in register 0xE00 and the remainder of the 48 bytes are stored consecutively in registers up to
location 0xE2F.
2.7.2
0xE30—CAP_FAC (Capture Facility Register)
The capture facility register configures the facility that the ATM cells will be captured from.
Bit
Default
Name
Description
7-5
4-0
—
0
—
Reserved
This field is programmed with the facility that ATM cells will be captured from.
CAPFCL
2.7.3
0xE31—CAP_CNTL (Capture Control Register)
The capture control register enables the capture circuit to store an incoming ATM cell as well as determine the type
of ATM cell stored
Bit
Default
Name
Description
7-2
1
—
0
—
Reserved
CAPTYPE
This bit selects whether the next incoming ICP cell is stored or simply the next ATM cell,
regardless of type, is stored.
0 = ICP Cell only
1 = Any cell (Data Cell, Filler Cell, or ICP/SICP Cell)
0
0
ENCAP
Enables the capture circuit to store the next incoming cell qualified by the cell type programmed
in bit 1.
This bit is written to a ‘1’ to arm the capture circuit to store the ATM cell.
This bit is should be written to a ‘0’ once the ATM cell is captured. See register 0xE32 for the
capture status.
®
28529-DSH-001-K
Mindspeed Technologies
244
Mindspeed Proprietary and Confidential
Registers
2.7.4
0xE32—CAP_STAT (Capture Status Register)
The capture status register indicates the status of the ATM cell capture.
Bit
Default
Name
Description
7-1
0
—
Reserved
0
CELLCAP
This bit shows whether an ATM cell has been captured. This status bit is only valid when the
Capture Control bit is enabled.
1 = Cell has been stored
0 = Cell has not been stored
®
28529-DSH-001-K
Mindspeed Technologies
245
Mindspeed Proprietary and Confidential
3.0 Product Specification
3.1
Absolute Maximum Ratings
The absolute maximum ratings in Table 3-1 indicate the maximum stresses that the M2852x can tolerate without
risking permanent damage. These ratings are not typical of normal operation of the device. Exposure to absolute
maximum rating conditions for extended periods of time may affect the device’s reliability. This device should be
handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than
+0.5 V can induce destructive latchup.
Table 3-1.
Absolute Maximum Ratings (General)
Parameter
Value
Supply Voltage - VDD33
Supply Voltage - VDD18
ESD Voltage (VGG)
–0.5 to +3.6 V
–0.5 to +1.98 V
–0.5 to +5.5 V
–0.5 to (VDD33 + 1.89V)
–40 °C to 125 °C
–40 °C to 85 °C
+240 °C for 10 seconds
+125 °C
Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature
Junction Temperature
Static Discharge Voltage (Human Body Model)
Static Discharge Voltage (Charge Device Model)
Latch-up Current
±2000 V
±350 V
±150 mA at 85 °C
±20 mA
DC Input Current
NOTE:
Please refer to Mindspeed SMT application note for the Pb-free devices and for the detail explination of how JEDEC determines the reflow
temperatures based on package thickness:
http://mindspeed.com/mspd/support/quality/SMT-PB-free.pdf
Table 3-2.
Absolute Maximum Ratings (M28525/M28529)
Parameter
Value
θ
No Airflow
~20°C/W
JA
®
28529-DSH-001-K
Mindspeed Technologies
246
Mindspeed Proprietary and Confidential
Product Specification
3.2
Recommended Operating Conditions
Table 3-3.
Recommended Operating Conditions
Symbol
Parameter
Minimum
Nominal
Maximum
Units
VDD33
VDD18
Tamb
3.3V Power supply
3.135
1.71
-40
3.3
1.8
25
3.465
1.89
85
V
V
1.8V Power supply
Ambient operating temperature
°C
3.3
DC Characteristics
Table 3-4 lists the DC characteristics of the M2852x. Table 3-5 lists Power Characteristics of the device.
Table 3-4.
DC Characteristics
Parameter
Minimum
Typical
Maximum
Comments
Power Supply VDD33
3.0
1.71
3.0
0
3.3
1.8
3.6
1.89
5.5
VDC ±10%
VDC ±5%
VDC
Power Supply VDD18
(1,2)
(3)
ESD Voltage VGG (3.3 V or 5 V)
Input Low Voltage (VIL)—TTL
Input High Voltage (VIH)—TTL
Output Voltage Low (TTL)
3.3/5
—
—
—
0.8
VDC
2.0
—
5.25
0.4
VDC
Volts;
I
= 4.0 mA
OH
Output Voltage High (TTL)
2.4
—
—
Volts;
= 1500 µA
I
OH
Input Leakage Current
–10
–10
—
—
—
—
—
—
10
10
7
µA; Vin = PWR or GND
Three-state Output Leakage Current
Input Capacitance
µA; Vout = PWR or GND
pF
pF
pF
Output Capacitance
—
7
Bidirectional Capacitance
—
7
Footnote:
(1) With 5 V logic input, VGG should be tied to 5 V. With 3.3 V logic input, VGG should be tied to 3.3 V. VGG must be equal or greater than
power supply voltage.
(2) When VGG is operated at 5 V, sequence VGG to VDD33 as discussed in Chapter 4.0.
(3) Typical value for VGG is 3.3 or 5 V.
®
28529-DSH-001-K
Mindspeed Technologies
247
Mindspeed Proprietary and Confidential
Product Specification
Table 3-5.
Power Characteristics (M28529)
Conditions Parameter
Minimum
Typical
Maximum
Comments
E1
VDD33
—
—
100
290
—
—
mW
mW
Utopia-Serial
VDD18
IMA_SysClk = 49.152MHz
IMA_RefClk = 49.152MHz
MicroClk = 25MHz
8 IMA Groups with 4 Links each
T1
VDD33
VDD18
—
—
100
240
—
—
mW
mW
Utopia-Serial
IMA_SysClk = 37.056MHz
IMA_RefClk = 49.152MHz
MicroClk = 25MHz
8 IMA Groups with 4 Links each
Interleaved Highway
Utopia-Serial
IMA_SysClk = 49.152MHz
IMA_RefClk = 49.152MHz
MicroClk = 25MHz
VDD33
VDD18
—
—
100
355
—
—
mW
mW
8 IMA Groups with 4 Links each
E1
VDD33
VDD18
—
—
200
260
—
—
mW
mW
Utopia-Utopia
IMA_SysClk = 49.152MHz
IMA_RefClk = 49.152MHz
MicroClk = 25MHz
8 IMA Groups with 4 Links each
DSL 2.304Mbs
Utopia-Utopia
IMA_SysClk = 66MHz
IMA_RefClk = 49.152MHz
MicroClk = 66MHz
VDD33
VDD18
—
—
235
410
—
—
mW
mW
8 IMA Groups with 4 Links each
DSL 5.4Mbs
Utopia-Utopia
IMA_SysClk = 66MHz
IMA_RefClk = 49.152MHz
MicroClk = 66MHz
VDD33
VDD18
—
—
300
425
—
—
mW
mW
8 IMA Groups with 4 Links each
®
28529-DSH-001-K
Mindspeed Technologies
248
Mindspeed Proprietary and Confidential
Product Specification
3.4
Timing Specifications
This section provides timing diagrams and descriptions for the various interfaces of the M2852x. The timing
relationship labels are numbered when they occur more than once in a diagram, so each label is unique. This
numbering aids in identifying the appropriate label in the timing table. Signals are measured at the 50% point of the
changing edge, except for those involving high impedance transitions, which are measured at 10% and 90%.
Figure 3-1 and Figure 3-2 illustrate how input and output waveforms are defined.
Figure 3-1. Input Waveform
2.0 V
1.4 V
0.8 V
t
per
Figure 3-2. Output Waveform
2.4 V
1.4 V
0.4 V
t
t
pwh
pwl
t
per
®
28529-DSH-001-K
Mindspeed Technologies
249
Mindspeed Proprietary and Confidential
Product Specification
3.4.1
Reset Timing
Figure 3-3 and Table 3-6 show the timing requirements for the asynchronous reset input to the device.
Figure 3-3. Reset Timing
tw
Reset*
Table 3-6.
Reset Timing Parameters
Parameter
Symbol
Minimum
Typical
Maximum
Units
t
Reset minimum pulse width
100
ns
w
3.4.2
Microprocessor Timing
Figures 3-4 through 3-7 and Tables 3-7 through 3-10 show the timing requirements and characteristics of the
microprocessor interface. Capacitive load on all signals is 50pF.
Figure 3-4. Microprocessor Timing —Asynchronous Read
MicroAddr[11:0]
tpwl
tpwh
ts
th
MCS*
MRd*
tpwl
ts
th
ten
tpd
tdis
MicroData[7:0]
tenzl
tdislz
MRdy
MWr*
(High)
(Low)
MSyncMode
®
28529-DSH-001-K
Mindspeed Technologies
250
Mindspeed Proprietary and Confidential
Product Specification
Table 3-7.
Microprocessor Timing Parameters - Asynchronous Read
Description Minium
Label
Maximum
Units
(1)
t
Microprocessor Clock
Pulse Width High
Pulse Width Low
15
ns
ns
ns
ns
ns
ns
ns
per
t
4 * t
4 * t
2
—
—
—
—
10
pwh
per
per
t
pwl
(2)
t
Setup, MicroAddr[11:0] to the falling edge of (MCS* + MRd*)
s
(3)
t
Hold, MicroAddr[11:0] from the rising edge of (MCS* + MRd*)
7
h
(2)
t
Enable, MicroData[7:0] from the falling edge of (MCS* + MRd*)
4
en
pd
t
Propagation Delay, MicroData[7:0] from the falling edge of (MCS* +
2 *t
3 * t +10
per
per
(2)
MRd*)
(3)
t
Disable, MicroData[7:0] from the rising edge of (MCS* + MRd*)
4
4
10
10
ns
ns
ns
dis
(2)
t
Enable, MRdy from the falling edge of (MCS* + MRd*)
enzl
(2)
t
Disable, MRdy from the falling edge of (MCS* + MRd*)
3 * t
4 * t +10
per
dislz
per
Footnote:
(1) The microprocessor clock is required by internal logic but has no relationship with the I/O signals.
(2) Timing starts from whichever is asserted last.
(3) Timing relative to whichever goes inactive first.
(4) Timing relative to a 50pF load.
Figure 3-5. Microprocessor Timing —Asynchronous Write
MicroAddr[11:0]
MicroData[7:0]
ts2
th1
th2
tpwl
tpwh
ts1
MCS*
th1
th2
tpwl
ts1
tpwh
MWr*
tenzl
tdislz
MRdy
MRd*
(High)
(Low)
MSyncMode
®
28529-DSH-001-K
Mindspeed Technologies
251
Mindspeed Proprietary and Confidential
Product Specification
Table 3-8.
Microprocessor Timing Parameters - Asynchronous Write
Description Minimum
Label
Maximum
Units
(1)
t
Microprocessor Clock
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
per
pwl
t
Pulse Width Low (MCS* + MWr*)
4 * t
4 * t
2
—
—
—
—
per
per
t
Pulse Width High (MCS* + MWr*)
pwh
(2)
t
Setup, MicroAddr[11:0] to the falling edge of (MCS* + MWr*)
s1
h1
(3)
(2)
t
Hold, MicroAddr[11:0] from the rising edge of (MCS* + MWr*)
Setup, MicroData[7:0] from the falling edge of (MCS* + MWr*)
7
t
—
7
t
per
s2
h2
(3)
t
Hold, MicroData[6:0] from the rising edge of (MCS* + MWr*)
—
10
(2)
t
Enable, MRdy from the falling edge of (MCS* + MWr*)
4
enzl
(2)
t
Disable, MRdy from the falling edge of (MCS* + MWr*)
3 * t
4 * t +10
dislz
per
per
Footnote:
(1) The microprocessor clock is required by internal logic but has no relationship with the I/O signals.
(2) Timing starts from whichever is asserted last.
(3) Timing relative to whichever goes inactive first.
(4) Timing relative to a 50pF load.
Figure 3-6. Microprocessor Timing —Synchronous Read
tper
MicroClk
ts
ts
ts
ts
th
th
th
MCS*
MWR*
MAS*
th
Microaddr[11:0]
ten
tpd
tdis
MicroData
MRdy
tenzl
tdislz
MicroInt*
MSyncMode
(High)
®
28529-DSH-001-K
Mindspeed Technologies
252
Mindspeed Proprietary and Confidential
Product Specification
Table 3-9.
Microprocessor Timing Parameters - Synchronous Read
Label
Description
Minimum
Maximum
Units
t
Microprocessor Clock Period
40
40
5
ns
%
per
t
Microprocessor Clock Period Duty Cycle
Setup to the rising edge of MicroClk
60
—
—
15
26
15
15
15
duty
t
ns
ns
ns
ns
ns
ns
ns
s
t
Hold from the rising edge of MicroClk
Enable from the rising edge of MicroClk
Propagation Delay from the rising edge of MicroClk
Propagation Delay from the falling edge of MicroClk
Enable from the rising edge of MicroClk
Disable from the rising edge of Microclk
2
h
t
2
en
pd
dis
t
2
t
2
t
2
enzl
t
2
dislz
Footnote:
(1) Timing relative to a 50pF Load
Figure 3-7. Microprocessor Timing —Synchronous Write
tper
MicroClk
th
th
th
ts
MCS*
MWr*
ts
ts
ts
ts
MAS*
th
MicroAddr[11:0]
th
MicroData[7:0]
MRdy
tenzl
MicroInt*
(High)
MSyncMode
®
28529-DSH-001-K
Mindspeed Technologies
253
Mindspeed Proprietary and Confidential
Product Specification
Table 3-10. Microprocessor Timing Parameters - Synchronous Write
Label Description
Minimum
Maximum
Units
t
Microprocessor clock period
40
40
5
ns
%
per
t
Microprocessor Clock Period Duty Cycle
Setup to the rising edge of MicroClk
Hold from the rising edge of MicroClk
Enable from the rising edge of MicroClk
60
—
—
15
duty
t
ns
ns
ns
s
t
2
h
t
2
enzl
Footnote:
(1) Timing relative to a 50pF load
3.4.3
PHY-side Interface Timing (Serial Mode)
The PHY-side interface on the MaxIMA supports three different modes of operation, serial, interleaved and
UTOPIA. Figure 3-8 through 3-13 show the timing diagrams for T1/E1/DSL mode. Table 3-11 and Table 3-12 show
the PHY-side timing requirements for T1/E1/DSL mode.
Figure 3-8. PHY-side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 0, TxDatShft = 0)
tp e r
tp w h
tp w l
S P T x C lk
t h
ts
th
t s
S P T x S y n c
(In p u t)
t p d
t p d
t p d
S P T x S y n c
(O u tp u t)
S P T x D a ta
Figure 3-9. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 1, TxDatShft = 0)
tp e r
tp w h
tp w l
S P T x C lk
t h
ts
th
t s
S P T x S y n c
(In p u t)
t p d
t p d
t p d
S P T x S y n c
(O u tp u t)
S P T x D a ta
®
28529-DSH-001-K
Mindspeed Technologies
254
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-10. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 0, TxDatShft = 1)
tp e r
tp w h
tp w l
S P T x C lk
t h
ts
th
t s
S P T x S y n c
(In p u t)
tp d
tp d
S P T x S y n c
(O u tp u t)
tp d
S P T x D a ta
Figure 3-11. PHY-Side Serial T1/E1/DSL Mode Transmit Timing (TxClkPol = 1, TxDatShft = 1)
tp e r
tp w h
tp w l
S P T x C lk
t h
ts
th
t s
S P T x S y n c
(In p u t)
tp d
tp d
S P T x S y n c
(O u tp u t)
tp d
S P T x D a ta
Table 3-11. PHY-side Serial T1/E1/DSL Mode Transmit Timing Parameters
Symbol
Parameter
Minimum
Typical
Maximum
Units
t
Serial transmit clock period
50
20
20
5
ns
ns
ns
ns
ns
ns
per
t
Serial clock pulse width (high)
Serial clock pulse width (low)
pwh
t
pwl
(1)
t
Setup to sptxclk rise(fall) edge
s
(1)
t
Hold from sptxclk rise(fall) edge
3
h
(1)
t
Delay from sptxclk rise(fall) edge
1
20
pd
Footnote:
(1) Timing synchronized to falling edge when TxClkPol = 1
General Note:
1. The TxClkPol (bit 3) in the IOMODE register determines whether timing is referenced to the positive or negative clock edge.
2. All outputs are assumed to have 20 pF loading.
®
28529-DSH-001-K
Mindspeed Technologies
255
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-12. PHY-side Serial T1/E1/DSL Mode Receive Timing (Positive Clock Edge Timing- RxClkPol = 0)
tper
tpwh
tpwl
SPRxClk
SPRxData
SPRxSync
th1
ts1
ts2
ts2
th2
th2
Figure 3-13. PHY-side Serial T1/E1/DSL Mode Receive Timing (Negative Clock Edge Timing- RxClkPol = 1)
tper
tpwl
tpwh
SPRxClk
ts1
th1
SPRxData
ts2
th2
ts2
th2
SRPxSync
Table 3-12. PHY-side Serial T1/E1/DSL Mode Receive Timing Parameters
Symbol
Parameter
Minimum
Typical
Maximum
Units
t
Serial receive clock period
50
20
20
5
ns
ns
ns
ns
ns
ns
ns
per
t
Serial receive clock pulse width (high)
Serial receive clock pulse width (low)
pwh
t
pwl
(1)
t
Setup to sprxclk rise(fall) edge
s1
h1
(1)
t
Hold from sprxclk rise(fall) edge
3
(1)
t
Setup to sprxclk rise(fall) edge
5
s2
h2
(1)
t
Hold from sprxclk rise(fall) edge
3
Footnote:
(1) Timing Synchronized to falling clock edge when RxClkPol = 1
General Note:
1. The RxClkPol (bit 5) in the IOMODE register determines whether timing is synchronized to the positive or negative clock edge.
2. All outputs are assumed to have 20 pF loading.
®
28529-DSH-001-K
Mindspeed Technologies
256
Mindspeed Proprietary and Confidential
Product Specification
3.4.4
Fractional T1/E1 Mode Timing
Figure 3-14 and show the PHY-side interface timing when configured for Fractional T1/E1 mode. Table 3-13 and 3-
14 show the PHY-side timing requirements for Fractional T1/E1 mode.
Figure 3-14. Fractional T1/E1 Transmit Timing
tper
tpwh
tpwl
SPTxCLK
ts
th
SPTxSYNC
SPTxDATA
tpd
tpd
Table 3-13. Fractional T1/E1 Transmit Timing Parameters
Symbol Parameter
Minimum
Typical
Maximum
Units
t
Fractional transmit clock period
50
20
20
5
ns
ns
ns
ns
ns
ns
per
t
Fractional transmit clock pulse width (high)
Fractional transmit clock pulse width (low)
Set up time to sptxclk rising edge
pwh
t
pwl
t
s
t
Hold time from sptxclk falling edge
Delay from sptxclk rising edge
5
h
t
1
20
pd
®
28529-DSH-001-K
Mindspeed Technologies
257
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-15. Fractional T1/E1 Receive Timing
tper
tpwh
tpwl
SPRxCLK
ts1
th1
SPRxSYNC
ts2
th2
SPRxDATA
Table 3-14. Fractional T1/E1 Receive Timing Parameters
Symbol Parameter
Minimum
Typical
Maximum
Units
t
Serial receive clock period
50
20
20
ns
ns
ns
ns
ns
ns
ns
per
t
Serial receive clock pulse width (high)
Serial receive clock pulse width (low)
Setup to sprxclk rising edge
pwh
t
pwl
t
5
5
s1
h1
t
Hold from sprxclk falling edge
Setup to sprxclk rising edge
t
10
10
s2
h2
t
Hold from sprxclk rising edge
®
28529-DSH-001-K
Mindspeed Technologies
258
Mindspeed Proprietary and Confidential
Product Specification
3.4.5
PHY-side Interface Mode (Interleaved Highway)
Figure 3-16 and 3-21 show the PHY-side interface timing when configured for Interleaved Highway mode. Table 3-
15 and 3-16 show the PHY-side timing requirements for Interleaved Highway mode.
Figure 3-16. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 0, IHTxDatShftx = 0))
tper
tpwl
tpwh
IHTxClk
th
ts
th
ts
IHTxSync
IHTxInDo
ts
th
th
ts
tpd
IHTxData
Figure 3-17. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 1, IHTxDatShftx = 0)
tper
tpwh
tpwl
IHTxClk
ts
ts
th
th
IHTxSync
th
ts
ts
th
IHTxInDo
IHTxData
tpd
®
28529-DSH-001-K
Mindspeed Technologies
259
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-18. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 0, IHTxDatShftx = 1)
tper
tpw h
tpw l
IH TxC lk
ts
ts
th
th
IH TxS ync
IH TxInD o
IH TxD ata
th
ts
ts
th
tpd
Figure 3-19. PHY-side Interleaved Highway Mode Transmit Timing (IHTxClkPolx = 1, IHTxDatShftx = 1)
tp e r
tp w l
tp w h
IH T xC lk
ts
ts
th
th
IH T xS yn c
IH T xIn D o
IH T xD a ta
th
ts
ts
th
tp d
Table 3-15. PHY-side Interleaved Highway Mode Transmit Timing Parameters
Symbol
Parameter
Minimum
Typical
Maximum
Units
t
IH transmit clock period
50
20
20
5
ns
ns
ns
ns
ns
ns
per
t
IH transmit clock pulse width (high)
IH transmit clock pulse width (low)
pwh
t
pwl
(1)
t
Setup to ihtxclk rise(fall) edge
s
(1)
t
Hold from ihtxclk rise(fall) edge
3
h
(1)
t
Delay from ihtxclk rise(fall) edge
2
20
pd
Footnote:
(1) Timing synchronized to falling clock edge when IHTxClkPolx = 1
General Note:
1. All outputs are assumed to have 20 pF loading.
®
28529-DSH-001-K
Mindspeed Technologies
260
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-20. PHY-side Interleaved Highway Mode Receive Timing (Positive Edge - IHRxClkPolx = 0)
tper
tpwl
tpwh
IHR xClk
ts
ts
ts
th
th
th
ts
th
IHR xSync
IHR xInDo
IHR xData
ts
th
Figure 3-21. PHY-side Interleaved Highway Mode Receive Timing (Negative Edge - IHRxClkPolx = 1)
tpe r
tpw l
tp w h
IH R xC lk
ts
th
ts
th
IH R xS ync
IH R xInD o
IH R xD ata
ts
th
ts
th
th
ts
Table 3-16. PHY-side Interleaved Highway Mode Receive Timing Parameters
Symbol
Parameter
Minimum
Typical
Maximum
Units
t
IH receive clock period
50
20
20
5
ns
ns
ns
ns
ns
per
t
IH receive clock pulse width (high)
IH receive clock pulse width (low)
pwh
t
pwl
(1)
t
Setup to ihrxclk rise(fall) edge
s
(1)
t
Hold from ihrxclk rise(fall) edge
3
h
Footnote:
(1) Timing synchronized with falling clock edge when RxClkPolx = 1
General Note:
1. All outputs are assumed to have 20 pF loading.
®
28529-DSH-001-K
Mindspeed Technologies
261
Mindspeed Proprietary and Confidential
Product Specification
3.4.6
PHY-Side Interface Timing (UTOPIA)
Figures 3-22 through 3-23 and Tables 3-17 through 3-18 show the timing requirements and characteristics of the
PHY-side UTOPIA interface.
Figure 3-22. PHY-side UTOPIA Transmit Timing
tper
phyUTxClk
tpd
phyUtxEnb*
tpd
phyUTxAddr[4:0]
tpd
phyUTxData[15:0]
tpd
phyUTxSOC
tpd
phyUTxPrty
th
ts
phyUTxClav
Table 3-17. PHY-side UTOPIA Transmit Timing Parameters
Symbol
Parameter
Minimum
Typical
Maximum
Units
(1)
t
UTOPIA transmit clock period
30.3
ns
%
per
t
UTOPIA transmit clock dutycycle
Setup to phyutxclk rise edge
Hold from phyutxclk rise edge
Enable from phyutxclk fall edge
50
duty
t
8
1
ns
ns
ns
s
t
h
t
-5
7
pd
Footnote:
(1) This clock is a divide-by-2 of IMA_SysClk.
General Note:
1. Timing applies with 0-50pF loads on the outputs.
®
28529-DSH-001-K
Mindspeed Technologies
262
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-23. PHY-side UTOPIA Receive Timing
tper
phyURxClk
tpd
phyURxEnb*
tpd
phyURxAddr[4:0]
phyURxData[15:0]
phyURxSOC
th
ts
th
ts
th
ts
phyURxPrty
th
ts
phyURxClav
Table 3-18. PHY-side UTOPIA Receive Timing Parameters
Symbol
Parameter
Minimum
Typical
Maximum
Units
(1)
t
UTOPIA receive clock period
30.3
ns
%
per
t
UTOPIA receive clock dutycycle
Setup to phyurxclk rise edge
Hold from phyurxclk rise edge
Enable from phyurxclk fall edge
50
duty
t
8
1
ns
ns
ns
s
t
h
t
-5
7
pd
Footnote:
(1) This clock is a divide-by-2 of IMA_SysClk.
General Note:
1. Timing applies with 0-50pF loads on the outputs.
®
28529-DSH-001-K
Mindspeed Technologies
263
Mindspeed Proprietary and Confidential
Product Specification
3.4.7
UTOPIA Interface Timing (ATM-Side)
Figures 3-24 through 3-25 and Tables 3-19 through 3-22 show the timing requirements and characteristics of the
ATM-side UTOPIA interface.
Figure 3-24. ATM-side UTOPIA Transmit Timing
tper
atmUTxClk
atmUTxEnb*
ts
th
atmUTxAddr[4:0]
atmUTxData[15:0]
ts
ts
ts
th
th
th
atmUTxSoc
atmUTxPrty
tpd
tdis
ten
atmUTxClav
Table 3-19. ATM-side UTOPIA Transmit Timing Parameters (IMA Enabled - 16 Bit Mode)
Symbol
Parameter
Minimum
Typical
Maximum
Units
(1)
t
UTOPIA transmit clock period
20
ns
%
per
t
UTOPIA transmit clock dutycycle
Setup to atmutxclk rise edge
Hold from atmutxclk rise edge
Delay from atmutxclk rise edge
Enable from atmutxclk rise edge
Disable from atmutxclk rise edge
40
4
60
duty
t
ns
ns
ns
ns
ns
s
t
1
h
t
1
15
15
15
pd
t
1
en
t
1
dis
General Note:
1. Timing applies with 0-30pF loads on the outputs.
®
28529-DSH-001-K
Mindspeed Technologies
264
Mindspeed Proprietary and Confidential
Product Specification
Table 3-20. ATM-side UTOPIA Transmit Timing Parameters (IMA Bypassed - 8/16 Bit Mode, IMA
Enabled - 8 Bit Mode)
Symbol
Parameter
Minimum
Typical
Maximum
Units
t
UTOPIA transmit clock period
UTOPIA transmit clock dutycycle
Setup to atmutxclk rise edge
Hold from atmutxclk rise edge
Delay from atmutxclk rise edge
Enable from atmutxclk rise edge
Disable from atmutxclk rise edge
30.3
40
8
ns
%
per
t
60
duty
t
ns
ns
ns
ns
ns
s
t
1
h
t
1
20
20
20
pd
t
1
en
t
1
dis
General Note:
Timing applies with 0-30pF loads on the outputs.
Figure 3-25. ATM-side UTOPIA Receive Timing
tper
atmURxClk
ts
ts
th
atmURxEnb*
th
atmURxAddr[4:0]
tpd
ten
tdis
atmURxData[15:0]
ten
tdis
tdis
tdis
tpd
tpd
tpd
atmURxPrty
ten
atmURxSoc
ten
atmURxClav
®
28529-DSH-001-K
Mindspeed Technologies
265
Mindspeed Proprietary and Confidential
Product Specification
Table 3-21. ATM-side UTOPIA Receive Timing Parameters (IMA Enabled - 16 Bit Mode)
Symbol
Parameter
Minimum
Typical
Maximum
Units
(1)
t
UTOPIA receive clock period
20
ns
%
per
t
UTOPIA receive clock dutycycle
Setup to atmurxclk rise edge
Hold from atmurxclk rise edge
Delay from atmurxclk rise edge
Enable from atmurxclk rise edge
Disable from atmurxclk rise edge
40
4
60
duty
t
ns
ns
ns
ns
ns
s
t
1
h
t
1
15
15
15
pd
t
1
en
t
1
dis
General Note:
1. Timing applies with 0-30 pF loads on the outputs.
Table 3-22. ATM-side UTOPIA Receive Timing Parameters (IMA Bypassed - 8/16 Bit Mode, IMA
Enabled - 8 Bit Mode)
Symbol
Parameter
Minimum
Typical
Maximum
Units
t
UTOPIA receive clock period
30.3
40
8
ns
%
per
t
UTOPIA receive clock dutycycle
Setup to atmurxclk rise edge
Hold from atmurxclk rise edge
Delay from atmurxclk rise edge
Enable from atmurxclk rise edge
Disable from atmurxclk rise edge
60
duty
t
ns
ns
ns
ns
ns
s
t
1
h
t
1
20
20
20
pd
t
1
en
t
1
dis
General Note:
1. Timing applies with 0-30 pF loads on the outputs.
®
28529-DSH-001-K
Mindspeed Technologies
266
Mindspeed Proprietary and Confidential
Product Specification
3.4.8
External Memory Interface Timing Diagram
Figure 3-26. External Memory Timing
tper
Write Cycle
Read Cycle
MemCtrl_CLK
tapd
tapd
tadpd
tcpd
tapd
MemAddr
tadpd
tadpd
tadpd
MemCtrl_ADSC*
tcpd
tcpd
tcpd
MemCtrl_CE*
twpd
twpd
MemCtrl_WE*
MemCtrl_OE*
topd
topd
trdh
trds
twdpd
twdh
memdata
Write Data
Read Data
®
28529-DSH-001-K
Mindspeed Technologies
267
Mindspeed Proprietary and Confidential
Product Specification
Table 3-23. External Memory Timing Parameters
Symbol Parameter
Minimum
Typical
Maximum
Units
t
Pulse Width Low
Pulse Width High
Period
8
8
-
-
ns
ns
ns
ns
pwl
t
pwh
t
20
1
-
per
t
Propagation Delay, MemAddr from rising edge of
MemCtrl_CLK
10
apd
t
Propagation Delay, MemCtrl_ADSC from rising edge of
MemCtrl_CLK
1
1
1
1
-
10
10
10
10
10
ns
ns
ns
ns
ns
adpd
t
Propagation Delay, MemCtrl_CE* from rising edge of
MemCtrl_CLK
cpd
t
Propagation Delay, MemCtrl_WE* from rising edge of
MemCtrl_CLK
wpd
t
Propagation Delay, MemCtrl_OE* from rising edge of
MemCtrl_CLK
opd
t
Propagation Delay, valid write data from rising edge of
MemCtrl_CLK
wdpd
t
Hold, valid write data from rising edge of MemCtrl_CLK
Setup, read data to rising edge of MemCtrl_CLK
Hold, read data from rising edge of MemCtrl_CLK
1
5
1
-
-
-
ns
ns
ns
wdh
t
rds
rdh
t
Footnote:
(1) All outputs are assumed to have a load of 20pf
3.4.9
JTAG Interface Timing
Figure 3-27 and Table 3-24 show the timing requirements and characteristics of the JTAG interface.
Figure 3-27. JTAG Timing
tper
TCK
trec
TRST*
ts
th
TMS
TDI
ts
th
tdis1
tdis2
ten
tpd
TDO
®
28529-DSH-001-K
Mindspeed Technologies
268
Mindspeed Proprietary and Confidential
Product Specification
Table 3-24. JTAG Timing Parameters
Symbol Parameter
Minimum
Typical
Maximum
Units
t
tck clock period
100
40
ns
%
per
t
tck clock duty cycle
60
duty
t
Recovery, tck rise edge from trst_n rise edge
Setup to tck rise edge
10
ns
ns
ns
ns
ns
ns
ns
rec
t
10
s
t
Hold from tck rise edge
Delay from tck fall edge
Enable from tck fall edge
Disable from tck fall edge
Disable from tck fall edge
10
h
t
15
15
15
15
pd
t
en
t
t
dis1
dis2
Footnote:
(1) All outputs are assumed to have a load of 80pf
3.4.10
One-second Interface Timing
Figure 3-28 and Table 3-25 show the timing requirements and characteristics of the one-second interface.
Figure 3-28. One-second Timing
t
t
t
per
pwh1
pwl1
8kHzIn
t
t
pd
pd
OneSecIO
General Notes:
When OneSecIO is configured as an output, it is equal to 8kHzIn/8000.
500027_033
Table 3-25. One Second Timing Parameters
Label
Description
Min
Max
Unit
8KHzIn Clock Frequency
8KHzIn Duty Cycle
0.01
40%
1
100
60%
20
KHz
t
per
t
Propagation Delay, OneSecOut from the rising edge of OneSecClk
ns
pd
®
28529-DSH-001-K
Mindspeed Technologies
269
Mindspeed Proprietary and Confidential
Product Specification
3.5
Package Specification
3.5.1
Mechanical Description
The M28525/9 is a 484-ball, 27mm PBGA package. A mechanical drawing of the device is provided in Figure 3-29
and Figure 3-30.
Figure 3-29. M28525/9 Mechanical Drawing (Bottom View)
®
28529-DSH-001-K
Mindspeed Technologies
270
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-30. M28525/9 Mechanical Drawing (Top and Side Views)
®
28529-DSH-001-K
Mindspeed Technologies
271
Mindspeed Proprietary and Confidential
Product Specification
3.6
Interface Pin Description
Figure 3-31. M28529 Pinout Diagram, UTOPIA-to-Serial (Bottom View)
®
28529-DSH-001-K
Mindspeed Technologies
272
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-32. M28525 Pinout Diagram Utopia-to-Serial (Bottom View)
®
28529-DSH-001-K
Mindspeed Technologies
273
Mindspeed Proprietary and Confidential
Product Specification
Figure 3-33. M28525/9 Pinout Diagram UTOPIA-to-UTOPIA (Bottom View)
®
28529-DSH-001-K
Mindspeed Technologies
274
Mindspeed Proprietary and Confidential
4.0 Appendices
4.1
IMA Version 1.1 PICS Proforma
To evaluate conformance of a particular implementation, it is necessary to have a statement of which capabilities
and options have been implemented for a given protocol. Such a statement is called a Protocol Implementation
Conformance Statement (PICS).
4.1.1
Scope
This annex provides the PICS proforma for the Inverse Multiplexing for ATM (IMA) Version 1.1 Specification as
described in AF-PHY-0086.001[A-1] in compliance with the relevant requirements, and in accordance with the
relevant guidelines, given in ISO/IEC 9646-2[A-3].
4.1.2
Definitions
This document uses the following terms defined in ISO/IEC 9646-1[A-2]:
•
a Protocol Implementation Conformance Statement (PICS) is a statement made by the supplier of an
implementation or a system, stating which capabilities have been implemented for a given protocol,
•
a PICS Proforma is a document in the form of a questionnaire, designed by the protocol specifier or the
conformance test suite specifier, which when completed for an implementation or a system, becomes the
PICS, and
•
a static conformance review is a review of the extent to which the static conformance requirements are met by
the implementation, accomplished by comparing the PICS with the static conformance requirements
expressed in the relevant protocol specification.
4.1.3
Symbols and Conventions
M—Mandatory
O—Option (may be selected to suit the implementation, provided that any requirements applicable to the options
are observed)
4.1.4
Conformance
The supplier of a protocol implementation, which is claimed to conform to AF-PHY-0086.001[A-1], is required to
complete a copy of the PICS proforma provided in the following sections of this annex and is required to provide the
information necessary to identify both the supplier and the implementation.
®
28529-DSH-001-K
Mindspeed Technologies
275
Mindspeed Proprietary and Confidential
Appendices
4.1.5
IMA PICS Proforma
4.1.5.1
Global Statement of Conformance
The implementation described in this PICS Proforma meets all of the mandatory requirements of the protocol
specification.
Yes__XX
No__
Note: Answering “No” indicates non-conformance to the protocol specification. Non-supported mandatory
capabilities are to be identified in the following tables, with an explanation in the “Comments” section of each table
as to why the implementation is “non conforming”.
4.1.5.2
Instructions for Completing the PICS Proforma
Each question in this section refers to a major function of the protocol. Answering “Yes” to a particular question
states that the implementation supports all of the mandatory procedures for that function, as defined in the
referenced section of AF-PHY-0086.001[A-1]. Answering “No” to a particular question in this section states that the
implementation does not support that function of the protocol.
A supplier may also provide additional information, categorized as exceptional (X) or supplementary information.
This additional information should be provided in the Support column as items labeled X<I> for exceptional or S<I>
for supplementary information, respectively for cross-reference purposes, where <I> is any unambiguous number.
4.1.5.3
Table 4-1.
Item
IMA Protocol Functions
Basic IMA Protocol (BIP) Definition Functions (1 of 5)
Cond. for Status
Protocol feature
Ref.
Support
Status
Pred.
BIP.1
BIP.2
BIP.3
Does the implementation support a number N (1 ≤ N ≤ 32) of transmission
links within an IMA group operating at the same nominal link cell rate
(LCR)?
M
(R-1)
Yes X No__
Does the implementation support the IMA interface connected to another
interface over clear channel facilities (implies cells generated by transmit
IMA shall only be terminated at the receive IMA)?
M
M
(R-2)
(R-3)
Yes X No__
Yes X No__
Does the interface specific TC sublayer of the implementation pass all cells
to the IMA sublayer or provide an indication that a cell was received (this
includes HEC errored cells)?
BIP.4
BIP.5
BIP.6
BIP.7
BIP.8
Does the implementation prohibit cell rate decoupling at the interface
specific TC sublayer?
M
M
M
M
M
(R-4)
(R-5)
(R-6)
(R-7)
(R-8)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Does the implementation assign a LID unique within the IMA group to each
Tx IMA link on each physical link?
Does the implementation ensure that the LID does not change while the link
is a member of the IMA group?
Does the implementation distribute ATM cells arriving from the ATM layer
over the N links in a cyclic round-robin fashion, and on a cell-by-cell basis?
Does the implementation distribute ATM cells over the links using an
ascending order based on the LID assigned to each link within the IMA
group?
®
28529-DSH-001-K
Mindspeed Technologies
276
Mindspeed Proprietary and Confidential
Appendices
Table 4-1.
Basic IMA Protocol (BIP) Definition Functions (2 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
BIP.9
Does the implementation support the ICP cell format defined in Table 2 on
page 31 to convey IMA configuration, synchronization, status, and defect
information to the far-end?
M
(R-9)
Yes X No__
BIP.10 Does the implementation perform cell rate decoupling by inserting IMA Filler
cells in place of ATM cells when there is no cell available at the ATM layer?
M
M
(R-10)
(R-11)
Yes X No__
Yes X No__
BIP.11 Does the implementation accept, on receive, ATM cells from the N links
according to ascending order based on the LID received in the ICP cells on
the incoming link?
BIP.12 Does the implementation, on receive, compensate for link differential delays
and rebuild the original ATM cell stream?
M
M
(R-11)
(R-11)
Yes X No__
Yes X No__
BIP.13 Does the implementation discard received Filler cells and cells with bad
HEC?
BIP.14 Does the implementation process and discard incoming ICP cells?
M
M
(R-11)
(R-11)
Yes X No__
Yes X No__
BIP.15 Does the implementation aggregate, on receive, the ATM cell stream to the
ATM layer?
BIP.16 Does the implementation preserve the order of incoming cells?
M
M
(R-11)
(R-12)
Yes X No__
Yes X No__
BIP.17 Does the implementation use the ICP cell to maintain IMA protocol
synchronization?
BIP.18 Does the implementation use the ICP cell to maintain link delay
synchronization?
M
M
M
M
M
(R-12)
(R-13)
(R-14)
(R-15)
(R-16)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
BIP.19 Does the implementation transmit first the most significant bit of each octet
of the IMA OAM cell?
BIP.20 Does the implementation support the same cell header for both the Filler and
ICP cell formats as defined in Table 1 on page 28 and Table 2 on page 31?
BIP.21 Does the implementation use bit 7 of octet 7 (CID field) of the Filler and ICP
cells to identify the IMA OAM cell as an ICP or Filler cell?
BIP.22 Does the implementation use octets 52-53 as specified in ITU-T
Recommendation I.610 [A-5] for octets 52-53 of the OAM cells of the F1/F3
flows?
BIP.23 Does the implementation support the Filler cell format defined in Table 1 on
page 28?
M
M
M
M
M
M
(R-17)
(R-18)
(R-19)
(R-20)
(R-21)
(R-22)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
BIP.24 Does the implementation support the ICP cell format defined in Table 2 on
page 31?
BIP.25 Does the implementation transmit the content of the link specific fields
appearing in class A over the link for which these fields apply?
BIP.26 Does the implementation transmit the same content of fields appearing in
classes B and C of the ICP cell over all links within an IMA group?
BIP.27 Does the implementation use the LID bits (bits 4-0 of octet 7) in the ICP cell
to identify the Link ID (range being 0 to 31)?
BIP.28 Does the implementation use the “Tx State” field, located in the Link “x”
Information field in an ICP cell, to report the transmit state of the IMA link on
which the NE IMA is transmitting ICP cells carrying LID = “x” (“x” being a
value between 0 and 31)?
®
28529-DSH-001-K
Mindspeed Technologies
277
Mindspeed Proprietary and Confidential
Appendices
Table 4-1.
Basic IMA Protocol (BIP) Definition Functions (3 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
BIP.29 Does the implementation use the “Rx State”, located in the Link “x”
Information field in an ICP cell, to report the receive state of the incoming
IMA link on which the FE IMA is transmitting ICP cells carrying LID = “x”
(“x” being a value between 0 and 31)?
M
(R-23)
Yes X No__
BIP.30 Does the implementation use the “Rx Defect Indicators” field, located
in the Link “x” Information field in an ICP cell, to report the Rx defect
indicators corresponding to the incoming IMA link on which the FE IMA is
transmitting ICP cells carrying LID = “x” (“x” being a value between 0 and
31)?
M
(R-24)
Yes X No__
BIP.31 Does the implementation always transmit ICP cells with Octet 50 unused and
set to “0x6A” as defined in ITU-T Recommendation I.432 [A-4]?
M
M
M
M
M
M
M
(R-25)
(R-26)
(R-27)
(R-28)
(R-29)
(R-30)
(R-31)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
BIP.32 Does the implementation reserve the End-to-End Channel field (Octet 51) as
a proprietary channel?
BIP.33 Does the implementation set the End-to-End Channel field (Octet 51) to “0”
when not using this field?
BIP.34 Does the implementation not rely on the processing of the End-to-End
Channel field for any IMA functionality?
BIP.35 Does the implementation only consider the information within ICP cells
exhibiting neither a HEC nor a CRC-10 error?
BIP.36 Does the implementation always transmit "0x03" over the OAM Label in the
Filler and ICP cells?
BIP.37 If the implementation does not support the IMA version proposed by the
OAM Label received from the far-end IMA unit, does the implementation
report the “Config-Aborted - Unsupported IMA Version" state over the
“Group Status and Control” field?
BIP.38 Does the implementation transmit IMA frames, composed of M consecutive
cells, on each link within the IMA group?
M
M
M
M
M
M
M
M
M
O
(R-32)
(R-33)
(R-34)
(R-35)
(R-36)
(R-36)
(R-37)
(R-38)
(R-39)
(O-1)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
BIP.39 Does the implementation send ICP cells on each link once per IMA frame,
hence every M cells?
BIP.40 Does the implementation use the IFSN field in the ICP cell to indicate the
sequence number of the IMA frame?
BIP.41 Does the implementation increment the IFSN field in the ICP cell from 0 to
255 and repeat the sequence?
BIP.42 Does the implementation increment the IFSN field in the ICP cell with each
IMA frame on a per-link basis?
BIP.43 Within an IMA frame, does the implementation place identical IFSN values in
the ICP cells sent on each link?
BIP.44 Does the implementation align the transmission of the IMA frame on all links
within an IMA group?
BIP.45 Does the implementation use the ICP Cell Offset field (octet 9) to indicate the
location of the ICP cell within the IMA frame of length M cells?
BIP.46 Does the implementation always set the value of the ICP cell offset between
0 and M-1 where M is the IMA frame length in cells?
BIP.47 Does the implementation distribute the ICP cells, from link to link within the
IMA group, in an uniform fashion across the IMA frame?
®
28529-DSH-001-K
Mindspeed Technologies
278
Mindspeed Proprietary and Confidential
Appendices
Table 4-1.
Basic IMA Protocol (BIP) Definition Functions (4 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
BIP.48 Does the implementation select the offset of the ICP cell sent of any link
when the link is assigned a LID?
M
(R-40)
Yes X No__
BIP.49 Does the implementation retain the offset of the ICP cell sent on a given link
until the link is no longer part of the group?
M
M
(R-40)
(R-41)
Yes X No__
Yes X No__
BIP.50 Does the implementation always use the Frame Length field in the ICP cell to
indicate the value of M?
BIP.51 Does the implementation support M = 128?
BIP.52 Does the implementation support M = 32?
BIP.53 Does the implementation support M = 64?
BIP.54 Does the implementation support M = 256?
M
O
(R-42)
(O-2)
(O-2)
(O-2)
(R-43)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
O
O
BIP.55 Does the implementation only change the value M at group
start-up time?
M
BIP.56 Does the implementation use on transmit the value configured by the UM?
(O-2)
(O-2)
M
M
(CR-1)
(CR-2)
Yes X No__
Yes X No__
BIP.57 Does the implementation allow different values of M in both Tx and Rx
directions?
BIP.58 Does the implementation synchronize its incoming links using the received
M value for IMA frame synchronization?
(O-2)
M
M
(CR-3)
(R-44)
Yes X No__
Yes X No__
BIP.59 Does the implementation abort the start-up procedure using the
corresponding code in the Group Status and Control field of the ICP cell
when it does not support the received M?
BIP.60 Does the implementation allow to configure the value M?
O
(O-3)
Yes X No__
Yes X No__
BIP.61 Does the implementation set the SCCI field to the previously transmitted
SCCI field value, incremented modulo 256, to indicate a change on at least
one of the fields appearing in octets 12 through 49 in the transmitted ICP
cell?
M
(R-45)
BIP.62 Does the implementation use the SCCI field to identify received ICP cells for
processing when ICP cells are monitored on more than one link, or when the
monitored link has changed?
M
M
(R-46)
(R-46)
Yes X No__
Yes X No__
BIP.63 Does the implementation process the fields in octets 12 through 49 if the
SCCI field has advanced beyond the SCCI value of the last processed ICP
cell?
BIP.64 Does the implementation select the IMA ID at group start-up time?
BIP.65 Does the implementation transmit the IMA ID in the IMA ID field?
BIP.66 Does the implementation allow to configure the value of IMA ID?
M
M
O
(R-47)
(R-48)
(O-4)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
BIP.67 Does the implementation use the “Group Symmetry Mode” field, specified in
Table 2 on page 31, to indicate the symmetry of the IMA group?
M
(R-49)
BIP.68 Does the implementation ensure that the symmetry of the group is only
established or changed at group start-up time?
M
M
O
(R-50)
(R-51)
(O-5)
Yes X No__
Yes X No__
Yes X No__
BIP.69 Does the implementation support the Symmetrical Configuration and
Operation mode?
BIP.70 Does the implementation support the Symmetrical Configuration and
Asymmetrical Operation mode?
®
28529-DSH-001-K
Mindspeed Technologies
279
Mindspeed Proprietary and Confidential
Appendices
Table 4-1.
Basic IMA Protocol (BIP) Definition Functions (5 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
BIP.71 Does the implementation support the Asymmetrical Configuration and
Operation mode?
O
(O-6)
Yes X No__
BIP.72 Does the implementation abort the start-up procedure using the appropriate
code defined in the “Group Status and Control” field of the ICP cell (as
specified in Table 2 on page 31) if the NE does not support the symmetry
mode proposed by the FE?
M
M
O
(R-52)
(R-52)
(O-7)
Yes X No__
Yes X No__
Yes X No__
BIP.73 Does the implementation abort the start-up procedure using the appropriate
code defined in the “Group Status and Control” field of the ICP cell (as
specified in Table 2 on page 31) if the symmetry mode proposed by the FE
and the configured symmetry mode of the NE do not match?
BIP.74 In order to allow a fast recovery when (O-5) or (O-6) is used at the NE and
when the FE IMA unit can only be configured to the “Symmetrical
Configuration and Operation” mode, does the implementation adjust to
“Symmetrical Configuration and Operation”.
BIP.75 Does the implementation support only the valid combinations of group
symmetry modes at each end of the IMA virtual link as specified in Table 4
on page 36?
M
O
(R-53)
(O-8)
Yes X No__
Yes X No__
BIP.76 Does the implementation allow configuration of the group mode?
Comments: Maximum group size is 8 links.
Table 4-2.
QoS Requirements Functions
Cond. for
Status
Status
Pred.
Item
Protocol feature
Ref.
Support
QOS.1 Does the implementation support all ATM traffic/QoS classes supported by
the ATM layer?
M
(R-54)
Yes X No__
Comments:
Table 4-3.
CTC and ITC Operation Functions (1 of 2)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
CIT.1
Does the implementation indicate to the FE in which transmit clock mode it
is running in the “Transmit Clock Mode” field in the ICP cell?
M
(R-55)
Yes X No__
CIT.2
CIT.3
Does the implementation support the CTC mode in the transmit direction?
M
M
(R-56)
(R-57)
Yes X No__
Yes X No__
Does the implementation only indicate to the FE that it is in the CTC mode
when all the “transmit” clocks of the links in the group are derived from the
same source?
CIT.4
CIT.5
Does the implementation support the ITC mode in the transmit direction?
O
O
(O-9)
Yes X No__
Yes X No__
Does the implementation indicate that it is in the ITC mode even if all the
transmit clocks of the links in the group are derived from the same source?
(O-10)
CIT.6
CIT.7
Does the implementation use the cell stuffing procedure to prevent link
transmit buffer under-run or over-run?
(O-9)
M
M
(CR-4)
(R-58)
Yes X No__
Yes X No__
Does the implementation indicate a stuff event in the ICP cell preceding a
stuff event using the mandatory LSI codes specified in Table 2 on page 30?
®
28529-DSH-001-K
Mindspeed Technologies
280
Mindspeed Proprietary and Confidential
Appendices
Table 4-3.
CTC and ITC Operation Functions (2 of 2)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
CIT.8
Does the implementation perform stuffing by repeating the ICP cell
containing the LSI code indicating that “this cell is 1 out of 2 ICP cells
comprising the stuff event”?
M
(R-59)
Yes X No__
CIT.9
Does the implementation also indicate an incoming stuff event in the fourth,
third, and second ICP preceding the stuff event using the optional LSI
codes?
O
(O-11)
Yes X No__
CIT.10 At any given link, does the implementation ensure it does not introduce a
stuff event more than once every 5*M ICP, Filler and ATM layer cells?
M
M
(R-60)
(R-61)
Yes X No__
Yes X No__
CIT.11 Does the implementation remove one of any two consecutive ICP cells with
LSI code indicating “this cell is 1 out of the 2 ICP cells comprising the stuff
event”?
CIT.12 Does the implementation ensure that the SICP cell is not counted as a cell
for the purposes of determining the IMA round-robin sequence?
M
(R-61)
Yes X No__
CIT.13 Does the implementation support CTC and ITC modes on receive?
M
M
(R-62)
(R-63)
Yes X No__
Yes X No__
CIT.14 Does the implementation inform the UM of a mismatch between the FE and
NE IMA transmit clock modes?
CIT.15 Does the implementation ensure that a restart is not caused if the
implementation detects a mismatch between the FE and NE Transmit clock
modes?
M
O
(R-63)
(O-12)
Yes X No__
Yes X No__
CIT.16 Does the implementation rely on at least one ICP cell with a correct CRC-10
in order to process the incoming stuff cell indication code (this is
recommended)?
Comments:
Table 4-4.
IMA Data Cell (IDC) Rate Implementation Functions (1 of 2)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IDC.1
IDC.2
IDC.3
IDC.4
Does the implementation ensure on transmit that a Filler cell is not injected if
an ATM layer cell is available for scheduling?
M
(R-64)
(R-64)
(R-65)
(R-66)
Yes X No__
Does the implementation only check on transmit that an ATM layer cell is
available and accept that cell only when the Tx IDCC ticks?
M
M
M
Yes X No__
Yes X No__
Yes X No__
Does the implementation only select the TRL from the set of links whose
transmit state is Active?
If there is no link in the Active state, does the implementation select one of
the links in the Usable state, if any, or one of the links in the Unusable state
otherwise?
IDC.5
Does the implementation only select or change the TRL during the following
situations:
M
(R-67)
Yes X No__
during group start-up,
when the previously selected TRL's transmit state changes from Active to
any other state (e.g., Usable, Unusable, or Not In Group) while another link’s
transmit state is Active, or
when the previously selected TRL’s transmit state changes from Usable to
Unusable or Not In Group while another link’s transmit state is Active or
Usable?
®
28529-DSH-001-K
Mindspeed Technologies
281
Mindspeed Proprietary and Confidential
Appendices
Table 4-4.
IMA Data Cell (IDC) Rate Implementation Functions (2 of 2)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IDC.6
IDC.7
IDC.8
IDC.9
Does the implementation indicate the selected or changed TRL to the FE over
the “Transmit Timing Information” field in the ICP cell?
M
(R-68)
Yes X No__
Does the implementation derive the Tx IDCC from the selected TRL
according to Equation 1 on page 40?
M
M
M
M
(R-69)
(R-70)
(CR-5)
(CR-6)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
When running in the CTC mode, does the implementation introduce a stuff
event every 2048 ICP, Filler and ATM layer cells on all links?
Does the implementation introduce a stuff event every 2048 ICP, Filler and
ATM layer cells on the TRL?
(O-9)
IDC.10 Does the implementation introduce stuff events on links other than the TRL (O-9)
in order to compensate for the timing difference between the TRL and the
other links?
IDC.11 Does the implementation remove CDV attributed to the presence of ICP cells
by a mechanism equivalent to providing a small smoothing buffer into which
cells are placed after reordering and after removing ICP cells?
M
M
M
(R-71)
(R-72)
(R-73)
Yes X No__
Yes X No__
Yes X No__
IDC.12 If the TRL is in the Working state and the FE has, for at least 100
milliseconds, identified a given link as the TRL, does the implementation
derive the Rx IDCR using the incoming link indicated by the FE as the TRL?
IDC.13 Does the implementation have an equivalent behavior to the following: when
the IMA data cell clock at the receiver ticks, one cell is removed from the
smoothing buffer; if the cell is a Filler cell, then the Filler cell is discarded and
nothing passed to the ATM layer; if the cell is not a Filler cell, then it is passed
to the ATM layer?
Comments:
Table 4-5.
Link Differential Delay (LDD) Functions
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
LDD.1 Does the implementation introduce a differential delay among the
constituent links of a maximum of 2.5 cell times at the physical link rate?
M
(R-74)
(R-75)
(O-13)
Yes X No__
LDD.2 Does the implementation tolerate up to at least 25 milliseconds of link
differential delay on receive?
M
O
Yes X No__
Yes X No__
LDD.3 Does the implementation allow configuring the link differential delay
tolerance?
Comments:
Table 4-6.
IMA Interface Operation (IIO) Functions (1 of 4)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IIO.1
IIO.2
Does the implementation support the Tx LSM defined in Table 8 on page 52?
M
M
(R-76)
(R-77)
Yes X No__
Yes X No__
Does the implementation support the Rx LSM defined in Table 9 on page
53?
IIO.3
Does the implementation signal the current state of the Tx LSM to the FE
IMA unit via the ICP cells?
M
(R-78)
Yes X No__
®
28529-DSH-001-K
Mindspeed Technologies
282
Mindspeed Proprietary and Confidential
Appendices
Table 4-6.
IMA Interface Operation (IIO) Functions (2 of 4)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IIO.4
IIO.5
IIO.6
Does the implementation perform the actions corresponding to the Tx LSM
sub-states?
M
(R-78)
Yes X No__
Does the implementation update the Tx LSM according the occurrence of
the events listed in Table 8 on page 52?
M
M
(R-78)
(R-78)
Yes X No__
Yes X No__
Does the implementation treat sequentially the incoming events that trigger
the Tx LSM, although the order of treatment is implementation specific if
these events appear simultaneously?
IIO.7
IIO.8
IIO.9
Does the implementation signal the current state of the Rx LSM to the FE
IMA unit via the ICP cells?
M
M
M
M
(R-78)
(R-78)
(R-78)
(R-78)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Does the implementation perform the actions corresponding to the Rx LSM
sub-states?
Does the implementation update the Rx LSM according the occurrence of
the events listed in Table 9 on page 53?
IIO.10 Does the implementation treat sequentially the incoming events that trigger
the Rx LSM, although the order of treatment is implementation specific if
these events appear simultaneously?
IIO.11 Does the implementation report any change of the Tx and Rx LSMs within
the next 2*M (where M is the M used by the IMA transmitter) cells on that
link over the “Tx State” and “Rx State” fields of the Link Information field
(refer to Table 3 on page 32)?
M
(R-79)
Yes X No__
IIO.12 Does the implementation use one of the Unusable encodings when reporting
the Unusable state?
M
O
(R-80)
(O-14)
(R-81)
(R-82)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
IIO.13 Does the implementation use “Inhibited”, “Failed”, “Fault” or “Mis-
connected” as a reason when reporting the Unusable state?
IIO.14 Does the implementation re-evaluate the TX and Rx LSMs state upon each
incoming ICP cell with new state indication?
M
M
IIO.15 Does the implementation allow the valid combinations of Tx and Rx LSM
states and disallow the invalid combinations when running in the
Symmetrical Configuration and Operation mode?
IIO.16 Does the implementation allow the valid combinations of Tx and Rx LSM
states and disallow the invalid combinations when running in the
Symmetrical Configuration and Asymmetrical Operation mode?
M
(R-82)
Yes X No__
IIO.17 Does the implementation allow all combinations of Tx and Rx LSM states
when running in the Asymmetrical Configuration and Operation mode?
M
M
(R-82)
(R-83)
Yes X No__
Yes X No__
IIO.18 Does the implementation report any GSM states, with the exception of the
Not Configured state, to the FE group using the corresponding value defined
in the “Group Status and Control” field?
IIO.19 Does the implementation always send over each link the same value in the
“Group Status and Control” field for at least 2 consecutive IMA frames?
M
M
M
(R-84)
(R-85)
(R-86)
Yes X No__
Yes X No__
Yes X No__
IIO.20 Does the implementation validate the Rx OAM Label, Rx M, and Rx IMA ID
over at least one link before moving into the Start-up-Ack state?
IIO.21 Does the implementation use the validated Rx OAM Label, Rx M, and Rx
IMA ID to achieve IMA frame synchronization as defined in Section 11 on
page 68?
®
28529-DSH-001-K
Mindspeed Technologies
283
Mindspeed Proprietary and Confidential
Appendices
Table 4-6.
IMA Interface Operation (IIO) Functions (3 of 4)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IIO.22 Does the implementation ensure that at least P links in the transmit
M
(R-87)
Yes X No__
Tx
direction and P links in the received direction can be moved into the Active
Rx
state before moving the GSM into the Operational state?
IIO.23 Does the implementation ensure that P is greater than zero?
M
M
M
(R-88)
(R-88)
(R-89)
Yes X No__
Yes X No__
Yes X No__
Tx
IIO.24 Does the implementation ensure that P is greater than zero?
Rx
IIO.25 Does the implementation ensure that P and P are equal when the
Tx
Rx
configured in the Symmetrical Configuration and Operation mode?
IIO.26 Does the implementation allow configuration of the value of P ?
O
O
(O-15)
(O-15)
(R-90)
Yes X No__
Yes X No__
Yes X No__
Tx
IIO.27 Does the implementation allow configuration of the value of P
?
Rx
IIO.28 Does the implementation report the Config-Aborted state for at least one
second when the configuration requested by the FE is unacceptable?
M
IIO.29 Does the implementation support the GSM state transitions as defined in 13
on page 60?
M
M
M
M
M
M
M
(R-91)
(R-92)
(R-92)
(R-92)
(R-92)
(R-93)
(R-93)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
IIO.30 Does the implementation determine and report that the group is up when
both the local and remote GSMs are Operational?
IIO.31 Does the implementation determine and report that the group is down when
either the local or the remote GSM is not operational?
IIO.32 Does the implementation report the proper reasons why the GSM is not
operational?
IIO.33 Does the implementation report the highest priority reason according to
Table 14 on page 61?
IIO.34 Does the implementation report the entrance of the GTSM into the Down
state to the UM and ATM Layer Management?
IIO.35 Is the report of the entrance of the GTSM into the Down state the only
notification to the ATM Layer Management about Physical Layer defects or
failures?
IIO.36 Does the implementation report the return of the GTSM to the Up state to
the UM and ATM Layer Management?
M
M
(R-94)
(R-95)
Yes X No__
Yes X No__
IIO.37 Does the implementation ensure it does not drop any ATM layer cells when
adding or recovering links while the GSM is maintained in the Operational
state?
IIO.38 Does the implementation ensure that it does not drop any ATM layer cells
when deleting or inhibiting links while the GSM is maintained in the
Operational state?
M
M
M
(R-96)
(R-97)
(R-98)
Yes X No__
Yes X No__
Yes X No__
IIO.39 When running the group start-up procedure, does the implementation
ensure that all accepted links have their states changed to Tx=Usable in the
same update of the ICP cell?
IIO.40 When running the group start-up procedure and after the Tx state of all
accepted links has been reported in a previous update of the ICP cell, does
the implementation ensure that all accepted links have their states changed
to Rx=Active in the same update of the ICP cell?
IIO.41 When running the group start-up procedure and after the Rx state of all
accepted links has been reported in a previous update of the ICP cell, does
the implementation ensure that all accepted links have their states changed
to Tx=Active in the same update of the ICP cell?
M
(R-99)
Yes X No__
®
28529-DSH-001-K
Mindspeed Technologies
284
Mindspeed Proprietary and Confidential
Appendices
Table 4-6.
IMA Interface Operation (IIO) Functions (4 of 4)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IIO.42 When running the group start-up procedure, does the implementation wait a
minimum of one second, unless all the configured links are being reported
Tx=Usable by FE, before reporting links Rx=Active?
M
(R-100)
Yes X No__
IIO.43 When running the group start-up procedure, does the implementation wait a
minimum of one second, unless all the configured links are being reported
Rx=Active by FE, before reporting links Tx=Active?
M
M
(R-101)
(R-102)
Yes X No__
Yes X No__
IIO.44 Does the implementation synchronize the insertion of new links or
recovered links added using the slow recovery mechanism, defined in
Section 12.1.3.1 on page 74, within the IMA RR?
IIO.45 Does the implementation execute only one LASR procedure per IMA group
at any time (even if more than one link is inserted at the same time)?
M
M
(R-103)
(R-104)
Yes X No__
Yes X No__
IIO.46 Does the implementation delay the insertion of one or more new links or a
possible slow link recovery when the LASR is in progress until the link
addition procedure is completed or aborted?
IIO.47 When running the LASR procedure, does the implementation ensure that all
the inserted links have their states changed to Tx=Usable in the same update
of the ICP?
M
M
(R-105)
(R-106)
Yes X No__
Yes X No__
IIO.48 When running the LASR procedure and after the Tx state of all accepted
links has been reported Usable in a previous update of the ICP cell, does the
implementation ensure that all the inserted links have their states changed
to Rx=Active in the same update of the ICP cell?
IIO.49 When running the LASR procedure and after the Rx state of all accepted
links has been reported Active in a previous update of the ICP cell, does the
implementation ensure that all the inserted links have their states changed
to Tx=Active in the same update of the ICP cell?
M
(R-107)
Yes X No__
IIO.50 When running the LASR procedure, does the implementation wait a
minimum of one second, unless all the inserted links are being reported
Tx=Usable by FE, before reporting links Rx=Active?
M
M
(R-108)
(R-109)
Yes X No__
Yes X No__
IIO.51 When running the LASR procedure, does the implementation wait a
minimum of one second, unless the inserted links are being reported
Rx=Active by FE, before reporting links Tx=Active?
Table 4-7.
IMA Frame Synchronization (IFS) Mechanism Functions (1 of 2)
Cond. for Status
Protocol feature
Item
Ref.
Support
Status
Pred.
IFS.1
Does the implementation perform IMA frame synchronization on each link,
M
(R-110)
Yes X No__
based on the IFSM defined in Figure 19 on page 69 and Table 16 on page
69?
IFS.2
Does the implementation operate the IFSM for each link independently of
any link defects and link delay compensation?
M
(R-111)
Yes X No__
IFS.3
IFS.4
IFS.5
IFS.6
Does the implementation support the default value 2 for Alpha(α)?
Does the implementation support the default value 2 for Beta(β)?
Does the implementation support the default value 1 for Gamma(γ)?
Does the implementation support the value 1 for Alpha(α)?
M
M
M
O
(R-112)
(R-112)
(R-112)
(O-16)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
®
28529-DSH-001-K
Mindspeed Technologies
285
Mindspeed Proprietary and Confidential
Appendices
Table 4-7.
IMA Frame Synchronization (IFS) Mechanism Functions (2 of 2)
Cond. for Status
Protocol feature
Item
Ref.
Support
Status
Pred.
IFS.7
IFS.8
IFS.9
Does the implementation support the value 1 for Beta(β)?
O
O
O
O
O
O
O
O
M
(O-16)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Does the implementation support the value 3 for Beta(β)?
Does the implementation support the value 4 for Beta(β)?
(O-16)
(O-16)
(O-16)
(O-16)
(O-16)
(O-16)
(O-16)
(R-113)
IFS.10 Does the implementation support the value 5 for Beta(β)?
IFS.11 Does the implementation support the value 2 for Gamma(γ)?
IFS.12 Does the implementation support the value 3 for Gamma(γ)?
IFS.13 Does the implementation support the value 4 for Gamma(γ)?
IFS.14 Does the implementation support the value 5 for Gamma(γ)?
IFS.15 Does the implementation assume that any occurrence of HEC/CRC errored
cell in the ICP cell position was an ICP cell?
IFS.16 Does the implementation ignore the cell content of a HEC/CRC errored cell in
the ICP cell position?
M
O
M
O
O
O
(R-113)
(O-17)
(R-114)
(O-18)
(O-18)
(O-19)
Yes X No__
Yes X No__
Yes X No__
IFS.17 Does the implementation go into the Hunt state from any other state when
no longer getting cells from the physical layer?
IFS.18 Does the implementation maintain IMA frame synchronization for cases 1, 2,
3, and 6 identified in Figure 20 on page 71?
IFS.19 Does the implementation maintain IMA frame synchronization for case 4
identified in Figure 20 on page 71?
Yes X No__
Need (O-11)
IFS.20 Does the implementation maintain IMA frame synchronization for case 5
identified in Figure 20 on page 71?
Yes X No__
IFS.21 Does the implementation maintain IMA frame synchronization for case 7
identified in Figure 20 on page 71 when passing stuff indication over more
than one of the previous ICP cells and when Beta(β) is greater than 2?
Yes X No__
Need (O-11)
Comments: (O-11) required to support (O-18) and (O-19).
Table 4-8.
IMA Interface OAM Operation Functions (1 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
OAM.1 Does the implementation report the following link remote defect indicators:
link defects, LIF, and LODS?
M
(R-115)
Yes X No__
OAM.2 If several defects are detected at the same time, does the implementation
report the defect with the highest priority, as listed in Table 17 on page 72?
M
M
(R-116)
(R-117)
Yes X No__
Yes X No__
OAM.3 Does the implementation report any Rx defect to the far-end IMA within the
next 2*M cells to be transmitted after the defect state has been entered as
specified in Section 12.1.3 on page 72 (where M is the M used by the IMA
transmitter)?
OAM.4 Does the implementation perform error handling as specified in Figure 21 on
page 73 and Figure 22 on page 74?
M
M
(R-118)
(R-119)
Yes X No__
Yes X No__
OAM.5 On a given link, does the implementation pass to the ATM layer from the IMA
sublayer any cells accumulated before the occurrence of an OCD or OIF
anomaly on that link?
®
28529-DSH-001-K
Mindspeed Technologies
286
Mindspeed Proprietary and Confidential
Appendices
Table 4-8.
IMA Interface OAM Operation Functions (2 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
OAM.6 Does the implementation inhibit the passing from the IMA sublayer to the
ATM layer of any cells received on a link during an OCD or OIF anomaly
condition reported on that link?
M
(R-120)
Yes X No__
OAM.7 Does the implementation replace with Filler cells all ATM layer cells received
M
(R-121)
Yes X No__
on a link after an OCD or OIF anomaly condition has been detected on that
link?
OAM.8 Does the implementation only report an Rx defect in the backward direction
after LIF or LODS defect state is entered?
M
M
M
M
M
M
M
M
M
M
(R-122)
(R-123)
(R-124)
(R-124)
(R-124)
(R-124)
(R-124)
(R-124)
(R-124)
(R-125)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.9 Does the implementation report the LIF or LODS defect as specified in
Section 12.1.2 on page 72?
OAM.10 Does the implementation detect errored ICP cells as indicated in Table 18 on
page 77?
OAM.11 Does the implementation detect invalid ICP cells as indicated in Table 18 on
page 77?
OAM.12 Does the implementation detect missing ICP cells as indicated in Table 18 on
page 77?
OAM.13 Does the implementation report OIF events as indicated in Table 18 on page
77?
OAM.14 Does the implementation report LIF defects as indicated in Table 18 on page
77?
OAM.15 Does the implementation report LODS defects as indicated in Table 18 on
page 77?
OAM.16 Does the implementation report RDI-IMA defects as indicated in Table 18 on
page 77?
OAM.17 Does the implementation increment IV-IMA for every detected errored,
invalid or missing ICP cell, except during seconds when a SES-IMA or UAS-
IMA condition is reported, as indicated in Table 19 on page 77?
OAM.18 Does the implementation increment OIF-IMA for each reported OIF anomaly,
except during seconds when a SES-IMA or UAS-IMA condition is reported,
as indicated in Table 19 on page 77?
O
M
M
(O-20)
Yes X No__
Yes X No__
Yes X No__
OAM.19 Does the implementation increment SES-IMA for every one second interval
containing ≥ 30% of the ICP cells counted as IV-IMA, as indicated in Table
19 on page 77?
(R-126)
(R-126)
OAM.20 Does the implementation increment SES-IMA for every one interval of one
second containing one or more link defects (e.g., LOS, OOF/LOF, AIS, and
LCD), except during seconds when an UAS-IMA condition is reported, as
indicated in Table 19 on page 77?
OAM.21 Does the implementation increment SES-IMA for every one second interval
containing one or more LIF link defects, except during seconds when an
UAS-IMA condition is reported, as indicated in Table 19 on page 77?
M
M
(R-126)
(R-126)
Yes X No__
Yes X No__
OAM.22 Does the implementation increment SES-IMA for every one second interval
containing one or more LODS link defects, except during seconds when a
UAS-IMA condition is reported, as indicated in Table 19 on page 77?
®
28529-DSH-001-K
Mindspeed Technologies
287
Mindspeed Proprietary and Confidential
Appendices
Table 4-8.
IMA Interface OAM Operation Functions (3 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
OAM.23 Does the implementation increment SES-IMA-FE for every one second
interval containing one or more RDI-IMA defect, except during seconds
when a UAS-IMA-FE condition is reported, as indicated in Table 19 on page
77?
M
(R-127)
Yes X No__
OAM.24 Does the period of NE unavailability begin at the onset of 10 contiguous
SES-IMA (including the first 10 seconds to enter the UAS-IMA condition), as
indicated in Table 19 on page 77?
M
M
M
M
M
M
(R-128)
(R-128)
(R-128)
(R-129)
(R-129)
(R-129)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.25 Does the period of NE unavailability end at the onset of 10 contiguous
seconds with no SES-IMA (excluding the last 10 seconds to exit the UAS-
IMA condition), as indicated in Table 19 on page 77?
OAM.26 Does the implementation increment UAS-IMA for each one second interval
when the UAS-IMA condition is reported, as indicated in Table 19 on page
77?
OAM.27 Does the period of FE unavailability begin at the onset of 10 contiguous SES-
IMA (including the first 10 seconds to enter the UAS-IMA condition), as
indicated in Table 19 on page 77?
OAM.28 Does the period of FE unavailability end at the onset of 10 contiguous
seconds with no SES-IMA-FE (excluding the last 10 seconds to exit the UAS-
IMA-FE condition), as indicated in Table 19 on page 77?
OAM.29 Does the implementation increment UAS-IMA-FE for each one second
interval when the UAS-IMA-FE condition is reported, as indicated in Table 19
on page 77?
OAM.30 Does the implementation increment Tx-UUS-IMA for each second when the
NE Tx LSM is Unusable, as indicated in Table 19 on page 77?
M
M
M
M
M
M
M
M
M
M
O
(R-130)
(R-131)
(R-132)
(R-133)
(R-134)
(R-134)
(R-135)
(R-135)
(R-135)
(R-135)
(O-21)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.31 Does the implementation increment Rx-UUS-IMA for each second when the
NE Rx LSM is Unusable, as indicated in Table 19 on page 77?
OAM.32 Does the implementation increment Tx-UUS-IMA-FE for each second when
the FE Tx LSM is reported Unusable, as indicated in Table 19 on page 77?
OAM.33 Does the implementation increment Rx-UUS-IMA-FE for each second when
the FE Rx LSM is reported Unusable, as indicated in Table 19 on page 77?
OAM.34 Does the implementation increment Tx-FC each time the Tx-Mis-Connected
link failure condition is entered, as indicated in Table 19 on page 77?
OAM.35 Does the implementation increment Tx-FC each time the Tx-Fault link failure
condition is entered, as indicated in Table 19 on page 77?
OAM.36 Does the implementation increment Rx-FC each time the LIF link failure
condition is entered, as indicated in Table 19 on page 77?
OAM.37 Does the implementation increment Rx-FC each time the LODS link failure
condition is entered, as indicated in Table 19 on page 77?
OAM.38 Does the implementation increment Rx-FC each time the Rx-Mis-Connected
link failure condition is entered, as indicated in Table 19 on page 77?
OAM.39 Does the implementation increment Rx-FC each time the Rx-Fault link failure
condition is entered, as indicated in Table 19 on page 77?
OAM.40 Does the implementation increment Tx-FC-FE each time the Tx-Unusable-FE
link failure condition is entered, as indicated in Table 19 on page 77?
®
28529-DSH-001-K
Mindspeed Technologies
288
Mindspeed Proprietary and Confidential
Appendices
Table 4-8.
IMA Interface OAM Operation Functions (4 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
OAM.41 Does the implementation increment Rx-FC-FE each time the RFI-IMA link
failure condition is entered, as indicated in Table 19 on page 77?
O
(O-22)
Yes X No__
OAM.42 Does the implementation increment Rx-FC-FE each time the Rx-Unusable-FE
link failure condition is entered, as indicated in Table 19 on page 77?
O
O
O
(O-22)
(O-23)
(O-24)
Yes X No__
Yes X No__
Yes X No__
OAM.43 Does the implementation increment Tx-Stuff-IMA for each stuff event
inserted in the transmit direction, as indicated in Table 19 on page 77?
OAM.44 Does the implementation increment Rx-Stuff-IMA for each stuff event
detected in the receive direction, except during seconds when a SES-IMA or
UAS-IMA condition is reported, as indicated in Table 19 on page 77?
OAM.45 Does the implementation increment GR-UAS-IMA for each second when the
GTSM is down, as indicated in Table 19 on page 77?
M
M
M
O
(R-136)
(R-137)
(R-137)
(O-25)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.46 Does the implementation increment GR-FC each time the Config-Aborted
group failure condition is entered, as indicated in Table 19 on page 77?
OAM.47 Does the implementation increment GR-FC each time the Insufficient-Links
group failure condition is entered, as indicated in Table 19 on page 77?
OAM.48 Does the implementation increment GR-FC-FE each time the Start-up-FE
group failure condition is entered, as indicated in Table 19 on page 77?
OAM.49 Does the implementation increment GR-FC-FE each time the Config-
Aborted-FE group failure condition is entered, as indicated in Table 19 on
page 77?
O
(O-25)
OAM.50 Does the implementation increment GR-FC-FE each time the Insufficient-
O
(O-25)
Yes X No__
Links-FE group failure condition is entered, as indicated in Table 19 on page
77?
OAM.51 Does the implementation increment GR-FC-FE each the Blocked-FE group
failure condition is entered, as indicated in Table 19 on page 77?
O
O
O
(O-25)
(O-26)
(O-27)
Yes X No__
Yes X No__
Yes__ No X
OAM.52 Does the implementation accumulate IMA performance parameters over 15
minute intervals?
OAM.53 Does the implementation accumulate IMA performance parameters over 24
hour intervals?
OAM.54 Does the implementation keep the current/previous and recent data?
OAM.55 Does the implementation use the current data for threshold crossing?
OAM.56 Does the implementation keep the current/previous and recent data?
OAM.57 Does the implementation use the current data for threshold crossing?
(O-26)
M
M
M
M
M
(CR-7)
(CR-8)
(CR-9)
(CR-10)
(R-138)
Yes X No__
Yes__ No X
Yes__ No X
Yes__ No X
Yes X No__
(O-26)
(O-27)
(O-27)
OAM.58 Does the implementation report a LIF failure alarm for the persistence of a
LIF defect at the NE?
OAM.59 Does the implementation report a LODS failure alarm for the persistence of a
LODS defect at the NE?
M
M
M
M
(R-139)
(R-140)
(R-141)
(R-142)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.60 Does the implementation report a RFI-IMA failure alarm for the persistence
of a RDI-IMA defect at the NE?
OAM.61 Does the implementation report Tx-Mis-Connected failure alarm when the Tx
link is detected as mis-connected?
OAM.62 Does the implementation report Rx-Mis-Connected failure alarm when the
Rx link is detected as mis-connected?
®
28529-DSH-001-K
Mindspeed Technologies
289
Mindspeed Proprietary and Confidential
Appendices
Table 4-8.
IMA Interface OAM Operation Functions (5 of 5)
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
OAM.63 Does the implementation report a Tx Fault failure alarm for any
implementation specific Tx fault declared at the NE?
O
(O-28)
Yes X No__
OAM.64 Does the implementation report a Rx Fault failure alarm for any
implementation specific Rx fault declared at the NE?
O
M
M
M
(O-29)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.65 Does the implementation report a Tx-Unusable-FE failure alarm when it
receives Tx-Unusable from FE?
(R-143)
(R-144)
(R-145)
OAM.66 Does the implementation report a Rx-Unusable-FE failure alarm when it
receives Rx-Unusable from FE?
OAM.67 Does the implementation report a Start-up-FE failure alarm when it receives
this signal from FE (the declaration of this failure alarm may be delayed to
ensure the FE remains in Start-up)?
OAM.68 Does the implementation report a Config-Aborted failure alarm when the FE
tries to use unacceptable configuration parameters?
M
M
M
M
(R-146)
(R-147)
(R-148)
(R-149)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.69 Does the implementation report a Config-Aborted-FE failure alarm when the
FE reports unacceptable configuration parameters?
OAM.70 Does the implementation report an Insufficient-Links failure alarm when less
than P transmit links or P receive links are active?
Tx
Rx
OAM.71 Does the implementation report an Insufficient-Links-FE failure alarm when
the FE reports that less than P transmit links or P receive links are
Tx
Rx
active?
OAM.72 Does the implementation report a Blocked-FE failure alarm when the FE
reports that it is blocked?
M
M
M
(R-150)
(R-151)
(R-152)
Yes X No__
Yes X No__
Yes X No__
OAM.73 Does the implementation report GR-Timing-Mismatch when the FE transmit
clock mode is different than the NE transmit clock mode?
OAM.74 In the case of the LIF, LODS, RFI-IMA and Fault failure alarms, does the
implementation support 2.5 0.5 seconds as a default persistence checking
time to enter a failure alarm condition?
OAM.75 In the case of the LIF, LODS, RFI-IMA and Fault failure alarms, does the
implementation support 10 0.5 seconds as a default persistence clearing
time to exit the failure alarm condition?
M
O
(R-152)
(O-30)
Yes X No__
Yes X No__
Yes X No__
Yes X No__
OAM.76 In the case of the LIF, LODS, RFI-IMA and Fault failure alarms, does the IMA
allow configuration of other values for default persistence checking time to
enter a failure alarm condition?
OAM.77 In the case of the LIF, LODS, RFI-IMA and Fault failure alarms, does the IMA
allow configuration of other values for default persistence checking time to
exit the same failure alarm condition?
O
(O-30)
OAM.78 Does the implementation ensure that the Tx-Fault failure alarm, as defined in (O-28)
(O-28) on page 79, is not cleared until the fault that led to the declaration of
the alarm is no longer present for the duration specified to clear the alarm in
(R-152) on page 80?
M
(CR-11)
OAM.79 Does the implementation ensure that the Rx-Fault failure alarm, as defined in (O-29)
(O-29) on page 79, is not cleared until the fault that led to the declaration of
the alarm is no longer present for the duration specified to clear the alarm in
(R-152) on page 80?
M
(CR-12)
Yes X No__
Comments: 24 hour PM intervals require external software. No threshold crossing feature in driver. Link Fault failures are not defined in standard.
®
28529-DSH-001-K
Mindspeed Technologies
290
Mindspeed Proprietary and Confidential
Appendices
Table 4-9.
Test Pattern Procedure (TPP) Functions
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
TPP.1
TPP.2
Does the implementation activate the Test Pattern procedure in the transmit
direction?
O
(O-31)
Yes X No__
Does the implementation use the Test Link Command field in the ICP cell (as
defined in the Tx Test Control field in Table 2 on page 31) to request the FE to
activate the loop back of the test pattern contained in the Tx Test Pattern
field?
(O-31)
M
(CR-12)
Yes X No__
TPP.3
TPP.4
TPP.5
Does the implementation use the Tx LID field defined in the Tx Test Control
field in Table 2 on page 31 to identify to the FE which transmit link the FE
should extract the Tx Test Pattern from in the received ICP cells?
(O-31)
(O-31)
(O-31)
M
M
M
(CR-12)
(CR-12)
(CR-12)
Yes X No__
Yes X No__
Yes X No__
Does the implementation send any changed values of the Test Link
Command, Tx LID and Tx Test Pattern fields in ICP cells for at least 2
consecutive IMA frames over each link within the IMA group?
Does the implementation continue to send the same values of the Test Link
Command, Tx LID and Tx Test Pattern fields as long as the IMA transmitter
wants the FE IMA unit to loop back the test pattern?
TPP.6
TPP.7
Does the implementation monitor the incoming ICP cells on the links already
recognized in the group to detect a change of the Test Link Command?
M
M
(R-153)
(R-154)
Yes X No__
Yes X No__
If the Test Link Command field is detected as active over the links already
recognized in the group and over the test link, does the implementation copy
the value of the Tx Test Pattern field received from the test link, indicated
over the Tx LID field, into the Rx Test Pattern field on every subsequent ICP
cell sent over all outgoing links in the group?
TPP.8
TPP.9
Does the implementation continue sending the same value over the Rx Test
Pattern field until the IMA transmitter has received an indication to stop
looping the pattern, to loop a new pattern received from the same link over
the Tx Test Pattern, or to loop the test pattern received from another link
(indicated over the Tx LID field)?
M
(R-155)
Yes X No__
Does the implementation return the “0xFF” pattern over the Rx Test Pattern
field when the incoming test command is inactive or the test link is not
detected?
M
M
(R-156)
(R-157)
Yes X No__
Yes X No__
TPP.10 Does the implementation only handle one test pattern per IMA group at any
given time?
Comments:
®
28529-DSH-001-K
Mindspeed Technologies
291
Mindspeed Proprietary and Confidential
Appendices
Table 4-10. IMA Interaction with Plane Management Functions
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
IPM.1 Does the implementation process IMA group configuration indications
received from the Plane Management?
M
(R-158)
Yes X No__
IPM.2 Does the implementation process IMA link addition/deletion indications
received from the Plane Management?
M
M
M
(R-158)
(R-158)
(R-158)
Yes X No__
Yes X No__
Yes X No__
IPM.3 Does the implementation send IMA service operational status change
indications to the Plane Management?
IPM.4 Does the implementation send Tx/Rx cell rate change indications to the
Plane Management?
Comments: Plane Management software required to interface with driver API.
Table 4-11. Management Information Base (MIB) Functions
Cond. for Status
Item
Protocol feature
Ref.
Support
Status
Pred.
MIB.1
MIB.2
Does the implementation support a UM based on SNMP?
O
(O-32)
Yes X No__
Yes__ No X
Does the implementation implement the mandatory objects in the IMA-MIBs
defined in Appendix A on page 106?
(O-32)
(O-32)
M
(CR-17)
MIB.3
Does the implementation implement the optional objects in the IMA MIBs
defined in Appendix A on page 106?
O
(O-33)
Yes__ No X
Comments: Support for MIB objects implemented. Requires SNMP agent software to create MIB using driver API.
4.1.6
PICS Proforma References
1. The ATM Forum, AF-PHY-0086.001, Inverse Multiplexing for ATM (IMA) Specification Version 1.1.
2. ISO/IEC 9646-1: 1990, Information technology - Open systems interconnection - Conformance testing
methodology and framework - Part 1: General concepts (See also ITU-T Recommendation X.290 (1991)).
3. ISO/IEC 9646-2: 1990, Information technology - Open systems interconnection - Conformance testing
methodology and framework - Part 2: Abstract test suite specification (See also ITU-T Recommendation X.291
(1991)).
4. ITU-T Recommendation I.432 Series, “B-ISDN User-Network Interface - Physical Layer Specification”, April
1996.
5. ITU-T Recommendation I.610, “B-ISDN Operation and Maintenance Principles and Functions”, 1995.
4.2
Boundary Scan
Please contact Mindspeed for information and files for Boundary Scan.
®
28529-DSH-001-K
Mindspeed Technologies
292
Mindspeed Proprietary and Confidential
Appendices
4.3
Power Sequencing
The VGG pin provides ESD protection when interfacing with 5V systems. VGG must be connected to 5V for 5V I/O
tolerance. When 5V tolerance is not required it is recommended that VGG be tied to the same power supply as
VDD33.
During power up and power down the designer should take caution as VGG should not exceed VDD33 by more
than 3.6V, except for short durations identified in the note below. VGG must never be less than VDD33 by more
than 0.5V.
VGG can exceed VDD33 by up to 5V ( 10%) for short durations of less than 10 ms.
VGG must never be less than VDD33 by more than 0.5V.
NOTE:
®
28529-DSH-001-K
Mindspeed Technologies
293
Mindspeed Proprietary and Confidential
www.mindspeed.com
General Information:
Telephone: (949) 579-3000
Headquarters - Newport Beach
4000 MacArthur Blvd., East Tower
Newport Beach, CA 92660
®
© 2006 Mindspeed Technologies , Inc. All rights reserved.
®
®
Information in this document is provided in connection with Mindspeed Technologies ("Mindspeed ") products.
These materials are provided by Mindspeed as a service to its customers and may be used for informational
purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any
separate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes
no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and
product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and
shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its
specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL
DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR
COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE
MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS,
WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed
customers using or selling Mindspeed products for use in such applications do so at their own risk and agree to
fully indemnify Mindspeed for any damages resulting from such improper use or sale.
®
28529-DSH-001-K
Mindspeed Technologies
294
Mindspeed Proprietary and Confidential
相关型号：
©2020 ICPDF网 联系我们和版权申明