28500-DSH-002-C_15_技术文档

CX28500

Multichannel Synchronous

Communications Controller

Data Sheet

®

28500-DSH-002-C

Mindspeed Technologies

October 2006

Mindspeed Proprietary and Confidential

Ordering Information

Model Number

Package

Operating Temperature

CX28500EBG

35 mm TBGA

–40 – 85 °C

^{–40 – 85}°C

CX28500G-12*

35 mm TBGA

(RoHS compliant)

*The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information.

Revision History

Revision

Level

Date

Description

500052A

500052B

—

July 2001

February 2002

July 2002

Created.

Updated to Revision B.

500052C

Updated to Revision C.

28500-DSH-002-A

28500-DSH-002-B

28500-DSH-002-C

November 2002

June 2004

Formerly document number 500052D.

Updated and made various corrections.

October 2006

Added RoHS information.

Updated format.

®

28500-DSH-002-C

Mindspeed Technologies

ii

Mindspeed Proprietary and Confidential

CX28500

Multichannel Synchronous Communications Controller

The CX28500 is an advanced Multichannel Synchronous

Communications Controller. It formats and deformats up to 1024 High-

Distinguishing Features

ꢀ

1024-channel HDLC controller

OSI Layer 2 protocol support

General purpose HDLC (ISO 3309)

ꢁ X.25 (LAPB)

level Data Link Control (HDLC) channels in a CMOS integrated circuit.

CX28500 operates at Layer 2 of the Open Systems Interconnection (OSI)

protocol reference model. It provides a comprehensive, high-density

solution for processing of HDLC channels for internetworking applications

such as Frame Relay, Integrated Services Digital Network (ISDN), D-

channel signaling, X.25, Signaling System 7 (SS7), Data Exchange

Interface (DXI), Inter System Link Protocol (ISLP), and LAN/WAN data

transport. Under minimal Host supervision, CX28500 manages table-like

data structures of channel data buffers in Host memory by performing

Direct Memory Access (DMA) of up to 1024 channels.

ꢁ Frame relay (LAPF/ANSI T1.618)

ꢁ ISDN D-channel (LAPD/Q.921)

ꢁ ISLP support

32 Independent serial interfaces, which

support:

ꢀ

ꢁ Mixed Data Rates (combination of T1/E1/

T3/E3, etc.) as long as they do not exceed

each port’s respective bandwidth

limitation and the overall device

bandwidth of 390 Mbps per direction

ꢁ 32 T1/E1 data streams

CX28500 interfaces to 32 independent serial data streams, such as T1/E1

signals. It then transfers data across the popular 32-bit or 64-bit Peripheral

Component Interface (PCI) bus to system memory at a rate up to 66 MHz.

The CX28500 has an aggregate data throughput of 390 Mbps. Each serial

interface can be operated up to 13.0 MHz. Six Serial Interfaces can be

operated at rates up to 52 MHz. Logical channels can be mapped as any

combination of Digital Signal Level 0 (DS0) time slots to support ISDN

hyperchannels (N x 64 Kbps). Additionally, logical channels can operate in

ꢁ 6 HSSI interfaces (52 Mbps)

ꢁ DC to 13.0 Mbps serial interfaces

ꢁ 32 x 8.192 MHz TDM busses

Configurable logical channels

ꢁ Standard DS0 (56, 64 Kbps)

ꢁ Subchanneling (N x 8 Kbps)

ꢀ

subchanneling mode (N x 8 Kbps) by mapping a combination of DS0 time ꢁ Hyperchannel (N x 64 Kbps)

ꢁ Unchannelized mode

Per-channel protocol mode selection

ꢁ Non-FCS mode

ꢁ 16-bit FCS mode

ꢁ 32-bit FCS mode

slots and/or the individual bits of a DS0 time slot (8 bits). For example, a

56 Kbps channel can be achieved by mapping 7 bits out of 8 possible bits

in a time slot (7 x 8 Kbps = 56 Kbps). CX28500 also includes a 32-bit

expansion port for bridging the PCI bus to local microprocessors or

peripherals. A Joint Test Action Group (JTAG) port enables boundary-

scan testing to replace bed-of-nails board testing.

ꢀ

ꢁ Transparent mode (unformatted data)

Hardware Flow Control (CTS)

Selectable Endian configuration on data

Per-channel DMA buffer management

ꢁ Table-like data structures

ꢁ Variable size transmit/receive FIFO

ꢀ

Functional Block Diagram

HOST

Interface

(PCI)

0

Rx Line

Processor

RSLP

ꢀ

Per-channel message length check

ꢁ Select no length checking

Device

Configuration

Registers

ꢁ Select from three 14-bit registers to

compare message length

Serial

Interface

Unit

TSBUS

or

PCM

RxDMA

and

TxDMA

Direct PCI bus interface

PCI

Interface

ꢁ 32/64-bit, 33/66 MHz operation

ꢁ Bus master and slave operation

ꢁ PCI Version 2.1

Host back-to-back transaction over the PCI

HSSI interfaces (52 Mbps)

Local expansion bus interface (EBUS)

ꢁ 32-bit multiplexed address/data bus

TSBUS

Support of 64-bit ECC host memory

Low power, 3.3 V CMOS operation

JTAG boundary scan access port

35 mm x 35 mm 580-pin BGA

(SIU)

Highway

Tx Line

Processor

TSLP

PCI

Configuration

Space

ꢀ

(Function 0)

31

ꢀ

Test

EXP BUS

Local BUS

JTAG

Access

Available in Green (RoHS compliant) as well

as standard version

®

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iii

Mindspeed Proprietary and Confidential

Table of Contents

Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 CX28500’s Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.2 CX28500 Serial Port Throughput Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3 CX28500’s Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.3.1

1.3.2

1.3.3

PCI—Peripheral Components Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

EBUS—Local Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

TSBUS—Time Slot Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.4 CX28500 Layering Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.5 CX28500’s Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.6 CX28500 Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.6.1

1.6.2

1.6.3

1.6.4

1.6.5

T1/T3 WAN Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

T3/E3 Frame Relay Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

128 Port DSL Access Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

SONET/SDH Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Line Card SONET/ATM SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.7 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.8 System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.9 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

1.10 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.11 Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.12 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

1.13 CX28500 Hardware Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.0 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.1 Serial Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

2.2 Serial Line Processor (SLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

2.3 Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2.3.1

General Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

2.4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.0 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.1 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

®

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iv

Mindspeed Proprietary and Confidential

Table of Contents

3.1.1

3.1.2

3.1.3

PCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

PCI Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Fast Back-to-Back Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

3.1.3.1

Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

3.1.3.2

Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back Transactions . .43

3.1.4

PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

3.2 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

3.2.1

PCI Master and Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

3.2.1.1

3.2.1.2

3.2.1.3

3.2.1.4

3.2.1.5

3.2.1.6

3.2.1.7

Register 0, Address 00h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Register 1, Address 04h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Register 2, Address 08h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Register 3, Address 0Ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Register 4, Address 10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Register 5–14, Address 14h–38h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Register 15, Address 3Ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

3.2.2

3.2.3

3.2.4

PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

PCI Throughput and Latency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Host Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.0 Expansion Bus (EBUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 EBUS—Operational Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.1.6

4.1.7

4.1.8

4.1.9

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Address Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Data Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Bus Access Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

PCI to EBUS Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

4.1.10 Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

4.1.10.1 Multiplexing Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

5.0 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.1 Serial Port Interface Definition in Conventional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Frame Synchronization Flywheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Change Of Frame Alignment (COFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Out Of Frame (OOF)/Frame Recovery (FREC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

General Serial Port Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Channel Clear To Send (CTS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

5.2 Serial Port Interface Definition in TSBUS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

5.2.1

5.2.2

5.2.3

5.2.4

TSBUS Frame Synchronization Flywheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

TSBUS Change Of Frame Alignment (COFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

TSBUS Out Of Frame (OOF)/Frame Recovery (FREC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

TSBUS Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

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Table of Contents

5.2.5

5.2.6

5.2.7

5.2.8

5.2.9

TSBUS Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

TSBUS Channel Clear To Send. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

TSBUS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Payload TSBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Overhead TSBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5.2.9.1

Overhead Data Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

5.2.9.2

TSBUS Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

6.0 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1 Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

6.1.1

Register Map and Shared Memory Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

6.2 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

6.2.1

Service Request Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

6.2.1.1

Service Request Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

6.2.1.2

Service Request Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

6.2.2

6.2.3

6.2.4

Port Alive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Soft Chip Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

General PCI Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

6.3 Interrupt Level Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

6.3.1 Interrupt Queue Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

6.3.1.1

6.3.1.2

6.3.1.3

Interrupt Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Interrupt Status Descriptor Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

6.4 Global Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

6.5 EBUS Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

6.6 Receive Path Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

RSLP Channel Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

RSLP Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

RDMA Buffer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

RDMA Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

RSIU Time Slot Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

6.6.5.1

Time Slot Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

6.6.5.2

RSIU Time Slot Configuration Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

6.6.6

RSIU Time Slot Pointer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

6.6.6.1 Time Slot Allocation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

6.6.7

6.6.8

RSIU Port Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

RSLP Maximum Message Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

6.7 Transmit Path Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

6.7.1

6.7.2

6.7.3

6.7.4

6.7.5

TSLP Channel Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

TSLP Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

TDMA Buffer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

TDMA Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

TSIU Time Slot Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

6.7.5.1

Time Slot Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

6.7.5.2

TSIU Time Slot Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

6.7.6

TSIU Time Slot Pointer Assignment Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

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Table of Contents

6.7.6.1

Time Slot Allocation Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

6.7.7

TSIU Port Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

6.8 Receive and Transmit Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

6.8.1

6.8.2

6.8.3

Transmit Message Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

6.8.1.1 Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Receive Message Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

6.8.2.1 Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

6.8.3.1

Transmit Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

6.8.3.2

Receive Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

6.8.4

6.8.5

6.8.6

6.8.7

6.8.8

Head Pointer Table and Its Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Message Descriptor (MD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Buffer Status Descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Data Buffer Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

7.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

7.1.1

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

7.1.1.1

Hard PCI Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

7.1.1.2

Soft Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

7.1.2

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

7.1.2.1

7.1.2.2

7.1.2.3

7.1.2.4

7.1.2.5

7.1.2.6

PCI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Service Request Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Global and EBUS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Interrupt Queue Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Channel and Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

Typical Initialization Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

7.2 Channel Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

7.2.1

7.2.2

7.2.3

Channel Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

7.2.1.1

Transmit Channel Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

7.2.1.2

Receive Channel Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Channel Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

7.2.2.1

Transmit Channel Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

7.2.2.2

Receive Channel Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Channel Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

7.2.3.1

Receive Channel Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

7.2.3.2

Transmit Channel Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

7.2.4

7.2.5

Channel Reactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Unmapped Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

8.0 Basic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.1 Protocol-Independent Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

8.1.1

8.1.2

Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

8.2 HDLC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

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8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

Frame Check Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Opening/Closing Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Abort Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Zero-Bit Insertion/Deletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Message Configuration Bits–HDLC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

8.2.5.1

8.2.5.2

8.2.5.3

Idle Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Inter-Message Pad Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Ending a Message with an Abort or Sending an Abort Sequence . . . . . . . . . . . . . . . . . . . . .132

8.2.6

8.2.7

Transmit Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

8.2.6.1

8.2.6.2

8.2.6.3

End Of Buffer [EOB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

End Of Message [EOM] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

ABORT Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Receive Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

8.2.7.1

8.2.7.2

8.2.7.3

8.2.7.4

8.2.7.5

8.2.7.6

End Of Buffer [EOB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

End Of Message (EOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Change to Abort Code (CHABT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Change to Idle Code (CHIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Frame Recovery (FREC) or Generic Serial PORT (SPORT) Interrupt . . . . . . . . . . . . . . . . . .134

Receive COFA Recovery (RCREC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

8.2.8

8.2.9

Transmit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

8.2.8.1

8.2.8.2

8.2.8.3

Transmit Underrun [BUFF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Transmit Change Of Frame Alignment (COFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Transmit COFA Recovery (TCREC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Receive Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

8.2.9.1

8.2.9.2

8.2.9.3

8.2.9.4

8.2.9.5

8.2.9.6

8.2.9.7

8.2.9.8

Receive Overflow [BUFF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Receive Change Of Frame Alignment (COFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Out Of Frame (OOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Frame Check Sequence (FCS) Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Octet Alignment Error (ALIGN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Abort Termination (ABT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Long Message (LNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Short Message (SHT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

8.3 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

8.3.1

Message Configuration Bits–Transparent Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

8.3.1.1

8.3.1.2

8.3.1.3

Idle Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Inter-Message Pad Fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Ending a Message with an Abort or Sending an Abort Sequence . . . . . . . . . . . . . . . . . . . . .141

8.3.2

8.3.3

Transmit Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

8.3.2.1

End Of Buffer [EOB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

8.3.2.2

End Of Message [EOM] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Receive Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

8.3.3.1

8.3.3.2

8.3.3.3

End Of Buffer [EOB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

End Of Message (EOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Frame Recovery (FREC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

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8.3.3.4

Receive COFA Recovery (RCREC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

8.3.4

8.3.5

Transmit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

8.3.4.1

Transmit Underrun [BUFF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

8.3.4.2

Transmit Change Of Frame Alignment (COFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Receive Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

8.3.5.1

8.3.5.2

8.3.5.3

8.3.5.4

Receive Overflow [BUFF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Receive Change Of Frame Alignment (COFA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Out Of Frame (OOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Short COFA (SHT COFA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

9.0 Self-Servicing Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.0 Electrical and Mechanical Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

10.1 Electrical and Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

10.1.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.1.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

10.1.4 Power-up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.2 Timing and Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.2.2 Host Interface (PCI) Timing and Switching Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

10.2.3 Expansion Bus (EBUS) Timing and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

10.2.4 EBUS Arbitration Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

10.2.5 Serial Interface Timing and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

10.2.6 Test and Diagnostic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

10.3 Package Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

10.4 Mechanical Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

Appendix A: CX28500 PCI Bus Latency and Utilization Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

A.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

A.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

A.3 Assumptions/Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

A.4 PCI Transaction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

A.4.1

A.4.2

Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

A.5 Receive Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

A.6 Transmit Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

A.7 Allocation of Internal SLP Buffer (FIFO) Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

A.8 Maximum Feasible PCI Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

A.9 Maximum Endurable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

A.10 PCI Bus Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

A.11 Maximum Tolerable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

A.12 Other Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

A.13 Summary and Explanation of Terms Used in Calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

A.14 Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

A.15 Differences in the Combined T1 Payload and Overhead Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

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Appendix B: Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back Transactions. 182

Appendix C: T3 Frame Relay Switch Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Appendix D: Example of Little-Big Endian Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Appendix E: TSBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

E.1 Connection Between CX28500 and Other TSBUS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

E.1.1

VSP Mapping of Intermixed Digital Level 2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

E.2 Timing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

E.2.1

E.2.2

E.2.3

Payload Bus, AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197

Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

E.3 Overhead Bus, AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

E.3.1

E.3.2

Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

E.4 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

Appendix F: Notation, Acronyms, Abbreviations, and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

F.1 Radix Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

F.2 Bit Stream Convention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

F.3 Acronyms, Abbreviations, and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

F.3.1

F.3.2

Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Appendix G: Scope of Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

G.1 Applicable Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

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Figure 1-1. CX28500 as a Data Link Layer Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Figure 1-2. Mid-Range Router Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Figure 1-3. High-Range Router Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Figure 1-4. DSLAM or IAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Figure 1-5. Gigabit Router Line Card for OC-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Figure 1-6. Line Card SONET/ATM SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Figure 1-7. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Figure 1-8. CX28500 Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Figure 1-9. Pin Configuration Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Figure 2-1. Serial Interface Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

Figure 3-1. Host Interface Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41

Figure 3-2. Address Lines During Configuration Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

Figure 4-1. EBUS Functional Block Diagram with Local MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51

Figure 4-2. EBUS Functional Block Diagram without Local MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52

Figure 4-3. EBUS Connection, Non-Multiplexed Address/Data, 8 Framers, No Local MPU . . . . . . . . . . . . . . . . . . . . . . . . . 4-57

Figure 4-4. EBUS Connection, Non-Multiplexed Address/Data, 16 Framers, No Local MPU . . . . . . . . . . . . . . . . . . . . . . . . 4-58

Figure 4-5. EBUS Connection, Multiplexed Address/Data, 8 Framers, No Local MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

Figure 4-6. EBUS Connection, Multiplexed Address/Data, 4 Framers, No Local MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

Figure 5-1. RDMA State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64

Figure 5-2. TDMA State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65

Figure 5-3. TSBUS Number of Time Slots into a Payload or Overhead Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-69

Figure 6-1. Interrupt Notification to Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89

Figure 6-2. Transmit Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108

Figure 6-3. Receive Message Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109

Figure 10-1. PCI Clock (PCLK) Waveform, 3.3 V Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-152

Figure 10-2. PCI Output Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-154

Figure 10-3. PCI Input Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-154

Figure 10-4. EBUS Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155

Figure 10-5. EBUS Output Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-156

Figure 10-6. EBUS Input Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-156

Figure 10-7. EBUS Write/Read Cycle, Intel-Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-157

Figure 10-8. EBUS Write/Read Cycle, Motorola-Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-158

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Figure 10-9. Serial Interface Clock (RCLK,TCLK) Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-159

Figure 10-10.Serial Interface Data Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-160

Figure 10-11.Serial Interface Data Delay Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-161

Figure 10-12.Transmit and Receive T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-162

Figure 10-13.Transmit and Receive Channelized non T1 (i.e., N x 64) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-163

Figure 10-14.JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-164

Figure 10-15.580-Pin BGA Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-166

Figure B-1. PCI Burst Write: Two 64-bit Fast Back-to-Back Transactions to Same Target . . . . . . . . . . . . . . . . . . . . . . . . . B-182

Figure B-2. PCI Burst Write: Two 32-bit Fast Back-to-Back Transactions to Same Target . . . . . . . . . . . . . . . . . . . . . . . . . B-183

Figure B-3. PCI Burst Read: Two 64-bit Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-184

Figure B-4. PCI Burst: Two 32-bit Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-185

Figure B-5. PCI Burst Write Followed by Burst Read: Fast Back-to-Back to Same Target . . . . . . . . . . . . . . . . . . . . . . . . . B-186

Figure B-6. PCI Burst Read Followed by Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-187

Figure C-1. High-End Router Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-188

Figure C-2. DS3/E3 Line Unit Interface Connection with T3/E3 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-189

Figure C-3. T3/E3 Framer Connection with HDLC Controller (T3/E3 Payload Path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-189

Figure C-4. T3/E3 Framer Connection with HDLC Controller (T3/E3 Overhead Path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-190

Figure E-1. CX28500 Time Slot Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-193

Figure E-2. Source/Destination of TSBUS Block Line-Side Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-195

Figure E-3. Payload Time Slot Bus Transmit Data (TSB_TDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-198

Figure E-4. Payload Time Slot Bus Transmit Stuff Indicator (TSB_TSTUFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-199

Figure E-5. Payload Time Slot Bus Receive Data (TSB_RDAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-200

Figure E-6. Payload Time Slot Bus Receive Stuff Indicator (TSB_RSTUFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-200

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Table 1-1. Supported Serial Port Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Table 1-2. Allowed CX28500 Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Table 1-3. Data Path Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Table 1-4. Examples of Serial Port Configurations With 33 MHz PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Table 1-5. Examples of Serial Port Configurations With 66 MHz PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Table 1-6. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Table 1-7. I/O Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Table 1-8. CX28500 Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

Table 3-1. PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44

Table 3-2. Register 0, Address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45

Table 3-3. Register 1, Address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

Table 3-4. Register 2, Address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48

Table 3-5. Register 3, Address 0Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48

Table 3-6. Register 4, Address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

Table 3-7. Register 5-14, Address 14h–38h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

Table 3-8. Register 15, Address 3Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

Table 4-1. EBUS Service Request Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53

Table 4-2. EBUS Service Request Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53

Table 6-1. PCI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71

Table 6-2. Indirect Register Map Address Accessible via Service Request Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71

Table 6-3. Service Request Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73

Table 6-4. Service Request Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73

Table 6-5. Service Request Descriptor—OPCODE Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-74

Table 6-6. Device Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76

Table 6-7. Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76

Table 6-8. EBUS Configuration Service Request Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77

Table 6-9. Field Descriptions of ECD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-77

Table 6-10. Channel Configuration Service Request Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78

Table 6-11. Fields Description of CCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-78

Table 6-12. Receive Port Alive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-79

Table 6-13. Transmit Port Alive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-79

Table 6-14. Interrupt Queue Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81

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Table 6-15. Interrupt Queue Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81

Table 6-16. Interrupt Queue Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-81

Table 6-17. DMA Interrupt Descriptors Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-83

Table 6-18. Non-DMA Interrupt Descriptors Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-84

Table 6-19. Interrupt Status Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-86

Table 6-20. Global Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-89

Table 6-21. EBUS Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-91

Table 6-22. RSLP Channel Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92

Table 6-23. RSLP Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-92

Table 6-24. RDMA Buffer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-94

Table 6-25. RDMA Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-94

Table 6-26. RSIU Time Slot Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96

Table 6-27. RSIU Time Slot Pointer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97

Table 6-28. RSIU Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97

Table 6-29. Maximum Message Length Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100

Table 6-30. TSLP Channel Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-100

Table 6-31. TSLP Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-101

Table 6-32. TDMA Buffer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-102

Table 6-33. TDMA Channel Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-102

Table 6-34. TSIU Time Slot Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104

Table 6-35. TSIU Time Slot Pointers Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105

Table 6-36. TSIU Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-105

Table 6-37. Transmit and Receive Base Address Head Pointer (TBAHP and RBAHP) Content . . . . . . . . . . . . . . . . . . . . . . 6-111

Table 6-38. Transmit and Receive Head Pointer Table (THPT and RHPT) Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-111

Table 6-39. Transmit or Receive Message Descriptor Table (TMDT) or (RMDT) Content . . . . . . . . . . . . . . . . . . . . . . . . . 6-112

Table 6-40. Transmit Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113

Table 6-41. Receive Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-114

Table 6-42. Transmit Buffer Status Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115

Table 6-43. Receive Buffer Status Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-116

Table 6-44. Data Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-117

Table 6-45. Data Buffer Pointer in PCH Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-118

Table 10-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-149

Table 10-2. Recommended 3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-150

Table 10-3. DC Characteristics for 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-150

Table 10-4. PCI Interface DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-151

Table 10-5. PCI Clock (PCLK) Waveform Parameters, 3.3 V Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-152

Table 10-6. PCI Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153

Table 10-7. PCI Input/Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153

Table 10-8. PCI I/O Measure Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153

Table 10-9. EBUS Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155

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Table 10-10. EBUS Input/Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155

Table 10-11. EBUS Input/Output Measure Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-156

Table 10-12. Serial Interface Clock (RCLK, TCLK) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-159

Table 10-13. Serial Interface Input/Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-159

Table 10-14. Serial Interface Input/Output Measure Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-160

Table 10-15. Test and Diagnostic Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-164

Table 10-16. Test and Diagnostic Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-164

Table 10-17. CX28500 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-165

Table A-1. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-173

Table A-2. Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-173

Table A-3. Calculated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-173

Table A-4. Including Spare Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-174

Table A-5. Non –“Spare Time” Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-175

Table A-6. Example One . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-176

Table A-7. Example Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-177

Table A-8. Example Three . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-180

Table D-1. Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-191

Table D-2. Big Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-191

Table E-1. System Side Interface: Payload Time Slot Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-193

Table E-2. System Side Interface: Overhead Time Slot Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-194

Table E-3. System Side Interface: Overhead Time Slot Bus Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-195

Table E-4. VSP Mapping of Intermixed Digital Level 2 Signals Containing Either DS1 or E1 Signals . . . . . . . . . . . . . . . . E-196

Table E-5. Transmit Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-199

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1.0 Introduction

The CX28500 HDLC controller (CX28500) is a 1024-channel communications controller that operates at Layer 2 of

the Open System Interconnection (OSI) protocol reference. It provides a comprehensive, high density solution for

HDLC channels for internetworking applications.

•

HDLC/SDLC

LAPB, LAPD

Digital Access Cross-Connect (DAC)

Frame Relay Switches and Access Devices (FRAD)

ISDN-D channel signalling

X.25

SMDS/ATM DXI

LAN/WAN access data

SONET/SDH add/drop multiplexers (ADMs)

Terminal multiplexers (TMs)

High Range/Gigabit Routers

CX28500 interfaces to 32 independent serial data streams such as T1/E1, T3/E3, STS-1/STM-1, and DS3. It

signals and transfers data across the high performance 32/64-bit Peripheral Component Interface (PCI) bus to

system memory at a rate up to 66 MHz. Each serial port can be configured to support different types of interfaces.

All of the CX28500’s serial ports are individually programmable to operate as conventional or TSBUS serial ports.

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1.1

CX28500’s Operational Modes

Table 1-1 explains the CX28500’s supported serial port mode.

Table 1-1.

Supported Serial Port Modes

CX28500 Serial Port Modes

Description

(1)

Conventional Unchannelized

In this mode, Transmit Synchronization (TSYNC) and Receive Synchronization (RSYNC) are ignored. The

serial input/output data stream is a bit-stream without framing or alignment. The bit-stream belongs to a

single logical channel. The CX28500 conventional, unchannelized mode can operate up to 13 Mbps for all 32

serial ports. The first six ports can operate unchannelized T3/E3, HSSI, or STS-1/STM-1 bit-stream up to 52

Mbps per serial interface (for reference, see Section 1.2).

(1)(2)

Conventional Channelized

The serial bit-stream is treated as a frame of N time slots (where N is less than or equal to 4096, given that

other restrictions are met). The maximum bandwidth embedded into the PCM highway for the first six ports

is STS-1 rate (51.84 Mbps). The byte and frame synchronization performed is based on receive and transmit

sync pulse (RSYNC and TSYNC). (For a detailed description of these signals, see Chapter 5.0.)

(1)

Conventional T1 mode

The serial bit-stream is treated as a frame of N time slots (where N has the same meaning as in channelized

mode). If the serial port is configured in T1 mode then the port operates according to the T1 framing

definition (i.e., 24 time slots, where the first bit is the F-bit). The difference between channelized mode and

T1 mode is that in T1 mode, the F-bit of the T1 frame is masked off and is dropped on input, and is

generated for the output (for proper timing only—a T1 framer is needed to generate the correct F-bit).

(2)(3)

TSBUS

The TSBUS serial interface bit-stream is treated as a frame of N time slots (where N is defined as greater

than or equal to 6, and the aggregate number of time slots across all ports in any direction does not exceed

the 4096 available time slots in each direction, receive or transmit) or variable bandwidth time slots called

Virtual Serial Ports (VSPs). Byte synchronization and frame synchronization is performed based on the

TSBUS sync pulse STB (i.e., bus strobe). Mixed T1/E1 paths in one T3, mixed VT1.5/VT2 paths mapped to

VTGs in one STS1, and mixed VC11/VC12 paths mapped to TUG2 in STM-1 are allowed using this serial port

configuration.

FOOTNOTE:

(1)

A conventional serial port is defined as seven input/output signals as follows: Transmit Clock (TCLK), Transmit Synchronization (TSYNC),

Transmit Data (TDAT), Receive Clock (RCLK), Receive Synchronization (RSYNC), Receive Data (RDAT), Receive Out-Of-Frame, or Clear

To Send (ROOF/ CTS). (For a detailed description of these signals, see Section 2.1.)

Channelized mode refers to a data bit stream segmented into frames. Each frame consists of a series of 8-bit time slots. The frame

synchronization is maintained in both the transmit and receive direction by using the Transmit Synchronization (TSYNC) and Receive

Synchronization (RSYNC) input signals.

A Time Slot Bus (TSBUS) is defined as seven input/output signals as follows: Transmit Clock (TCLK), Transmit Stuff (TSTUFF), Transmit

Data (TDAT), Strobe (STB), Receive Clock (RCLK), Receive Stuff (RSTUFF), Receive Data (RDAT). (For a detailed description of these

signals, see Chapter 5.0).

(2)

(3)

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1.2

CX28500 Serial Port Throughput Limits

Each of the CX28500 serial ports can be configured to operate in any of the preceding operational modes. The

following restrictions apply:

1. The overall number of time slots cannot exceed 4096.

2. The overall number of channels cannot exceed 1024.

3. Only the first 6 ports can be configured to operate as high speed ports—T3 (44.7 Mbps), E3 (34.4 Mbps), and

HSSI (52 Mbps).

4. The total accumulated data rate of all serial port clocks in either receive or transmit direction must be less than

250 Mbps for a PCI bus rate of 33 MHz and 390 Mbps for a PCI bus rate of 66 MHz.

Allowed CX28500 port configurations are represented in Table 1-2.

Table 1-2.

Allowed CX28500 Port Configurations

4 Mbps

8 Mbps

13 Mbps

34.4 Mbps

44.7 Mbps

51.8 Mbps

Speed of Port

(1)

32

6

Number of Ports

FOOTNOTE:

(1)

For high speed ports such as T3 (44.736 Mbps), E3 (34.368 Mbps), HSSI (51.840 Mbps) the data path of the remaining ports may

operate at less than or equal to 4 Mbps or 8 Mbps (see Table 1-3).

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Table 1-3.

Data Path Combinations

Low Speed

High Speed

Path

Combinations

Aggregate

Port Speed

2 Mbps 4 Mbps 8 Mbps 10 Mbps 13 Mbps 34.4 Mbps⁽¹⁾

(2.048) (4.096) (8.192) (10.240) (12.960) (E3-34.368)

44.7 Mbps⁽¹⁾51.8 Mbps⁽¹⁾

(T3-44.736) (HSSI-51.840)

Allowed

Number of

Ports

—

26

17

26

—

14

22

9

—

11

7

—

9

—

6

—

6

—

6

380.7 Mbps

312.7 Mbps

383.1 Mbps

386.4 Mbps

384.8 Mbps

381.1 Mbps

382.7 Mbps

380.3 Mbps

385.1 Mbps

388.8 Mbps

387.6 Mbps

321.7 Mbps

364.3 Mbps

259.5 Mbps

—

6

—

6

—

6

—

–

—

–

6

17

—

6

—

6

—

6

14

—

6

—

6

—

GENERAL NOTE:

1. These data path combinations are meant to illustrate the flexibility in data path configuration, and are not suggesting that these are the

only supported configurations. Again, they are here for illustration purposes only. Other data rates and path combinations are achievable,

as long as device-aggregate bandwidth restrictions and per-port bandwidth restrictions are met.

FOOTNOTE:

(1)

A high speed port can be E3 (34.4 Mbps), T3 (44.7 Mbps), or HSSI (52 Mbps) without exceeding the maximum of six serial ports.

CX28500’s configuration options are extremely flexible. Each logical channel can be assigned to a physical stream

ranging from 8 Kbps (sub-channeling mode) to 52 Mbps.

CX28500’s serial ports can interface to a standard PCM highway or TSBUS bus, which can be configured to

operate at any of the serial port rates given in Tables 1-4 and 1-5.

Table 1-4.

Examples of Serial Port Configurations With 33 MHz PCI Clock

Configuration

Total Bandwidth

PCI Clock

32 x T1

32 x E1

49.408 Mbps

65.536 Mbps

165.44 Mbps

131.072 Mbps

250 Mbps

33 MHz

2 x 52 + 30 x E1

32 x 2E1

Maximum

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Table 1-5.

Examples of Serial Port Configurations With 66 MHz PCI Clock

Configuration

Total Bandwidth

PCI Clock

4 x 52

208 Mbps

320 Mbps

66 MHz

32 x 10

(1)

6 x 52 + 6 x 13

32 x 4E1

390 Mbps

262.144 Mbps

251.232 Mbps

310 Mbps

4 x 52 + 28 x T1

6 x T3 + 26 x T1

26 x 8 + 4 x T3

Maximum

387 Mbps

390 Mbps

GENERAL NOTE: STS-1 data rates (51.84Mbps) are achieved when used in combination with the M29503 over the TSBUS.

FOOTNOTE:

(1)

Half of the OC-12 data rate, including overhead.

The send and receive data can be formatted in the HDLC messages or left unformatted (transparent mode) over

any combination of bits within a selected time slot. CX28500’s protocol message type is specified on a per-channel

basis.

1.3

CX28500’s Bus Interfaces

1.3.1

PCI—Peripheral Components Interface

An on-device PCI 2.1 compliant controller, known as the Host interface, is provided. Access to CX28500 is

available through PCI read, write, and configuration cycles. The PCI bus interface supports DMA bursts for

extremely high message throughput applications, up to 780 Mbps of the aggregate serial port bandwidth (i.e., 390

Mbps per direction).

1.3.2

EBUS—Local Expansion Bus

The CX28500 provides an on-device 32-bit local expansion bus (EBUS) controller that allows a Host processor to

access peripheral memory space on the EBUS. Physical devices interface directly to CX28500 over the PCI using

the configurable memory mapping features.

Although EBUS utilization is optional, the most notable application for the EBUS is the connection to peripheral

devices (e.g., CX28365, a 12-port T3/E3 framer) local to CX28500’s serial ports.

1.3.3

TSBUS—Time Slot Bus

CX28500 provides a TSBUS interface for variable bandwidth time slots, Virtual Serial Port (VSP). A VSP is defined

as an entity—quantified by clock bus rate divided by number of time slots—which provides multiple asynchronous

paths over a single serial port. A programmable number of VSPs per TSBUS are allowed by using the existing start

and end address time slot pointer mechanism. The pointer mechanism allows CX28500 to allocate any number of

VSPs on a given serial port, providing that the total number of VSPs allocated across all ports does not exceed

4096, the total number of logical channels does not exceed 1024, and the serial port clock speed does not exceed

52 MHz. While operating in TSBUS mode, the minimum number of time slots required is 8 per serial port. The

programmable number of time slots, implemented by the pointer mechanism (i.e., configurable start and end

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addresses) allows any number of VSPs to be concatenated into a single logical channel. This concatenation allows

mixed VTG path options without changing the number of time slots assigned to the TSBUS port. In the TSBUS

transmit direction, CX28500 requires the stuff status for each time slot to be presented at its TSTUFF input exactly

8 time slots in advance of the actual time slot for which the stuff status is applied. The amount of the TSTUFF

advance is fixed at 8 time slots even though the number of time slots within a frame might vary. For the receive

direction CX28500 requires the stuff status for each time slot to be presented at its RSTUFF input on the current

time slot for which the stuff is applied (For a detailed description, see the timing diagrams in Appendix E.)

1.4

CX28500 Layering Model

Independent of the particular layering scheme used, or the functions of the layers, the operation of layered

protocols is based on the fundamental idea of a layering principle (refer to Figure 1-1).

Level 2 of the protocol stack specifies how data travels between a Host and the packet switch to which it connects.

Because raw hardware delivers only a stream of bits, the level 2 protocol must define the format of frames and

specify how the machines recognize frame boundaries. This function is one of CX28500’s features, including error

detection (e.g., a frame checksum). Usually, protocols use the term “frame” to refer to a unit of data as it passes

between a Host and a packet switch.

CX28500, as a high-throughout communications controller for synchronous or asynchronous path applications,

multiplexes and demultiplexes up to 1024 data channels and allows upper protocols to recognize frame boundaries

and check if a frame has been transferred successfully. Examples of CX28500’s potential applications as a layer 2

protocol device and examples of device communication with other upper layers are described in Section 1.5.

Figure 1-1. CX28500 as a Data Link Layer Device

EBUS

TSBUS

PCI

Physical

Layer

Link

Layer

Upper

Layer

PCM

Highway

CX28500 Features

- Variable speed per

channel port

- Variable number of

time slots per port

- Variable number of

channels per port

- Variable number of

time slots per logical channel

- Packet switch

- Cell switch

- Processor

- HSSI

- SONET/SDH

- T3/E3

- T1/E1

- X.25

- MODEMS/DSL

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1.5

CX28500’s Applications

The potential applications for CX28500 are in data communications and telecommunications markets, such as the

following:

•

WAN access equipment

•

Router

Remote Access Server

Frame Relay Switch

ISDN basic-rate (BRI) or primary-rate interfaces (PRI)

Edge Switch (ATM or Frame Relay)

Protocol Converter

Enterprise Switch (Frame Relay or ATM)

SONET/SDH Packet Switches

High-Range Router/Gigabit Router

•

Transmission Equipment

•

Digital Access Cross-Connects (DACs)

Digital Loop Carries (DLCs)

Wireless Communication

Cellular Base Station Controllers

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1.6

CX28500 Applications Examples

1.6.1

T1/T3 WAN Access

An example of a Mid-Range Router Application for channelized DS3 and unchannelized/channelized DS1 line

interface is illustrated in Figure 1-2.

Figure 1-2. Mid-Range Router Application

EBUS

28DS1 Overhead

Channelized

T3

1

2

TSBUS

DS3 Signals

Host

CX28333

LIU

CX29503

28DS1 Payload

TSBUS

B

r

i

PCI

CX28500

d

g

e

T1 Signals

T1

T1₀

CX28398

CX28380

7

Framers

SM

4

T1₂₇

(Channelized or

Unchannelized T1)

T1 Signals

EBUS

LEGEND:

CX28333-DS3/E3 line Interface Unit.

CX29503–M13 Framers; 28 DS1 signals can be multiplexed into and demultiplexed from 1 DS3 signal or various

combinations of E1 and DS1 signals that can be multiplexed into and demultiplexed from 1 DS3 signal.

7xCX28380–T1/E1 Line Interface Unit.

4xCX28398 or 2xCX28395–T1/E1/Framers.

CX28500–HDLC Controller.

GENERAL NOTE:

The application handles T1/E1 and T3/E3 signals both in North American digital telephony hierarchy and in the European

digital telephony hierarchy.

500052_079

The block diagram illustrates how the CX28500 interconnects with 3 different buses:

•

PCI bus used for communication between CX28500, central Host processor and shared memory.

EBUS used for communication with peripheral devices.

TSBUS used to provide multiple asynchronous paths between the DS3 framers and the central Host

processor. The TSBUS also provides paths for inter-processor control (IPC) channels between the DS3

framers and the central Host processor. This example illustrates how 30 of CX28500’s 32 serial ports are used

in a Mid-Range Router Application. The T3/E3 data path (payload) occupies only one TSBUS port and the

overhead path occupies another TSBUS port.

•

Feature List:

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•

30 ports

PCI bus that operates to redirect packets from and to local RAM via a PCI bridge

EBUS that provides a path of control and performance monitoring for local devices

Two TSBUS ports that provide the path for 28 DS1 payload data and 28 DS1 overhead data as a mixed

combination of asynchronous paths

•

Simultaneous connection of CX28500’s serial port modes, including channelized TSBUS mode and T1/E1,

either channelized or unchannelized

•

Variable speed per port and channel

Configurable allocation of the time slots

Sufficient bandwidth to perform 28 DS1 paths and 1 DS3 path simultaneously

Low cost and powerful line card interface

High level chip integration

High performance HDLC controller

This application uses 30 of the available 32 serial ports. For PCI bus operation, the central Host processor

examines the packet’s sequence and number, and manipulates the table header in local RAM to perform HDLC

packet formatting and de-formatting.

1.6.2

T3/E3 Frame Relay Switch

This application illustrates a connection between CX28500 and CX28344 T3/E3 Framer specifying an 6 DS3 serial

ports application for an unchannelized DS3

High-End Router.

Feature List:

•

Supports full-rate DS3 byte streams with T3/E3 overhead and payload

Supports a byte stream of 32 dwords burst size that travels over the PCI bus/bridge and is directly accessible

as shared memory for the Host to process

•

Uses a high-speed port priority scheme. Figure 1-3 illustrates how the first payload data path ports are

connected at the lower port numbers and the Terminal Data Link (TDL) overhead data paths are connected to

the low priority ports.

•

Uses framers that can be optimally configured through an optional microprocessor. This path can be used as a

inter-processor communication (IPC) path for control and performance monitoring.

Supports concurrent paths of payload and overhead. (The first six ports run simultaneously at 44.2 Mbps, the

others run simultaneously at the TDL rate (192 Kbps).

For the detailed description of the application’s device connections, see Appendix C.

NOTE:

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Figure 1-3. High-Range Router Application

6 Ports T3/E3

Payload (TDL)

See Figure C-3,

T3/E3 Framer Connection

with HDLC Controller

(T3/E3 Payload Path)

COAX

(Typ)

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

T3/E3

CX28333

T3/E3

CX28343

T3 Framer

LIU

Shared

Memory

See Figure C-2,

B

r

DS3/E3 Line Unit

Interface Connection

with T3/E3 Framer

PCI

System

Bus

i

CX28500

d

g

e

CPU

PORT 8

PORT 9

T3/E3

CX28343

T3 Framer

PORT 10

PORT 11

PORT 12

PORT 13

PORT 14

PORT 15

CX28333

LIU

6 Ports T3/E3 Overhead (TDL)

See figure C-4, T3/E3 Framer

Connection with HDLC Controller

(T3/E3 Overhead Path)

EBUS

Optional

Local

MPU

MEM

LEGEND:

CX28333 – DS3/E3 Line Interface Unit

CX28332 – DS3/E3 Line Interface Unit

CX28343 – T3 Framer

CX28500 – HDLC Controller

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1.6.3

128 Port DSL Access Concentrator

Figure 1-4 illustrates a scalable application of an Internet Access Device (IAD).

Figure 1-4. DSLAM or IAD

EBUS

COAX

(Typ)

T3

T3/E3

PORT 0

PORT 1

PORT 2

CX28343

T3/E3

Framer

T3

CX28333

LUI

135M

EBUS

Unit 0

CX28500

PCI

2M

DSL

Modems

PCM

16M

PORT 4

x8

Unit 15

PCM

16M

2M

PORT 19

PORT 20

DSL

Modems

CSP

Control Serial Port

x8

Physical Layer

Data Link Layer

500052_005

CX28500, the HDLC controller, which operates at Layer 2 of OSI, communicates with the physical layer devices—

CX28333 (T3/E3 Line Interface Framer) and eight units of eight DSL modems. The modems are connected to

CX28500’s serial port at the 16 Mbps rate into a PCM highway. CX28500’s first three ports run channelized T3 and

the other 16 ports run at 16 Mbps so that the total port aggregated rate is 260.6 Mbps. The example shows how a

bank of eight modems can be configured by the serial line Control Serial Port (CSP). The CSP port provides the

advantage of a Message Buffer Inter-Processor Control (MBIPC) channel.

1.6.4

SONET/SDH Mapper

Figure 1-5 illustrates a Gigabit Router Line Card which can perform packet processing for one OC-12/STM-4 line.

Feature List:

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•

EBUS bus configuration to local devices

PCI bus which acts as CX28500’s configuration/status interface

Power solutions for HDLC processing messages (two HDLC controllers running at 66 MHz)

IPC channel processor

Performance monitoring

Scalable configuration up to OC-48

T3/E3 data link over the TSBUS channel

This configuration allows the Power PC (PPC) to receive and transmit data link messages

over these channels via its local RAM (using DMA and buffer table) instead of having to

service individual channel FIFOs with direct read/write access on each device. This

effectively removes all PPC real-time constrains, the only remaining real-time activity is to

handle the single line interrupt from the Mapper to the PPC.

NOTE:

Figure 1-5. Gigabit Router Line Card for OC-12

EBUS

SIBUS

TSBUS

BAM

CX29503

HDLC

CX28500

SIBUS

BAM

CX29503

SONET

SDH

Optics

Mapper

CX29610

TSBUS

SIBUS

BAM

CX29503

HDLC

CX28500

BAM

CX29503

LEGEND:

PCI

EBUS = Expansion Bus

TSBUS = 84 Time Slot Bus (x3)

SIBUS = SONET Interleaved Bus

PCI = 66 MHz, 64-bit Data Bus

ROM = Read Only Memory

PPC = Power PC

PPC

RAM

BAM = Broadband Access Multiplexer (e.g. 29503)

Mapper = SONET/SDH Mapper/Framer (e.g. 29610)

ROM

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1.6.5

Line Card SONET/ATM SAR

Figure 1-6 illustrates the Line Card SONET/ATM SAR.

Feature List:

•

Higher data aggregation

Higher number of interfaces

Chip cost reduced by increasing the number of interfaces serving a large number of logical channels

Efficient bus occupancy when data is transferred between Link Layer Controller and memory

Fully independent serial port configuration

Different types of interfaces handled simultaneously (channelized DS3 and channelized T1/E1)

32 independent serial ports

Conventional mode supported by seven signals (RDAT, RCLK, RSYNC, ROOF, TDAT, TCLK, and TSYNC)

Local bus architecture

Per-channel DMA buffer management, linked list data structure handled in local memory

Increased PCI utilization accomplished by supporting different classes of traffic with fully per-channel

programmable threshold values of internal buffers. These configurable buffer thresholds allow the user to take

advantage of PCI bursts in transferring data between CX28500’s internal memory and shared memory.

Figure 1-6. Line Card SONET/ATM SAR

PCI

Bridge

CPU

DS3

T3

Quad

DS3/T3

Framer

Triple

T3/E3/STS1

LIU

CX28344

CX28333

Memory

(RAM)

CX28500

1024 Channel

HDLC Controller

with Full Duplex

T1/E1

(per Channel) DMA

1

ATM

SAR

Dual

T3/E3/STS1

LIU

CX28233

M13

(Mux/Demux)

+

CX28332

Framers

ATM

PHY With

SONET

Framer

T1/E1

28

CX28223

Expansion Bus

Interface

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1.7

Feature Summary

The CX28500’s feature list includes the following:

•

A 1024-channel, full-duplex link layer controller for synchronous applications is provided.

32 full-duplex physical interfaces (i.e., ports) with independent clock rates are provided. CX28500 implements

32 serial ports that are individually programmable to operate either as conventional serial ports or TSBUS

serial ports. Conventional serial ports’ input/out data streams can be configured as channelized or

unchannelized bit streams. As for TSBUS serial ports, they are channelized by definition. Clock rates may be

as high as 52 MHz (for the first six ports) or 13 MHz (for the remaining 26 ports, see Table 1-2).

•

General purpose HDLC (ISO 3309) is supported.

•

HDLC/SDLC

HSSI

ISDN D-channel (LAPD/Q.921)

X.25 (LAPB)

SS7

Frame Relay (LAPF/ANSI T1.618)

Inter System Link Protocol (ISLP) support

LAPDm support

ATM/SMDS DXI

Transparent unformatted mode

Point-to-Point-Protocol (PPP)

•

Hyperchannels and subchannels are supported.

• Hyperchannel mode

•

ISDN Primary Rate Interface (PRI)

ISDN Primary Rate Adapter (PRA)

Fractional T1 (FT1)

Fractional E1 (FE1)

Fractional Nx64K

SONET/SDH/PDH paths connected via TSBUS, which include: Mixed VT1.5/VT2 paths, Mixed TU-11/

TU-12 paths, and Mixed T1/E1 paths

•

Multiple lines muxed to 1 port, which include: Digital Subscriber Line Access Multiplexer (DSLAM) and

T1/E1 Frame Relay

•

Subchanneling mode

Each channel can be programmed to either use a complete DS0 time slot or mask any subset of a time

slot. A signal mask is defined per-channel basis that has an enabled bit per each time slot. The mask bit

indicates whether the whole DS0 or part of it is enabled

•

ISDN Basic Rate Interface (BRI)

ISDN Basic Rate Adapter (BRA)

Frame Relay 56K and Nx56K

Compressed Voice Transparent Channels (e.g., ADPCM)

Centralized Signaling Channel Controllers, which include: Link Access Procedure D-Channel (LAPD),

Common Channel Signaling (CCS), and Signaling System #7 (SS7)

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•

Unchannelized mode

•

Digital Comm/Termination Equipment (DCE/DTE) interfaces

High Speed Serial Interface (HSSI)

Inter-Process Communication (IPC)

V-Series DTE/DCE Interfaces (V.35)

SDSL Modems and Access Concentrators

T3/E3 Frame Relay

•

Variable path primitives are supported.

•

Path Payload

•

Sub-channeling (N × 8 Kbps) where N is between 1 and 7, the fractional bits in an 8-bit time slot.

DS0 (64 Kbps)

N × 64 Kbps, allows all types of hyperchanneling, channelized, unchannelized, or path payload as long

as the bandwidth does not exceed the respective port’s bandwidth limitation

•

Higher speed ports

•

Unchannelized T3 (44.736 Mbps)

Unchannelized E3 (34.368 Mbps)

HSSI (52 Mbps)

Path overhead (Performance Monitoring and Provisioning) T1

•

Facilities Data Link (FDL)

Common Channel Signalling (CCS)

T3/E3 Terminal Data Link (TDL)

V.51 and V.52 signalling channels

•

Per-channel protocol selection is supported

•

Non-FCS mode

16-bit FCS mode

32-bit FCS mode

Transparent mode

Configurable logical channels are supported

•

Standard DS0

Hyperchannel

Subchannel

•

Programmable time slot allocation is supported

Pointer mechanism

Per-channel DMA buffer management is supported

•

32 KB per direction receive and transmit (64 Kb per chip) internal FIFO

Configurable DMA threshold per-channel basis

Programmable FIFO size per-channel basis

Configurable number of buffer descriptors per channel

Flexible buffer descriptor handling

•

Self Service mechanism

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•

Clear to Send (CTS) per-channel control of data transmission

Direct PCI bus interface is supported

•

PCI Bus Interface (rev. 2.1)

32/64-bit multiplexed Address/Data bus minimizes pincount

33/66 MHz operation

Burst DMA capability (i.e., up to 32 dwords) minimizes the bus occupancy

•

EBUS—Expansion Bus Interface is provided

•

32-bit multiplexed Address/Data

Allows Host to control other local devices

Facilitates Host access to any local memory

TSBUS interface

•

Variable bandwidth time slot

Multiple asynchronous paths over single port

Allows SONET/SDH/PDH paths connection

•

Mixed VT1.5/VT2 paths

Mixed TU-11/TU-12 paths

Mixed T1/E1 paths

•

580-pin BGA package is used

3.3 V/2.5 V supply; 5 V-tolerant inputs

JTAG access is provided

Low power CMOS technology is used

1.8

System Overview

CX28500 supports 32 fully independent serial ports that can be configured to run in channelized, unchannelized,

T1 or TSBUS mode.

For example, in the channelized mode, the first six ports can operate at 51.84 Mbps (STS-1 rate) while another 22

ports can operate at 8.192 Mbps (4xE1 rate). Four more ports will be unused. Each STS-1 frame transports 28xT1,

1xT3, 21xE1 or mixed T1/E1 VTG paths. The configuration is valid as long as the overall number of time slots per

the whole device is 4096 time slots or less. For other restrictions see Section 1.2.

Alternatively, any of CX28500’s ports can interface unchannelized data streams (HDLC or unformatted). In this

mode, each of the first six ports can be configured to operate up to 52 Mbps and any of the remaining 26 ports up

to 13 Mbps. The restriction is that the overall bandwidth must not exceed 390 Mbps (per direction) while operating

at 66 MHz PCI clock cycles or 250 Mbps (per direction) while operating at 33 MHz PCI clock cycles.

CX28500 manages buffer memory for each of the active data channels with common table processing structures.

The on-device features allow data transmission between buffer memory and the serial interfaces with minimum

Host processor intervention. This allows the Host processor to concentrate on managing the higher layers of the

protocol stack.

Figure 1-7 illustrates CX28500’s system overview.

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Figure 1-7. System Overview

PCI

Bus

Local

Bus

Serial

Physical

JTAG

Interface 0

HDLC

Serial

Line

RxDMA

TxDMA

System

Host

Processors

Host

Interface

Serial

Interface

Unit

(TSLP

RSLP)

Local

Bus

PCI

(SIU)

Bridge

Expansion

Physical

Interface 30

Bus

Interface

(EBUS)

System

Memory

Physical

Serial

Interface 31

CX28500

Interface 31

Optional

Components

EBUS

Local

Host

Local

Memory

500052_008

The TSBUS interface provides multiple asynchronous paths where all TSBUS frames run at 51.84 Mbps. The

supported TSBUS framer configurations that are mapped into and from VSPs are as follows:

•

There are 28 PDH framers and 28 SONET/SDH framers. Either of these two categories of framers can be

mapped directly to the VSPs for a given configuration.

When using the PDH framers, each framer can be independently configured as a DS1 framer or as an E1

framer.

The SONET/SDH category of framers has two subcategories as the name implies. When using the SONET/

SDH framers, they all have to be configured as either SONET framers (one subcategory) or as SDH framers

(the other subcategory). The configurations of the SONET/SDH framers cannot have mixed subcategories.

When configuring for the SONET subcategory of framers, each framer can be independently configured as a

VT1.5 framer or as a VT2.0 framer. The SDH subcategory of framers is similarly configured. Each SDH framer

can be independently configured as a VC-11 framer or as an E1 framer.

The supported TSBUS frame structures are DS1s, E1s mapped via DS2, VT1.5, VT2.0, VC-11, VC-12.

The following mixed mappings are also supported by selectively configuring each framer:

•

DS1s and E1s extracted from mixed DS2s via the PDH framers

DS1s and E1s extracted from mixed VTGs via the SONET framers

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•

VC-11s and VC-12s extracted from mixed TUG-2s via the SDH framers

The frame structure is designed to transport the unchannelized STS-1 Synchronous Payload Envelope (SPE).

The frame structure is designed to transport the unchannelized DS3 payload.

The frame structure is designed to transport 16 E1 signals that are mapped to and from E3.

1.9

Block Diagram

Figure 1-8 illustrates the CX28500 conceptual block diagram.

Figure 1-8. CX28500 Top Level Block Diagram

Serial Port 0

RCLK0,

6

64

AD[63:0]

CBE[7:0]*

PAR, PAR64

REQ64*

FRAME*

TRDY*

IRDY*

STOP*

DEVSEL*

IDSEL

PERR*

Data

Stream

8

2

TCLK0,

Rx Line

Processor

RSLP

RSYNC0 (RSTUFF0),

TSYNC0 (TSTUFF0)

RDAT0,

Data

Dwords

8

Serial

Interface

Unit

ROOF0/CTS0(TSTB0),

Data

Stream

1

TDAT0

RxDMA

and

TxDMA

(SIU)

HOST

Interface

(PCI)

Data

Stream

Serial Port 31

ACK64*

SERR*

Data

Dwords

6

RCLK31,

TCLK31,

Data

Stream

REQ*

GNT*

RSYNC31 (RSTUFF31),

TSYNC31(TSTUFF31),

RDAT31,

Tx Line

Processor

TSLP

8

INTA*

ROOF31/CTS31(TSTB31),

PRST_

PCLK

1

TDAT31

Data

32

CTRL

3

Test

Access

Test Mode

EBUS

JTAG

4

500052_001

The following is a description of the block diagram.

•

Host Interface (PCI): This block provides the communication path between the Host and CX28500.

Expansion Bus (EBUS): The EBUS is an extension of the Host Interface, which provides the Host with access

to control other devices on the local PC board.

•

Serial Interface Unit (SIU): This block provides the interface between 32 serial ports and the Receive and

Transmit Serial Line Processors block. A temporal buffering space is provided by SIU that is 48 bits per port,

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divided as 32 bits (4 bytes) for the transmit direction and 16 bits (3 bytes) for the receive direction. SIU controls

the data access to the Rx and Tx Serial Line Processors. Given that CX28500 supports two types of serial

ports, one is the conventional interface, the other TSBUS interface—SIU needs to operate depending on serial

port type (for detailed descriptor information, see Chapter 5.0).

•

Transmit Serial Line Processor (TSLP): This block provides the interface between the DMA and SIU. The data

provided by DMA is processed by TSLP according to the channel type (transparent/HDLC, etc.) before it is

transmitted to the line.

Receive Serial Line Processor (RSLP): This block provides the interface between the SIU and DMA. The data

provided by SIU is processed by RSLP according to the channel type (transparent/HDLC, etc.) before it is

transmitted to the line.

RxDMA and TxDMA: This block provides the interface between the Host Memory (PCI) and the Transmit and

Receive Serial Line Processors (TSLP and RSLP). The DMA contains the main storage of data—a dual port

RAM of 32 KB per each direction, receive and transmit. This space acts as a holding buffer for incoming (Rx)

and outgoing (Tx) data.

•

JTAG: This is a special test port used for serial boundary scan on a PCB, as well as access to internal scan

paths and embedded memory for test purposes.

1.10

Receive Data Path

At the SIU level, all line signals are synchronized with the system PCI clock, which runs either at 33 MHz or 66

MHz. The received data serial stream is stored in SIU local buffers.

Each cycle, the SIU transfers a byte received from one of the 32 serial ports to the Receive Serial Line Processor

(RSLP). The order in which ports get serviced by the SIU depends on their priorities. A lower numbered port has a

higher priority than a higher numbered port, hence lower number ports are serviced before higher number ports.

For each serial port that was served, SIU translates the time slot into a channel number by using the internal map,

and provides specific parameters for RSLP to further process the incoming data.

The RSLP is a three–stage pipeline processor that performs the functions of an HDLC processor (formatting data),

as well as data concatenation (i.e., to merge bytes in double words) required by RxDMA. The RSLP processed

data is transferred to RxDMA together with a related status, which indicates the status of data.

The RSLP received data is stored in the internal memory before it is transferred to the Host. The internal memory

can be configured on a per-channel basis in programmable units called the channel’s internal buffer space or

channel’s FIFO. The user must configure the channel FIFO in quad dwords granularity by programming the start

and end address of each FIFO (see Table 6-24, RDMA Buffer Allocation Register, bit fields RDMA_ENDAD and

RDMA_STARTAD). When the threshold is crossed, a request to the RxDMA to serve that specific channel is

generated. If either an HDLC complete message (defined by an opening and closing flag) or an EOM message

resides in the channel FIFO, then a request will be generated towards RxDMA to serve the channel regardless of

the threshold value. The request is queued in the RxDMA Service Request Queue, which contains all the channels

pending service requests. The request is serviced when it reaches the top of the RxDMA Service Requests Queue.

If the channel request gets to the top of the RxDMA Service Request Queue, then the RxDMA will transfer the

content of the channel FIFO to the Host memory. After each transaction is completed, the channel is queued at the

end of RxDMA Service Request Queue until all channel data content is transferred to the Host memory.

1.11

Transmit Data Path

For transmit direction, the user allocates the buffer space in quad dwords granularity for each channel by

programming the start and end addresses of each channel FIFO (see Table 6-32, TDMA Buffer Allocation

Register, bit fields TDMA_ENDAD and TDMA_STARTAD). Transmission begins on a request generated by the

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TxSIU when it is ready for transmission. The request, in terms of a channel number, is passed to the TSLP. If the

TSLP has data for the requested channel, then it will give that data to the TxSIU. Otherwise, it will generate a

request, also a channel number, to the TxDMA. The TxDMA serves the channel based on its FIFO fill-state and its

data availability. A channel is queued in TxDMA Service Request Queue when the channel FIFO contains less than

the threshold value, or at least 32 empty dwords for the channel.

When a channel request gets to the top of the TxDMA Service Requests Queue, the TxDMA will serve this channel

until the channel FIFO is full. Since this may involve more than one PCI transaction, the channel is inserted at the

end of the TxDMA Service Request Queue after each transaction. The TxDMA gets data from shared memory on

a per-channel basis when the internal FIFO is not full. If TxDMA has either enough data or a complete HDLC

message, then it will start transferring data to the TSLP. The TSLP, in turn, does the necessary formatting, if any,

and sends the data to the TxSIU for transmission. The SIU uses a fixed priority scheme where port A has priority

over port B (when A is smaller than B). For the selected port, the SIU uses a internal map conversion to identify

which channel number data is transferred.

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1.12

Pin Configuration

Figure 1-9 provides a diagram of the CX28500 Pin Configuration, and Table provides a pin description.

Figure 1-9. Pin Configuration Diagram

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

A

B

A

B

C

D

N

N N

D

N

E

N

E

F

G

H

J

K

N

L

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

N

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

GND

VGG

VDD_io

VDD_C

Signal pins as described in Table 1-6 and 1-8.

These pins are not connected

N

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Table 1-6.

Pin Description

Number

Label

Number

Label

Number

Label

A1

A2

A3

A4

A5

A6

A7

A8

A9

GND

A34

B1

GND

B33

B34

C1

GND

TDAT[17]

TCLK[17]

RDAT[17]

TCLK[16]

RDAT[16]

TCLK[15]

B2

B3

C2

B4

C3

B5

RSYNC/RSTUFF[17]

TSYNC/TSTUFF[16]

GND

C4

TSYNC/TSTUFF[17]

B6

C5

ROOF/CTS/STB/SPORT

[17]

B7

C6

TDAT[16]

ROOF/CTS/STB/SPORT

[14]

B8

TSYNC/TSTUFF[15]

RDAT[15]

C7

RSYNC/RSTUFF[16]

TDAT[15]

B9

A10

A11

TCLK[14]

C8

B10

B11

B12

B13

B14

B15

GND

ROOF/CTS/STB/SPORT

[13]

C9

RSYNC/RSTUFF[15]

TSYNC/TSTUFF[14]

RSYNC/RSTUFF[14]

TSYNC/TSTUFF[13]

RDAT[13]

RDAT[14]

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

TCLK[13]

A12

A13

RCLK[13]

GND

ROOF/CTS/STB/SPORT

[12]

TCLK[12]

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

RCLK[12]

ROOF/CTS/STB/SPORT

[11]

TSYNC/TSTUFF[12]

RDAT[12]

TDAT[11]

B16

B17

GND

RCLK[11]

ROOF/CTS/STB/SPORT

[10]

TCLK[11]

TDAT[10]

RDAT[11]

TSYNC/TSTUFF[10]

RDAT[10]

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

TCLK[10]

RCLK[10]

GND

ROOF/CTS/STB/SPORT [9]

RCLK[9]

TSYNC/TSTUFF[9]

RDAT[9]

TCLK[9]

ROOF/CTS/STB/SPORT [8]

TDAT[8]

TCLK[8]

GND

RCLK[8]

RDAT[8]

ROOF/CTS/STB/SPORT [7]

TDAT[7]

TCLK[7]

RCLK[7]

GND

RSYNC/RSTUFF[7]

TDAT[6]

ROOF/CTS/STB/SPORT [6]

TCLK[6]

RCLK[6]

TDAT[5]

GND

RSYNC/RSTUFF[6]

TSYNC/TSTUFF[5]

RCLK[5]

ROOF/CTS/STB/SPORT [5]

TCLK[5]

RSYNC/RSTUFF[5]

TDAT[4]

RDAT[5]

TSYNC/TSTUFF[4]

GND

ROOF/CTS/STB/SPORT [4]

TCLK[4]

RCLK[4]

RSYNC/RSTUFF[4]

GND

RDAT[4]

GND

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Number

Label

Number

Label

Number

Label

C33

C34

D1

GND

D34

E1

TDAT[3]

F2

F3

TSYNC/TSTUFF[18]

GND

RSYNC/RSTUFF[18]

RDAT[18]

VGG

TCLK[18]

GND

E2

F4

RCLK[18]

D2

GND

E3

F5

GND

D3

GND

E4

GND

F30

F31

F32

F33

F34

G1

G2

G3

G4

VDD_io

D4

GND

E5

GND

No Connect

RSYNC/RSTUFF[3]

RDAT[3]

D5

RCLK[17]

E6

VDD_io

GND

D6

ROOF/CTS/STB/SPORT

[16]

E7

E8

VDD_c

GND

ROOF/CTS/STB/SPORT [2]

RSYNC/RSTUFF[19]

GND

D7

D8

RCLK[16]

E9

ROOF/CTS/STB/SPORT

[15]

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

F1

VDD_io

GND

RDAT[19]

D9

RCLK[15]

VDD_c

GND

ROOF/CTS/STB/SPORT

[18]

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

TDAT[14]

RCLK[14]

G5

G30

G31

G32

G33

G34

H1

VDD_c

VDD_io

GND

TDAT[13]

GND

RSYNC/RSTUFF[13]

TDAT[12]

No Connect

TDAT[2]

VDD_c

GND

RSYNC/RSTUFF[12]

TSYNC/TSTUFF[11]

RSYNC/RSTUFF[11]

RSYNC/RSTUFF[10]

TDAT[9]

GND

VDD_io

GND

TSYNC/TSTUFF[2]

TDAT[19]

VDD_c

GND

H2

TSYNC/TSTUFF[19]

TCLK[19]

H3

VDD_io

GND

RSYNC/RSTUFF[9]

TSYNC/TSTUFF[8]

RSYNC/RSTUFF[8]

TSYNC/TSTUFF[7]

RDAT[7]

H4

RCLK[19]

GND

H5

VDD_c

GND

H30

H31

H32

H33

H34

J1

VDD_c

No Connect

TCLK[2]

VDD_io

GND

TSYNC/TSTUFF[6]

RDAT[6]

RCLK[2]

VDD_c

GND

RSYNC/RSTUFF[2]

RCLK[20]

RSYNC/RSTUFF[20]

RDAT[20]

No Connect

GND

No Connect

J2

No Connect

TSYNC/TSTUFF[3]

TCLK[3]

RCLK[3]

TDAT[18]

No Connect

J3

No Connect

J4

ROOF/CTS/STB/SPORT

[19]

GND

ROOF/CTS/STB/SPORT [3]

GND

J5

VDD_io

GND

J30

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Number

Label

Number

Label

Number

Label

J31

J32

J33

J34

K1

RDAT[2]

N2

N3

GND

T30

T31

VDD_c

ROOF/CTS/STB/SPORT [1]

TDAT[1]

RSYNC/RSTUFF[22]

RDAT[22]

VDD_io

ROOF/CTS/STB/SPORT

[25]

N4

T32

T33

T34

U1

TDAT[25]

GND

TSYNC/TSTUFF[1]

TDAT[20]

N5

N30

N31

N32

N33

N34

P1

GND

TSYNC/TSTUFF[25]

TDO

K2

GND

No Connect

RCLK[0]

K3

TSYNC/TSTUFF[20]

TCLK[20]

U2

TMS

K4

GND

U3

TRST

K5

GND

RSYNC/RSTUFF[0]

U4

TCK

K30

K31

K32

K33

K34

L1

VDD_io

ROOF/CTS/STB/SPORT

[22]

U5

VDD_io

No Connect

TCLK[1]

P2

P3

TDAT[22]

TSYNC/TSTUFF[22]

TCLK[22]

GND

U30

U31

U32

U33

U34

V1

GND

TCLK[25]

RCLK[25]

RSYNC/RSTUFF[25]

RDAT[25]

TDI

GND

P4

RCLK[1]

P5

RCLK[21]

P30

P31

P32

VDD_io

L2

RSYNC/RSTUFF[21]

RDAT[21]

RDAT[0]

L3

ROOF/CTS/STB/SPORT

[24]

V2

TM[0]

L4

ROOF/CTS/STB/SPORT

[20]

V3

TM[1]

P33

P34

R1

TDAT[24]

L5

VDD_c

V4

TM[2]

TSYNC/TSTUFF[24]

TCLK[23]

L30

L31

L32

L33

L34

M1

GND

V5

GND

No Connect

V30

V31

V32

V33

V34

VDD_io

R2

RCLK[23]

RSYNC/RSTUFF[1]

RDAT[1]

TCLK[26]

TSYNC/TSTUFF[26]

TDAT[26]

R3

RSYNC/RSTUFF[23]

RDAT[23]

R4

ROOF/CTS/STB/SPORT [0]

R5

VDD_c

ROOF/CTS/STB/SPORT

[21]

ROOF/CTS/STB/SPORT

[26]

R30

R31

R32

R33

R34

T1

GND

M2

M3

TDAT[21]

TCLK[24]

W1

W2

EBE[0]

TSYNC/TSTUFF[21]

TCLK[21]

RCLK[24]

GND

M4

RSYNC/RSTUFF[24]

RDAT[24]

W3

EBE[1]

M5

GND

W4

EBE[2]

M30

M31

M32

M33

M34

N1

VDD_c

ROOF/CTS/STB/SPORT

[23]

W5

VDD_c

No Connect

TDAT[0]

W30

W31

W32

W33

W34

GND

T2

T3

T4

T5

GND

RDAT[26]

RSYNC/RSTUFF[26]

GND

TDAT[23]

TSYNC/TSTUFF[23]

GND

TSYNC/TSTUFF[0]

TCLK[0]

RCLK[22]

RCLK[26]

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Number

Label

Number

Label

Number

Label

Y1

Y2

EBE[3]

BGACK

HLDA

AC30

AC31

GND

AG1

AG2

AG3

AG4

AG5

AG30

AG31

AG32

AG33

AG34

AH1

AH2

AH3

AH4

AH5

AH30

AH31

AH32

AH33

AH34

AJ1

EAD[13]

EAD[12]

EAD[11]

EAD[10]

VDD_c

ROOF/CTS/STB/SPORT

[29]

Y3

AC32

AC33

AC34

AD1

RDAT[28]

RSYNC/RSTUFF[28]

RCLK[28]

EAD[24]

EAD[23]

EAD[22]

EAD[21]

GND

Y4

HOLD

Y5

GND

Y30

Y31

Y32

Y33

Y34

VDD_c

TCLK[27]

GND

TDAT[31]

AD2

TSYNC/TSTUFF[27]

TDAT[27]

ROOF/CTS/STB[31]

RDAT[30]

RSYNC/RSTUFF[30]

EAD[9]

AD3

AD4

ROOF/CTS/STB/SPORT

[27]

AD5

AA1

AA2

ALE

AD30

AD31

AD32

AD33

AD34

AE1

VDD_c

GND

ECLK

RD

RCLK[29]

TCLK[29]

TSYNC/TSTUFF[29]

TDAT[29]

EAD[20]

GND

EAD[8]

AA3

EAD[7]

AA4

WR

GND

AA5

VDD_io

GND

VDD_c

AA30

AA31

RCLK[31]

TCLK[31]

GND

ROOF/CTS/STB/SPORT

[28]

AE2

AE3

EAD[19]

EAD[18]

VDD_io

AA32

AA33

AA34

AB1

RDAT[27]

RSYNC/RSTUFF[27]

RCLK[27]

EAD[31]

GND

AE4

TSYNC/TSTUFF[31]

EAD[6]

AE5

AE30

AE31

GND

AJ2

EAD[5]

ROOF/CTS/STB/SPORT

[30]

AJ3

EAD[4]

AB2

AJ4

EAD[3]

AB3

EAD[30]

EAD[29]

GND

AE32

AE33

AE34

AF1

RDAT[29]

GND

AJ5

VDD_io

AB4

AJ30

AJ31

AJ32

AJ33

AJ34

AK1

GND

AB5

RSYNC/RSTUFF[29]

EAD[17]

No Connect

RDAT[31]

RSYNC/RSTUFF[31]

EAD[2]

AB30

AB31

AB32

AB33

AB34

AC1

VDD_io

TCLK[28]

TSYNC/TSTUFF[28]

GND

AF2

EAD[16]

AF3

EAD[15]

AF4

EAD[14]

TDAT[28]

EAD[28]

EAD[27]

EAD[26]

EAD[25]

VDD_c

AF5

GND

AK2

EAD[1]

AF30

AF31

AF32

AF33

AF34

VDD_io

AK3

EAD[0]

AC2

RCLK[30]

TCLK[30]

TSYNC/TSTUFF[30]

TDAT[30]

AK4

VDD_io

AC3

AK5

GND

AC4

AK6

GND

AC5

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Number

Label

Number

Label

Number

Label

AK7

AK8

VDD_c

GND

AL9

AL10

AL11

AL12

AL13

AL14

AL15

AL16

AL17

AL18

AL19

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

AL31

AL32

AL33

AL34

AM1

AM2

AM3

AM4

AM5

AM6

AM7

AM8

AM9

AM10

AD[24]

AD[22]

AD[19]

C/BE[2]*

DEVSEL

SERR*

AD[14]

AD[10]

C/BE[0]*

AD[01]

REQ64*

C/BE[4]*

AD[61]

AD[58]

AD[54]

AD[50]

AD[47]

AD[43]

AD[39]

AD[36]

AD[32]

VDD_io

GND

AM11

AM12

AM13

AM14

AM15

AM16

AM17

AM18

AM19

AM20

AM21

AM22

AM23

AM24

AM25

AM26

AM27

AM28

AM29

AM30

AM31

AM32

AM33

AM34

AN1

AD[18]

FRAME*

STOP*

PAR

AK9

VDD_io

GND

AK10

AK11

AK12

AK13

AK14

AK15

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AK31

AK32

AK33

AK34

AL1

VDD_c

GND

AD[13]

AD[09]

AD[07]

AD[02]

ACK64*

C/BE[5]*

AD[62]

AD[59]

AD[55]

AD[51]

AD[48]

AD[44]

AD[40]

AD[37]

AD[33]

GND

VDD_io

GND

VDD_c

GND

VDD_io

GND

VDD_c

GND

VDD_io

GND

VDD_c

GND

VDD_io

GND

VDD_c

GND

VDD_io

GND

RBS[1]

RBS[2]

RBS[3]

RBS[4]

GND

RBS[0]

GND

AN2

GND

AN3

GND

AN4

GND

AN5

GND

AL2

GND

AN6

GNT*

AL3

GND

AN7

GND

AL4

GND

PCLK

AN8

AD[26]

IDSEL

GND

AL5

GND

AD[30]

AD[27]

C/BE[3]*

AD[21]

AN9

AL6

PRST*

AD[31]

AD[28]

AN10

AN11

AN12

AL7

AD[17]

IRDY*

AL8

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Number

Label

Number

Label

AN13

AN14

AN15

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

AN26

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AP1

GND

AP15

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23

AP24

AP25

AP26

AP27

AP28

AP29

AP30

AP31

AP32

AP33

AP34

AD[11]

AD[08]

AD[05]

AD[04]

AD[00]

C/BE[7]*

PAR64

AD[60]

AD[57]

AD[53]

AD[49]

AD[46]

AD[42]

AD[38]

AD[35]

VGG

C/BE[1]*

AD[12]

GND

AD[06]

AD[03]

GND

C/BE[6]*

AD[63]

GND

AD[56]

AD[52]

GND

AD[45]

AD[41]

GND

AD[34]

GND

AP2

GND

AP3

GND

AP4

GND

AP5

INTA*

REQ*

AD[29]

AD[25]

AD[23]

AD[20]

AD[16]

TRDY*

PERR*

AD[15]

AP6

AP7

AP8

AP9

AP10

AP11

AP12

AP13

AP14

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1.13

CX28500 Hardware Signals Description

CX28500 is packaged in a 35 mm × 35 mm, 580-pin BGA.

The pin input/output functions are defined in Table 1-7.

Pin labels, signal names, I/O functions, and signal definitions are provided in Table 1-8. An active low signal is

always denoted with a trailing asterisk (*).

Table 1-7.

I/O Pin Types

I/O

Definition

I

O

Input. High impedance, TTL.

Output. CMOS.

I/O

t/s

s/t/s

Input/Output. TTL input/CMOS output.

Three-state. Bidirectional three-state input/output pin.

Sustained three-state. This is an active-low, three-state signal owned by only one driver at a time. The driver that drives an s/t/

s signal low must drive it high for at least one clock cycle before allowing it to float. A pullup is required to sustain the

deasserted value.

o/d

Open drain. This output is driven low only, and a pullup is required to sustain the deasserted value.

FOOTNOTE:All outputs are CMOS drive levels and can be used with CMOS or TTL-logic.

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Table 1-8.

CX28500 Hardware Signal Definitions (1 of 7)

Pin Label

Signal Name

I/O

Definition

ECLK

Expansion Bus Clock

t/s O The EBUS clock can be configured to operate at the PCI clock rate (i.e.,

33 MHz or 66 MHz), or at half of the PCI clock rate (i.e., 33/2 MHz or 66/

2 MHz), in which case the PCI clock is divided by two (see field EC_KDIV

in Table 6-21).

(6)

EAD[31:0]

Expansion Bus

t/s I/O EAD[31:0] is a multiplexed address/data bus.

Address and Data

EBE[3:0]*

Expansion Bus

Byte Enables

s/t/s O EBE* contains byte-enabled information for the EBUS transaction. For

details on how these signals are used and controlled by the Host, see

Chapter 4.0.

WR* (R/WR*)

Write Strobe

s/t/s O High-to-low transition enables write data from CX28500 into peripheral

®

device. Rising edge defines write. (In Motorola mode, R/WR* is held

high throughout read and held low throughout write. Determines

meaning of DS* strobe.)

RD*

(DS*)

Read Strobe

s/t/s O High-to-low transition enables read data from peripheral into CX28500.

Held high throughout write operation. (In Motorola mode, DS*

transitions low for both read and write operations and is held low

throughout the operation.)

ALE

(AS*)

Address Latch Enable

s/t/s O High-to-low transition indicates that EAD[30:0] bus contains valid

address. Remains asserted low through the data phase of the EBUS

access. (In Motorola mode, high-to-low transition indicates EBUS

contains a valid address. Remains asserted for the entire access cycle.)

HOLD

(BR*)

Hold Request

(Bus Request)

t/s O When asserted, CX28500 requests control of the EBUS.

HLDA

(BG*)

Hold Acknowledge

(Bus Grant)

I

When asserted, CX28500 has access to the EBUS. It is held asserted

when there are no other masters connected to the bus, or asserted as a

handshake mechanism to control EBUS arbitration. If in Intel mode, then

it should be pulled-down. If in Motorola mode, then it should be pulled-

up.

BGACK*

Bus Grant Acknowledge

t/s O When asserted, CX28500 acknowledges to the bus arbiter that the bus

grant signal was detected and a bus cycle is sustained by CX28500 until

this signal is deasserted. This is used in Motorola mode only.

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Table 1-8.

CX28500 Hardware Signal Definitions (2 of 7)

Pin Label

Signal Name

I/O

Definition

TCLK[31:0]

Transmit Clock

I

If the serial port is configured in conventional mode, then TCLK controls

the rate at which data is transmitted and synchronizes transitions for

TDATx and sampling of TSYNCx and CTSx, if CTSxis enabled. If the port

is configured as a TSBUS port, then TCLK controls the rate at which data

is transmitted and synchronizes transitions for TDATx and sampling of

TSTUFFx and STBx (STBx only for transmit circuitry).

TSYNC[31:0]/

TSTUFF[31:0]

Transmit

Synchronization/

TSBUS Transmit Stuff

I

If the serial port is configured in conventional mode, then this signal is

defined as TSYNC. TSYNC is sampled on the specified active edge of the

corresponding TCLKx clock. (See TSYNC_EDGE bit field in Table 6-

36, TSIU Port Configuration Register.)

When TSYNCx signal goes from low to high then the start of transmit

frame is indicated.

TSYNCx is ignored if the serial port is configured to operate in

unchannelized mode.

If the serial port is configured in T1 mode, then the corresponding data

bit that latched out during the same bit time period (but not necessarily

sampled at the same clock edge) is the F-bit of the T1 frame.

If the serial port is configured in channelized mode, then the

corresponding data bit that latched out during the same bit time period

(but not necessarily sampled at the same clock edge) is Bit-0 of the first

time slot of the N×64 frame.

Since CX28500’s flywheel mechanism is always used in channelized

mode, no other synchronization signal is required to track the start of

each subsequent frame. However, if a SYNC pulse, if it exists, occurs

anywhere but at the frame boundaries, which are tracked by the flywheel

mechanism, a COFA is generated for that port.

If the port is configured to operate as TSBUS port, then this signal is

defined as TSTUFF. The TSTUFF values are to either stuff (no TDAT

output) or not stuff (TDAT valid).

TSTUFF is sampled on the specified active edge of the corresponding

TCLKx. (See TSTUFF_EDGE bit field in Table 6-36, TSIU Port

Configuration Register.)

If the serial port operates in channelized TSBUS mode, then TSTUFF

assertion indicates that no data needs to be transmitted in the 8th time

slot after the assertion of the TSTUFF.

Note that while operating in channelized TSBUS mode, CX28500 requires

the following:

1. The stuff status for each time slot to be presented at its TSTUFF

input exactly eight time slots in advance of the actual time slot

for which the stuff status is to be applied. The amount of the

TSTUFF advance is fixed at eight time slots, even though the

number of time slots within a frame may vary.

2. Assertion of this signal anytime during the time slot is required.

But, for good practice, it is recommended that this signal is

asserted within the first two bits of the time slot.

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Table 1-8.

CX28500 Hardware Signal Definitions (3 of 7)

Pin Label

Signal Name

I/O

Definition

TDAT[31:0]

Transmit Data

t/s O Serial data latched out on active edge of transmit clock, TCLKx. If channel

is unmapped to time slot, data bit is considered invalid and CX28500

outputs either three-state signal or logic 1 depending on TRITx bit field

value in Table 6-36, TSIU Port Configuration Register. To avoid collision

with other drivers, this signal is three-stated until the detection of the first

TSYNC pulse, and during COFA.

RCLK[31:0]

Receive Clock

I

If the serial port is configured in conventional mode, then RCLK controls

the rate at which data is transmitted and synchronized transitions for

RDATx and sampling of RSYNCx and SPORT, if SPORT is enabled. If the

port is configured as a TSBUS port, then RCLK controls the rate at which

data is received and synchronizes transitions for RDATx and sampling of

RSTUFFx.

RSYNC[31:0]/

RSTUFF[31:0]

Receive

Synchronization/

Receive Stuff

I

If the port operates in a conventional mode, then this signal is defined as

RSYNC. RSYNC is sampled on the specified active edge of the

corresponding receive clock, RCLKx. (See RSYNC_EDGE bit field in

Table 6-28, RSIU Port Configuration Register.)

RSYNCx is ignored if the serial port is configured to operate in

unchannelized mode.

If RSYNCx signal goes from low to high, then the start of a receive frame

is indicated. For T1 mode, the corresponding sampled and stored data bit

during the same bit-time period (not necessarily sampled on the same

clock edge) is the F-bit.

For the channelized mode, the corresponding data bit sampled and

stored during the same bit-time period (not necessarily sampled on the

same clock edge) is Bit-0 of the first time slot of the N×64 frame.

Since CX28500’s flywheel mechanism is always used in channelized

mode, no other synchronization signal is required to track the start of

each subsequent frame. However, if a SYNC pulse, if it exists, occurs

anywhere but at the frame boundaries, which are tracked by the flywheel

mechanism, a COFA is generated for that port.

If the port operates as a TSBUS port then this signal is RSTUFF. The

RSTUFF is sampled on the specified active edge of the corresponding

TCLKx. (See RSTUFF_EDGE bit field in Table 6-28, RSIU Port

Configuration Register.) RSTUFF in this case assertion indicates that

this time slot contains no data.

RDAT[31:0]

Receive Data

I

Serial data sampled on active edge of receive clock, RCLKx.

If the channel is mapped to a time slot, input bit is sampled and

transferred to memory. If the channel is unmapped to time slot, data bit

is considered invalid and CX28500 ignores the received sample.

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Table 1-8.

CX28500 Hardware Signal Definitions (4 of 7)

Pin Label

Signal Name

I/O

Definition

(2)(3)(5)

ROOF[31:0]

Receiver Out-Of-Frame/

Channelized Clear To Send/

TSBUS Strobe

I

If ROOFx, the signal is sampled on the specified active edge of the

corresponding receive clock RCLKx (see ROOF_EDGE bit field in Table 6-

28, RSIU Port Configuration Register).

When it is asserted high, an Out-Of-Frame (OOF) condition interrupt is

indicated, if OOFIEN bit field is set to 1 in RSIU Port Configuration

Register.

(2)(3)(5)

/ROOF/CTS[31.0]

/STB/

(2)(4)(5)

SPORT[31:0]

While ROOFx is asserted, the received serial data stream is considered

Out-Of-Frame. If OOFABT bit field is set to 1 in Table 6-28, RSIU Port

Configuration Register, the receive process is disabled for the entire port

and it remains disabled until ROOFx is deasserted, otherwise, the receive

process is enabled.

Upon ROOFx deassertion, if OOFIEN bit field is set to 1 in RSIU Port

Configuration Register, an interrupt Frame Recovery (FREC) is generated.

The data processing resumes for all affected channels.

This signal can also operate as a general Serial Port Interrupt (SPORT) by

clearing the OOFABT bit field and setting the OOFIEN bit field in RSIU Port

Configuration Register (i.e., OOFABT = 0 and OOFIEN = 1). When the

ROOFx signal transitions from high-to-low (deassertion), a SPORT

interrupt is generated and data stream is not affected. If this signal is

used as a general purpose interrupt, no interrupt is generated until this

signal goes from high to low.

If CTSx, the signal is sampled on the specified active edge of the

corresponding transmit clock, TCLKx. (See CTS_EDGE bit field in

Table 6-28, RSIU Port Configuration Register.)

If CTS transitions from high-to-low (is deasserted), then the channel

assigned to the time slot will send continuous idle characters after the

current message has been completely transmitted. The message

transmission data continues when this CTS transitions from low to high

again (is asserted). The response time to CTS is a 32 bit-time, meaning

that a new message might be transmitted if the message starts within the

next 32 bits after CTS was deasserted.

If TSTBx, the signal is sampled twice:

1. Once by the receive circuitry on the specified edge of the

corresponding receive clock, RCLKx. (See RSTB_EDGE bit field

in Table 6-28, RSIU Port Configuration Register.)

2. Once by the transmit circuitry on the specified edge of the

corresponding transmit clock, TCLKx. (See TTSTB_EDGE bit

field in Table 6-36, TSIU Port Configuration Register.)

If TSTB transitions from low to high assertion, then it marks the first bit

of time slot 0 within the TSBUS frame.

Since there is a single TSTB for both directions, receive and transmit, the

number of configured time slots (RSIU Time Slot Pointers Assignment

Register and TSIU Time Slot Pointers Register) and the RPORT_TYPE or

TPORT_TYPE value (RSIU Port Configuration Register and TSIU Port

Configuration Register) specifying whether the serial port operates in

channelized or unchannelized mode must be identically configured for

both directions per serial port. Unexpected CX28500 behavior may be

generated if this restriction is violated.

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Table 1-8.

CX28500 Hardware Signal Definitions (5 of 7)

Pin Label

Signal Name

I/O

Definition

AD[63:0]

PCI Address

and Data

t/s I/O AD[63:0] is a multiplexed address/data bus. A PCI transaction consists of

an address phase during the first clock period followed by one or more

data phases. AD[7:0] is the LSB. As a master, CX28500 supports both

32- and 64-bit operations. As a target, it supports only 32-bit operations.

PCLK

PCI Clock

I

PCLK provides timing for all PCI transitions. All PCI signals except

PRST*, INTA*, and INTB* are synchronous to PCLK and are sampled on

the rising edge of PCLK. CX28500 supports a PCI clock up to 66 MHz.

PRST*

PCI Reset

I

This input resets all functions on CX28500.

CBE[7:0]*

PCI Command

and Byte Enables

t/s I/O During the address phase, CBE[3:0]* contain command information

while CBE[7:4]* are unused; during the data phases, CBE[7:0]* contain

information denoting which byte lanes are valid.

PCI commands are defined as follows:

CBE[3:0]

0000b

Command Type

Interrupt Acknowledge

Special Cycle

Oh

1h

6h

7h

Ah

Bh

Ch

Dh

Eh

Fh

0001b

0110b

0111b

1010b

1011b

1100b

1101b

1110b

1111b

Memory Read

Memory Write

Configuration Read

Configuration Write

Memory Read Multiple

Dual Address Cycle

Memory Read Line

Memory Write and Invalidate

Note that the CX28500 does not accept target (slave) transactions if the

CBE bits are not all 0 (zeroes). Such transactions successfully complete

on the PCI bus, but are silently ignored by the CX28500 device. The CBE

bits function normally during all other times.

PAR

PCI Parity

t/s I/O The number of 1s on PAR, AD[31:0], and CBE[3:0]* is an even number.

PAR always lags AD[31:0] and CBE* by one clock. During address

phases, PAR is stable and valid one clock after the address; during the

data phases it is stable and valid one clock after TRDY* on reads and one

clock after IRDY* on writes. It remains valid until one clock after the

completion of the data phase.

PAR64

PCI MSB parity

PCI Frame

t/s I/O Same as PAR for CBE[7:4]* and AD[63:32].

FRAME*

s/t/s I/ FRAME* is driven by the current master to indicate the beginning and

O

duration of a bus cycle. Data cycles continue as FRAME* stays asserted.

The final data cycle is indicated by the deassertion of FRAME*. For a non-

burst, one-data-cycle bus cycle, this pin is only asserted for the address

phase.

REQ64*

Request 64-bit Transfer

t/s I/O CX28500 asserts this signal when it needs to perform a 64-bit transfer.

This signal is used during PCI reset to inform the system that the PCI is

64-bits wide.

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Table 1-8.

CX28500 Hardware Signal Definitions (6 of 7)

Pin Label

Signal Name

I/O

Definition

ACK64*

Acknowledge 64-bit

Transfer

s/t/s I/ ACK64* asserted indicates the selected target is ready to perform a 64-

bit transaction.

O

STOP*

IRDY*

PCI Stop

s/t/s I/ STOP* asserted indicates the selected target is requesting the master to

stop the current transaction.

O

PCI Initiator Ready

PCI Target Ready

PCI Device Select

s/t/s I/ IRDY* asserted indicates the current master’s readiness to complete the

current data phase.

O

TRDY*

DEVSEL*

IDSEL

s/t/s I/ TRDY* asserted indicates the target’s readiness to complete the current

data phase.

O

s/t/s I/ When asserted, DEVSEL* indicates that the driving device has decoded

O

its address as the target of the current cycle.

PCI Initialization Device

Select

I

This input is used to select CX28500 as the target for configuration read

or write cycles.

SERR*

System Error

o/d O Any PCI device can assert SERR* to indicate a parity error on the address

cycle or parity error on the data cycle of a special cycle command or any

other system error where the result will be catastrophic. CX28500 will

assert SERR* if it detects a parity error on the address cycle or

encounters an abort condition while operating as a PCI master.

Since SERR* is not an s/t/s signal, restoring it to the deasserted state is

done with a weak pullup (same value as used for s/t/s).

Note that CX28500 does not input SERR*. It is assumed that the Host

will reset CX28500 in the case of a catastrophic system error.

PERR*

Parity Error

s/t/s I/ PERR* is asserted by the agent receiving data when it detects a parity

O

error on a data phase. It is asserted one clock after PAR is driven, which

is two clocks after the AD and CBE* parity was checked.

If CX28500 masters a PCI write cycle and—after supplying the data

during the data phase of the cycle—detects this signal being asserted by

the agent receiving the data, then CX28500 generates a PERR interrupt.

If CX28500 masters a PCI read cycle and—after receiving the data during

the data phase of the cycle—calculates that a parity error has occurred,

CX28500 asserts this signal and also generates the PERR Interrupt

Descriptor towards the Host.

INTA*

REQ*

GNT*

PCI CX28500

Interrupt

o/d O INTA* is driven by CX28500 to indicate a CX28500 Layer 2 interrupt

condition to the Host processor.

PCI Bus Request

t/s O CX28500 drives REQ* to notify the PCI arbiter that it desires to master

the bus. Every master in the system has its own REQ*.

PCI Bus Grant

I

The PCI bus arbiter asserts GNT* when CX28500 is free to take control of

the bus, assert FRAME*, and execute a bus cycle. Every master in the

system has its own GNT*.

RBS [4:0]

PCI Read Burst Size

t/s 0 Reports the number of dwords CX28500 attempts to read during its

subsequent master burst read transaction. These lines are driven only

during address phase of the master read transaction, where a value of

00000 means one-dword and a value of 11111 means 32 dwords.

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Introduction

Table 1-8.

CX28500 Hardware Signal Definitions (7 of 7)

Pin Label

Signal Name

I/O

Definition

TCK

JTAG Clock

I

Used to clock in the TDI and TMS signals and as clock out TDO signal.

TRST*

JTAG Enable

An active-low input used to put the chip into a special test mode. This pin

should be pulled low in normal operation.

TMS

JTAG Mode Select

I

The test signal input decoded by the TAP controller to control test

operations.

TDO

TDI

JTAG Data Output

JTAG Data Input

Test Mode

t/s O The test signal used to transmit serial test instructions and test data.

I

The test signal used to receive serial test instructions and test data.

TM[0]

TM[1]

TM[2]

Test modes, reserved for manufacturer testing. Must be tied low for

normal operation.

VDD_c

VDD_io

Power

Input Tolerance

Ground

—

VDD_c is power supply for internal logics. VDD_io is power supply for

input and output.

VGG

ESD diode clamp supply for 5 volts tolerant input where VGG = 5 volts,

otherwise VGG = VDDi = VDDo = 3.3 volts.

GND

Ground pins for internal logics, input, and output are connected to a

common ground.

No Connect

These pins have no connection. They are reserved for future revisions.

FOOTNOTE:

(1)

While operating in TSBUS mode, there is no damage expected when sampling STBx twice, since the RCLKx and TCLKx are the same

signals for a specific port. However, this may require some additional restrictions for the board designers when these clocks are routed.

This signal is used either as Receiver Out-Of-Frame or a Transmit Clear to Send or a TSBUS strobe. (OOF/FREC behavior selected by

OOFABT = 1, CTS behavior selected by CTSENB = 1, STB behavior selected by TPORT_TYPE or RPORT_TYPE.) See related bit fields

configuration (i.e., RSIU Port Configuration Register and TSIU Port Configuration Register). ROOF/CTS/STB/SPORT signals are from the

same pin.

If the serial port operates in conventional mode, then this signal is used either as a ROOFx or CTSx signal.

If the port operates channelized TSBUS mode, then the signal is used as the TSBUS strobe signal, which indicates the beginning of the

TSBUS frame.

(2)

(3)

(4)

(5)

(6)

Only one pin in the device defines all these functions.

The address line A31 must be asserted in all transactions.

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2.0 Internal Architecture

The CX28500 consists of the following functional blocks:

•

Serial Interface Unit (SIU)—TSIU and RSIU for the transmit and receive directions

Serial Line Processing (SLP)—TSLP and RSLP for the transmit and receive directions

Direct Memory Access Controller (DMA)

Interrupt Controller (INTC)

Figure 2-1 illustrates the different signal connection between the SIU and the host interface while the CX28500 is

configured to operate in conventional or channelized TSBUS mode.

Figure 2-1. Serial Interface Functional Block Diagram

Mask Enabled, COFA, Poll,

First TS, Channel Number

Synchronization/Stuff

Data

Rx Control

Rx Data

RSLP

Rx DMA

Out-of-Frame

Rx Event/Errors

Rx Event

Rx Event/Error

Tx Event/Error

Interrupt

Controller

Tx Event

Mask Enabled, COFA, Poll,

First TS, Channel Number

Tx Event/Errors

Tx Data

Synchronization/Stuff

TSLP

Tx DMA

Data

Tx Control

Clear to Send

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Internal Architecture

2.1

Serial Interface Unit (SIU)

The SIU is the module that logically connects the 32 serial ports (line interface unit) with serial line processing by

performing the serial-to-parallel conversion for the receive side, and parallel to serial for the transmit side. The SIU

contains two main blocks, RSIU for the receive path and TSIU for the transmit path. The RSIU main function is

multiplexing 32 serial ports into one logical port for the receive serial line processing block. The TSIU main function

is demultiplexing one logical port from the transmit serial line processing block to 32 serial ports.

The SIU main functions:

•

Multiplexing/demultiplexing 32 serial ports to one port for the receive path, and one port to 32 serial ports for

the transmit path, respectively.

•

Performs frame integrity check while operating in channelized mode. SIU verifies the length of incoming/

outgoing frames according to the configured number of time slots. In case of error a Change Of Frame

Alignment (COFA) is reported (see COFA description both modes convention and TSBUS mode).

•

Translates the time slot to logical channel number using the configured receive and transmit time slot map.

Provides a poll indication per port, see RPOLLTH or TPOLLTH bit fields in RSIU Port Configuration register

and TSIU Port Configuration register, which counts the frames of the poll interval of 1, 2, 4, 8, 16, 64, 128, or

256 frame interval.

•

Generates the following interrupts:

•

RxOOF, where ROOF signal is asserted

RxFREC, where ROOF signal is deasserted

RxCOFA, where RSYNC signal is asserted in an unexpected place

RxCREC, where COFA condition is off for the receive port

TxCOFA, where TSYNC signal is asserted in an unexpected place

TxCREC, where COFA condition is off for the transmit port

TSIU (Transmit Serial Interface Unit) is responsible for informing TSLP (Transmit Serial Line Processor) when it is

time to perform a transmit channel poll by counting a programmable (TPOLLTH) number of frames. For the TSBUS

mode, one frame is defined as the STB strobe interval. TSIU is also responsible for requesting transmit data from

TSLP for each transmitted time slot (i.e., for each VSP).

As for the RSIU, when data comes through the serial ports, it is stored in local buffers. At this stage, all line signals

are synchronized to the system clock, or the PCI bus rate (either 33 MHz or 66 MHz). At each cycle, the RSIU

transfers a byte received from one of the 32 ports to the Receive Serial Line Processor (RSLP). For the port being

served, the RSIU translates the time slot to a channel number (using an internal map) and provides certain

parameters that are needed by the RSLP to process the incoming data. Similar to the TSIU, for the TSBUS mode,

one frame is defined as the STB strobe interval.

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Internal Architecture

2.2

Serial Line Processor (SLP)

The serial line processors (RSLP and TSLP) service the bytes in the receive and transmit path. The SLP

coordinates all byte-level transactions between SIU and DMA. The SLP also interacts with the INTC to notify the

Host of events and errors during the serial line processing.

The RSLP main functions are the following:

•

HDLC mode handling

•

Search opening and closing flag (7Eh)

Abort detection (7Fh)

Check max/min message length

Verify byte alignment

Check FCS

Detect change of pad-fill

Zero deletion

•

Transparent mode

Start to receive data from the first time slot assigned to the logical channel

•

Bit polarity inversion

Handle channel activation/deactivation

Handle OOF/COFA and overflow

Invert incoming data

Handle subchanneling

Interrupts

•

BUFF, SHT, CHIC, CHABT

The TSLP main functions are the following:

•

HDLC mode handling

•

Generate opening/closing /shared flag (7Eh)

Zero insertion after five consecutive 1 s bit-stuffing

Generate FCS depending upon the protocol

Handle CTS

Generate pad fill between frames

•

Transparent mode

•

Start to transmit data from the first time slot assigned to the logical channel

Generate pad fill between messages

•

Handle channel activation/deactivation

Handle COFA and under-run

Invert outgoing data

Handle subchanneling

Interrupts

•

BUFF, and EOM

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2.3

Direct Memory Access Controller

The direct memory access controller (RxDMA and TxDMA) manages all of the memory operations between a

correspondent’s SLP and the Host interface. DMA takes requests from SLP to either fill or flush internal FIFO

buffers, sets up an access to the data buffers in shared memory, and requests access to the PCI bus through the

Host interface.

2.3.1

General Feature List

•

Handles 1024 logical channels.

Supports 32- or 64-bit DMA transactions for 32- or 64-bit PCI bus transactions, respectively.

Configurable Internal Buffer Allocation

Full control of internal buffer size and internal buffer threshold per channel

•

FIFO flushing capability (after soft chip reset, channel activation, and channel deactivation service request)

•

Buffer Descriptor Handling

•

Separate Buffer Descriptors per channel

LAST bit field set in buffer descriptor indicates the Buffer Descriptor table length (maximum length is 4096

Buffer Descriptors entries)

•

Automatic fetch of Transmit and Receive Head Pointer Table (THPT and RHPT)

Automatic fetch of Transmit Head pointer Table (THPT) and Receive Head Pointer Table (RHPT) enables

the Buffer Descriptor tables switching without interfering normal operation (channel Jump)

•

Autonomous management of Buffer Descriptors

Automatic fetch for next Buffer Descriptor

Automatic Buffer Status Descriptor update and interrupts for End Of Buffer (EOB), Ownership (ONR) and End

Of Message (EOM) conditions

•

Automatic polling of Buffer Descriptor

•

Complete Buffer Control

•

Buffer Pointer

Buffer Length

Ownership (Host/CX28500)

End Of Buffer Interrupt Mask (EOBIEN)

Poll/No poll Control

•

Self-service mechanism

•

Zero host intervention required

Support self-service for receive to transmit loopback

Automatic Tx Abort Command generation

Per Channel Configuration

•

INHRBD—Status descriptor update/ignore

EOMIEN—Error-free End Of Message (EOM) interrupt enable/disable

ERRIEN Errored EOM enable/disable

ONRIEN—Ownership error

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Internal Architecture

Interrupts

•

EOM—End Of Service Request without an error

EOM—End Of Message with error (Overflow, OOF, COFA, FCS, ALIGN, ABT LNG)

ONR—Ownership error

EOB—End Of Buffer

2.4

Interrupt Controller

The Interrupt Controller takes receive and transmit events/errors from RSIU, RSLP, RxDMA and TSIU, TSLP, and

TxDMA respectively. The Interrupt Controller coordinates the transfer of internally queued descriptors to an

interrupt queue in shared memory and coordinates notification of pending interrupts to the Host.

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3.0 Host Interface

CX28500’s Host interface performs the following major functions:

•

Transfers data between the serial interface and shared memory over the PCI bus.

Stores configuration state information.

CX28500 does not support Function 1. The access to the EBUS is performed via a service request command,

which provides a better utilization of the PCI bus for local devices located on the EBUS.

Figure 3-1 illustrates the Host interface block diagram.

Figure 3-1. Host Interface Functional Block Diagram

Host

Interface

Device

Configuration

Registers

Clock

Control

PCI

Interface

PCI

Interface

Data

Tx Control

Rx Control

Interrupt

Serial

Interface

Unit

Tx Data

Rx Data

Interrupts

PCI

Configuration

Space

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Host Interface

3.1

PCI Interface

The Host interface in CX28500 is compliant with the PCI Local Bus Specification 2.1. CX28500 provides a PCI

interface specific to 3.3 V and 33/66 MHz operation and supports as master a 32-bit or 64-bit bus with multiplexed

address and data lines, and as a slave, a 32-bit PCI bus.

The PCI Local Bus Specification (Revision 2.1, June 1, 1995) is an architectural, timing,

electrical, and physical interface standard that provides a mechanism for a device to

interconnect with processor and memory systems over a standard bus.

NOTE:

The Host interface can act as a PCI master and a PCI slave, and contains CX28500’s PCI configuration space and

internal registers. When CX28500 needs to access shared memory, it masters the PCI bus and completes the

memory cycles without external intervention.

3.1.1

PCI Initialization

Generally, when a system initializes a module containing a PCI device, the configuration manager reads the

configuration space of each PCI device on a PCI bus. Hardware signals select a specific PCI device based on a

bus number, a slot number, and a function number. If a device that is addressed (via signal lines) responds to the

configuration cycle by claiming the bus, then that function’s configuration space is read out from the device during

the cycle. Since any PCI device can be a multifunction device, every supported function’s configuration space

needs to be read from the device. Based on the information read, the configuration manager will assign system

resources to each supported function within the device. Sometimes new information needs to be written into the

function’s configuration space. This is accomplished with a configuration write cycle.

CX28500 is a single function device that has device-resident memory to store the required configuration

information. CX28500 supports Function 0 only.

3.1.2

PCI Bus Operations

CX28500 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as

required during device operation. CX28500 supports only dword write transactions.

As a PCI slave, CX28500 responds to the following PCI bus operations:

•

Memory Read

Memory Write

Configuration Read

Configuration Write

Memory Read Multiple (treated like Memory Read in slave mode)

Memory Read Line (treated like Memory Read in slave mode)

Memory Write and Invalidate (treated like Memory Write)

As a PCI slave, CX28500 does not support bursted read or write PCI transactions.

NOTE:

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As a PCI master, CX28500 generates the following PCI bus operations:

•

Memory Read

Memory Read Line

Memory Read Multiple (generated only in master mode)

Memory Write

3.1.3

Fast Back-to-Back Transactions

Fast back-to-back transactions allow agents to utilize bus bandwidth more effectively. CX28500 supports PCI fast

back-to-back transactions both as a bus target and bus master. CX28500 can also execute fast back-to-back

transactions regardless of the PCI configuration settings (for details see bit 9 TARGET_FBTB bit field, in Table 6-

20, Global Configuration Descriptor).

Fast back-to-back transactions are allowed on PCI when contention on TRDY*, DEVSEL*, STOP*, or PERR* is

avoided.

CX28500, as a master supporting fast back-to-back transactions, places the burden of avoiding contention on itself.

While acting as a slave, CX28500 places the burden on all the potential targets. As a master, CX28500 may

remove the Idle state between transactions when it can guarantee that no contention occurs. This can be

accomplished when the master’s current transaction is to the same target as the previous transaction. While

supporting this type of fast back-to-back transaction, CX28500 understands the address boundaries of the

potential target, so that no contention occurs. The target must be able to detect a new assertion of FRAME* without

the bus going to Idle state.

3.1.3.1

Operation Mode

During a fast back-to-back transaction, the master starts the next transaction if GNT* is still asserted. If GNT* is

deasserted, the master has lost access to the bus and must relinquish the bus to the next master. The last data

phase completes when FRAME* is deasserted, and IRDY* and TRDY* (or STOP*) are asserted. The current

master starts another transaction on the clock following the completion of the last data phase of the previous

transaction. During fast back-to-back transaction, only the master and target involved need to distinguish

intermediate transaction boundaries using only FRAME* and IRDY* (there is no bus Idle state). When the

transaction is over, all the agents see an Idle state.

3.1.3.2

Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back

Transactions

Appendix B shows an example of an arbitration for fast back-to-back and non-fast back-to-back transactions. The

transactions shown are bursts of 2, 3, 4, 5, or 6 dwords read-write transferred while the address-data is either 32-

bit or 64-bit wide.

3.1.4

PCI Configuration Space

This section describes how CX28500 implements the required PCI configuration register space. The intent of PCI

configuration space definition is to provide an appropriate set of configuration registers that satisfy the needs of

current and anticipated system configuration mechanisms, without specifying those mechanisms or otherwise

placing constraints on their use. These registers allow for the following:

•

Full device relocation, including interrupt binding

Installation, configuration, and booting without user intervention

System address map construction by device-independent software

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CX28500 only responds to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request on to

another PCI bus are ignored.

CX28500 is a single function PCI agent; therefore, it implements configuration space for Function 0 only.

The address phase during a CX28500 configuration cycle indicates the function number and register number being

addressed, which can be decoded by observing the status of the address lines AD[63:0]. Figure 3-2 illustrates the

address lines during configuration cycle.

Figure 3-2. Address Lines During Configuration Cycle

Bit

Number

63/31

8 7

2 1

0

(3)

(2)

6-Bit

Register

Number

(1)

Don’t Care

2-Bit

Type

Number

FOOTNOTE:

(1)

CX28500 supports Function 0 only.

CX28500 supports Registers 0 through 15, inclusively.

CX28500 supports Type 0 configuration cycles.

(2)

(3)

500052_019a

The value of the signal lines AD[10:8] selects the function being addressed. Since CX28500 supports Function 0

only, it ignores these bits.

The value of the signal lines AD[7:2] during the address phase of configuration cycles selects the register of the

configuration space to access. Valid values are 0 through 15. Accessing registers outside this range results in an

all 0s value being returned on reads, and no action being taken on writes.

The value of the signal lines AD[1:0] must be 00b for CX28500 to respond. If these bits are 0 and the IDSEL* signal

line is asserted, then CX28500 responds to the configuration cycle.

The Base Code register contains the Class Code, Sub Class Code, and Register Level Programming Interface

registers. Table 3-1 illustrates the PCI Configuration Space.

Table 3-1.

PCI Configuration Space

Register

Number

Byte Offset (hex)

31

24

16

8

0

1

2

3

4

00h

04h

08h

0Ch

10h

Device ID

Status

Vendor ID

Command

Base Code

Header Type

Revision Id

Reserved

Latency Timer

CX28500 Base Address Register (BAR)

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Table 3-1.

PCI Configuration Space

Register

Number

Byte Offset (hex)

31

24

16

8

0

5

14h

—

Reserved

—

14

15

38h

3Ch

Max Latency

Min Grant

Interrupt Pin

Interrupt Line

All writable bits in the configuration space are reset to 0 by the hardware reset, PRST* asserted. After reset,

CX28500 is disabled and only responds to PCI configuration write and PCI configuration read cycles. Write cycles

to reserved bits and registers have no effect. Read cycles to reserved bits always result in 0 being read.

3.2

PCI Configuration Registers

3.2.1

PCI Master and Slave

CX28500 is a single function PCI device that provides the necessary configuration space for a PCI bus controller to

query and configure CX28500’s PCI interface. PCI configuration space consists of a device-independent header

region (64 bytes) and a device-dependent header region (192 bytes). CX28500 provides the device-independent

header section only. Access to the device-dependent header region results in 0s being read, and no effect on

writes.

Three types of registers are available in CX28500:

1. Read-Only (RO)—Return a fixed bit pattern if the register is used or a 0 if the register is unused or reserved.

2. Read-Resettable (RR)—Can be reset to 0 by writing a 1 to the register.

3. Read/Write (RW)—Retain the value last written to it.

Sixteen dword registers make up CX28500’s PCI Configuration Space. Tables 3-2 through 3-8 specify the contents

of these registers.

3.2.1.1

Register 0, Address 00h

Name

Table 3-2.

Reset

Value

Bit Field

Type

31:16

15:0

Device Id

8500h—64 channels

RO

8501h—384 channels

8502h—676 channels

8503h—1024 channels

Vendor Id

14F1h

RO

3.2.1.2

Register 1, Address 04h

The Status register records status information for PCI bus related events. The Command register provides coarse

control to generate and respond to PCI commands.

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At reset, CX28500 sets the bits in this register to 0, meaning CX28500 is logically disconnected from the PCI bus

for all cycle types except configuration read and configuration write cycles.

Table 3-3.

Register 1, Address 04h (1 of 2)

Bit

Field

Reset

Value

Name

Type

Description

31

Status

0

RR

Detected Parity Error. This bit is set by CX28500 whenever it detects a parity error, even

if parity error response is disabled.

30

29

0

RR

Detected System Error. This bit is set by CX28500 whenever it asserts SERR*.

Received Master Abort. This bit is set by CX28500 whenever a CX28500-initiated cycle

is terminated with master-abort.

28

0

RR

Received Target Abort. CX28500 sets this bit when a CX28500-initiated cycle is

terminated by a target-abort.

27

0

RO

Unused.

26:25

01b

DEVSEL Timing. Indicates CX28500 is a medium-speed PCI device. This means the

longest time it will take CX28500 to return DEVSEL* when it is a target is 3 clocks.

24

23

0

RR

Data Parity Detected. CX28500 sets this bit when three conditions are met:

1. CX28500 asserted PERR* or observed PERR*.

2. CX28500 was the master for that transaction.

3. Parity Error Response bit is set.

1b

RO

Fast Back-to-Back Capable. Read Only. Indicates that when CX28500 is a target, it is

capable of accepting fast back-to-back transactions when the transactions are not to the

same agent.

22

21

0

RO

Unused.

1b

66 MHz Capable. Read Only. Indicates the PCI interface is capable of operating at 66

MHz rate.

20:16

0

RO

Unused.

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Table 3-3.

Register 1, Address 04h (2 of 2)

Bit

Field

Reset

Value

Name

Type

Description

15:10

9

Command

0

RO

Unused.

RW

Fast back-to-back enable. This bit controls whether or not CX28500, while acting as

master, can perform fast back-to-back transactions to different devices. The

configuration software routine sets this bit if all bus agents in the system are fast back-

to-back capable.

ꢁ

If 1, CX28500 can generate fast back-to-back transactions to different agents.

If 0, CX28500 can generate fast back-to-back transactions to the same agent.

Note that this bit would be presumably set by the system configuration routine after

ensuring that all targets on the same bus had the Fast Back-to-Back Capable Bit set. If

the target is unable to provide the fast back-to-back capability, the target does not

implement this bit and it is automatically retuned as zero when Status register is read.

8

0

RW

SERR enable.

ꢁ

If 1, disables CX28500’s SERR* driver.

If 0, enables CX28500’s SERR* driver and allows reporting of address parity

errors.

7

6

0

RO

Wait cycle control. CX28500 does not support address stepping.

RW

Parity error response. This bit controls CX28500’s response to parity errors.

ꢁ

If 1, CX28500 takes normal action when a parity error is detected on a cycle as

the target.

ꢁ

If 0, CX28500 ignores parity errors.

5

4

0

RO

VGA palette snoop. Unused.

Memory write and invalidate. The only write cycle type CX28500 generates is memory

write.

3

2

0

RO

Special cycles. Unused. CX28500 ignores all special cycles.

RW

Bus master.

ꢁ

If 1, CX28500 is permitted to act as bus master.

If 0, CX28500 is disabled from generating PCI accesses.

1

0

RW

RO

Memory space. Access control.

ꢁ

If 1, enables CX28500 to respond to memory space access cycles.

If 0, disables CX28500’s response.

0

I/O space accesses. CX28500 does not contain any I/O space registers.

GENERAL NOTE:

1. An active low signal is detected by a trailing asterisk (*).

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3.2.1.3

Register 2, Address 08h

This location contains the Class Code and Revision ID registers. The Class Code register contains the Base Code,

Sub Class, and Register Level Programming Interface fields. These are used to specify the generic function of

CX28500. The Revision ID register denotes the version of the device.

Table 3-4.

Register 2, Address 08h

Bit

Field

Reset

Name

Value

Type

Description

31:24

23:16

15:8

Class Code

02h

80h

0

RO

Function: Network Controller.

Type: Other.

Sub Class Code

Register Level

Indicates there is nothing special about programming CX28500.

Programming Interface

7:0

Revision Id

01h

RO

The revision ID numbers are: 00 for Rev A (-11P and -11R parts) and 01 for RevB (-12

parts).

3.2.1.4

Register 3, Address 0Ch

Table 3-5.

Register 3, Address 0Ch

Bit

Field

Reset

Value

Name

Type

Description

31:24

23:16

Reserved

0

RO

Unused.

Header Type

0h

CX28500 is a single function device with the standard layout of configuration register

space.

15:11

10:8

Latency Timer

0

RW

RO

The latency timer is an 8-bit value that specifies the maximum number of PCI clocks that

CX28500 can keep the bus after starting the access cycle by asserting its FRAME*. The

latency timer ensures that CX28500 has a minimum time slot for it to own the bus, but

places an upper limit on how long it owns the bus.

7:0

Reserved

0

RO

Unused.

GENERAL NOTE:

1. An active low signal is detected by a trailing asterisk (*).

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Host Interface

3.2.1.5

Register 4, Address 10h

Table 3-6.

Register 4, Address 10h

Bit

Field

Reset

Value

Name

Type

Description

31:20

CX28500

Base Address Register

0

RW

Allows for 1 MB-bounded PCI bus address space to be blocked off as CX28500 space.

CX28500 will respond as a PCI slave with DEVSEL* to all memory cycles whose address

bits 31:20 match the value of bits 31:20 of this register, and those upper address bits are

non-0, and memory space is enabled in the Register 1, COMMAND bit field.

Reads to addresses within this space that are not implemented read back 0; writes have

no effect.

19:4

0

RO

When appended to bits 31:20, these bits specify a 1 MB bound memory range. 1 MB is

the only amount of address space that a CX28500 can be assigned.

3

2:1

0

RO

CX28500 memory space is not prefetchable.

CX28500 can be located anywhere in 32-bit address space.

This base register is a memory space base register, as opposed to I/O mapped.

GENERAL NOTE:

1. An active low signal is detected by a trailing asterisk (*).

3.2.1.6

Register 5–14, Address 14h–38h

Table 3-7.

Register 5-14, Address 14h–38h

Bit

Field

Reset

Value

Name

Type

Description

31:0

Reserved

0

RO

Unused.

3.2.1.7

Register 15, Address 3Ch

Table 3-8.

Register 15, Address 3Ch

Bit

Field

Reset

Value

Name

Type

Description

31:24

23:16

Maximum Latency

0Fh

RO

Specifies how quickly CX28500 needs to gain access to the PCI bus. The value is

specified in 0.25 µs increments and assumes a 33 MHz clock. A value of 0Fh means

CX28500 needs to gain access to the PCI bus every 130 PCI clocks, expressed as 3.75

µs in this register.

Minimum Grant

01h

RO

This value specifies, in 0.25 µs increments, the minimum burst period CX28500 needs.

CX28500 does not have any special MIN_GNT requirements. In general, the more

channels CX28500 has active, the worse the bus latency and the shorter the burst cycle.

15:8

7:0

Interrupt Pin

Interrupt Line

01h

0

RO

Defines which PCI interrupt pin CX28500 uses. 01h means CX28500 uses pin INTA*.

RW

Communicates interrupt line routing. System initialization software writes a value to this

register indicating which Host interrupt controller input is connected to CX28500’s

INTA* pin.

GENERAL NOTE:

1. An active low signal is detected by a trailing asterisk (*).

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Host Interface

3.2.2

PCI Reset

CX28500 resets all internal functions when it detects the assertion of the PRST* signal line. Upon reset, the

following occurs:

•

All PCI output signals are three-stated immediately and asynchronously with respect to the PCI clock input,

PCLK.

•

All EBUS output signals are three-stated immediately and asynchronously with respect to the EBUS clock

output, ECLK.

•

All writable/resettable internal register bits are reset to their default values.

All PCI data transfers are terminated immediately.

All serial data transfers are terminated immediately.

CX28500 is disabled and responds only to PCI configuration cycles.

3.2.3

PCI Throughput and Latency Considerations

For reference to PCI throughput and latency considerations see Appendix A.

3.2.4

Host Interface

After a hardware reset, the PCI configuration space within CX28500 needs to be configured by the Host as follows:

•

Base address register

Fast back-to-back enable/disable

SERR* signal driver enable/disable

Parity error response enable/disable

Latency timer register

Interrupt line register

Bus mastering enable/disable

Memory space access enable/disable

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4.0 Expansion Bus (EBUS)

CX28500 provides access to a local bus interface on the CX28500 called the Expansion Bus (EBUS), which

provides a Host processor to access any address in the peripheral memory space on the EBUS.

Although EBUS utilization is optional, the most notable applications for the EBUS are the connections to peripheral

devices (e.g., Bt8370/Bt8398 T1/E1 framers, CX28398 (Octal DS1/E1 framers), CX28314/CX28313 (multiplexer-

demultiplexer DS1 to DS3 plus framer) that are local to CX28500’s serial port.

Unlike other generations of Conexant’s HDLC controllers (CX28478/CX28474A/CX28472A/CX28471A), CX28500

provides access to the EBUS through an interface similar to a mailbox interface. This interface provides all the

EBUS read and write accesses to be carried over the PCI bus, allowing PCI bursts. This mechanism improves the

PCI utilization when multiple EBUS accesses are necessary for accessing the configuration of the peripheral

devices. The PCI Function 1 is disabled. Therefore, CX28500’s EBUS service requests are capable of accepting or

generating burst on the PCI bus. However, the EBUS interface signals are not capable of performing burst.

Figures 4-1 and 4-2 illustrate block diagrams of the EBUS interface with and without local microprocessor (MPU).

Figure 4-1. EBUS Functional Block Diagram with Local MPU

Local

Expansion

Bus

EBUS

Interface

Regenerated

and

Clock

Inverted

MPU

Address/Data

Control

T1/E1

or T3/E3

Framers

Bus Arbitration

Bus

Arbiter

500052_017

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Expansion Bus (EBUS)

Figure 4-2. EBUS Functional Block Diagram without Local MPU

Local

Expansion

Bus

Local RAM

Clock

Address/Data

Clock

Downloadable

ROM

EBUS

Interface

Control

Address/Data

Peripheral

Devices

Bus Arbitration

500052_018

4.1

EBUS—Operational Mode

4.1.1

Initialization

After reset and after the PCI configuration is completed, CX28500 provides the Host the ability to read and write

peripheral devices located on the EBUS (refer to Table 4-1). The Host Service Request mechanism allows the Host

to instruct CX28500 to perform specific EBUS operations. CX28500 can perform bulk service request commands.

The Service Request Acknowledge (SACK) can be generated either after each service request command or at the

end of each bulk service request, depending on the value of SACKIEN bit field set in the service request

configuration descriptor. (See Table 4-2.) CX28500 processes an SRQ by reading the HSRP register which

contains the address of the first entry in the HSDT (or refer to Section 7.1.2.2). Once configured and enabled, the

Host can configure local devices connected to the EBUS by issuing the EBUS Access Service Request

(EBUS_WR or EBUS_RD). The command is a three dword memory location that contains the following dword-

fields:

•

Access Control Field

Shared Memory Pointer (Buffer Address) representing the starting address of the buffer location where the

device structure resides

•

EBUS Base Address Offset (the address of the first EBUS transaction)

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Expansion Bus (EBUS)

Table 4-1.

EBUS Service Request Descriptor

Dword

Number

Bit 31

Bit 0

dword 0

OPCODE[31:27]

SACKIEN[26]

Reserved [25:19]

FIFO_BURST[18]

EBUS Byte Enable

[17:14]

Length[13:0]

(2)

dword 1

dword 2

dword 3

Shared Memory Pointer[31:2]

(3)

EBUS Base Address Offset

(1)

Reserved

FOOTNOTE:

(1)

All reserved bits must be written with 0’s for forward compatibility.

The two LSB’s must be equal to zero for dword alignment.

The EBUS Base Address Offset is only 31 bits wide. The MSB (bit 31) must be set to 1 for all transactions.

(2)

(3)

Table 4-2.

EBUS Service Request Field Descriptions

Dword

Number

Size

(Bits)

Descriptor Field

Value

Description

dword 0

OPCODE

5

6

7

EBUS Write command (EBUS_WR)

EBUS Read command (EBUS_RD)

SACKIEN

1

—

Enable (1) or disable (0) acknowledge via interrupt in the end of the command

execution

Reserved

7

1

0

Reserved bits should be written with 0s.

FIFO_BURST

Do increment EBUS address (address on the target device) by one after each

EBUS access. This is used to access a continuous segment or block of memory

on the target device that is connected to the EBUS.

1

Do not increment EBUS address for this access. On some devices, memory

accesses are carried out the writing/reading of one memory location. By setting

FIFO_BURST to one, CX28500 does not increment the EBUS address after an

access. Hence, the address stays the same for the next EBUS access.

EBUS Byte Enable

(EBE)

4

—

The value driven over EBE[3:0]*. Each bit controls a corresponding byte access

on the EBUS. For example, an EBE[3:0] value of 0001 means that Host data

passes to the device attached to the EBUS on byte 0, the least significant byte, of

the EBUS while the other three bytes are inaccessible.

Length

14

32

—

Number of EBUS transactions.

dword 1

dword 2

Shared Memory

Pointer

The Shared Memory Pointer (Buffer Address) is a dword–aligned address of the

first buffer to or from which data needs to be transferred from or to the EBUS.

The two LSB’s must be equal to zero for dword alignment.

EBUS Base Address

Offset

31

—

The EBUS Base Address Offset is the address for the first EBUS transaction. Bit

31 of this dword must be set to 1 in every transaction.

When an EBUS_RD is issued, CX28500 executes a PCI bursted write of EBUS transactions and will store the data

(EAD[31:0]) in an internal buffer. When the EBUS transaction ends, CX28500 bursts the data over the PCI to the

location specified by Shared Memory Pointer (Buffer Address). The EBE[3:0]* drives the programmed EBUS Byte

Enabled (EBE) value set in the Access Control Field dword. If EBE[3:0]* is different from 0000, the Host must

determine which bytes are valid for access.

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Expansion Bus (EBUS)

If an EBUS Write command is enabled, CX28500 transfers—via a PCI burst read—the data from the Host memory

into an internal buffer. The data is transferred over the EBUS in a series of write transactions. The EBE[3:0]* drives

the programmed value EBUS Byte Enabled (EBE) value set in the Access Control Field dword. If EBE[3:0]* is

different from 0000, the Host must insert the valid bytes into the appropriate location.

4.1.2

Clock

The ECLK, Expansion Bus Clock, can be configured to operate at the PCI bus rate of either 33 MHz or 66 MHz, or

at half of the PCI bus rate of 33/2 MHz and 66/2 MHz, respectively. This option is selectable by setting the value of

ECLKDIV bit field in EBUS Configuration register. The signal is output on the ECLK signal line. Whether or not a

device on the EBUS requires a synchronous interface, the ECLK signal is available all the time the PCI clock is

available (PCLK). The EBUS clock output can be disabled by appropriately setting the ECKEN bit field in EBUS

Configuration register. If ECLK is disabled, the ECLK output is three-stated.

After PCI reset, the ECLK output pin is three-stated and the ECKEN field in EBUS Configuration register is cleared.

4.1.3

Interrupt

Unlike Conexant’s other HDLC controllers (CX28478/CX28474/CX28472), CX28500 is not connected to the EINT*

pin of the EBUS. The EBUS interrupt line should be connected to PCI interrupt INTB* directly, if it is needed.

4.1.4

Address Duration

CX28500 is able to extend the duration that the address bits are valid for any given EBUS address phase. This is

accomplished by specifying a value between 0 and 7 in the ALAPSE bit field in EBUS Configuration register. The

value specifies the additional ECLK periods the address bits remain asserted. That is, a value of 0 specifies the

address remains asserted for one ECLK period, and a value of 7 specifies the address remains asserted for 8

ECLK periods. Disabling the ECLK signal output does not affect the delay mechanism.

Both pre- and post-address cycles are always present during the address phase of an EBUS cycle. The pre-

address cycle is one ECLK period long and provides CX28500 time to transition between the address phase and

the following data phase. The pre- and post-cycles are not included in the Address Duration.

4.1.5

Data Duration

CX28500 is able to extend the duration that the data bits are valid for any given EBUS data phase. This is

accomplished by specifying a value between 0 and 15 in the ELAPSE bit field in EBUS Configuration register. The

value specifies the additional ECLK periods the data bits remain asserted. That is, a value of 0 specifies the data

remains asserted for one ECLK period, and a value of 15 specifies the data remains asserted for 16 ECLK periods.

Disabling the ECLK signal output does not affect the delay mechanism.

A pre-data and post-data cycle is always present during the data phase of an EBUS cycle. The pre-data cycle is

one ECLK period long and provides CX28500 sufficient setup and hold time for the data signals. The post-data

cycle is one ECLK period long and provides CX28500 sufficient time to transition between the data phase and the

following bus cycle termination. The pre- and post-cycles are not included in the Data Duration.

4.1.6

Bus Access Interval

CX28500 can be configured to wait a specified amount of time after it releases the EBUS and before it requests the

EBUS a subsequent time. This is accomplished by specifying a value between 0 and 15 in the BLAPSE bit field in

EBUS configuration register. The value specifies the additional ECLK periods CX28500 waits immediately after

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Expansion Bus (EBUS)

releasing the bus. That is, a value of 0 specifies CX28500 will wait for one ECLK period, and a value of 15 specifies

16 ECLK periods. Disabling the ECLK signal output does not affect this wait mechanism.

The bus grant signal (HLDA/BG*) is deasserted by the bus arbiter only after the bus request signal (HOLD/BR*) is

deasserted by CX28500. As the amount of time between bus request deassertion and bus grant deassertion can

vary from system to system, it is possible for a misinterpretation of the old bus grant signal as an approval to

access the EBUS. CX28500 provides the flexibility— through the bus access interval feature—to wait a specific

number of ECLK periods between subsequent bus requests. If the signal (HLDA/BG*) is permanently asserted,

then there is a minimum of 3 ECLK periods between transactions.

Refer to EBUS timing diagrams—Figure 10-7, EBUS Write/Read Cycle, Intel-Style (Intel) and Figure 10-8, EBUS

Write/Read Cycle, Motorola-Style (Motorola).

4.1.7

PCI to EBUS Interaction

CX28500 provides a significant improvement in the EBUS interface compared to previous Conexant HDLC

devices. PCI utilization is dramatically improved by enabling the EBUS accesses, reads and writes, to be burst over

the PCI bus—when EBUS is extensively used to access EBUS peripheral during normal operation.

4.1.8

Microprocessor Interface

A microprocessor can be added to handle peripheral devices that require additional processing power. The

MPUSEL bit field in EBUS Configuration register specifies the type of microprocessor interface to use for the

EBUS.

If Intel-style protocol is selected, the following signals are effective:

•

ALE–Address Latch Enable, asserted high by CX28500 to indicate that the address lines contain a valid

address. This signal remains asserted for the duration of the access cycle.

•

RD*–Read, strobed low by CX28500 to enable data reads out of the device and is held high during writes.

WR*–Write, strobed low by CX28500 to enable data writes into the device and is held high during reads.

HOLD–Hold Request, asserted high by CX28500 when it requests the EBUS from a bus arbiter.

HLDA–Hold Acknowledge, asserted high by bus arbiter in response to HOLD signal assertion. Remains

asserted until after the HOLD signal is deasserted. If the EBUS is connected and there are no bus arbiters on

the EBUS, then this signal must be asserted high at all times.

•

HLDA is treated as an asynchronous signal.

If Motorola-style protocol, the following signals are effective:

•

AS*–Address Strobe, driven low by CX28500 to indicate that the address lines contain a valid address. This

signal remains asserted for the duration of the access cycle.

•

DS*–Data Strobe, strobed low by CX28500 to enable data reads or data writes for the addressed device.

R/WR*–Read/Write, held high throughout read operation and held low throughout write operation by CX28500.

This signal determines the meaning (read or write) of DS*.

•

BR*–Bus Request, asserted low by CX28500 when it requests the EBUS from a bus arbiter.

BG*– Hold Acknowledge, asserted low by bus arbiter in response to BR* signal assertion. Remains asserted

until after the BR* signal is deasserted. If the EBUS is connected and there are no bus arbiters on the EBUS,

then this signal must be asserted low at all times.

•

BGACK*–Bus Grant Acknowledge, asserted low by CX28500 when it detects BGACK* currently deasserted.

As this signal is asserted, CX28500 begins the EBUS access cycle. After the cycle is finished, this signal is

deasserted indicating to the bus arbiter that CX28500 has released the EBUS.

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Expansion Bus (EBUS)

4.1.9

Arbitration

The HOLD and HLDA (Intel) or BR* and BG* (Motorola) signal lines are used by CX28500 to arbitrate for the

EBUS.

For Intel-style interfaces, the arbitration protocol is as follows (refer to Figure 10-7, EBUS Write/Read Cycle, Intel-

Style).

1. CX28500 three-states EAD[31:0], EBE*[3:0]. WR*, RD*, and ALE*.

2. CX28500 requires EBUS access and asserts HOLD.

3. CX28500 checks for HLDA assertion by bus arbiter.

4. If HLDA is found to be deasserted, CX28500 waits for the HLDA signal to become asserted before continuing

the EBUS operation.

5. If HLDA is found to be asserted, CX28500 continues with the EBUS access as it has control of the EBUS.

6. CX28500 drives the address lines (EAD[30:0]), EBE*[3:0], WR*, RD*, and ALE*. The data lines (EAD[31:0])

are driven one cycle later than the other aforementioned signals.

7. CX28500 completes EBUS access and deasserts HOLD.

8. Bus arbiter deasserts HLDA shortly thereafter.

9. CX28500 three-states EAD[31:0], EBE*[3:0]. WR*, RD*, and ALE*.

For Motorola-style interfaces, the arbitration protocol is as follows (refer to Figure 10-8, EBUS Write/Read Cycle,

Motorola-Style).

1. CX28500 three-states EAD[31:0], EBE*[3:0]. R/WR*, DS*, and AS*.

2. CX28500 requires EBUS access and asserts BR*.

3. CX28500 checks for BG* assertion by bus arbiter.

4. If BG* is found to be deasserted, CX28500 waits for the BG* signal to become asserted before continuing the

EBUS operation.

5. If BG* is found to be asserted, CX28500 continues with the EBUS access as it has control of the EBUS.

6. If BGACK* is not asserted CX28500 assumes control of the EBUS by asserting BGACK*.

7. CX28500 drives the address lines (EAD[30:0]), EBE*[3:0], R/WR*, DS*, AS*. The data lines (EAD[31:0]) are

driven one cycle later than the other aforementioned signals.

8. Shortly after the EBUS cycle is started, CX28500 deasserts BR*.

9. Bus arbiter deasserts BG* shortly thereafter.

10. CX28500 completes EBUS cycle.

11. CX28500 deasserts BGACK*.

12. CX28500 three-states EAD[31:0], EBE*[3:0]. R/WR*, DS*, and AS*.

4.1.10

Connection

Utilizing the EBUS address lines, EAD[17:0], and the byte enable lines, EBE[3:0]*, the EBUS can be connected in

either a multiplexed or non-multiplexed address and data mode.

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Expansion Bus (EBUS)

Figures 4-3 and 4-4 illustrate two examples of non-multiplexed address and data modes. Figure 4-3 illustrates four

separate byte-wide framer devices connected to the EBUS with each byte enable line used as the chip select for

separate devices, which allows a full dword data transfer over the EBUS.

Figure 4-3. EBUS Connection, Non-Multiplexed Address/Data, 8 Framers, No Local MPU

EAD[31:24]

EAD[23:16]

EAD[31:0]

EAD[15:8]

EAD[7:0]

EAD[8:0]

Data Addr

Bt8370

CS*

Data Addr

Bt8370

CS*

Data Addr

Bt8370

CS*

Data Addr

Bt8370

CS*

AS*, R/WR*, DS*,

ECLK Control Lines

Device 0,4

Device 1,5

Device 2,6

Device 3,7

EAD9

dev 0,4

EBE[0]*

Chip

Select

Logic

EBE[3:0]*

EBE[1]*

EBE[2]*

EBE[3]*

GENERAL NOTE:

1. EBEx[3:0]* selects device x in each framer block.

2. EAD[31:0], AS* are supplied to each framer block.

3. EBEx*, AS* are supplied to each chip select block.

500052_050

Figure 4-4 illustrates how additional address lines can be combined with each byte enable line during the address

phase to support multiple framer banks with each bank containing four byte-wide framer devices.

The framers configuration in shared memory is that only the Least Significant Byte (LSB) contains the information

of one frame configuration, the others are unused.

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Expansion Bus (EBUS)

Figure 4-4. EBUS Connection, Non-Multiplexed Address/Data, 16 Framers, No Local MPU

EAD[31:24]

EAD[23:16]

EAD[15:8]

EAD[7:0]

EAD[31:0]

EAD[8:0]

8

9

8

9

8

9

8

9

Data Addr Data Addr Data Addr Data Addr

Bt8370 Bt8370 Bt8370 Bt8370

CS* CS* CS* CS*

dev 0 dev 1 dev 2 dev 3

EAD[10, 9]

Control

Lines

dev 0, bank 0

Control

Chip

Select

Logic

EBE[3:0]*

dev 0, bank 1

dev 0, bank 2

dev 0, bank 3

GENERAL NOTE:

1. EBEx[3:0]* selects device x in each framer block.

2. EAD[31:0], AS* are supplied to each framer block.

3. EBEx*, AS* are supplied to each chip select block.

500052_051

In the multiplexed address and data mode, four byte-wide peripheral devices are connected to the EBUS. In this

mode, 8 bits of the 32-bit EBUS transfer data to and from each device individually.

The multiplexed address and data mode example does not allow for 4-byte data transfers.

NOTE:

Figure 4-5 illustrates the EBUS connection, multiplexed address/data, 8 Framers, no local MPU.

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Expansion Bus (EBUS)

Figure 4-5. EBUS Connection, Multiplexed Address/Data, 8 Framers, No Local MPU

EAD[8:0]

Data Addr

Bt8370

CS*

Data Addr

Bt8370

CS*

Data Addr

Bt8370

CS*

Data Addr

Bt8370

CS*

AS*, R/WR*, DS*,

ECLK Control Lines

CS0*,CS4*

EAD[10:9]

Chip

CS1*,CS5*

CS2*,CS6*

EBE[3:0]*

Select

CS3*,CS7*

500052_052

4.1.10.1

Multiplexing Address

Figure 4-6 illustrates the EBUS connections of four 8-bit peripheral devices.

The four devices are multiplexing the address in shared memory. The framer’s configuration software has to read

the whole block of framers configuration before it starts demultiplexing data per device.

Figure 4-6. EBUS Connection, Multiplexed Address/Data, 4 Framers, No Local MPU

EAD[31:0]

AD[0:X]

EBUS

ADDR

LATCH

A0 - A9

Bt8370

CX28500

EAD[25:31]

EAD[16:24]

BE2

A0 - A9

BE1

BE0

Bt8370

EAD[8:15]

EAD[0:7]

A0 - A9

500052_053

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5.0 Serial Interface

The Serial Interface Unit (SIU) is the module that logically connects the 32 serial ports (line interface unit) with

serial line processing by performing the serial-to-parallel conversion for the receive side, and parallel to serial for

the transmit side. The SIU contains two main blocks, RSIU for the receive path and TSIU for the transmit path. The

RSIU main function is multiplexing 32 serial ports into one logical port for the receive serial line processing block.

The TSIU main function is demultiplexing one logical port from the transmit serial line processing block to 32 serial

ports.

The SIU main functions:

•

Multiplexing/demultiplexing 32 serial ports to one port for the receive path, and one port to 32 serial ports for

the transmit path, respectively.

•

Performs frame integrity check while operating in channelized mode. SIU verifies the length of incoming/

outgoing frames according to the configured number of time slots. In case of error a Change Of Frame

Alignment (COFA) is reported (see COFA description both modes convention and TSBUS mode).

•

Translates the time slot to logical channel number using the configured receive and transmit time slot map.

Provides a poll indication per port, see RPOLLTH or TPOLLTH bit fields in RSIU Port Configuration register

and TSIU Port Configuration register, which counts the frames of the poll interval of 1, 2, 4, 8, 16, 64, 128, or

256 frame interval.

•

Generates the following interrupts:

•

RxOOF, where ROOF signal is asserted

RxFREC, where ROOF signal is deasserted

RxCOFA, where RSYNC signal is asserted in an unexpected place

RxCREC, where COFA condition is off for the receive port

TxCOFA, where TSYNC signal is asserted in an unexpected place

TxCREC, where COFA condition is off for the transmit port

TSIU (Transmit Serial Interface Unit) is responsible for informing TSLP (Transmit Serial Line Processor) when it is

time to perform a transmit channel poll by counting a programmable (TPOLLTH) number of frames. For the TSBUS

mode, one frame is defined as the STB strobe interval. TSIU is also responsible for requesting transmit data from

TSLP for each transmitted time slot (i.e., for each VSP).

As for the RSIU, when data comes through the serial ports, it is stored in local buffers. At this stage, all line signals

are synchronized to the system clock, or the PCI bus rate (either 33 MHz or 66 MHz). At each cycle, the RSIU

transfers a byte received from one of the 32 ports to the Receive Serial Line Processor (RSLP). For the port being

served, the RSIU translates the time slot to a channel number (using an internal map) and provides certain

parameters that are needed by the RSLP to process the incoming data. Similar to the TSIU, for the TSBUS mode,

one frame is defined as the STB strobe interval.

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Serial Interface

5.1

Serial Port Interface Definition in Conventional Mode

A receive serial port unit (RSIU) connects to four input signals: RCLK, RDAT, RSYNC, and ROOF. A transmit serial

port unit (TSIU) connects to three input signals and one output signal: TCLK, TSYNC, CTS, and TDAT, respectively.

The SIU is responsible for receiving and transmitting data bytes to the Transmit Serial Line Processor (TSLP) and

Receive Serial Line Processor (RSLP). The receive and transmit data and synchronization signals are

synchronous to the receive and transmit line clocks, respectively. CX28500 can be configured to sample in and

latch out data signals and sample in status and synchronization signals on either the rising or falling edges of the

respective line clock, namely RCLK and TCLK. This configuration is accomplished by setting the ROOF_EDGE,

RSYNC_EDGE, RDAT_EDGE, TSYNC_EDGE, and TDAT_EDGE bit fields as detailed in Table 6-28, RSIU Port

Configuration Register and Table 6-36, TSIU Port Configuration Register. The default, after reset, is to sample

in and latch out data synchronization and status on the falling edges of the respective line clock. The port mode is

configured by programming the RPORT_TYPE and TPORT_TYPE bit fields in RSIU Port Configuration Register

and TSIU Port Configuration Register, respectively. When configured to operate in conventional mode, the

receive and transmit directions are not related to each other so that each direction can be programmed

independently of the other.

5.1.1

Frame Synchronization Flywheel

CX28500 utilizes the TSYNC and RSYNC signals to maintain a time-base, which keeps track of the active bit in the

current time slot. The mechanism is referred to as the frame synchronization flywheel. The flywheel counts the

number of bits per frame and automatically rolls over the bit count according to the programmed mode. The

TSYNC or RSYNC input marks the first bit in the frame. The mode specified in the RPORT_TYPE bit field in

Table 6-28, RSIU Port Configuration Register and TPORT_TYPE bit field in Table 6-36, TSIU Port

Configuration Register and the start and end address of time slot pointer determines the number of bits in the

frame. A flywheel exists for both the transmit and the receive functions for every port.

The flywheel is synchronized when CX28500 detects TSYNC = 1 or RSYNC = 1, for transmit or receive functions,

respectively. Once synchronized, the flywheel maintains synchronization without further assertion of the

synchronization signal. Additional sync pulses do not interfere with the flywheel mechanism as long as they are

synchronized correctly.

A time slot counter within each port is reset once in each frame and tracks the current time slot being serviced. In

the receive side, synchronization starts at the beginning of frame. In the transmit side, however, synchronization

starts four time slots later since there is an associated latency between when the TSIU requests the TSLP for data

and when the TSLP supplies the TSIU with the requested data.

In unchannelized mode, CX28500 ignores the TSYNC and RSYNC signals and the frame

synchronization flywheel mechanism is ignored.

NOTE:

5.1.2

Change Of Frame Alignment (COFA)

A Change Of Frame Alignment (COFA) condition is defined as a frame synchronization event detected when it was

not expected, and also includes the detection of the first occurrence of frame synchronization when none was

present. In unchannelized mode, there are no COFA conditions because the TSYNC and RSYNC signals are

ignored in this mode.

In the receive direction, when a COFA condition is detected by the serial interface, an internal COFA signal is

asserted until the COFA condition is declared off. A COFA condition is declared “off” when there was a complete

frame without an unexpected SYNC pulse. Thus, an internal COFA signal is asserted for at least two frame

periods. During the frame period that the internal COFA is asserted, CX28500’s serial line processor (SLP)

terminates all messages that are found to be active during the COFA condition. For each receiver and transmitter

channel found to be active and processing a message, the corresponding message descriptor’s owner bit is

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returned to the Host, and a Buffer Status Descriptor is written with the COFA error encoding. The Buffer Status

Descriptor is written if the INHRBSD bit field in the RDMA Channel Configuration register is disabled (set to 1).

CX28500 then proceeds to the next message descriptor (MD) from the Receive Message Descriptor Table

(RMDT). In the transmit direction, however, CX28500 cannot recover from COFA without the Host’s intervention.

For example, a new channel activation is required.

Assertion of COFA condition generates a COFA interrupt encoded in the Interrupt Status Descriptor (ISD) toward

the Host if this interrupt is unmasked (see Table 6-28, RSIU Port Configuration Register and Table 6-36, TSIU

Port Configuration Register, respectively RCOFA_EN or/and TCOFA_EN bit fields).

If a synchronization signal (SYNC) is received (low to high transition on TSYNC or RSYNC) while the internal

COFA is asserted, an Interrupt Descriptor with the COFA interrupt encoding is generated immediately if this

interrupt is not masked.

When the internal COFA is deasserted, CX28500 generates an Interrupt Descriptor with CREC event encoding if

the interrupt is unmasked.

The receive serial bit stream processing resumes when the COFA condition is declared off. If channels are

configured in HDLC mode, then channels resume immediately if the COFA condition is declared off. While in

Transparent mode, channels start operating in the first time slot assigned to the logical channel. Thus, after a

RxCOFA, no channel recovery action is required because the channel recovers automatically.

For each transmitter path, the active channel (regardless of message processing) is immediately deactivated. As a

recovery channel action, the Host needs to reactivate the channel upon termination of the COFA condition. COFA

detection is not applicable in unchannelized mode. When COFA condition occurs, the transmit output is three-

stated. If operating in T1 mode, the F-bit cannot be three-stated after a COFA condition.

5.1.3

Out Of Frame (OOF)/Frame Recovery (FREC)

The Receiver Out-Of-Frame (ROOF) signal is asserted by the serial interface sourcing the channelized data to

CX28500. This signal indicates that the interface device has lost frame synchronization.

In the case of multiplexed E1 lines (2xE1, 4xE1), any given port ROOF signal can be asserted and deasserted as

the time slots are received from an Out-Of-Frame E1 followed by an in-frame E1.

ROOF assertion is detected by the Receiver Serial Interface (RSIU). If ROOF is asserted high and OOFIEN bit

field in the RSIU Port Configuration Descriptor is set, an OOF interrupt is generated toward the Host. For each

receive HDLC message that encountered an OOF condition, the corresponding Message Descriptor’s owner bit is

returned to the Host and a Buffer Status Descriptor is written with the OOF error encoding, along with EOM. The

EOM indicates that the current message is effectively ended as a result of a receiving error. The Buffer Status

Descriptor is written to Host memory only if configured to do so on a per-channel basis in the RDMA Channel

Configuration register. CX28500 then proceeds to the next Message Descriptor in the list of messages. As for the

RSIU, it starts to search for the opening flag of the next frame. For Transparent mode channels, the OOF causes

the data that is being transferred to the Host to be replaced by an all 1s sequence. No special actions are taken in

this case, and the Host must rely on the OOF interrupt to learn about the OOF.

While ROOF is asserted, if OOFABT bit field in the RSIU Port Configuration Descriptor is set, the receive process

is disabled. Thus CX28500 terminates any active messages for all active channels operating over the port;

otherwise, the receive process is enabled.

Notice that the OOF signal is examined on a per-time slot basis. Therefore, OOF assertion affects only those

logical channels that are mapped to time slots where OOF is asserted. The remaining time slots on the same serial

port are not affected by the OOF assertion on a specific time slot.

For ROOF to be deasserted, CX28500 must detect at least one frame without any OOF’s. As ROOF is deasserted,

CX28500 immediately restarts normal processing on all active channels. One to three time slots after deassertion

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of ROOF is detected, CX28500 generates an interrupt descriptor with the FREC (Frame Recovery) interrupt

encoding if the interrupt is not masked (OOFIEN = 1, RSIU Port Configuration Descriptor).

5.1.4

General Serial Port Interrupt

The ROOF signal can be used as a general serial port interrupt (SPORT).

If OOFABT is zero, OOFIEN is set, and ROOF signal deasserts or transitions from high to low, SPORT interrupt is

generated and the data stream processing is not affected. When ROOF transitions from low to high, the SPORT

interrupt is cleared.

5.1.5

Channel Clear To Send (CTS)

CX28500 transmit path can be configured to obey a Channelized Clear To Send (CTS) external signal on a per-

port basis by enabling the CTS_ENB bit in the TSIU Port Configuration register. CTS is sampled on the specified

active edge of TCLK depending on CTS_EDGE in Table 6-36, TSIU Port Configuration Register.

If CTS is deasserted (low), the channel assigned to the time slot sends continuous idle characters after the current

message has been completely transmitted. If CTS is asserted (high), message transmission continues.

When configured to operate in CTS mode, the channels of this specific port will not start a new message

transmission if the CTS is a logical 0. The channel response time to react to changes in the channelized CTS

signal is up to 32 line clocks.

5.1.6

Frame Alignment

CX28500 utilizes the TSYNC and RSYNC signals to maintain a timebase that keeps track of the active bit in the

current time slot. The mechanism is referred to as the frame synchronization flywheel. The flywheel counts the

number of bits per frame and automatically rolls over the bit count according to the programmed mode. The

TSYNC or RSYNC inputs mark the first bit in the frame. The flywheel is synchronized when CX28500 detects

TSYNC = 1 or RSYNC = 1, for transmit or receive functions, respectively. Once synchronized, the flywheel

maintains synchronization without further assertion of the synchronization signal.

The serial data stream that CX28500 can manage consists of either packetized data or unpacketized data.

CX28500 supports two types of data-stream modes: HDLC and Transparent.

In Transparent mode, message processing for every channel begins in the first time slot marked as the first time

slot in the channel’s frame structure. A user needs to configure the first time slot in the RSIU Time Slot

Configuration Descriptor. In the transmission side, the user needs to mark the last time slot where the channel

appears in the frame. This is done by setting the LAST_TS bit in the TSIU Time Slot Configuration Descriptor.

For a channel configured in HDLC mode—either transmit or receive direction, the channel waits for a

synchronization signal from the internal frame synchronization flywheel before starting processing of a new

message after channel activation. A Frame Synchronization signal must be provided once; after that, CX28500

keeps track of subsequent frame bit location with its flywheel mechanism.

The Frame Alignment is not relevant when the port is configured in Unchannelized mode, although in

Unchannelized mode each time slot is treated as the first time slot. By configuring more than one time slot in

unchannelized mode, (i.e., using TTS_ENDAD /RTS_ENDAD and TTS_STARTAD/RTS_STARTAD mechanism to

define one frame) the number of time slots between frames are considered as a virtual frame synchronization for

controlling the polling interval. (See Table 6-36, TSIU Port Configuration Register and Table 6-28, RSIU Port

Configuration Register).

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5.1.7

Polling

After channel activation, CX28500 must fetch Message Descriptors (MD) from shared memory to start the

message flow in and out of shared memory.

As an MD is fetched, CX28500 checks the owner bit to verify whether the buffer is available for CX28500. If the

owner bit indicates that the Host still owns the buffer, the Host has not prepared the data for processing in the data

buffers. If poll bit is enabled, CX28500 polls the Buffer Descriptor until the owner bit is switched to CX28500-owned.

If the owner bit is still Host-owned and no poll (NP = 1) and if TONRIEN/RONRIEN bit field is set to 1 in TDMA

Channel Configuration register or RDMA Channel Configuration register, an (ONR) interrupt is generated toward

the Host.

If the Host owns the buffer and polling is enabled, the channel direction is suspended from processing messages,

and CX28500 periodically polls the owner bit in the Buffer Descriptor until the owner bit is CX28500-owned. The

channel is capable of leaving this suspended state autonomously. Figures 5-1 and 5-2 illustrate the details.

Figure 5-1. RDMA State Machine

Always

INHRBSD = 1 While there is an EOM or EOB

CX28500 - Owned

Read

Message

Descriptor

(MD)

Owner = 0

INHRBSD = 0

(Allow Status

Write)

Write

Data

Poll (NP = 0)

Host - Owned

(Owner = 1)

CX28500 Owns

the BD

EOM or

EOB

Poll (NP = 0)

Not

EOM

CX28500 Owned

(Owner = 0)

Write

Poll

Buffer

Descriptor

(BD)

Not

EOB

Buffer Status

Descriptor

(BSD)

Host - Owned

(Owner = 1)

NP = 1

Read

Head

Pointer

RDMA

Suspend

State

CH_JUMP

CH_ACT

ONR

RxONR

ONRIEM = 1

CH_ACT

500052_054

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Figure 5-2. TDMA State Machine

Always

INHTBSD = 1

While there is an EOM and EOB

Read

Message

Descriptor

(MD)

CX28500 - Owned

Owner = 1

INHTBSD = 0

(Allow Status

Write)

Read

Data

Poll (NP = 0)

Host - Owned

(Owner = 0)

CX28500 Owns

the BD

EOM or

EOB

Poll (NP = 0)

CX28500 Owned

(Owner = 1)

Not

Write

Poll

Buffer

Not

EOB

EOM

Buffer Status

Descriptor

(BSD)

Descriptor

(BD)

Host-Owned

(Owner = 0 NP=1

0

Read

Head

Pointer

TDMA

Suspend

State

CH_JUMP

CH_ACT

ONR

TxONR

if TONRIEM = 1

an ONR Interrupt

is Generated

CH_ACT

500052_055

The frequency of polling is controlled independently for each port by the RPOLLTH or TPOLLTH bit fields in RSIU

Port Configuration register and TSIU Port Configuration register (poll throttle) bit fields in Table 6-28, RSIU Port

Configuration Register for the Rx direction and Table 6-36, TSIU Port Configuration Register for the Tx

direction.

The RPOLLTH or TPOLLTH bit fields in RSIU Port Configuration register and TSIU Port Configuration register, bit

field specifies how often CX28500 checks the owner bit in a Host-owned Buffer Descriptor. The values correspond

to 1, 2, 4, 8, 16, 64, 128, and 256 frame periods.

For polling to work properly and efficiently, it is mandatory that the FIRST (receive time

slot)/LAST (transmit time slot) indications be configured for each channel regardless of the

operational mode (i.e., HDLC, transparent, etc.). The polling mechanism in the CX28500

uses these markings as triggering points. When configured correctly, CX28500 polls on a

channel once at the selected poll throttle rate instead of polling at every time slot allocated

to that channel, as in the case of hyperchannels. When a channel consists of only one time

slot, as in a DSO channel, its corresponding receive time slot should have the FIRST_TS bit

set. Likewise, its corresponding transmit time slot should have the LAST_TS bit set.

NOTE:

If the serial port is configured to unchannelized mode, this mechanism is still implemented. The user programs the

Section 6.7.6 (for the transmit) or Section 6.6.6 (for the receive) as follows:

1. Program the STARTAD to point to the single entry that is used for this port in the Time Slot Configuration

Descriptor.

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2. Program the ENDAD to point at the entry STARTAD+N where N is the size of the frame to be used for the poll

mechanism; N may be zero, too.

5.2

Serial Port Interface Definition in TSBUS Mode

A port operation mode is configured by programming the TPORT_TYPE and RPORT_TYPE bit fields in RSIU and

TSIU Port Configuration registers. TPORT_TYPE and RPORT_TYPE must have the same number of time slots

configured for each TSBUS port, and STB sampling edges must be programmed the same for both receive and

transmit directions. When configured to operate in TSBUS mode, the frame synchronizing signals for both receive

and transmit directions are driven by the STB signal. This leaves the RSYNC and TSYNC unused, which become

RSTUFF and TSTUFF signals, respectively. Additionally, both RxClk and TxClk signals must be synchronized so

that the sampling of STB in both directions is consistent.

5.2.1

TSBUS Frame Synchronization Flywheel

The CX28500’s TSTB signal maintains a time-base that keeps track of the active bit in the current time slot. The

mechanism is referred to as the frame synchronization flywheel. The flywheel counts the number of bits per frame

and automatically rolls over the bit count according to the programmed mode. The TSTB input marks the first bit in

the frame. A flywheel exists for both the transmit and receive directions for each port. The TSB assertion works the

first bit of time slot in the TSBUS frame. The flywheel is synchronized when CX28500 detects TSTB = 1. Once

synchronized, the flywheel maintains synchronization without further assertion of the synchronization signal.

A time slot counter within each port is reset at the beginning of each frame and tracks the current time slot being

serviced.

5.2.2

TSBUS Change Of Frame Alignment (COFA)

A COFA condition is defined as a frame synchronization event detected when it is not expected. A COFA condition

also detects if the first occurrence of frame synchronization was not present. A COFA condition can occur only if

TSTB is asserted in any time slot position that is not the first time slot of the frame. The flywheel always counts the

number of time slots allocated to a specific TSBUS port (when the port is enabled). If TSTB is asserted at any time

other than a time coincident with CX28500’s interval flywheel rollover (the first bit of TS0), COFA is reported on

both receive and transmit port directions.

When a COFA condition is detected by the serial interface, an internal COFA signal is asserted until the COFA

condition is declared off. A COFA condition is declared off when there is a complete frame without an unexpected

TSTB pulse. Thus, an internal COFA signal is asserted for at least two frame periods. During the frame period

when the internal COFA is asserted, CX28500’s serial line processor (SIU) terminates all messages that are found

to be active during the COFA condition. For each receiver and transmitter channels found to be active and

processing a message, the corresponding message descriptor’s owner bit is returned to the Host, and a Buffer

Status Descriptor is written with the COFA error encoding. The Buffer Status Descriptor is written if the INHRBSD

bit field in the RDMA Channel Configuration register is disabled (set to 1). CX28500 then proceeds to the next

message descriptor (MD) from Table 6-39, Transmit or Receive Message Descriptor Table (TMDT) or (RMDT)

Content.

Assertion of COFA condition generates a COFA interrupt encoded in the Interrupt Status Descriptor (ISD) toward

Host if this interrupt is unmasked. (See Table 6-28, RSIU Port Configuration Register and Table 6-36, TSIU Port

Configuration Register, respectively RCOFA_EN or/and TCOFA_EN bit fields.)

If a synchronization signal (TSTB) is received (low to high transition on TSTB) while the internal COFA is asserted,

an Interrupt Descriptor with the COFA interrupt encoding is generated immediately if this interrupt is not masked.

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When the internal COFA is deasserted, CX28500 generates an Interrupt Descriptor with CREC event encoding if

the interrupt is unmasked.

The receive serial bit stream processing resumes when the COFA condition is declared off. If channels are

configured in HDLC mode, channels resume immediately when the COFA condition is declared off. While in

Transparent mode, channels start operating in the first time slot assigned to the logical channel. Thus, after a

RxCOFA, no channel recovery action is required since the channel recovers automatically.

For each transmitter path, the active channel (regardless of message processing) is immediately deactivated. As a

recovery channel action, Host needs to reactivate the channel upon termination of the COFA condition. COFA

detection is not applicable in unchannelized mode. When a COFA condition occurs, the transmit output is three-

stated.

5.2.3

TSBUS Out Of Frame (OOF)/Frame Recovery (FREC)

There is no Out Of Frame (OOF) condition while operating in TSBUS mode. The ROOF signal is used as a TSTB

input pin (for reference see Figure E-1, CX28500 Time Slot Interface Pins).

5.2.4

TSBUS Frame Alignment

The serial data stream that CX28500 can manage consists of either packetized data or unpacketized data.

CX28500 supports two types of data-stream modes: HDLC and Transparent.

In Transparent mode, message processing for every channel begins in the time slot marked as the first time slot in

the channel’s structure. Regardless of the channel protocol, the user needs to configure the first time slot for both

receive and transmit directions (see RFIRST_TS and TFIRST-TS bit fields in Table 6-26, RSIU Time Slot

Configuration Descriptor and Table 6-34, TSIU Time Slot Configuration Descriptor).

For a channel configured for HDLC mode, either transmit or receive direction, the channel will wait for a

synchronization signal from the internal frame synchronization flywheel before starting processing new messages

after channel activation.

A Frame Synchronization Signal (TSTB) must be provided one time, after that, CX28500 keeps track of

subsequent frame bit location within the flywheel mechanism.

5.2.5

TSBUS Polling

The polling mechanism is the same as in the conventional mode.

5.2.6

TSBUS Channel Clear To Send

While operating in TSBUS mode, there is no CTS signal since the related input pin is defined to be TSTB (for

reference see Figure E-1, CX28500 Time Slot Interface Pins).

5.2.7

TSBUS Interface

The TSBUS is a time slot interface. The digital communication data paths and overhead channels consist of

payload data and overhead data derived from either SONET or SDH data streams, and payload and overhead data

derived from either electrical DS3 or E3 data streams. One of the overhead channels may consist of HDSL

messages generated and received by the Command Status Processor (CSP). The messages are provided by the

local processor that is connected to access and configure local device registers. The TSBUS interface is capable of

full-duplex (bidirectional) transmission of data between one device and the CX28500 device. The interface consists

of two, 1-bit wide serial interfaces: a bidirectional payload TSBUS and bidirectional overhead TSBUS.

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ATSBUS frame structure is defined as an integer multiplication of bytes. There are seven signals that define the

TSBUS interface. In the TSBUS mode, the Rx and Tx are synchronous (i.e., the first bit of Tx and Rx frame is

sampled on the falling edge or rising edge of RCLK/TCLK on TDAT/RDAT). TSTB defines the frame

synchronization, which marks the first bit of Rx/Tx frame. TSTUFF acts as a flow control signal that indicates “stuff”

(update) to be sent on the following time slot mapped to the logical channel. TSTUFF is sampled in the first two bits

of the channel’s time slot.

In the TSBUS transmit direction, CX28500 requires the stuff status for each time slot to be presented at its

TSTUFF input exactly eight time slots in advance of the actual time slot for which the stuff status is applied. The

amount of the TSTUFF advance is fixed at eight time slots even though the number of time slots within a frame

might vary.

For the receive direction, CX28500 requires the stuff status for each time slot to be presented at its RSTUFF input

on the current time slot for which the stuff is applied.

5.2.8

Payload TSBUS

Examples of the payload TSBUS operates at a data rate of 51.84 Mbps. It carries the data path signals derived

from either SONET, SDH, electrical DS3, or the electrical E3 signals.

The data on the Payload TSBUS is framed and consists of 84 time slots.

5.2.8.0.1

Time Slot Bus Features

Payload Data Paths are as follows:

•

SONET/SDH Payload

Electrical DS3 to DS1—x28 DS1 672 time slots

F-bits not mapped with DS1 signals.

NOTE:

•

Electrical E3 to E1—x16 E1 Framers 651 time slots

Time Slot 0 not mapped.

NOTE:

•

STS-1 to DS3/E3 to X28 DS1 (672 time slots) / X21 E1 (651 time slots)

x28 DS1—672 time slots

x21 E1—651 time slots

x16 E1—496 time slots

VT1.5—672 time slots

VT2.0—651 time slots

VT1.5 to DS1—672 time slots

VT2.0 to E1—21 time slots

TUG-2 to DS1—672 time slots

TUG-2 to E1—651 time slots

DS1 F-bits—1 time slot

E1 Si bits—1 time slot

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5.2.9

Overhead TSBUS

Examples of the overhead TSBUS operates at a data rate of 12.96 Mbps. It carries PDH, or SDH overhead

communication channels and it carries the data monitoring and data configuration for the device that

communicates through TSBUS interface with CX28500.

The data on the overhead TSBUS is framed and consists of 84 time slots.

5.2.9.1

Overhead Data Channels

The sources and destinations of overhead data transferred to and from the Overhead TSBUS are as follows:

•

SONET

•

SONET/SDH Section DCCR—3 time slots

Line CDDM Overhead—9 time slots

SPE Path F2 User Data—1 time slot

SPE Path F3 User Data—1 time slot

SPE N1 Tandem Connection—1 time slot

•

DX3 – DS3 TDL Overhead—1 time slot

Command Status Processor (CSP)—100 time slots

5.2.9.2

TSBUS Time Slots

The number of time slots configured for data payload or overhead are illustrated in Figure 5-3.

Figure 5-3. TSBUS Number of Time Slots into a Payload or Overhead Frame

1 Byte per Time Slot

Payload and Overhead Time Slot

Bus Frame = 84 Time Slots

1

2

3

4

5

6

7

8

2

3

4

5

6

79 80 81 82 83 84

. . .

Time Slot No. 1 is First Byte of

Payload and Overhead TSBUS Frame

Time Slot No. 84 is Last Byte of

Payload and Overhead TSBUS Frame

500052_025

5.2.9.2.1

TSBUS References

For a detailed description of the TSBUS interface, see related documents:

1. Mindspeed’s CX29503 Data Sheet (Section 2.10).

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6.0 Memory Organization

CX28500 interfaces with a system Host using a set of data structures located in shared memory. CX28500 also

contains a set of internal registers, which control CX28500, that the Host can configure. This section describes the

various shared memory data structures and the layout of individual registers that are required for the operation of

CX28500.

6.1

Memory Architecture

CX28500 supports a descriptor-based memory architecture wherein data is continually moved into and out of a

table of data buffers in shared memory for each active channel. This assumes a system topology in which a Host

and CX28500 both have access to shared memory for data control and data flow. The data structures are defined

in a way that the control structures and the data structures may or may not reside in the same physical memory and

may or may not be contiguous. In other words, this data structure is a table of descriptors with pointers to data

buffers. The Host allocates and de-allocates the required memory space as well as the size and number of data

buffers within that space.

6.1.1

Register Map and Shared Memory Access

During CX28500's PCI initialization, the system controller allocates a dedicated 1 MB-memory range to CX28500.

The memory range allocated to CX28500 must not map to any other physical or shared memory. Instead, the

system configuration manager allocates a logical memory address range and notifies the system or bus controllers

that any access to these ranges must result in a PCI access cycle. CX28500 is assigned these address ranges

through the PCI configuration cycle. Once configured, CX28500 becomes a functional PCI device on the bus.

As the Host accesses CX28500's allocated address ranges, the Host initiates access cycles on the PCI bus. It is up

to individual CX28500 devices on the bus to claim these access cycles. As CX28500's address ranges are

accessed, CX28500 behaves as a PCI slave device while data is being read or written by the Host. CX28500

responds to all access cycles where the upper 12 bits of a PCI address match the upper 12 bits of CX28500’s Base

Address register (see Table 3-6, Register 4, Address 10h).

For CX28500, a 1 MB-memory space is assigned to the CX28500 Base Address register, which is written into the

PCI configuration space Address 10h, register 4 in PCI Configuration registers. Once a base address is assigned,

a register map is used to access individual device resident registers. The 1 MB-memory range assigned to

CX28500 does not restrict CX28500's PCI interface from attempting to access this memory space. However,

CX28500 cannot respond to an access cycle that CX28500 itself initiates as the bus master.

The register map provides the byte offset from the Base Address register where registers reside. The register map

layout is given in Table 6-1, PCI Register Map. It should be noted that there are two address spaces. The first one

includes registers that are directly accessed by the Host through the PCI, and the second includes the registers

existing in shared memory that are accessed by CX28500 only through the Service Request Mechanism.

Therefore, the same address offsets, or registers, may appear in both register maps memory spaces.

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The only registers that can be directly accessed by the Host as slave reads or writes are the Rx Port Alive, the Tx

Port Alive, the Interrupt Status Descriptor, the Interrupt Queue Pointer, the Interrupt Queue Length, the Service

Request Length, the Service Request Pointer, and the Soft Reset registers specified in CX28500’s Register Map.

When the Host writes directly into a corresponding register, CX28500 behaves as a PCI slave while this write is

performed.

All other registers need to be accessed through the Service Request Mechanism. After the PCI reset, when

CX28500 is ready for configuration, these registers are updated with the appropriate shared memory values

through a Configuration Write Service Request. After the Host has configured the shared memory image of

CX28500’s registers, and CX28500 has finished its local configuration (i.e., SRQ_LEN bit field in Service Request

Length is reset to zero), the Host issues a service request by writing directly into the Service Request Length

register. Writing to this location the actual value of the Service Request Descriptor Table Length from shared

memory causes CX28500 to start performing the Service Request Descriptor Table.

Table 6-1.

PCI Register Map

Byte

Offset

Number of

instances

Reset

Value

Access

Type

PCI

Configuration

Register 4

Register

Receive Port Alive

Transmit Port Alive

00000h

00004h

00008h

0000Ch

00010h

00014h

00018h

00020h

Per Port

Per Chip

0

Read Only

Read/Write

Write Only

CX28500

Base Address

Register

(3)

Interrupt Status Descriptor

Interrupt Queue Pointer

Interrupt Queue Length

Service Request Length

Service Request Pointer

Soft Chip Reset

(2)

3FF

0

FOOTNOTE:

(1)

There are two address spaces. The first address space includes registers that are directly accessed by

Host through the PCI. The second address space (shown in Table 6-2) represents the CX28500’s register

map accessible by CX28500 via the Service Request Mechanism. Therefore, all the registers shown in this

table can be directly accessed by the Host.

During internal initialization, the Service Request Length becomes non-0 to prevent the Host from writing

to this register since the Host can only modify this register when its value is 0. After initialization, this

register is returned to 0, allowing the Host to modify its content.

The Interrupt Status Descriptor is partially readable and partially writable. The write pointer cannot be

modified, but the read pointer is modifiable. Any write accesses to the write pointer are ignored by

CX28500.

(2)

(3)

Table 6-2.

Indirect Register Map Address Accessible via Service Request Mechanism (1 of 2)

Number of

Access

Type

Register

Address

dword

Reset Value

instances

Registers

RSLP Channel Status

00000h

01000h

02000h

03000h

04000h

1024

4096

Per Channel

Per Time Slot

0

Read Only

Read/Write

Write Only

Read/Write

RSLP Channel Configuration

RDMA Buffer Allocation

RDMA Configuration

—

RSIU Time Slot Configuration

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Table 6-2.

Indirect Register Map Address Accessible via Service Request Mechanism (2 of 2)

Number of

dword

Registers

Number of

instances

Access

Type

Register

Address

Reset Value

RSIU Time Slot Pointer

08000h

08080h

08100h

08104h

08108h

0810Ch

08110h

08114h

08118h

10000h

11000h

12000h

13000h

14000h

18000h

18080h

32

Per Port

—

0

Read/Write

Read Only

Read/Write

RSIU Port Configuration

RSLP Max Message Length1

RSLP Max Message Length2

RSLP Max Message Length3

Receive Base Address Head Pointer (RBAHP)

Transmit Base Address Head Pointer (TBAHP)

EBUS Configuration

1

Per Chip

—

0

1

Per Chip

1

Per Chip

1

Per Chip

1

Per Chip

0

1

Per Chip

0

Global Configuration

1

Per Chip

0

TSLP Channel Status

1024

4096

32

Per Channel

Per Time Slot

Per Port

0

TSLP Channel Configuration

TDMA Buffer Allocation

—

0

TDMA Configuration

TSIU Time Slot Configuration

TSIU Time Slot Pointer

TSIU Port Configuration

32

Per Port

GENERAL NOTE:

1. These registers must be accessed through the Service Request Mechanism. As shown in Table 6-7, these registers’ corresponding

addresses are written into bits [18:0] at the Indirect Register Map Address field, which is located in the Device Configuration Descriptor.

2. For better performance and ease of implementation, it is recommended that this Service Request memory block be separated into two

blocks for access. Service Request Block 1 starts at address 00000h and ends at address 0811Ch. Service Request Block 2 starts at

address 10000h and ends at address 18100h. This separation is made possible by the unused memory gap occurring between the Global

Configuration register and the TSLP Channel Status registers.

It is critically important that upon channel activation, shared memory and internal registers must be initialized, valid,

and available to CX28500. CX28500 uses the information within the shared memory descriptors to transfer data

between the serial interface and shared memory. CX28500 assumes the information is valid once a channel is

activated.

6.2

Global Registers

6.2.1

Service Request Mechanism

The registers that need to be configured and checked to enable the activity of the service request mechanism are

as follows:

•

Service Request Length register (see Table 6-3)

Service Request Pointer register (see Table 6-4)

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The availability of the device to the Host for access is an example of information provided by querying the Service

Request Length register. After the PCI reset, CX28500 sets the SRQ_LEN field in Service Request register to all

1s or 0x3FF, until it performs all the internal initialization. Since the Host cannot modify the Service Request Length

register while it is non-0, the setting of this register to all 1s by CX28500 effectively prevents the Host from making

additional service requests that could interfere with its internal initialization. When CX28500 is finished with the

internal initialization, it clears this field to 0. The cleared SRQ_LEN indicates to the Host that it is ready. From this

point, the Host is able to directly write this field with the actual number of service requests that CX28500 needs to

perform to configure its registers. The number of SRQs written by the Host is stored in the SRQ_LEN field. While

processing the service request commands, the SRQ_LEN field indicates how many commands are yet to be

processed by CX28500 before a new command can be issued. Host slave writes to this register triggers the

execution of the service request list specified by the Service Request Pointer register.

Host slave writes to SRQ_LEN field, while the previous list of service requests has not been

processed (i.e., SRQ_LEN is reset) implies unpredictable behavior.

NOTE:

Table 6-3.

Service Request Length Register

Bit

Field Name

Value

Description

31:10

9:0

RSVD

0

Reserved.

SRQ_LEN [9:0]

—

Service Request Length.

After a PCI reset, Host reads the SRQ_LEN bit field through PCI slave access. While the SRQ_LEN

value equals 0x3FF, CX28500 is not ready to start the configuration of the device. If CX28500 resets

this value, the device is ready to be configured. Host directly writes at this location the number of

Service Request Descriptors (SRD) which were allocated in Service Request Descriptor Table

(SRDT) i.e., shared memory. The SRDs was previously initialized and configured in SRDT. This value

represents the number of service request commands queued by Host (i.e., the SRDT), that are

waiting to be performed. Real-time reads from SRQ_LEN provides the number of service request

commands that are waiting to be served.

Do not write SRQ_LEN until after the SRQ_PTR, or the address of the Service Request Descriptor

Table, is initialized. Because CX28500 starts to process service requests whenever SRQ_LEN is non-

0 by modifying SRQ_LEN to the non-0 before a valid SRQ_PTR is written, CX28500 processes the

invalid SRQ_PTR, resulting in unpredictable behaviors.

The Service Request Pointer register provides the address of the Service Request Descriptor Table (see Table 6-

4). Host needs to allocate and initialize this table in shared memory.

Table 6-4.

Service Request Pointer Register

Bit

Field Name

Value

Description

31:3

SRQ_PTR [31:3]

—

Service Request Pointer. These 29 bits are appended with 000b to form a 64-bit address Quadword

aligned. This address points to the first entry on the Service Request Descriptor Table allocated in

shared memory.

2:0

SRQ_PTR [2:0]

0

To ensure Quadword alignment.

6.2.1.1

Service Request Descriptor

A Service Request Descriptor (SRD) is a 4-dword location in shared memory. Actually, one represents an entry in

the SRD table. The SRD is defined as a union type in C, which allows different commands to be configured in a 4-

dword space. The SRD can handle three different configurations: Device Configuration Descriptor (DCD), EBUS

Configuration Descriptor (ECD), and Channel Configuration Descriptor (CCD).

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A list of service request commands is defined as a sequence of SRDs. The following instructions, referred to in the

document as OPCODE, are supported:

•

Configure a port/channel

Read specific descriptors

Activate or reactivate a channel

Deactivate a channel

Jump to new Buffer Descriptor table

No-operation command

Perform EBUS access (read or write)

Table 6-5 defines the Service Request Descriptor OPCODE.

A service request is issued to a specific channel, or per whole device. Each service request command is

acknowledged by sending a service request acknowledge interrupt descriptor back to the Host if the SACKIEN bit

is enabled in SRD. It is possible for the Host to issue multiple service requests successively without expecting or

receiving acknowledgments from each request if the SACKIEN bit was not set accordingly in the SRD.

Host can only set the SACKIEN bit in the last SRD so if a SACK Service Request Acknowledge interrupt is

received, it validates the whole list of service request commands.

Activate, Deactivate, or Jump commands could take a long time before they are actually executed by CX28500.

CX28500 returns the SACK (if SACKIEN bit is set) immediately after it started the command execution. Therefore,

the Host may not assume the command was actually executed just by detecting the SACK was returned. Another

interrupt, End Of Command Execution (EOCE), is defined for each of these three commands. The Host may

assume the command was actually executed only after receiving the appropriate EOCE.

In general, SACK is only issued after each service table entry is completed. However, for Activate, Deactivate, and

Jump commands, SACKs are issued after SLP is completed, but before DMA completes (see End of Command

interrupt).

Table 6-5.

OPCODE

NOP

Service Request Descriptor—OPCODE Description (1 of 2)

Value

Description

0h

No Operation.

This service request performs no action other than to facilitate a Host Service Acknowledge Interrupt (SACK). This

would be used as a UNIX ping-like operation to detect the presence of CX28500.

CONFIG_WR

1h

2h

Configuration Write.

This is a request to copy from shared memory data into CX28500’s internal registers. This service request can be

issued for either one register or for the whole CX28500 register map (up to 16 K-1 registers), depending on the

value of LENGTH bit field set in Service Request Descriptor.

Note that the Service Request Descriptor used for this command is Device Configuration Descriptor. The LENGTH bit

value in this descriptor is up to 16 K. Assuming that the Host configures an 16 K register structure in shared

memory and the LENGTH bit field is set accordingly, CX28500 configures the entire configuration in one service

request command in bursts of 32 dwords (i.e., the maximum allowed PCI burst).

CONFIG_RD

Configuration Read.

This is a request to copy the configuration of CX28500’s internal registers into shared memory. The configuration

located at the address specified by the CX28500 register Map Base Address Offset is read and copied to the address

specified by the shared memory address. The number of dwords copied is specified in the LENGTH bit field. The

user needs to instruct CX28500 to perform the correct number of reads so that when data is written in shared

memory, no data overlapping occurs. The Service Request Descriptor used for this command is Device

Configuration Descriptor.

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Table 6-5.

OPCODE

CH_ACT

Service Request Descriptor—OPCODE Description (2 of 2)

Value

Description

3h

Channel Activation.

This is a request to activate a single channel. CX28500 assumes that the channel was already configured. If the

channel is currently active, this command results in a destructive termination of the current message being

processed, as well as flushing any other messages residing in the channel’s FIFO. CX28500 fetches the channel’s

new head pointer from shared memory (actually from the Transmit Head Pointer Table (THPT) or Receive Head

Pointer Table (RHPT)), before it internally activates the channel. The Service Request Descriptor used for this

command is Channel Configuration Descriptor.

CH_DEACT

CH_JMP

4h

5h

Channel Deactivation.

This is a request to deactivate a channel. This command results in a destructive termination of the current message

being processed, and flushing of any other messages residing in the channel’s FIFO. The SRD used for this

command is Channel Configuration Descriptor.

Channel Jump.

This is a request to jump to a new head pointer buffer descriptor. If there is an active transfer of a message from or

to shared memory, the channel jump service request command (CH_JMP) is not executed until an EOM indication is

received. When an EOM indication is received (or if there is no active transfer), CX28500 fetches a new head pointer

buffer descriptor for this channel from shared memory (actually from the Transmit Head Pointer Table (THPT) or

Receive Head Pointer Table (RHPT)).

EBUS_WR

EBUS_RD

6h

7h

EBUS Write.

This is a request to execute write transaction(s) over the EBUS. Data is copied from Host memory to the EBUS.

EBUS Read.

This is a request to execute read transaction(s) over the EBUS. Data is copied from the EBUS Address specified in

the 3rd dword of EBUS Configuration Descriptor to the shared memory location specified in the 2nd dword of EBUS

Configuration Descriptor. The data length copied from one location to another location is specified by LENGTH bit

field in EBUS Configuration Descriptor. Note: The EBUS_RD and EBUS_WR Service Request mechanism allow a

maximum of 16 K dwords transfer to/from the EBUS. The transaction is split to bursts of 32 dwords over the PCI.

RSVD

8h-1Fh

Reserved

6.2.1.2

Service Request Descriptors

Each SRD is 4 dwords. The SRDs used by CX28500 are as follows:

•

Device Configuration Descriptor (DCD)

EBUS Configuration Descriptor (ECD)

Channel Configuration Descriptor (CCD)

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6.2.1.2.1

Device Configuration Descriptor (DCD)

Table 6-6 presents the structure of DCD.

Table 6-6.

Device Configuration Descriptor

Dword Number

Bit 31

Bit 0

(1)

dword 0

dword 1

dword 2

dword 3

OPCODE[31:27]

SACKIEN[26]

Reserved[25:14]

Length[13:0]

(2)

Shared Memory Pointer [31:2]

(1)

(2)

Reserved [31:19]

Indirect Register Map Address [18:2]

(1)

Reserved

FOOTNOTE:

(1)

All reserved bits must be written to 0 for forward compatibility.

Bits [1:0] must be equal to zero for dword alignment.

(2)

Table 6-7 describes these fields.

Table 6-7.

Device Configuration Field Descriptions

Dword

Number

Size

(bits)

Descriptor Field

Value

Description

OPCODE

5

1

2

0

1

CONFIG_WR

CONFIG_RD

SACK interrupt disabled

SACKIEN

SACK interrupt enabled. An appropriate interrupt is generated after the

command execution is completed.

dword 0

Reserved

Length

12

14

0

A read from this field returns all zeros. A write to this field does nothing.

—

Number of dword memory commands. Zero length equals 16 K, but valid

maximal length is [16 K–1]. Therefore, a length of 0 is invalid; do not use.

dword 1

dword 2

Shared Memory Pointer

32

19

—

Address in shared memory where the Host service request descriptor table

exists. The two LSBs must equal 0 for dword alignment.

Indirect Register Map

Address

Register Map Address to the specified register that needs to be configured.

This address is a dword-aligned address, meaning the 2 LSB must equal to

0. Bits [18:2] contain the map address while bits [31:19] are reserved.

GENERAL NOTE:

1. In general, reserved fields should be written with zeros.

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6.2.1.2.2

EBUS Configuration Descriptor (ECD)

Table 6-8 presents the EBUS Configuration Service Request Descriptor.

Table 6-8.

EBUS Configuration Service Request Descriptor

Dword

Number

Bit 31

Bit 0

dword 0

OPCODE[31:27]

SACKIEN[26]

Reserved [25:19]

FIFO_BURST[18]

EBUS Byte Enable

Length[13:0]

[17:14]

(1)

dword 1

dword 2

dword 3

Shared Memory Pointer[31:2]

(3)

EBUS Base Address Offset[30:0]

(2)

Reserved

FOOTNOTE:

(1)

Bits [1:0] must equal 0 for dword alignment.

All reserved bits must be written to zeros for forward compatibility.

Bit 31 must be set to 1 for all transactions.

(2)

(3)

Table 6-9 describes the ECD fields.

Table 6-9.

Field Descriptions of ECD

Dword

Number

Size

(bits)

Descriptor Field

Value

Description

OPCODE

5

1

6

7

0

1

0

1

EBUS_WR

EBUS_RD

SACKIEN

SACK interrupt disabled.

SACK interrupt enabled.

Reserved

7

1

A read from this field returns all zeros. A write to this field does nothing.

Do increment address by 1 after each EBUS access.

dword 0

FIFO-BURST

Do not increment EBUS address for this access. This feature allows same

location access (i.e., FIFO read/write).

EBUS Byte Enable

Length

4

—

Determinates which byte lanes carry meaningful data in EBUS

transactions. The BE [0] applies to byte 0 (LSB).

14

32

Number of dwords to transfer over EBUS (up to 16 K dwords, in bursts of

up to 32 dwords per burst). LENGTH = 0 is not allowed.

dword 1

dword 2

Pointer Shared Memory

The address of shared memory EBUS base address, where the

configuration of local devices exists. This pointer is dword-aligned, hence

bits [1:0] must equal to 0.

(1)

EBUS Base Address Offset

31

—

EBUS base (byte-aligned) address for an EBUS transaction.

FOOTNOTE:

(1)

Bit 31 must be set to 1 for all transactions.

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6.2.1.2.3

Channel Configuration Descriptor (CCD)

Table 6-10 presents the structure of CCD.

Table 6-10. Channel Configuration Service Request Descriptor

Dword Number

Bit 31

Bit 0

(1)

dword 0

dword 1

dword 2

dword 3

OPCODE[31:27]

SACKIEN[26]

Reserved[25:11]

Direction[10]

Channel[9:0]

(1)

Reserved

(1)

Reserved

(1)

Reserved

FOOTNOTE:

(1)

All reserved bits must be written to zeros for forward compatibility.

Table 6-11 describes the CCD fields.

Table 6-11. Fields Description of CCD

Dword

Number

Size

(bits)

Descriptor Field

Value

Description

OPCODE

5

0

3

NOP

CH_ACTIV

CH_DEACT

CH_JUMP

4

5

SACKIEN

1

0

SACK interrupt disabled.

SACK interrupt enabled.

dword 0

1

Reserved

Direction

—

1

0

A read from this field returns all zeros. A write to this field does nothing.

The command is for the Receive channel.

0

1

The command is for the Transmit channel.

Channel

10

—

Channel number. This field is interpreted as a channel number for the CH_ACT,

CH_DEACT and CH_JUMP command. The field is interpreted as reserved for the NOP

command.

GENERAL NOTE: In general, reserved fields should be written to with zeros.

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6.2.2

Port Alive Registers

The Receive and Transmit Port Alive registers are read-only registers. These registers can only be accessed via

direct PCI read.

Each bit of the Receive and Transmit Port Alive register represents the device port number. Refer to Tables 6-12

and 6-13 for these registers.

Table 6-12. Receive Port Alive Register

Bit

Field Name

Value

Type

Description

31:0

RPA [31:0]

0

RO

This register controls the access to the Receive Port Configuration

register. If one of 32 bits is set to 1, then the Receive Port

Configuration for that specific port is allowed.

Table 6-13. Transmit Port Alive Register

Bit

Field Name

Value

Type

Description

31:0

TPA [31:0]

0

RO

This register controls the access to the Transmit Port Configuration

register. If one of 32 bits is set to 1, then the Transmit Port

Configuration for that specific port is allowed.

These registers operate as a gate which enables or disables the access to the Port Configuration register. If the

corresponding bit of the Receive and Transmit Port Alive register is set, a new port configuration for the specified

port is allowed.

After a PCI reset or Software Chip reset, all 32 bits of the Receive and Transmit Port Alive register are cleared (set

to 0). Each bit is automatically set to 1 after 8 or 16 serial clock cycle occur on that specific port. After the

corresponding bit is set to 1, the Host can write to the Port Configuration register. In addition, Port Alive can also be

reset by writing to the Port Configuration register. If the Host writes to a dead port, the SRQ completes but the

register is not modified.

The Host cannot program a new port configuration until the corresponding bit/port is set to 1 in the Port Alive

register depending upon the direction of receive or transmit.

A proper configuration sequence for accessing the Port Configuration register is as follows:

1. Host polls the Port Alive register for the specific port/direction and waits (at an interval of 8–16 line clocks) until

the corresponding bit in the Port Alive register is set.

2. Host issues a Service Request (SRQ) Port Configuration command and waits for a Service Request

Acknowledge (SACK), or polls the SR length to determine when the table entry is completed.

3. Host gets the SACK.

Writing to the Port Configuration register causes the corresponding bit from the Port Alive

register to be cleared. This bit is automatically set to 1 after 8 or 16 serial clocks occur;

therefore a new port configuration is allowed.

NOTE:

4. Host checks if a new port configuration is allowed by checking he corresponding bit in the Port Alive register.

Go to 1.

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6.2.3

Soft Chip Reset Register

Any write of any value to a Soft Chip Reset (SCR) generates a soft reset for CX28500. An SCR write affects

CX28500 exactly as PCI Reset, except that the PCI block is not reset. No PCI configuration is performed after a

SCR.

6.2.4

General PCI Note

While addressing CX28500 in slave mode, every PCI access must have all four byte enables active. Any PCI

accesses without all four bytes enabled is treated as if all four byte enables were inactive.

6.3

Interrupt Level Descriptors

CX28500 generates interrupts for a variety of reasons. Interrupts are events or errors detected by CX28500 during

internal processing. Interrupts are generated by CX28500 and forwarded to the Host for servicing.

CX28500 gathers the many events and errors (generated by all units such as RxDMA and TxDMA, RSLP and

TSLP, and SIU) and notifies the Host by asserting PCI interrupts. Interrupt descriptors are generated by CX28500

and forwarded to the Host for servicing. Individual types of interrupts can be masked from being generated by

setting the appropriate interrupt mask or interrupt disable bit fields in various descriptors. The interrupt mechanism,

each individual interrupt, and interrupt controlling mechanisms are discussed in this section.

6.3.1

Interrupt Queue Descriptor

CX28500 employs a single Interrupt Queue Descriptor to communicate interrupt information to the Host. This

descriptor is stored within CX28500 in an internal register. The descriptor in this register stores the location and the

size of an interrupt queue in allocated shared memory where the interrupt descriptors is directly pushed by

CX28500 while acting as a PCI bus master. CX28500 requires this information to transfer interrupt descriptors to

shared memory. All the interrupts are processed by the Host, in an Interrupt Service Routine (ISR). CX28500

directly writes Interrupt Descriptors into the shared memory Interrupt Queue using PCI bus master mode.

CX28500's PCI interface must be configured to allow bus mastering.

The Interrupt Queue Descriptor (i.e., Interrupt Queue Pointer and Interrupt Queue Length) is initialized by the Host

via a direct PCI write transaction. After a PCI Reset or Software Chip Reset (SCR), the Interrupt Queue Pointer is

the first register that needs to be initialized. A typical initialization procedure is as follows:

1. The Host writes in the Interrupt Queue Pointer register allocated by performing a direct write to the address of

the Interrupt Queue in shared memory.

2. The Host writes the Interrupt Queue Length register by performing a direct write to this location, the value of

the interrupt queue length allocated in shared memory.

The user can change, at any time, the length of the Interrupt Queue (IQLEN field in the

Interrupt Queue Length register) or the pointer value of the Interrupt Queue Pointer (IQPTR

field in the Interrupt Queue Pointer register). However, writing to these registers while the

chip is operating may result in flushing the interrupts held in the internal FIFO.

NOTE:

Tables 6-14 through 6-16 list the details of the Interrupt Queue descriptor.

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Table 6-14. Interrupt Queue Descriptor

Byte Offset

in CX28500 Register Map

Field Name

dwords

000Ch

0010h

Interrupt Queue Pointer

Interrupt Queue Length

1

Table 6-15. Interrupt Queue Pointer

Bit

Field Name

Value

Description

31:3

IQPTR [31:3]

—

These 29 bits are appended with 000b to form a 64-bit aligned address. This address points to the first

entry (Quadword) of the Interrupt Queue buffer. The Host can change this field while the chip is

operating. However, this results in flushing all interrupts residing in the internal interrupts FIFO.

2:0

IQPTR [2:0]

0

Ensures 64-bit alignment.

Table 6-16. Interrupt Queue Length

Bit

Field Name

Value

Description

31:15

14:0

RSVD

0

Reserved.

IQLEN[14:0]

—

This 15-bit number specifies the number of interrupt descriptors. The maximum size for an interrupt

queue is 32,768 descriptors. This is a 0-based number. A value of 1 indicates that the queue length is 2

descriptors long, the required minimum.

The Host can change this field while the chip is operating. However, this results in flushing all interrupts

residing in the internal interrupts FIFO. After reset, IQLEN is set to 0. This has the effect of blocking all

the interrupt processing by CX28500.

Similarly, writing a 0 to IQLEN forces CX28500 to stop writing interrupts. This feature can be used to

switch interrupt queues. To switch interrupt queues, first write a 0 to IQLEN. Next, write the base address

of the new interrupt queue into IQPTR in the Interrupt Queue Pointer. Finally, write the new interrupt

queue length into IQLEN.

Note(s): Since CX28500 must work with 64-bit alignment, there must be an even number of entries in the buffer.

6.3.1.1

Interrupt Descriptors

The interrupt descriptor describes the format of data transferred into the queue. There are two different types of

interrupt descriptor. The first type represents DMA's block-related interrupts, and the second type represents other

interrupts. Both types are 64-bit fields. Generically, the interrupt descriptor includes fields for the following:

•

Identifying the source of interrupt from within the CX28500 channel causing the interrupt (0–1023) and

direction (receive or transmit)

•

Events assisting the Host in synchronization channel activities

Errors and unexpected conditions resulting in lost data, discontinued message processing, or prevented

successful completion of a service request

•

Number of bytes transferred to or from shared memory

All the interrupts are associated with a channel or direction with the following exceptions:

1. When an OOF or COFA condition is detected on a serial port, only one interrupt is generated for the port until

the condition is cleared and the condition reoccurs.

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2. The ILOST interrupt bit indicates that an interrupt has been lost internally when CX28500 generates more

interrupt descriptors than can be stored in the internal Interrupt Queue. The latency of Host processing of the

Interrupt Queue (handling the interrupts in the IRS) in shared memory may cause an ILOST condition. This

condition is conveyed by CX28500 overwriting the ILOST bit field in the last interrupt descriptor in the internal

queue prior to being transferred to shared memory. The ILOST field is not specific to or associated with the

Interrupt Descriptor being overwritten. Only the ILOST bit is overwritten, and the integrity of the original

descriptor is maintained.

3. The PERR interrupt bit indicates that a parity error was detected by CX28500 during a PCI access cycle. This

condition is conveyed by CX28500 overwriting the PERR bit field in the last interrupt descriptor in the internal

queue prior to being transferred out to shared memory. The bit field is not specific to or associated with the

interrupt descriptor being overwritten. Only one bit is overwritten and the integrity of the original descriptor is

maintained.

The CX28500 has two types of interrupt descriptor. One is the DMA Interrupt Descriptor, and the other is the Non-

DMA Interrupt Descriptor.

The following items describe the errors/events reported in the DMA Interrupt Descriptor:

•

ILOST (Interrupt Lost)

RxEOB/TxEOB (Receive or Transmit End Of Buffer)

RxONR/TxONR (Receive or Transmit Owner bit error)

RxEOM (Receive End Of Message)

RxEOCE/TxEOCE (Receive or Transmit End Of Command, i.e., Activate, Deactivate or Jump Execution)

If EOM (i.e., the message is an end of message), the other errors/events reported in the DMA Interrupt

descriptor are as follows:

•

RxBUFF Overflow

RxCOFA Change Of Frame Alignment

RxOOF Out Of Frame

RxABT Abort Frame

RxLNG Long Message

RxALIGN Byte Alignment Error

RxFCS Frame Check Sequence Error

The following items describe the errors/events reported in the Non-DMA Interrupt Descriptor.

•

RxBUFF/TxBUFF (Receive and Transmit Buffer errors)

RxSHT/TxEOM (Receive Message Too Short, Transmit End Of Buffer)

RxCHABT (Receive Change to Abort)

RxCHIC (Receive Change to Idle Codes)

RxCOFA/TxCOFA (Receive and Transmit Change Of Frame Alignment)

RxOFF (Receive Out Of Frame)

ProgERR (Programming Error, an attempt to access an illegal address within CX28500) valid only when SACK

= 1, ignore Prog ERR otherwise

•

RxFREC/RxSPORT (Receive Frame Recovery, Receive Serial Port Interrupt)

RxCREC/TxCREC (Receive COFA Recovery, Transmit COFA Recovery)

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6.3.1.1.1

DMA Interrupt Descriptor Format

The DMA interrupt descriptor is 69 bits wide, and the detailed description of its field is provided in Table 6-17. The

most significant bit in the DMA interrupt descriptor is always read as 0.

Table 6-17. DMA Interrupt Descriptors Format (1 of 2)

Bit

Field Name

Value

Description

63

TYP

RSVD

CH [9:0]

RSVD

DIR

0

Interrupt descriptor type 0.

Reserved

62:58

57:48

47:43

42

—

The channel number causing the interrupt.

Reserved

0: Direction—receive

1: Direction—transmit

41:40

39:38

RSVD

—

Reserved

INT[1:0]

0: RxEOB/TxEOB, (Receive or Transmit End Of Buffer)

This event is generated when current data buffer has been completely processed, and the EOBIEN bit

field is set in the associated Receive/ Transmit Buffer Descriptor. The EOB interrupt reports the correct

number of received transmitted bytes in BLEN field.

1: RxONR/TxONR–Generated when the next Buffer Descriptor is not available to CX28500 when

expected, the NP bit field in the buffer descriptor is set and the DMA is in the middle of a message, and

the ownership interrupt is enabled (bit field ONR in RDMA Channel Configuration register or TDMA

Channel Configuration register).

2: RxEOM–Generated when End Of Message occurs (even if errors were detected). If EOMIEN (bit field in

the Receive Buffer Descriptor) is enabled, an RxEOM is generated regardless the value of EOBIEN. In

other words, the EOM gets higher priority than an EOB event. An EOM interrupt reports the correct

number of received bytes in BLEN field.

Only when RxEOM = 1, which means an end of messages has been reported for that particular message

and the RxERR field is relevant.

3: RxEOCE/TxEOCE–End Of Command Execution generated after service request channel activation,

deactivation or jump.

37:36

RSVD

—

Reserved

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Table 6-17. DMA Interrupt Descriptors Format (2 of 2)

Bit

Field Name

Value

Description

35:33

RxERR/

EOCE[2:0]

—

When this is an RxEOM interrupt then this field specifies the error type:

0: Receiver error (decoded)—no error.

1: RxBUFF—Overflow.

2: RxCOFA—Change Of Frame Alignment.

3: RxOOF—Out Of Frame.

4: RxABT—Abort Termination. It is generated when the received message is terminated with an abort

sequence (seven consecutive 1s) instead of the specific closing flag, 7Eh.

5: RxLNG—Long Message. Generated when received message length (after zero extraction) is greater

than the selected maximum message size. The message reception is terminated and transfer to shared

memory is not performed.

6: RxALIGN—Byte Alignment Error. It is generated when the message payload size (after zero

extraction), is not a multiple of 8 bits. This generally occurs with an FCS error. The FCS interrupt is not

generated if the ALIGN interrupt was issued.

7: RxFCS—Frame Check Sequence Error. It is generated when received HDLC frame is terminated with a

byte aligned 7Eh flag but the computed FCS does not match the received FCS.

When this is an RxEOCE or TxEOCE interrupt then this field specifies the command type that was

executed:

0: Activate

1: Deactivate

2: Jump

3–7: Reserved

32:28

27:14

RSVD

—

Reserved

BLEN[13:0]

Receiver—Number of received bytes.

Transmitter—Buffer length.

13:1

0

RSVD

ILOST

—

Reserved

0: No interrupts have been lost.

1: Interrupt Lost. Generated when internal interrupt queue is full and more interrupt conditions are

detected. Because CX28500 cannot store the newest interrupt descriptors, it discards the new interrupts

and overwrites this bit in the last interrupt in an internal queue prior to that interrupt being transferred

out to shared memory. The integrity of the descriptor being overwritten is maintained completely.

6.3.1.1.2

Non-DMA Interrupt Descriptor Format

The Non-DMA Interrupt Descriptor is 64 bits wide, and the detailed description of its field is provided in Table 6-18.

The most significant bit in the Non-DMA Interrupt Descriptor is always read as 1.

Table 6-18. Non-DMA Interrupt Descriptors Format (1 of 3)

Bit

Field Name

Value

Description

63

TYP

RSVD

1

Interrupt Descriptor Type 1.

Reserved.

62:58

57:48

47:43

42

—

CH [9:0]

RSVD

The channel number causing the interrupt.

Reserved.

CHDIR

0: Receive direction.

1: Transmit direction.

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Table 6-18. Non-DMA Interrupt Descriptors Format (2 of 3)

Bit

Field Name

Value

Description

41

RxBUFF/

TxBUFF

—

Receive or Transmit Buffer Errors

The data is lost. CX28500 has no place to read or write data internally. If reported as TxBUFF, the internal

buffer underruns. If reported as RxBUFF, the internal buffer overflows.

40:38

37

RSVD

—

Reserved.

RxSHT/

TxEOM

RxSHT—Receive direction message too short or other error causes a truncated message.

The error is generated when the received message length (after zero extraction in HDLC mode) is less

than or equal to the number of bits in FCS field. The message data is not transferred to shared memory.

TxEOM—Transmit direction End Of Message.

36:34

33

RSVD

—

Reserved.

RxCHABT/

TxRSVD

RxCHABT—Receive direction Change to Abort code.

The event is generated when a received pad fill code changes from 7Eh to 7Fh (15 consecutive 1s are

detected).

Transmit: reserved

32:30

29

RSVD

—

Reserved.

RxCHIC/

TxRSVD

RxCHIC—Receive direction Change to Idle Code (RxCHIC).

The event is generated when a received pad fill code changes from 7Fh to 7Eh, or upon the detection of

the first flag after channel activation.

Transmit: reserved.

28:25

24:20

19:18

17

RSVD

PRT [4:0]

RSVD

—

Reserved.

The port number causing the interrupt.

Reserved.

PRTDIR

0: Receive direction of port causing the interrupt.

1: Transmit direction of port causing the interrupt.

16

15

RxCOFA/

TxCOFA

—

Receive and Transmit Change Of Frame Alignment.

RxOOF/

TxRSVD

RxOOF—Receive direction Out Of Frame.

Generated when serial port is configured in channelized mode and Receiver-Out-Of-Frame (ROOF) input

signal assertion is detected.

Transmit: reserved.

14

RxFREC/

RxSPORT/

TxRSVD

—

RxFREC—Receive direction.

When ROOF signal deasserts, frame recovery (FREC) interrupt is generated. The serial port transitions

from Out-Of-Frame (OOF) back to in-frame.

RxSPORT—Receive Direction.

When ROOF signal is used as a general serial port interrupt line (SPORT).

If OOFABT=0 and OOFIEN=1 bit fields in RSIU Port Configuration register and ROFF transitions from

high-to-low, the SPORT Interrupt is generated. The data stream processing is not affected.

Transmit–Reserved.

13

CREC

—

COFA recovery—Generated when the internal COFA signal deasserts. The serial port transitions from

COFA back to in-frame.

12:4

3

RSVD

—

Reserved.

PROGERR

Reports a programming error: an attempt was made to perform a SRQ access to an illegal address within

CX28500. An illegal address is any address which is not defined in Table 6-2. Reports status of SACK,

only valid when SACK = 1.

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Table 6-18. Non-DMA Interrupt Descriptors Format (3 of 3)

Bit

Field Name

Value

Description

2

1

SACK

—

DMA service request acknowledge. Generated to conclude successfully a service request command of

Host service.

PERR

—

0: No PCI parity errors have been detected.

1: PCI Bus Parity Error. Generated when CX28500 detects a parity error on data being transferred into/

from CX28500, either from another PCI agent that writes into CX28500 registers or from CX28500 that

reads data from shared memory. This error is specific to the data phase of a PCI transfer while CX28500

is receiving data. PCI system error signal, SERR*, is ignored by CX28500. To mask the PERR interrupt—

in CX28500's PCI Configuration Space, Function 0, Register 1—Parity Error Response field must be set

to 0.

0

ILOST

—

0: No interrupts have been lost.

1: Interrupt Lost. Generated when CX28500’s (internal) interrupt queue is full and more interrupt

conditions are detected. As CX28500 has no way to store the newest interrupt descriptors, it discards the

new interrupts and overwrites this bit in the last interrupt in an internal queue prior to that interrupt being

transferred out to shared memory. The integrity of the descriptor being overwritten is maintained

completely.

6.3.1.2

Interrupt Status Descriptor Register

The interrupt status descriptor is located in a fixed position in CX28500’s internal register. CX28500 updates this

descriptor after each transfer of interrupt descriptors from its internal queue to the Interrupt Queue in shared

memory. The Host is required to read this descriptor from CX28500’s registers before it processes any interrupts.

The contents of the interrupt status descriptor are reset on hardware reset or soft chip reset or whenever any field

in the Interrupt Queue Descriptor is modified.

This internal register is directly accessed by the Host.

NOTE:

Table 6-19 lists the details of the Interrupt Status Descriptor.

Table 6-19. Interrupt Status Descriptor

Bit

Field Name

Host Access

Value

Description

31

MSTRABT

R

—

When CX28500 encounters a PCI abort while operating as a PCI master, it does

not attempt to recover from this error. In this case CX28500 asserts the SERR*

signal, and the MSTRABT bit and waits for the Host to reset (i.e., PCI reset or Soft

reset).

This bit is asserted when the target does not assert DEVSEL within a specific PCLK

cycles or when the target terminates a transaction in which CX28500 is the master,

with an abort (i.e., assertion of STOP# with a deassertion of DEVSEL) sequence.

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Table 6-19. Interrupt Status Descriptor

Bit

Field Name

Host Access

Value

Description

30:16

WRPTR[14:0]

R

—

Write Interrupt Pointer. 15-bit Quadword index from start of Interrupt Queue up to

where CX28500 is going to insert the next Interrupt Descriptors. The Host may

read this value to get the location of the last descriptor, which was not served yet,

in the queue. As the queue is circular, care must be taken to ensure roll over at

beginning and end of queue. Only CX28500 updates this value. The WRPTR is a

read only bit field.

15

INTFULL

R

—

0: Interrupt Queue Not Full–shared memory.

1: Interrupt Queue Full–shared memory. The Host writing ANY value to the

ReadPtr clears the INTFULL status bit.

14:0

RDPTR[14:0]

R/W

Read Interrupt Pointer. 15-bit Quadword index from start of Interrupt Queue up to

where The Host first unread Interrupt Descriptor resides. The Host may read this

value to get the location of the first descriptor, which was not served yet, in the

queue. As the queue is circular, care must be taken to ensure roll over at beginning

and end of queue. Only The Host updates this value. The ReadPtr is a read/write bit

field. Note: Writing the value of the ReadPtr automatically resets the INTFULL

status bit. Therefore, if the value written into RDPTR is the same value as was read

from this field, it is assumed that the Host did read all the interrupt descriptors.

6.3.1.3

Interrupt Handling

Initialization

6.3.1.3.1

Interrupt management resources are automatically reset upon the following:

•

Hardware reset

Soft reset

Write to Interrupt Queue Pointer by a direct PCI write

Write to Interrupt Queue Length by a direct PCI write

CX28500 uses two interrupt queues. One is internal to CX28500 and is controlled exclusively by the DMA block.

The other is the Interrupt Queue in shared memory, which is allocated and administered by the Host, and written to

(filled) by CX28500.

Upon initialization, the data in the status descriptor is reset to all 0s, indicating the first location for next descriptor,

the queue is not full, and no descriptors are currently in the queue. Any existing descriptors in the internal queue

are discarded.

The Host must allocate sufficient shared memory space for the Interrupt Queue. Up to 64 K dwords of queue space

are accessible by CX28500, setting the upper limit for the queue size. CX28500 requires a minimum of two

Quadwords of queue space. This sets the lower limit for the queue size.

The Host must store the pointer to the queue and the length in Quadwords of the queue in CX28500 within the

Interrupt Queue Descriptor registers. Issuing the appropriate Host service to CX28500 can do this. As CX28500

takes in the new values, it automatically resets the controller logic as indicated above. This mechanism can also be

used to switch interrupt queues while CX28500 is in full operation.

6.3.1.3.2

Interrupt Descriptor Generation

Interrupt conditions are detected in both error and non-error cases. CX28500 makes a determination based on

channel and device configuration whether reporting of the condition is to be masked or whether an Interrupt

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Descriptor is to be sent to the Host. If the interrupt is not masked, CX28500 generates a descriptor and stores it

internally prior to transferring it to the Interrupt Queue in shared memory.

The internal queue is capable of holding 512 descriptors while CX28500 arbitrates to master the PCI bus and

transfer the descriptors into the Interrupt Queue in shared memory.

As the PCI bus is mastered and after descriptors are transferred out to the shared memory, CX28500 updates the

Interrupt Status Descriptor. When CX28500 updates the WRPTR field in the Interrupt Status Descriptor, it asserts

the PCI INTA# signal line.

If during the transfer of descriptors, the Interrupt Queue in shared memory becomes full, CX28500 stops

transferring descriptors until the Host indicates more descriptors can be written out. CX28500 indicates that it

cannot transfer more descriptors into shared memory by setting the bit field INTFULL in the Interrupt Status

Descriptor.

In cases where the internal queue is full (either because the Host queue is full or there was not enough PCI

bandwidth) and new descriptors are generated, the new descriptors are discarded. CX28500 indicates it has lost

interrupts internally by overwriting the bit field ILOST in the last Interrupt Descriptor in the internal queue. The

ILOST indication represents one or more lost descriptors.

6.3.1.3.3

INTA# Signal Line

The Host must monitor the INTA# signal line at all times. An assertion of this line signifies the updating of the

WRPTR field in the Interrupt Status Descriptor, indicating that Interrupt Descriptors have been transferred to the

Interrupt Queue in shared memory from the internal interrupt queue.

Upon detection of the INTA# assertion, the Host must perform a direct read of the Interrupt Status Descriptor from

within CX28500. This descriptor provides the offset to the location of the first descriptor in the Host queue that has

not been served, the offset to the location of the last descriptor serviced by the Host, and the determination if the

queue is full. The INTA* signal is deasserted on each read of the Interrupt Status Descriptor.

The Host applies its interrupt service routines to service each of the descriptors. As the Host finishes servicing a

number of descriptors, it must write the offset to the location of the last serviced descriptor back into the RDPTR

field of the Interrupt Status Descriptor. A write to this field indicates to CX28500 that the descriptor locations, which

were waiting to be serviced, have been serviced and new descriptors can be written.

CX28500 continues to write to available space regardless of whether the Host updates the

RDPTR field. The difference between the two interrupt queue pointers RDPTR and WRPTR

indicates the number of interrupts still need to be serviced. When calculating the number of

outstanding interrupts, please make sure to take care of offsets, or pointers, wraparound.

NOTE:

Figure 6-1 illustrates the operation of INTA*.

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Figure 6-1. Interrupt Notification to Host

CX28500

Host

Interrupt

Handler

INTA*

Internal Logic

Unserviced Interrupt

Descriptors in the

Interrupt Queue

Memory

Interrupt

Queue

500052_056

6.4

Global Configuration Register

The Global Configuration Descriptor specifies configuration information applying to the entire device. This register

must be programmed before any channel is activated. The only two fields in this register that can be changed while

the chip is operating (i.e., not immediately after reset) are the INTRS field and the PCI_EN field.

The components and their descriptors are given in Table 6-20.

Table 6-20. Global Configuration Descriptor (1 of 2)

Bit

Field Name

Value

Description

31:15

14

RSVD

0

1

Reserved

PCHMODE

Normal operating mode (i.e., not Preserve Channel Mode)

Preserve Channel Mode. In this mode requires ECCMODE = 1:

1. CX28500 transfers in the Rx direction the channel number least significant 8 bits in bits

[25:8] in the first dword at Status Buffer Descriptor and the channel most significant 2 bits

in bits 1:0 of the second dword of the Status Buffer Descriptor (i.e., the data pointer).

2. In the Tx direction, CX28500 assumes that the field PADCOUNT in the Buffer Descriptor is 0.

This enables the Host to write any value that helps to better handle buffers circulation into

this location knowing that CX28500 does not use PADCOUNT and preserve this value in the

Status Buffer Descriptor.

Note that PCHMODE can be set only when ECCMODE bit is set. Doing otherwise causes unpredictable

behavior.

13

ECCMODE

0

Normal operating mode (i.e., not ECCMODE)

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Table 6-20. Global Configuration Descriptor (2 of 2)

Bit

Field Name

Value

Description

1

ECCMODE: CX28500 supports a 64-bit wide ECC memory as the shared memory. The special behavior

includes the following:

1. When updating Buffer Descriptors in the shared memory, the whole Buffer Descriptor is

written (i.e., 64 bits) rather than the status dword only.

2. When transferring incoming data to shared memory, any transfer which does not include the

end of message is ended in 64-bit alignment.

3. Since this mode makes sense only if the data buffers are 64-bit aligned, CX28500 assumes

that the three least significant bits in the data pointers of all (i.e., Tx and Rx) buffer

descriptors are 0 regardless of their actual value. CX28500 preserves the actual value when

updating the buffer descriptor with the status. Start of receive message indication—informs

host via SOM-bit in the Receive Buffer Status Descriptor (bit 2 of second dword) that this

data buffer contains the beginning of a message.

12

11

TARGET_64

—

0: Target (any target that CX28500 can access over the PCI) is not guaranteed to allow 64-bit transfers

when CX28500 is the master. In this case, a single 64-bit transaction is executed in two 32-bit accesses

even when operating in 64-bit PCI (for any transaction greater than a 64-bit transfer, CX28500 always

attempts to transfer 64 bits regardless of the setting of this bit).

1: Target (any target that CX28500 can access over the PCI) is guaranteed to allow 64-bit transfer. In

this case CX28500 always transfers 64 bits whenever possible.

TARGET_FBTB

0: Use the fast back-to-back feature as configured in the PCI configuration settings.

1: CX28500 as PCI master attempts to fast back-to-back the PCI transaction to other targets regardless

of PCI configuration settings.

This bit is defined to force CX28500’s fast back-to-back capability regardless of the PCI configuration.

The PCI specification states that if there is a single device in the system that does not support a fast

back-to-back transaction as a target, the fast back-to-back mode is disabled. Setting this bit to 1

instructs CX28500 to ignore the PCI configuration settings and execute fast back-to-back transactions

when appropriate.

The Host can set this bit only if CX28500 is always accessing the same target which is capable of fast

back to back transactions. This is not a violation of the PCI specification, rather it is an implementation

of allowed behavior.

10

BR

—

0: Little-Endian Storage Convention (Intel-style). The least significant byte to be stored in and retrieved

from the lowest memory address.

1: Big-Endian Storage Convention (Motorola-style).

An example of little-big Endian byte ordering is shown in Appendix E.

9:1

INTTRS[8:0]

Threshold of internal interrupt queue Service request.

This bit field contains the configuration parameter of DMA internal interrupt service request queue.

Once the internal queue contains at least one interrupt vector, a low priority DMA request is generated

toward the internal PCI arbiter. This request is removed when the internal queue is empty. If the internal

queue contains greater than or equal INTTRS number of descriptors, a high priority request is

generated toward the internal PCI arbiter. This request is removed when the internal queue contains

less than INTTRS descriptors. See the description in DMA Internal Arbiter. This field must never equal

0.

0

PCI_EN

—

0: PCI Interrupt disabled–global interrupt mask.

1: PCI Interrupt enabled.

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6.5

EBUS Configuration Register

The EBUS Configuration Descriptor, defined in Table 6-21, specifies the configuration parameters for EBUS

transactions. The Host must configure this register before any attempt to access the EBUS.

Table 6-21. EBUS Configuration Register

Bit

Field Name

Value

Description

31:14

RSVD

0

1

0

Reserved.

(1)

13

ECLKDIV

EBUS clock (ECLK) has the same frequency as the PCI clock (PCLK).

EBUS clock (ECLK) has half the frequency of the PCI clock (PCLK).

12

MPUSEL

Expansion Bus Microprocessor Selection–Motorola-style. Expansion bus supports the Motorola-style

microprocessor interface and uses Motorola signals: Bus Request (BR*), Bus Grant (BG*), Address

Strobe (AS*), Read/Write (R/WR*), and Data Strobe (DS*).

1

Expansion Bus Microprocessor Selection–Intel-style. Expansion bus supports the Intel-style

microprocessor interface and uses Intel signals: Hold Request (HOLD), Hold Acknowledge (HLDA),

Address Latch Enable (ALE*), Write Strobe (WR*), and Read Strobe (RD*).

11

ECKEN

0

1

Expansion Bus Clock Disabled. ECLK output is three-stated.

Expansion Bus Clock Enabled. CX28500 re-drives and inverts PCLK input onto ECLK output pin.

10:8

ALAPSE[2:0]

—

Expansion Bus Address Duration. CX28500 extends the duration of valid address bits during an EBUS

address phase to ALAPSE+1 number of ECLK periods. The control lines ALE* (Intel) or AS* (Motorola)

indicate that the address bits have had the desired setup time.

7:4

3:0

BLAPSE[3:0]

ELAPSE[3:0]

—

Expansion Bus Access Interval. CX28500 waits BLAPSE number of ECLK periods immediately after

relinquishing the bus. This wait ensures that all the bus grant signals driven by the bus arbiter have

sufficient time to be deasserted as a result of bus request signals being deasserted by CX28500.

Expansion Bus Data Duration. CX28500 extends the duration of valid data bits during an EBUS data

phase to ELAPSE+1 number of ECLK periods. The control lines RD* and WR* (Intel) or DS* and R/

WR* (Motorola) indicate the data bits have had the desired setup time.

FOOTNOTE:

(1)

After reset, the value of EBUS Configuration register is 0, except ECLKDIV bit field, which is 1. The user can change the clock division at

any time but the EBUS clock must be first reset (disabled), i.e., reset ECKEN bit, and after that a new value of ECLKDIV must be written

with ECKEN set.

6.6

Receive Path Registers

Receive path registers contain the information necessary to configure the receive direction. This configuration

includes registers that are related to the DMA block, Host interface, registers that control the RSLP line processor,

and RSIU.

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6.6.1

RSLP Channel Status Register

The RSLP Channel Status register is a Read Only (RO) register.

It provides information from RSLP block regarding the channel state and status. There is one RSLP Channel status

register for each of CX28500’s channels (i.e., 1024 registers).

Table 6-22. RSLP Channel Status Register

Bit

Field Name

Host

Value

Description

31:4

RSVD

R

0

Don’t care

0

Reserved.

3:1

0

Reserved.

RACTIVE

Channel Inactive.

The channel has been deactivated due to either a service request channel deactivation or

Reset (PCI Reset or Soft Chip Reset)

1

Channel Active. The channel has been activated by service request channel activation.

6.6.2

RSLP Channel Configuration Register

The Receive Channel Configuration register contains configuration bits applying to the logical channels within

CX28500. There are 1024 such registers, one for each channel. The RSLP Channel Configuration Descriptor

configures aspects of the channel common to all messages passing through the channel. One descriptor exists for

each logical channel direction. Table 6-23 lists the values and descriptions of each channel configuration

descriptor.

Table 6-23. RSLP Channel Configuration Register (1 of 2)

Bit

Field Name

Value

Description

31:30

RPROTCOL[1:0]

0

1

TRANSPARENT.

HDLC with no FCS.

Used in ISLP or full packet forwarding and/or channel monitoring application.

For this mode the SHT message detection is disabled. Any number of bytes can be transmitted and

received within any single message including messages of only one byte.

2

3

0

1

HDLC with FCS16 (FCS—2 bytes).

HDLC with FCS32 (FCS—4 bytes).

Data Inversion disabled.

29

RINV

Data Inversion enabled. Message is received from SIU with polarity change (the inversion is done to

all received bits).

28:21

RMASK[7:0]

—

Data Mask. Only bits with a value of 1 contain relevant data (e.g., Mask = 10000001, then only bits 0

and 7 contain channel's data). Enables the subchanneling feature.

20:5

4:3

RSVD

0

1

Reserved.

MAXSEL[1:0]

Message Length–Disable maximum message length check.

Message Length–Use MAXFRM1 bit field in the message length descriptor for maximum receive

message length limit.

2

3

Message Length–Use MAXFRM2 bit field in the message length descriptors maximum receive

message length limit.

Message Length–Use MAXFRM3 bit field in the message length descriptor for maximum receive

message length limit.

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Table 6-23. RSLP Channel Configuration Register (2 of 2)

Bit

Field Name

Value

Description

2

FCSTRANS

0

1

FCS Transfer Normal. Do not transfer received FCS into shared memory along with data message.

Non-FCS Mode. Transfer received FCS into shared memory along with data message. In a Non-FCS

Mode a SHT message detection is disabled.

1

0

BUFFIEN

IDLEIEN

0

1

0

1

Overflow Interrupt disabled.

Overflow Interrupt enabled.

CHABT, CHIC, SHT Interrupt disabled.

CHABT, CHIC, SHT Interrupt enabled. Receive Only. When receiver detects change to abort code,

change to idle code, or too-short message, this bit generates an interrupt to indicate condition.

6.6.3

RDMA Buffer Allocation Register

The Buffer Allocation register configures the internal receive memory.

There is one RDMA Buffer Allocation register for each logical channel (i.e., 1024 channels).

CX28500’s internal Rx memory is a 32-KB dual-port RAM, which can be split into 1024 parts, one part for each

channel. The allocation granularity is two dwords. For each active channel it is required to specify the following:

•

The starting location of internal data buffer

The ending location of internal buffer

A threshold. This value is triggered when a request from DMA needs to be generated to the internal PCI

arbiter. As soon as the channel’s internal FIFO contains more data bytes than this threshold, a request to the

RDMA to serve this channel is generated, meaning transferring data in the FIFO into shared memory. A

request to serve this channel is also generated, regardless of the value of the threshold, if a complete

message, or an End Of Message (EOM), resides in the channel’s FIFO.

The Host can issue a Service Request to change the value of this register only when the affected channel is

inactive. Additionally, internal data buffer allocation must conform to the following criteria:

1. Host must set the buffers so there is no overlap between buffers belonging to different channels.

2. Allocated memory segments should not have wraparounds. That is, ending addresses must be greater than

starting addresses.

3. The Host cannot allocate all of the FIFO to one channel. The maximal allocation to one channel is (all FIFO) –

1 quad dwords.

Each receive channel must be allocated buffer space before the channel can be activated. Other important

considerations for allocation of internal data buffers include the channel’s data rate and PCI latency tolerance. This

architecture of configured buffer allocation is completely flexible and allows the Host to assign larger FIFO buffers

to channels that operate at higher rates. For applications operating high-speed channels (i.e., hyperchanneling) the

Host can increase the FIFO allocation per channel. PCI latency tolerance equals the maximum length of time a

particular channel can operate normally between PCI bus transactions without reaching an internal overflow or

underflow condition. PCI latency tolerance is primarily dependent on each channel FIFO’s buffer size. Table 6.6.3

describes the bit fields in the RDMA Buffer Allocation register. There are 1024 RDMA Buffer Allocation registers,

one for each channel.

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Table 6-24. RDMA Buffer Allocation Register

Bit

Field Name

Value

Description

31:29

RSVD

RDMA_ENDAD[12:0]

RSVD

0

—

0

Reserved

(1)

28:16

15:13

12:0

Ending address of internal channel data buffer pointing to dword.

Reserved

(2)

RDMA_STARTAD[12:0]

—

Starting address of internal channel data buffer

GENERAL NOTE:

1. One channel maximum must be 32 KB–8 bytes (i.e., ENDAD = 1FFDh and STARTAD = 000h).

2. ENDAD must be greater than STARTAD (i.e., no rollover).

3. Minimal allocation to any channel ≥ 4 dwords (i.e., ENDAD – STARTAD ≥ 3).

FOOTNOTE:

(1)

RDMA_ENDAD must be an odd address (i.e., LSB must be 1).

RDMA_STARTAD must be an even address (i.e., LSB must be 0).

(2)

6.6.4

RDMA Configuration Register

This register, defined in Table 6-25, controls the per channel RxDMA operational mode. There are 1024 such

registers, one for each channel.

Table 6-25. RDMA Channel Configuration Register (1 of 2)

Bit

Field Name

Value

Description

31:18

RSVD

0

1

Reserved

17

EOCEIEN

End Of Command Execution Interrupt disabled.

End Of Command Execution Interrupt enabled. Interrupt generated when a command

(Activate, Deactivate or Jump) execution was completed.

(1)

16

INHRBSD

0

1

Inhibit Receive Buffer Status Descriptor disabled. At the end of each Receive Data Buffer,

overwrite Rx Buffer Descriptor with Rx Buffer Status Descriptor.

Inhibit Receive Buffer Status Descriptor enabled. At the end of each Receive Data Buffer,

do not overwrite Rx Buffer Descriptor with Rx Buffer Status Descriptor.

15

14

ONRIEN

ERRIEN

0

1

ONR Interrupt disabled.

ONR Interrupt enabled. Interrupt generated when a new buffer descriptor is read from the

Host memory and this buffer is Host-owned and NP bit field is 1.

0

1

Error Interrupt disabled.

Error Interrupt enabled. Interrupt generated when End Of Message detected and error

occurred (such as: too-long message, FCS error, and message alignment error or abort

condition).

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Table 6-25. RDMA Channel Configuration Register (2 of 2)

Bit

Field Name

Value

Description

13

EOMIEN

0

1

EOM Interrupt disabled.

EOM Interrupt enabled. Interrupt generated when End Of Message detected and no error

occurred (such as too-long message, FCS error, and message alignment error or abort

condition).

12:0

RDMA_ TRSHOLD[12:0]

—

Threshold value. As soon as the channel’s internal FIFO contains more than or equal

number of data dwords than the threshold, a request to the RDMA to serve this channel is

generated. The value programmed into this field must not exceed the channel’s buffer size,

and the threshold must not equal 0.

FOOTNOTE:

(1)

The normal mode of operation of the CX28500 is to overwrite the Rx Buffer Descriptor with Rx Buffer Status Descriptor. This bit is used

to inhibit this behavior, so that when it is set, the Rx Buffer Descriptor is not overwritten and the Host must rely on interrupts to find out

when the CX28500 relinquishes ownership of the buffers.

6.6.5

RSIU Time Slot Configuration Register

6.6.5.1

Time Slot Map

The receive time slot map consists of 4096 time slot descriptors. The entire receive map contains configuration

information for 4096 separate time slots. The CX28500’s serial ports support 4096 time slots, which can be

configured among the CX28500’s 32 receive serial ports by setting the RSIU Time Slot Pointer Assignment.

Numerous mappings of time slots are possible, multiple time slots can be mapped to a single channel; however

each time slot can map to only one channel at a time. For each serial port two time slot maps are required, one for

transmit functions and one for receive functions. The two separate maps are configured independently for transmit

(TSIU Time Slot Configuration Descriptor and TSIU Time Slot Pointer Assignment) and receive direction (RSIU

Time Slot Configuration Descriptor and RSIU Time Slot Pointer Assignment).

6.6.5.2

RSIU Time Slot Configuration Descriptor

For each time slot there is an RSIU Time Slot Configuration Descriptor.

There are 4096 entries in memory that set the translation between time slots and logical channels for each of

CX28500's 32 ports. The actual mapping of these time slot descriptors to the 32 ports is done by 32 sets of pointer

pairs (receive and transmit), one pair set for each port, which indicates the start and the end address of the

memory location that belongs to the configured port. Time Slot pointer allocation is described in RSIU Time Slot

Pointer Allocation.

The bit fields of RSIU Time Slot Configuration Descriptor include information:

•

Time slot is enabled or disabled

Time slot is a full DS0, or subchanneling enabled so that only a part of 64 Kbps transports information

Indicates if it is the first time slot assigned to the logical channel

Logical channel number

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For polling to work properly and efficiently, it is mandatory that the FIRST (receive time

NOTE:

slot)/LAST (transmit time slot) indications be configured for each channel regardless of the

operational mode (i.e., HDLC, transparent, etc.). The polling mechanism in the CX28500

uses these markings as triggering points. When configured correctly, CX28500 polls on a

channel once at the selected poll throttle rate instead of polling at every time slot allocated

to that channel, as in the case of hyperchannels. When a channel consists of only one time

slot, as in a DSO channel, its corresponding receive time slot should have the FIRST_TS bit

set. Likewise, its corresponding transmit time slot should have the LAST_TS bit set.

Table 6-26 specifies the content of each receive time slot configuration descriptor.

Table 6-26. RSIU Time Slot Configuration Descriptor

Bit

Field Name

Value

Description

31:13

RSVD

0

—

0

Reserved.

12:3

2

RCHANNEL[9:0]

RTS_ENABLE

Logical channel number assigned to the time slot.

Time Slot Disabled.

1

Time Slot Enabled.

1

0

RMASKEN_SB

RFIRST_TS

0

The RMASK_SB bit field (RSLP Channel Configuration Descriptor) is ignored. All the 8 bits of

the time slot are processed.

1

0

1

Allow data mask for the specified time slot. The bits specified by RMASK_SB bit field (RSLP

Channel Configuration Descriptor) are processed.

This bit field indicates that the specified time slot is not the first time slot of the logical

channel.

This bit field indicates that the specified time slot is the first time slot of the logical channel.

If a serial port is configured to operate in channelized mode, each channel defined to operate

over the serial port must have one time slot assigned to that logical channel that is the first

time slot for that channel. In unchannelized mode, this bit must be set in the single time slot

assigned.

GENERAL NOTE:

1. The timeslot map registers have no default values and may be active after reset, so they must be configured before activating the port.

6.6.6

RSIU Time Slot Pointer Allocation Register

There is one RSIU Time Slot Pointer Allocation Descriptor for each of CX28500’s 32 serial ports. This register sets

the start and end time slot address for the specific configured port. The difference between the configured end and

start address specifies the number of time slots allocated for the specified serial port.

6.6.6.1

Time Slot Allocation Rules

1. If both pointers point to the same location, this port should be configured to operate in unchannelized mode.

This is done by setting the RPORT_TYPE field in RSIU Port Configuration register to 0.

2. If there are two, three, or four time slots, the RPORT_TYPE field in RSIU Port Configuration register must be

set to 2, 3, or 4 respectively.

3. If there are more than four time slots, the RPORT_TYPE field in TSIU Port Configuration register must be set to

either 5, if it is not T1 framing, or 1 if it is.

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4. If serial port is configured to channelized TSBUS mode, RSIU Time Slot Pointer Allocation Descriptor is

configured to support more than eight time slots and the RPORT_TYPE bit field in RSIU Port Configuration

register must be set to channelized TSBUS mode.

In the case of unchannelized mode (i.e., the RPORT_TYPE field in RSIU Port Configuration register is

programmed to 0), CX28500 assumes that only one entry (the one pointed to by STARTAD) is used for this port.

This frees the ENDAD pointer to point to any location in the RSIU time slot memory. The differences in these

pointers now define the number of time slots to count for polling purposes as described in section Descriptor

Polling.

Table 6-27 describes the bit fields in RSIU Time Slot Pointer Allocation Descriptor.

Table 6-27. RSIU Time Slot Pointer Allocation Register

Bit

Field Name

Value

Description

31:28

RSVD

0

—

0

Reserved.

27:16

15:12

11:0

RENDAD_TS[11:0]

RSVD

Ending location in the Receive Time Slot Map of the last time slot assigned to this port.

Reserved.

RSTARTAD_TS[11:0]

—

Starting location in the Receive Time Slot Map of the first time slot assigned to this port.

6.6.7

RSIU Port Configuration Register

There is a Receive Port Configuration register for each serial port. It defines how CX28500 interprets and

synchronizes the received bit streams associated with the serial port.

Table 6.6.7 describes the bit fields in RSIU Port Configuration register.

Table 6-28. RSIU Port Configuration Register (1 of 3)

Bit

Field Name

Value

Description

31:14

13

RSVD

0

Reserved.

(1)

RXENBL

Receive Port Disabled. Logically resets the serial port, regardless of RTS_ENABLE bit

field in RSIU Time Slot Configuration Descriptor. This does not affect the bit values in

any time slot descriptor. When the serial port becomes inactive, no data is transferred to

the SLP.

1

Receive Port Enabled. This bit field acts as a logical AND between RTS_ENABLE bit field

in RSIU Time Slot Configuration Descriptor and time slot.

Logically, if RTS_ENABLE bit field in RSIU Time Slot Configuration Descriptor is enabled,

it allows all channels with time slot enable bits set to start processing data. This does not

affect the bit values in any time slot descriptor.

12

RSVD

0

Reserved.

GENERAL NOTE: Writing RXENBL from 0 to 1 forces the port to realign itself to the incoming sync (if channelized) and generate RCOFA. In

unchannelized port mode, the logical channel must be deactivated.

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Table 6-28. RSIU Port Configuration Register (2 of 3)

Bit

Field Name

Value

Description

11:9

RPORT_TYPE

0

1

Unchannelized mode. The user must configure time slot to contain one time slot.

T1 mode. This mode includes some number of time slots and one bit of overhead

coincident with frame or flywheel sync, and that one bit can be masked out.

2

3

4

5

6

Nx64—2 TS. The user must configure the time slot map to contain two time slots.

Nx64—3 TS. The user must configure the time slot map to contain three time slots.

Nx64—4 TS mode. The user must configure the time slot map to contain four time slots.

Nx64—The user must configure more than 4 time slots.

Channelized TSBUS mode. The user must configure the time slot map to contain at least

eight time slots.

7

0

Reserved

8:6

RPOLLTH[2:0]

Poll Throttle. Poll at every frame synchronization event. This mechanism can be used to

avoid bus saturation when multiple logical channels are active and idle and waiting for

buffers to service.

1

2

3

4

5

6

7

0

Poll at every 2nd frame synchronization event.

Poll at every 4th frame synchronization event.

Poll at every 8th frame synchronization event.

Poll at every 16th frame synchronization event.

Poll at every 64th frame synchronization event.

Poll at every 128th frame synchronization event.

Poll at every 256th frame synchronization event.

5

RSYNC_EDGE/

RSTUFF_EDGE

Receiver Frame Synchronization/ Receive Stuff Indication—Falling Edge. RSYNC/

RSTUFF input sampled in on falling edge of RCLK.

1

Receiver Frame Synchronization/ Receive Stuff Indication—Rising Edge. RSYNC/

RSTUFF input sampled in on rising edge of RCLK.

4

3

RDAT_EDGE

0

1

0

Receiver Data—Falling Edge. RDAT input sampled in on falling edge of RCLK.

Receiver Data—Rising Edge.

ROOF_EDGE/RTSTB_EDGE

Receiver Out Of Frame/ TSBUS Strobe—Falling Edge. ROOF/TSTB input sampled in on

falling edge of RCLK.

1

0

Receiver Out Of Frame/ TSBUS Strobe—Rising Edge. ROOF/TSTB input sampled in on

rising edge of RCLK.

2

1

OOFABT

OOFIEN

OOF Message Processing Enabled. When OOF condition is detected, continue

processing incoming data. SIU should not report about the OOF.

1

0

1

OOF Message Processing Disabled.

Out Of Frame/Frame Recovery Interrupt Disabled.

Out Of Frame/Frame Recovery Interrupt Enabled. If OOF/FREC is detected, generate

Interrupt indicating OOF/FREC.

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Table 6-28. RSIU Port Configuration Register (3 of 3)

Bit

Field Name

Value

Description

0

RCOFAIEN

0

Change Of Frame Alignment/Recovery from Change Of Frame Alignment Interrupts

Disabled.

1

Change Of Frame Alignment/Recovery from Change Of Frame Alignment Interrupts

Enabled. If COFA is detected, generate Interrupt indicating COFA. When COFA is

recovered from, generate a Recovery From COFA Interrupt indication.

FOOTNOTE:

(1)

It is not allowed to change configuration of the port while the port is enabled. Therefore, it is not allowed to disable the port and change

configuation in the same operation. It is also not allowed to change configuation and enable the port in the same operation. Both actions

need to be split to 2 seperate operations. If the port is active one must first clear the RXENBL bit, and only then write new configuration.

If the port is inactive, one must first write new configuration with the RXENBL bit cleared and then re-write the register with the same

configuration but with the RXENBL bit set.

The bit fields OOFIEN and OOFABT are related to each other in the following manner:

1. If both are 0: the signal ROOF is ignored by CX28500’s Rx side. This is the correct programming for TSBUS

mode or when the ROOF pin is used as CTS or not connected at all.

2. If both are 1: this is the case of OOF functionality with OOF interrupt. CX28500 interrupts the Host and

executes the appropriate behavior in the channels affected by the OOF. In addition, an OOF interrupt is

generated and later an OOF recovery interrupt when the OOF condition ends.

3. If OOFABT is 1 and OOFIEN is 0: CX28500 as the case of both 1s except that no interrupt is generated.

4. If OOFIEN is 1 but OOFABT is 0: This is the case where the ROOF pin is used as a general purpose interrupt

pin. CX28500 Rx blocks ignore the ROOF signal but an interrupt to the Host is generated when the ROOF

transitions from high to low.