28236-BRF-001-A [TE]

OC-3 ATM SAR Controller with UTOPIA Level 2;


型号：	28236-BRF-001-A
厂家：	TE CONNECTIVITY
描述：	OC-3 ATM SAR Controller with UTOPIA Level 2 ATM 异步传输模式
文件：	总4页 (文件大小：515K)
中文：	中文翻译
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OC-3 ATM SAR Controller with UTOPIA Level 2

CN8236

ATM OC-3 Service SAR Plus with xBR

Traffic Management

KEY FEATURES

AAL0, AAL3/4, AAL5, inter-

working function for AAL1/2

scheduling (cell-on-demand

scheduling)

Multi-peer architecture with

up to 32 peers

Mindspeed’s CN8236 Service Segmentation and

Reassembly (ServiceSAR) controller integrates ATM

terminal functions, PCI bus master and slave controllers,

and a UTOPIA 1 or 2 interface with service-specific func-

tions in a single package for AAL0, AAL3/4, and AAL5

operations. The ServiceSAR controller generates and

terminates ATM traffic (TM. 4.1) and automatically

schedules cells for transmission with patented xBR

traffic management. The CN8236 is targeted at 155

Mbps throughput systems where the number of VCCs is

relatively large, or the performance of the overall system

is critical. Examples of such networking equipment include

routers, Ethernet switches, ATM edge switches, or frame

relay switches.

Head-of-line blocking protec-

tion for multi-PHY operation

ATM TM 4.1 service cate-

gories: ABR, CBR, GFR, VBR-

rt, VBR-nrt, GFR

64 K VCC, 155 Mbps full duplex

with 2-cell PDU

UTOPIA Level 2, 8/16 bit

@ 50 MHz

Service-specific performance

accelerators – LECD filtering

and echo suppression,

CLP0+1, Frame Relay DE

interworking

33 MHz (up to 40 MHz), PCI 2.1

388 BGA, low-power

dissipation

Dynamic per-VCC scheduling

Flexible tunneling with mixed

service categories

(16 priorities)

Service-Specific Performance Accelerators

It dynamically schedules segmentation traffic to comply

with up to 16+CBR user-configured scheduling priorities

for the various traffic classes. Scheduling is controlled

by a schedule table configured by the user and based

on a user-specified time reference. ABR channels are

managed in hardware according to user-programmable

ABR templates. These templates tune the performance

of the CN8236’s ABR algorithms to a specific system’s

or network’s requirements.

The CN8236 incorporates numerous service-specific

features designed to accelerate and enhance system

performance. For example, the CN8236 implements

echo suppression of LAN traffic via LECID filtering,

and supports frame relay DE to CLP interworking.

Advanced xBR Traffic Management

The xBR traffic manager in the CN8236 supports multiple

ATM service categories. These include CBR, VBR (both

single and dual leaky bucket), UBR, GFR (guaranteed

frame rate), and ABR (explicit rate, relative rate and EFCI

marking). The CN8236 manages each VCC independently.

OC-3 Service SAR Controller

Multi-Queue Segmentation Processing

High-Performance

Host Architecture with Buffer Isolation

The CN8236’s segmentation coprocessor generates ATM cells

for up to 64 K VCCs. The segmentation coprocessor formats

cells on each channel according to segmentation VCC tables,

utilizing up to 32 independent transmit queues and reporting

segmentation status on a parallel set of

The CN8236 host interface architecture maximizes perform-

ance and system flexibility. The device’s control and status

queues enable host/SAR communication via write operations

alone. This “write-only architecture” lowers latency and PCI

bus occupancy. Flexibility is achieved by supporting a scalable

peer-to-peer architecture. Multiple host clients can be

addressed by the segmentation and reassembly (SAR) as

separate physical or logical PCI peers. Segmentation and

reassembly data buffers on the host system are identified by

buffer descriptors in SAR-shared (or host) memory, which

contain pointers to buffers. The use of buffer descriptors in

this way allows for isolation of data buffers from the mecha-

nisms that handle buffer allocation and linking. This provides a

layer of indirection in buffer assignment and management

that maximizes system architecture flexibility.

up to 32 segmentation status queues. The segmentation

coprocessor fetches client data from the host, formats ATM

cells while generating and appending protocol

overhead, and forwards these to the UTOPIA port. The

segmentation coprocessor operates as a slave to the xBR

traffic manager which schedules VCCs for transmission.

Multi-Queue Reassembly Processing

The CN8236’s reassembly coprocessor stores the payload

data from the cell stream received by the UTOPIA port into

host data buffers. Using a dynamic lookup method which

supports NNI or UNI addressing, the reassembly coprocessor

processes up to 64K VCCs simultaneously. The host supplies

free buffers on up to 32 independent free buffer queues. The

reassembly coprocessor performs all CPCS protocol checks

and reports the results of these checks and other status

data on one of 32 independent reassembly status queues.

Local Bus

Local Memory

Interface

Timer

Counters

Control/

Status

UTOPIA

Master/

Slave

Reassembly

Coprocessor

CX28250

PCI

Master/

Slave

DMA

Co-

Proc'r

Cell

FIFO

PHY

Device

Segmentation

Coprocessor

Multi-client

PCI Bus

Rx/Tx

CBR, VBR, ABR,

UBR, GFR

CN8236

Traffic Manager

CN8236 functional block diagram

CN8236

The ITU-T and ANSI selected ATM for Broadband-ISDN.

SONET/SDH, as specified by the ITU, is intended as the

Designer Toolkit

Mindspeed provides an evaluation environment for the CN8236

which provides a working reference design and facilities for

generating and terminating all service categories of ATM

traffic. This system accelerates ATM system development by

providing a rapid prototyping environment.

primary transport mechanism for ATM cells in WAN applica-

tions. ATM also plays a key role in next-generation consumer

applications for high-speed Internet access and wireless

access. The ADSL Forum and the Universal ADSL Working

Group chose ATM as the network layer protocol for G.lite and

G.DMT ADSL.

What is ATM?

Asynchronous transfer mode (ATM) has emerged as the

primary networking technology for next-generation, multiser-

vice communication networks. ATM-enabled services benefit

the Internet as well as emerging applications in science,

telemedicine, and distance learning. Just as the Internet revo-

lutionized worldwide communications, ATM brings new meaning

to high-speed networking.

ATM physical layer (ATM-PHY) IC devices adapt ATM cells to

and from a broad range of transmission rates ranging from

1.544 Mbps to 2.4 Gbps via a standard system interface called

UTOPIA.

ATM, which uses a fixed size packet, or cell, is a transport

protocol capable of providing a homogeneous network for all

traffic types, regardless of whether the application is to carry

conventional telephony, entertainment video, or data traffic

over LANs, MANs, or WANs.

Product Features

• Message and streaming status modes

• Virtual Tx FIFO buffer (PCI host)

• Non-word (byte) aligned host buffer

addresses

Service-Specific Performance

Accelerators

• LECID filtering and echo suppression

xBR Traffic Management

• TM4.1 Service Classes

– CBR

• Automatically detects presence of Tx

data or Rx free buffers

Multi-Queue Reassembly

Processing

• 32 reassembly queues

• 64K VCCs maximum*

• AAL5 and AAL3/4 CPCS checking

• AAL0

• Dual leaky bucket based on CLP

(frame relay)

–VBR (single, dual and CLP-based

leaky buckets)

• Virtual FIFO buffers (PCI bursts

treated as a single address)

• Frame relay DE interworking

• Internal SNMP MIB counters

– Real-time VBR

• Hardware indication of BOM

–ABR (explicit rate, relative rate

and EFCI marking)

• Allows isolation of system resources

• Status queue interrupt delay

• IP over ATM; supports both CLP0+1

and ABR shaping

– UBR

– PTI termination

Designer Toolkit

• Evaluation hardware

– GFC (controlled and uncontrolled

flows)

Flexible Architectures

• Multi-peer host

– Cell count termination

• Early Packet Discard, based on:

– Receive buffer underflow

– Receive status overflow

– CLP with priority threshold

–AAL5 max PDU length

– Rx FIFO buffer full

– Guaranteed Frame Rate (GFR)

(guaranteed MCR on UBR VCCs)

• Reference schematics

• Direct switch attachment via reverse

UTOPIA

• Generous Implementation of OAM-

PM Protocols

• 16 levels of priorities (16 + CBR)

• Dynamic per-VCC scheduling

• ATM terminal

– Host control

• Detection of all F4/F5 OAM flows

• Multiple programmable ABR

templates (supplied by Mindspeed

or user)

• Internal PM monitoring and

generation for up to 128 VCCs

– Local bus control

• Optional local processor New

Features

– Frame relay DE with priority

threshold

• Optional global OAM Rx/Tx queues

• In-line OAM insertion and generation

• Scheduler driven by selectable clock

– Local system clock

• 3.3 V, 388 BGA lowers power and

eases PCB assembly (0.75 W max)

– LECID filtering and echo

suppression

Standards-Based I/O

• 33 MHz PCI 2.1 (to 40 MHz)

– External reference clock

• AAL3/4 CPCS generation and

checking

– Per-VCC firewalls

• Internal RM OAM cell feedback path

• Serial EEPROM to store PCI

configuration information

• Dynamic channel lookup (NNI or UNI

addressing)

• Virtual FIFO buffer rate matching

(Source Rate Matching)

• PCI 2.1, including support for serial

EEPROM

• PHY interfaces

– Supports full address space

– Deterministic

• Per-VCC MCR and ICR

• Tunneling

• Enhancements to xBR Traffic

Manager

– UTOPIA master (Level 1)

– UTOPIA slave (Level 1)

– UTOPIA master (Level 2)

– UTOPIA slave (Level 2)

– Flexible VCI count per VPI

– Fewer ABR templates

– Improved CBR tunneling

–VP tunnels (VCI interleaving on

PDU boundaries)

– Optimized for signaling address

assignment

– CBR tunnels (cells interleaved as

UBR, VBR or ABR with an aggregate

CBR limit)

• Reduced memory size for VCC

lookup tables

• Flexible SAR-shared memory

architecture

• Message and streaming status

modes

• Increased addressing flexibility

• Optional local control interface

• 155 Mbps full-duplex (2-cell PDUs)

• Raw cell mode (52 octet)

• 200 Mbps half duplex

• Additional byte lane swappers for

increased system flexibility

• Boundary scan for board-

level testing

Multi-Queue Segmentation

Processing

• 32 transmit queues with optional

priority levels

• 155 Mbps full duplex (with

2-cell PDUs)

• UTOPIA Level 2, 8/16 bit 50 MHz

• Source loopback, for diagnostics

• Programmable size routing tags for

up to 64 byte cells

• Glueless connection to Mindspeed’s

ATM physical layer device, the

CX28250 and CN8223

• Distributed host or SAR-shared

memory reassembly

• Selectable single/separate

UTOPIA clocks

• 64 K VCCs maximum

• 8 Programmable reassembly hard-

ware time outs (per-VCC assignable)

• AAL5 and AAL3/4 CPCS generation

Standards Compliance

• UNI/NNI 3.1

• Interworking function for all

AAL1/2 scheduling

• AAL0 Null CPCS (optional use of PTI

for PDU demarcation)

• Global max PDU length for AAL5

• TM 4.0 / TM 4.1 compliant

• Bellcore GR-1248

• Per-VCC buffer firewall (memory

usage limit)

– Cell-on-demand scheduling

• ATM cell header generation

• Raw cell mode (52 octet)

• 200 Mbps half-duplex

• Updated PM-OAM processing

per i.610

• Simultaneous reassembly and

segmentation

• ATM Forum B-ICI V2.0

• SECBC calculated per GR-1248

Ordering Information

Model number: CN8236EBGB

• 155 Mbps full-duplex (with 2-cell

PDUs)

• Idle cell filtering

• Paging function in order to gluelessly

control RS8228 cell delineator

High-Performance Host

Architecture with Buffer

Isolation

• Variable length transmit FIFO buffer

Manufacturing part number:

28236-12P

• Robust EEPROM operation (SAR

provides power)

– CDV-host latency matching

(1 to 9 cells)

Product revision: B

• Compact PCI Hot Swap capabilities

• Write-only control and status

• Symmetric Tx and Rx architecture

– Buffer descriptors

– Queues

Package: 388-pin BGA

• Master PCI write over read

arbitration control

• Read multiple command for data

transfer

Operating temperature: -40°C to 85ºC

• Increase incoming DMA FIFO buffer

from 2 KB to 8 KB

• Up to 32 host clients control and

status queues

• User defined field circulates back to

the host (32 bits)

• Prepended VCC index on RSM

BOM cells

• Physical or logical clients

• Distributed host or SAR-shared

memory segmentation

– Enables peer-to-peer architecture

• Descriptor-based buffer chaining

• Scatter/gather DMA

• Optional reference clock drive

scheduler

• Simultaneous segmentation and

reassembly

• Head of line blocking protection for

multi-PHY operation

• Endian neutral (allows data word and

control word byte swapping, for both

big and little endian systems)

• Per-PDU control of CLP/PTI (UBR)

• Per-PDU control of AAL5 UU field

™

www.mindspeed.com/salesoffices

General Information: (949) 579-3000

Headquarters – Newport Beach

4000 MacArthur Blvd., East Tower

Newport Beach, CA 92660-3007

8236-BRF-001-A M01-0590

logo are trademarks of Mindspeed Technologies. All other trademarks are the property

of their respective owners. Although Mindspeed Technologies strives for accuracy in all

its publications, this material may contain errors or omissions and is subject to change

without notice. This material is provided as is and without any express or implied

warranties, including merchantability, fitness for a particular purpose and non-

infringement. Mindspeed Technologies shall not be liable for any special, indirect, inci-

dental or consequential damages as a result of its use.

28236-BRF-001-A [TE]

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