78P2341JAT-IH [TERIDIAN]
PCM Transceiver, 1-Func, PQCC28, PLASTIC, LCC-28;
| 型号： | 78P2341JAT-IH |
| 厂家： | 
TERIDIAN SEMICONDUCTOR CORPORATION |
| 描述： | PCM Transceiver, 1-Func, PQCC28, PLASTIC, LCC-28 PC 电信 电信集成电路 |
| 文件： | 总37页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PRELIMINARY DATASHEET
AUGUST 2003
DESCRIPTION
FEATURES
The 78P2341JAT is a low-power, single channel
DS3/E3/STS1 transceiver IC with integrated Jitter
Attenuator (JAT). It includes clock recovery and
transmitter pulse shaping functions for applications
using 75-ohm coaxial cable at distances up to 1350
feet. These applications include DSLAMs, T1,3/E1,3
digital multiplexers, SONET Add/Drop multiplexers,
PDH equipment, DS3 to Fiber optic and microwave
modems, and ATM WAN access for routers and
switches.
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements. It has an
integrated B3ZS/HDB3 ENDEC with a receive line
code violation detector, a loop-back mode, a clock
polarity selection mode, and the ability to receive a
DSX3 monitor signal.
•
Transmit and receive interface for E3, DS3 and
STS-1 applications
•
Designed for use with 75 ohm coaxial cable up
to 1350 ft long end-to-end or up to 900 ft long
from a DS3 cross-connect
•
•
•
Receive DS3-high and DSX3 monitor signals
Local and Remote loopback
Selectable B3ZS/HDB3 ENDEC with line code
violation detector
•
•
Standards-based LOS function
Optional serial-port based mode selection and
channel status monitoring
•
•
Receiver AGC corrects for up to 6dB of flat loss
Adaptive digital clock recovery (uses line-rate
reference clock input)
•
•
Receive output clock maintains nominal line-rate
frequency at all times
Fully integrated Jitter Attenuator (no external
VCXO required) configurable for transmit or
receive path
STANDARDS
•
•
Transmit line fault monitor
•
Jitter Tolerance: Telcordia GR-499-CORE [DS3]
and GR-253-CORE [STS1], ITU-T G.823 [E3]
and G.824 [DS3]
Requires no external current-setting resistor or
loop filter components
•
•
Single 3.3V supply operation
•
•
Loss of Signal: ITU-T G.775
Available in 28-pin PLCC or 48-pin TQFP
Jitter Transfer: ETSI TBR-24 1997 [E3];
Telcordia GR-499-CORE [DS3] and GR-253-
CORE [DS3/STS1]
BLOCK DIAGRAM
Controls Flags
RLBK
LBO E3 DS3
Transmit
TXNW
TXEN
Monitor
TPOS
TNEG
B3ZS /
LOUTP
LOUTN
Pulse
HDB3
Shaper
Encoder
TCLK
Attenuator
Jitter
Attenuator
ENDEC
RPOS
B3ZS /
HDB3
Data
Detector
Adaptive
Equalizer
LINP
LINN
RNEG
RCLK
AGC
Decoder
MON
TCLKP
RCLKP
Power
Distribution
Signal
Detector
Clock
Recovery
LOS
LLBK
PDTX PDRX
CKREF
Master
Bias
Generator
SCK
SDIO
Control
Registers
CKREF
- 1 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
The jitter tolerance of 78P2341JAT meets the
requirements of ITU-T G.823 for E3 rates; the
requirements of ITU-T G.824, GR-499 (Cat I and II)
for DS3 rates; and the requirements of GR-253 for
STS1 rates.
When the Jitter Attenuator is disabled, the jitter
transfer function meets the requirements of GR-499
for Category II DS3 interfaces.
FUNCTIONAL DESCRIPTION
The 78P2341JAT contains all the necessary
transmit and receive circuitry for connection
between E3, DS3, or STS-1 interfaces and
Framer/Mapper ICs.
OPERATING RATE
The Master Control Register (MSCR) determines
which mode the device operates in according to the
table below. The MSL0 pin is also provided for
mode selection in applications without a serial
control interface. Upon power-up or reset, the state
of the MSL0 pin is sensed and mapped into the DS3
and E3 register bits representing the appropriate
mode of operation. After power-up/reset, the state of
the MSL0 pin is ignored.
When the Jitter Attenuator is enabled, the
78P2341JAT meets the requirements of GR-499
and GR-253 for all categories of DS3/STS1
equipment and the ETSI TBR-24 requirements for
E3 rates.
standards,
To check conformance with other
please
refer
to
the
JITTER
ATTENUATOR TRANSFER FUNCTION section for
more detailed info.
REFERENCE CLOCK
Standard
MSL0 pin
DS3 bit
E3 bit
The clock recovery system employs a digital PLL,
which uses a line-rate reference clock frequency.
This reference frequency can be input to the CKREF
pin or it can utilize the transmitter clock input TCLK
when CKREF is left floating or pulled high.
E3
L
H
Z
Z
0
1
0
1
1
0
0
1
DS3
STS-1
STS-1
RECEIVER OPERATION
RECEIVER MONITOR MODE
The receiver inputs LINP and LINN are either
When the MON pin is high, 20dB of flat gain is
applied to the incoming signal before it is fed to the
receive equalizer. Alternately, the MON bit in the
Mode Control Register can be used if the Register
Control bit, REGEN, is enabled.
transformer-coupled or capacitor-coupled to the line
signal.
In applications where the highest
performance and isolation are required, a 1:1
transformer is used in the receive path. In
applications where isolation is provided elsewhere in
the circuit, capacitor coupling can be used. The
receiver inputs should be line terminated externally
with a termination resistor.
SIGNAL DETECT
When the received signal is below a minimum
threshold, the LOS signal (bit) in the Status Monitor
register is asserted. A time delay is provided before
this output is active so that transient interruptions do
not cause false indications. By default, the LOS
signal is also used to trigger an interrupt on the LOS
pin. Note that the error events that control the
assertion of the LOS pin can be configured in the
Interrupt Control Register (INTC).
The AMI signal first enters an AGC, which has a
selectable gain range setting. In normal operation,
the AGC can compensate for signals with up to 6dB
of flat loss. When Receiver Monitor Mode is
enabled, the AGC can compensate for a DSX3
monitor signal with 16 to 20 dB of flat loss. The
signal then enters a high performance adaptive
equalizer. The equalizer is designed to overcome
inter-symbol interference caused by long cable
lengths. Because the equalizer is adaptive, the
circuit will work with all square-shaped signals such
as DS3-high or 34.368 Mbit/s E3. The variable gain
differential amplifier automatically controls the gain
Note: In DS3 or STS-1 mode, when LBO is not
enabled, the transmitters have to be properly
terminated to ensure reliable LOS detection. If a
transmitter is not terminated, the resultant 2x signal
is large enough to couple to the neighboring
receivers through the ESD diodes, causing false
Signal Detect indication.
to maintain
a
constant voltage level output
regardless of the input voltage level.
- 2 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
LOOPBACK MODES
A third loopback mode is also available when using
the serial control interface. Local (Digital) Loopback
mode is controlled by the Jitter Attenuator Control
Register and only passes through the Jitter
Attenuator, bypassing all Analog blocks in the IC.
The LPBK pin is used to activate common loopback
modes as shown in the table below. The LLBK and
RLBK bits in the Mode Control Register can also
control these modes when the Register Control bit,
REGEN, is enabled.
Local (Digital) Loopback
LPBK
Controls Flags
RLBK
LBO E3 DS3
Transmit
Monitor
Loopback Mode
TXNW
TXEN
pin
TPOS
TNEG
B3ZS
HDB3
/
LOUTP
LOUTN
Pulse
Shaper
Encoder
TCLK
Local (Analog) Loopback
Attenuator
Jitter
Attenuator
ENDEC
L
Same as LLBK = ‘1’
RPOS
B3ZS
HDB3
/
Data
Adaptive
Equalizer
LINP
LINN
RNEG
RCLK
AGC
Detector
Decoder
Remote (Digital) Loopback
Z
MON
TCLKP
RCLKP
Power
Distribution
Signal
Detector
Clock
Recovery
LOS
Same as RLBK = ‘1’
LLBK
PDTX PDRX
Normal Operation
H
CKREF
Same as LLBK, RLBK = ‘0’
Master
Bias
Generator
SCK
SDIO
Control
Registers
CKREF
When in Local (Analog) Loopback, the transmit
output signals, LOUTP,N are internally routed to the
receiver inputs. Any incoming signals on LINP,N will
be ignored when in Local Loopback. For proper
operation in this mode, the transmitter needs to be
properly terminated with no hanging cables.
B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION
DETECT
The 78P2341JAT includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). When the ENDEC pin
is low, the ENDEC is selected and the decoder
generates a composite NRZ logic data stream
following the B3ZS (for DS3/STS-1) or HDB3 (for E3)
substitution codes via the RPOS pin as shown
below.
Local (Analog) Loopback
Tx JAT Off
Controls Flags
RLBK
LBO E3 DS3
Transmit
Monitor
TXNW
TXEN
TPOS
TNEG
TCLK
Tx JAT On
B3ZS
HDB3
/
LOUTP
LOUTN
Pulse
Shaper
Encoder
Attenuator
Jitter
Attenuator
ENDEC
RPOS
B3ZS
HDB3
/
Data
Detector
Adaptive
Equalizer
LINP
LINN
RNEG
RCLK
AGC
Decoder
ENDEC
RPOS
RNEG
Rx JAT On
Rx JAT Off
MON
TCLKP
RCLKP
Power
Signal
Detector
Clock
Recovery
LOS
Distribution
LLBK
1
Positive AMI
Negative AMI
PDTX PDRX
CKREF
Master
Bias
Generator
Receive Line Code
Violation Indicator
SCK
SDIO
Control
Registers
CKREF
0
NRZ data
When in Remote (Digital) Loopback, the received
signals and clock data, RPOS/RNEG/RCLK, are
internally routed to the transmitter input signals. Any
incoming data on TPOS, TNEG, or TCLK will be
ignored when in Remote Loopback.
The decoder also detects Receive Line Code
Violations (RLCV) and outputs a pulse via the
RNEG pin. Three different classes of line code
violations are detected.
Remote (Digital) Loopback
•
Too many zeros: More than two (three)
consecutive zeros in B3ZS (HDB3) mode.
Controls Flags
RLBK
LBO E3 DS3
Transmit
Monitor
TXNW
TXEN
TPOS
TNEG
TCLK
B3ZS
/
LOUTP
LOUTN
Pulse
•
Not enough zeros between bipolar pulse (B) and
bipolar violation pulse (V): (B,V) for B3ZS.
(B,V) or (B,0,V) for HDB3.
HDB3
Shaper
Encoder
Attenuator
Jitter
ENDEC
Attenuator
RPOS
B3ZS
HDB3
/
Data
Detector
Adaptive
Equalizer
LINP
LINN
RNEG
RCLK
AGC
Decoder
MON
•
Code violation: Even number of bipolar pulses (B)
detected between bipolar violation pulses (V).
TCLKP
RCLKP
Power
Signal
Clock
Recovery
LOS
Distribution
Detector
LLBK
PDTX PDRX
CKREF
Master
Bias
Generator
SCK
SDIO
Control
Registers
CKREF
- 3 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
On the transmit side, when the ENDEC pin is low,
NRZ input data is encoded to Positive and Negative
logic data following the B3ZS (for DS3/STS-1) or
HDB3 (for E3) substitution codes. The NRZ data is
input to the TPOS pin as shown below.
TRANSMIT MONITOR
The transmit monitor function detects activity on the
transmitter output at the LOUTP and LOUTN pins.
When there is a transmitter fault, as in an open or
short on the chip, the transformer, or the circuit
board, the transmit signal amplitude will be altered.
The transmit monitor detects the amplitude of the
driven signal.
The TXOK pin goes low when the amplitude of the
transmit signal is outside a valid amplitude range for
longer than a specified duration. Alternately, the
TXNW bit in the Status Monitor register can be used
to monitor the transmit amlitude.
ENDEC
TPOS
TNEG
1
0
Positive AMI
NRZ data
Negative AMI
‘Don’t Care’
The ENDEC bit in the Mode Control Register can
also control the ENDEC. The Register Control bit
(REGEN) must be enabled if using the register
settings to avoid conflict with external setting pins.
Note that the TXNW signal can also be used to
trigger an event on the LOS pin. This is done by
setting the TXER bit in the Interrupt Control Register
(INTC).
TRANSMITTER OPERATION
The transmitter accepts either NRZ coded data or
positive and negative AMI signals and generates
current pulses on the LOUTP and LOUTN pins.
When properly connected to a 1:2CT center-tapped
transformer, an AMI pulse is generated which can
drive a 75Ω coaxial cable.
When the recommended transformer is used and
when DS3 mode is selected, the transmitted pulse
shape at the end of the 75Ω terminated cable of 0 to
450 feet will fit the DS3 template in ANSI T1.102-
1993 and Telcordia GR-499-CORE standard
documents. For STS-1 applications, the transmitted
pulse for a short cable meets the requirements of
Telcordia GR-253-CORE. For E3 applications, the
transmitted pulse for a short cable meets the
requirements of ITU-T G.703.
JITTER ATTENUATOR
Jitter Attenuation function is provided on-chip. The
Jitter Attenuator can be configured to be in the
transmit or the receive path. When configured in the
transmit path, the input clock at TCLK pin is passed
through a very low bandwidth digital PLL. The
corresponding transmit data is buffered into a FIFO
and clocked out using the de-jittered output clock of
the PLL. When configured in the receive path, the
recovered clock is passed through the low
bandwidth digital PLL, and the corresponding
receive data is buffered into the FIFO and clocked
out using the de-jittered clock.
The Jitter Attenuator can be configured by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
LINE BUILD-OUT
JAEN
bit
JASL
bit
X
The Line Build-Out (LBO) function controls the
transmit amplitude and pulse shape in DS3 and
STS-1 modes. The selection of LBO depends on
the amount of cable the transmitter is connected to.
When less than 225 ft of cable is used, the LBO pin
(or LBO bit) should be high. When 225ft or more
cable is used, the LBO pin (or LBO bit) should be
low.
Jitter Attenuator Mode
0
Jitter Attenuator disabled
Jitter Attenuator configured
to be in the receive path
Jitter Attenuator configured
to be in the transmit path
1
0
1
1
LBO settings can be controlled either from pins or
from register settings, depending on the status of
the Register Control bit, REGEN. Note that LBO
settings are ignored when in E3 mode.
TRANSMIT ENABLE
The TXEN pin controls the transmitter output. When
low, the transmitter output is disabled. Alternately,
the TXEN bit in the Mode Control register can
control the transmitter if the Register Control bit is
enabled.
- 4 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
When serial interface control is not available, the
TXEN and MON pins are provided for Jitter
Attenuator mode selection. Upon power-up or reset,
the states of the TXEN and MON pins are sensed
and mapped into the JAEN and JASL register bits
representing the appropriate mode of operation.
After power-up/reset, the states of the TXEN and
MON pins are ignored for JAT controls (Transmit
Enable/Disable and Rx Monitor modes can still be
controlled). The states of the TXEN and MON pins,
and the corresponding Jitter Attenuator configuration
are shown below.
PLL Bandwidth
A PLL response with effectively one pole below 27
Hz is adequate to meet the ETSI TBR24 E3
standards. A PLL response with one pole below 40
Hz is adequate to meet the GR-499 (Cat I) DS3
standards. Either of the two bandwidths can be
selected via register setting. In either high or low
bandwidth mode, the PLL bandwidth is proportional
to the data rate as follows:
Line Rate
JABW bit
PLL Bandwidth (Hz)
0
1
0
1
0
1
13
188
17
245
20
E3
TXEN
pin
Jitter Attenuator Mode/Transmit
Driver Mode
DS3
Jitter Attenuator disabled (upon reset)
Disable transmit driver
L
Z
H
STS1
Jitter Attenuator enabled in transmit path
283
(upon reset)
Enable transmit driver
Jitter Attenuator disabled (upon reset)
Enable transmit driver
The default state of the JABW bit depends on which
line-rate is selected through the MSL0 pin. If E3 or
DS3 mode is selected, the default state is ‘0’. If
STS1 mode is selected, the default state is ‘1’.
Elastic Store Depth
To optimize the trade-off between data latency and
clock wander tolerance, the FIFO elastic store depth
can be selected through the serial port by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
MON
pin
L
Jitter Attenuator Mode/Receive
Monitor Mode
Jitter Attenuator disabled (upon reset)
Disable monitor mode
Z
Jitter Attenuator enabled in receive path
ESP[1:0]
Elastic Store Depth
bits
(upon reset)
Disable monitor mode
Jitter Attenuator disabled (upon reset)
Enable monitor mode
00
01
10
11
Pass-Through mode
16 UI
H
32 UI
64 UI (default)
The Elastic Store Depth selects the nominal FIFO
read pointer address. The total or maximum elastic
store depth is set to be twice as deep as the nominal
pointer address. The circular buffer length is always
twice as long as the nominal pointer address.
- 5 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
RCLK/TCLK POLARITY REVERSAL
SERIAL CONTROL INTERFACE
To simplify the interface with various framer
circuitries, clock polarities can be set with the ICKP
pin as described in the table below. Alternately,
TCLK polarity can be internally inverted by setting
the TCLKP bit, and RCLK polarity can be inverted
by setting the RCLKP bit. Both bits are located in
the Master Control Register (MSCR) and are only
active when the Register Control Enable (REGEN)
bit is enabled.
The serial port controlled register allows a generic
controller to interface with the 78P2341JAT. It is
used for mode settings, diagnostics and test, and
the retrieval of status and performance information.
The serial interface consists of two pins: Serial
Clock (SCK) and Serial Data In and Out (SDIO).
Serial Data In (SDI) and Serial Data Out (SDO) are
connected together internally to simplify the
operation. SCK is the clock input that times the data
on SDIO. Data on SDI is latched in on the rising-
edge of SCK, and data on SDO is clocked out using
the falling edge of SCK.
SDI is used to insert mode, address, and register
data into the chip. Address and Data information
are input least significant bit (LSB) first. The mode
and address bit assignment and register table are
shown in the following section.
ICKP
RCLK/TCLK polarity
Update on falling edge of RCLK
Sample on rising edge of TCLK
Update on rising edge of RCLK
Sample on falling edge of TCLK
Update on falling edge of RCLK
Sample on falling edge of TCLK
L
Z
H
SDO is a tristate capable output. It is used to output
register data during a read operation. SDO output is
normally high impedance, and is enabled only
during the duration when register data is being
clocked out. Read data is clocked out significant bit
(LSB) first.
The maximum clock frequency for register access is
20MHz, while the minimum is 5MHz. There must be
at least 10us between clock bursts.
POWER-DOWN FUNCTION
Power-down controls are provided to allow the
transceiver to be shut off. Transmit and receive
power-down can be set independently via the PDTX
and PDRX bits in the Mode Control Register. The
Serial Control Interface and Configuration Registers
are not affected by power-down.
INTERNAL POWER-ON RESET
The 78P2341JAT includes on-chip Power-On Reset
(POR) function to ensure the serial-port registers are
initialized to known default states upon power-up.
This reset signal also sets all state machines within
the transceiver to nominal operational states. The
internal reset signal is also brought out to the POR
pin. This pin is a multi-function pin which allows for
the following:
1) Override the internal POR signal by driving in an
external active-low reset signal;
2) Monitor the state of the internal POR signal (for
test and debug only);
3) Add external capacitor to delay the release of
the internal power-on reset signal to allow the
MSL0 pin to stabilize prior to release of reset
(approximately 8µs per nF added).
The internal resistance of the POR pin is
approximately 5kΩ. This pin is not available in the
28-pin PLCC version.
- 6 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Sub-Address
SA[1]
Bit 1
Bit 0
Read/
Write
Port Address
Assignment
PA[3]
PA[2]
PA[1]
PA[0]
SA[2]
SA[0]
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Reg.
Sub
Description
Master Control
Interrupt Control
Bit 7
Bit 6
Bit 5
Bit 4
ENDEC
<0>
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Name
REGEN
<0>
INPOL
<0>
E3
<X>
RCLKP
<0>
JAFLG
<0>
TCLKP
<0>
JAER
<0>
SRST
<0>
TXER
<1>
MSCR
DS3
<X>
0
1
--
(R/W)
INTC
(R/W)
RXER
<1>
--
--
--
2
3
4
5
6
7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
<0>
--
--
--
--
--
--
--
--
--
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
b) PA[3:0] = 1 : Specific Registers
Reg.
Sub
Description
Bit 7
Bit 6
Bit 5
Bit 4
--
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Name
LBO
<1>
MDCR
PDTX
<0>
PDRX
<0>
LLBK
<0>
RLBK
<0>
MON
<0>
TXEN
<1>
0
Mode Control
(R/W)
STAT
(R/O)
1
2
3
4
5
6
7
Status Monitor
Reserved
FERR
FLIM1
FLIM2
SLIP
<1>
<0>
--
LOS
TXNW
SGHI
<0>
<0>
--
SGLO
RSVD
--
<1>
<0>
<0>
<1>
<0>
JACR
(R/W)
Jitter Attenuator
Control
JAEN
<X>
JASL
<X>
JLBK
<0>
ESP[1]
<1>
ESP[0]
<1>
JABW
<X>
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
--
--
--
--
--
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
--
<0>
<0>
<0>
<0>
<0>
<0>
<0>
<0>
Note: Shaded registers in Register Table are reserved for TDK internal use only. Accessing reserved or
undefined registers may cause undesirable operation.
- 7 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
LEGEND
TYPE DESCRIPTION
TYPE DESCRIPTION
R/O
Read only
R/W Read or Write
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Register Control Enable:
0 : Pin selection overrides register settings.
1 : Device is controlled via register set.
7
REGEN
R/W
0
Line Speed Selection: Selects the line speed as well as the input clock
frequency at the CKREF pin.
[DS3 E3] = 00 : STS-1 (51.840MHz)
01 : E3 (34.368MHz)
6
5
DS3
E3
R/W
R/W
X
X
10 : DS3 (44.736MHz)
11 : STS-1 (51.840MHz)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset.
Encoder/Decoder Disable:
0 : selects NRZ digital data interface
1 : selects AMI digital data interface
4
ENDEC
R/W
0
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDEC pin
selection prevails.
RCLK Polarity Selection:
3
2
RCLKP
TCLKP
R/W
R/W
0
0
0 : Receive Data clocked out on the falling-edge of RCLK
1 : Receive Data clocked out on the rising-edge of RCLK
TCLK Polarity Selection:
0 : Transmit Data clocked in on the rising-edge of TCLK
1 : Transmit Data clocked in on the falling-edge of TCLK
1
0
RSVD
SRST
R/O
R/W
X
0
Reserved
Register Soft-Reset: When this bit is set, all registers are reset to their
default values. Also resets Jitter Attenuator to “centered” states. This
register bit is self-clearing.
- 8 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 0-1: INTERRUPT CONTROL REGISTER
This register selects the events that would cause the LOS pin to be activated. User may set as many bits as
required.
DFLT
BIT
NAME
TYPE
DESCRIPTION
Interrupt Pin Polarity Selection:
VALUE
7
INPOL
R/W
0
0 : Interrupt output is active-low
1 : Interrupt output is active-high
6:4
3
RSVD
R/O
R/W
X
0
Reserved
Reserved for test only. Must be set to ‘0’.
Jitter Attenuator Error Event:
JAFLG
2
1
0
JAER
RXER
TXER
R/W
R/W
R/W
0
1
0
When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)
will cause an interrupt to be flagged.
Receiver Error Event:
When set, loss of receive signal (as indicated by the LOS bit) will cause
an interrupt to be flagged.
Transmitter Error Event:
When set, transmitter fault (as indicated by the TXNW bit) will cause an
interrupt to be flagged.
- 9 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
SPECIFIC REGISTERS
For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and
the read/write operation will be ignored.
ADDRESS 1-0: MODE CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Transmitter Power-Down:
0 : Normal Operation
1 : Power-Down
7
PDTX
R/W
0
Receiver Power-Down:
0 : Normal Operation
1 : Power-Down
6
PDRX
R/W
0
Transmitter Line Build-Out (DS3 and STS-1 only):
0 : ≥ 225ft of cable attached to the cross-connect
1 : < 225ft of cable attached to the cross-connect
(Note this bit is inactive when REGEN bit is ‘0’ )
5
4
3
LBO
RSVD
LLBK
R/W
R/W
R/W
1
0
0
Reserved
Local (Analog) Loopback Mode Enable:
0 : Normal operation
1 : Loops LOUTP and LOUTN back onto LINP and LINN
(Note this bit is inactive when REGEN bit is ‘0’ )
Remote (Digital) Loopback Enable:
0 : Normal Operation
1 : Loops RCLK, RPOS, and RNEG back onto TCLK, TPOS, and TNEG
(Note this bit is inactive when REGEN bit is ‘0’ )
2
1
0
RLBK
MON
TXEN
R/W
R/W
R/W
0
0
1
Monitor Mode Enable: Used for reception of split-off signals that are flat-
attenuated by at least 16dB but no more than 20dB.
0 : Disable
1 : Enable
(Note this bit is inactive when REGEN bit is ‘0’ )
Transmitter Output Enable:
0 : Transmit driver is disabled
1 : Normal Operation
(Note this bit is inactive when REGEN bit is ‘0’ )
- 10 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 1-1: STATUS MONITOR REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator FIFO Error Flag: This bit is set whenever a FIFO
overflow or underflow occurred. It is reset after a read operation to this
register.
0 : Proper Operation
1 : FIFO Overflow/Underflow
7
FERR
R/O
R/O
X
X
6:4 JAF[2:0]
Jitter Attenuator Monitor Flags: Used for internal test only. Ignore during
normal operation.
Loss-of-Signal Indication:
0 : Signal Detector detecting a valid receive input signal
1 : Standards-based Loss-of-Signal indication
3
LOS
R/O
X
Note: RPOSx and RNEGx are forced low when LOS=’1’ ; RCLK will
continue to output a line rate clock
Transmitter Not-Working Indication:
0 : Transmitter OK
1 : Transmitter not working
2
1
0
TXNW
SGHI
R/O
R/O
R/O
X
X
X
Signal High Indication: Used for internal test only. Ignore during normal
operation
Signal Low Indication:
0 : Receive signal level OK
SGLO
1 : Receive signal level too low / Loss of signal
- 11 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS 1-3: JITTER ATTENUATOR CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator Enable:
0 : Disables jitter attenuation function
1 : Enables jitter attenuation function
7
JAEN
R/W
X
Note: The default value of this register bit depends on the state of the
TXEN and MON pins upon power up or a reset.
Jitter Attenuation Selection:
0 : Jitter Attenuator on the receive path
1 : Jitter Attenuator on the transmit path
6
JASL
R/W
X
Note: The default value of this register bit depends on the state of the
TXEN and MON pins upon power up or a reset.
Jitter Attenuator Local Loopback Enable:
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and RCLKx, RPOSx,
5
4
JLBK
R/W
R/W
0
0
RNEGx connected to JAT output
Note: If both RLBK and JLBK bits are set, RLBK mode takes priority.
Reserved. Must be set to zero.
RSVD
FIFO Elastic Store Pointer Selection:
00 : Pass-through
ESP
[1:0]
3:2
1
R/W
R/W
11
0
01 : 8 UI
10 : 16 UI
11 : 32 UI
RSVD
Reserved. Must be set to zero.
Jitter Attenuator Bandwidth Selection:
0 : Low bandwidth
1 : High bandwidth
(see JAT Bandwidth Selection Table on page 5)
0
JABW
R/W
X
Note that the default value of this register bit depends on the power-up
state of the MSL0 pin. If the state of the MSL0 pin selects E3 or DS3
mode, the default value of JABW is ‘0’. If the state of the MSL0 pin
selects STS1 mode, the default value of JABW is ‘1’.
- 12 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION
LEGEND
TYPE
A
CI
CIU
CID
DESCRIPTION
Analog Pin
CMOS Digital Input
CMOS Digital Input w/ Pull-up
CMOS Digital Input w/ Pull-down
TYPE DESCRIPTION
CIS
CO
COZ
S
CMOS Schmitt Trigger Input
CMOS Digital Output
CMOS Tristate Digital Output
Supply
TRANSMITTER PINS
PIN
PIN
NAME
TYPE DESCRIPTION
TQFP PLCC
Transmit Positive Data/Transmit NRZ:
When ENDEC =’1’, a logic one on this pin generates a positive AMI pulse
on the coax. This pin should not be high at the same time that
corresponding TNEG is high.
16
17
14
15
CI
CI
TPOS
TNEG
When ENDEC =’0’, data on this pin is encoded and converted into
positive and negative AMI pulses.
Transmit Negative Data:
When ENDEC bit =’1’, a logic one on this pin generates a negative AMI
pulse on the coax. This pin should not be high at the same time that
corresponding TPOS is high.
When ENDEC bit =’0’, this pin is ignored.
Transmitter Clock Input:
This clock signal is used to latch the respective TPOS and TNEG
signals into the 78P2341JAT. The frequency should correspond to the
line-rate frequency as follows:
18
16
CIS
TCLK
E3 : 34.368 MHz
DS3: 44.736 MHz
STS-1: 51.840 MHz
If CKREF pin pulled high or left floating, TCLK is also used as the
reference clock for the 78P2341JAT.
Line Out:
9
11
9
11
LOUTP
LOUTN
Differential AMI Outputs. Requires a 1:2CT center-tapped transformer
and a shunt termination resistor. See APPLICATION INFORMATION
section for more info.
A
- 13 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
RECEIVER PINS
PIN
PIN
NAME
TYPE DESCRIPTION
Reference Clock Input:
TQFP PLCC
This clock should be from a clean source (± 20 ppm) and represents
the line-rate frequency as follows:
E3 : 34.368 MHz
DS3: 44.736 MHz
STS-1: 51.840 MHz
26
19
CIU
CKREF
Tying this pin high or leaving it floating forces the 78P2341JAT to use
the clock applied to the transmitter clock input (TCLK) as the reference
source.
Receive Clock: Recovered receive clock.
Note: When Loss of Signal (LOS) occurs, RCLK will output the
reference clock applied at CKREF (or TCLK if CKREF is pulled high or
left floating).
33
34
23
24
CO
CO
RCLK
RNEG
Receive Negative Data:
When ENDEC =’1’, this pin indicates reception of a negative AMI pulse on
the coax.
When ENDEC =’0’, this pin outputs a one when a receive line code
violation is detected.
Receive Positive Data/NRZ Data:
When ENDEC =’1’, this pin indicates reception of a positive AMI pulse
35
25
CO
A
RPOS
on the coax cable.
When ENDEC =’0’, it outputs decoded NRZ data.
Line In:
42
44
1
3
LINP
LINN
Differential AMI Inputs. Should be 1:1 transformer-coupled and
terminated with a shunt resistor. See APPLICATION INFORMATION
section for more info.
- 14 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
CONTROL AND STATUS PINS
PIN
PIN
NAME
TYPE DESCRIPTION
TQFP PLCC
Data-Rate Mode Selection:
Low = E3 mode
High = DS3 mode
Float = STS-1 mode
15
28
13
21
A
A
MSL0
Note: This pin is only sensed upon power up or a reset.
Receive Monitor and Jitter Attenuator Mode Selection:
Low = Disable monitor mode and disable RX jitter attenuation
High = Enable monitor mode and disable RX jitter attenuation
Float = disable monitor mode and enable RX jitter attenuation
MON
(Note this pin is inactive when REGEN register bit is ‘1’ )
12
13
XX
12
A
Power-On Reset: See Power-On Reset description on use of this pin.
POR
Line Build-Out: Logic low used with 225ft or more of cable. Logic high
used with less than 225ft of cable.
(Note this pin is inactive when REGEN register bit is ‘1’ )
CID
LBO
Loopback Enable:
Low = Local Loopback. Transmitter looped back to Receiver
High = Normal Operation
40
22
28
18
A
A
LPBK
Float = Remote Loopback. Receiver looped back to Transmitter
(Note this pin is inactive when REGEN register bit is ‘1’ )
Transmit Tri-state and Jitter Attenuator Mode Selection:
Low = Disable transmit output driver and disable TX jitter attenuation
High = Enable transmit output driver and disable TX jitter attenuation
Float = Enable transmit output driver and enable TX jitter attenuation
TXEN
Invert Clock Polarity Selection:
Low=Update on falling edge of RCLK, Sample on rising edge of TCLK
High=Update on falling edge of RCLK, Sample on falling edge of TCLK
Float=Update on rising edge of RCLK, Sample on falling edge of TCLK
10
10
A
ICKP
(Note this pin is inactive when REGEN register bit is ‘1’ )
ENDEC enable (active-low): When low, activates B3ZS/HDB3 ENDEC
on receiver and transmitter logic signals.
(Note this pin is inactive when REGEN register bit is ‘1’ )
Jitter Attenuator Error: Logic high indicates FIFO over/underflow.
Same as the FERR bit in the Status Monitor Register.
27
36
20
A
ENDEC
XX
CO
JAERR
Loss of Signal (active low): When low, indicates the receive signal
(LINP,N) is below the threshold level for 128 periods (default setting).
Can be configured to represent any combination of LOS, TXNW, and
FERR error events through the Interrupt Control Register
39
30
27
A
LOS
Transmitter OK: Logic high when transmitter amplitude within valid
ranges.
Inversed logic of the TXNW bit in the Status Monitor register.
XX
CO
TXOK
- 15 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
SERIAL-PORT PINS
PIN
PIN
NAME
TYPE DESCRIPTION
TQFP PLCC
SCK
47
2
4
CIS
Serial Clock: Controls the timing of SDI and SDO.
Serial Data Input and Output: Inputs mode and address information.
Also inputs register data during a Write operation. Both address and data
are input least significant bit first.
Outputs register information during a Read operation. Data is output
least significant bit first
CI
COZ
SDIO
5
POWER AND GROUND PINS
It is recommended that all supply pins be connected to a single power supply plane and all ground pins be
connected to a single ground plane.
NAME
PIN TQFP
PIN PLCC
TYPE
DESCRIPTION
VCC
5, 6, 20, 21
7, 17
S
Analog Power Supply
3, 4, 7, 8,
43, 45, 46
GND
2, 6, 8
S
Analog Ground
VCCD
GNDD
37, 38
31, 32
26
22
S
S
Digital Power Supply
Digital Ground
- 16 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these limits may permanently damage the device.
PARAMETER
RATING
Supply Voltage (VCC/VCCD)
Storage Temperature
Junction Temperature
Pin Voltage (LOUTP, LOUTN)
Pin Voltage (all other pins)
Pin Current
-0.5 to 4.0 V
-65 to 150° C
-40 to 125 °C
VCC + 1.5 VDC
-0.3 to (VCC+0.6) VDC
±100 mA
RECOMMENDED OPERATING CONDITIONS
Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges.
PARAMETER
RATING
DC Voltage Supply (VCC/VCCD)
Ambient Operating Temperature
3.0 to 3.6 V
-40 to 85°C
DC CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
VCC = 3.3V
DS3 mode
Supply Current
Idd
Max. cable length
JAT Enabled:
JAT Disabled:
99
83
mA
mA
VCC = 3.3V
Transmitter disabled
DS3 mode
Max. cable length
JAT Enabled:
JAT Disabled:
Supply Current
Iddr
46
30
mA
mA
- 17 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
ANALOG PINS CHARACTERISTICS:
The following table is provided for informative purpose only. Not tested in production.
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
LINP and LINN
Ground reference
Vblin
1.9
2.6
V
Common-Mode Bias Voltage
LINP and LINN Differential
Input Impedance
Rilin
10
5
kΩ
kΩ
POR Input Impedance
Ripor
DIGITAL I/O CHARACTERISTICS:
Pins of type CI, CIU, CID:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
0.8
UNIT
V
V
µA
kΩ
kΩ
pF
Input Voltage Low
Input Voltage High
Input Current
Pull-up Resistance
Pull-down Resistance
Input Capacitance
Vil
Vih
Iil, Iih
Rpu
Rpd
Cin
2.0
-1
53
43
1
113
118
Type CIU only
Type CID only
70
58
10
Pins of type CIS:
PARAMETER
SYMBOL
Vt+
Vt-
Iil, Iih
Cin
CONDITIONS
MIN
1.45
0.85
-1
NOM
MAX
1.55
0.95
1
UNIT
V
V
µA
pF
Low-to-High Threshold
High-to-Low Threshold
Input Current
Input Capacitance
10
Pins of type CO and COZ:
PARAMETER
SYMBOL
Vol
CONDITIONS
Iol = 8mA
Ioh = -8mA
MIN
NOM
MAX
0.4
UNIT
V
V
Output Voltage Low
Output Voltage High
Output Transition Time
Tristate Output Leakage
Current
Voh
Tt
2.4
CL = 20pF; (20-80%)
3
1
ns
Iz
Type COZ only
-1
µA
- 18 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
SERIAL-PORT TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
SDIO to SCK setup time
2
ns
t
su
SDIO to SCK hold time
2
ns
ns
t
h
SCK to SDIO propagation
delay
3
t
prop
SCK
tsu th
tprop
1
SA0
SA1
SA2
PA0
PA1
PA2
PA3
D0
D1
D2
D3
D4
D5
D6
D7
Z
SDIO
SDI
SDO
Read Operation
SCK
tsu th
X
0
SA0
SA1
SA2
PA0
PA1
PA2
PA3
D0
D1
D2
D3
D4
D5
D6
D7
X
SDIO
SDI
Write Operation
- 19 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER TIMING CHARACTERISTICS:
PARAMETER
Clock Duty Cycle
Transition Time
Setup Time
SYMBOL
TTCF/TTC
TTCT
TTDPS
TTDPH
CONDITIONS
MIN
40
1
2.5
2.5
NOM
MAX
60
5
UNIT
%
ns
ns
ns
Hold Time
TIMING DIAGRAM: Transmitter Waveforms (E3/DS3/STS-1)
TTCF
TTCT
TTC
TCLK
TCLKP=LOW
TTCT
TCLK
TCLKP=HIGH
TTDPH
TTDPS
TPOS
TNEG
TTDNH
TTDNS
- 20 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
CKREF Duty Cycle
--
--
40
60
%
w.r.t. line-rate
frequency
CKREF Frequency Stability
-20
+20
ppm
Transition Time
RCLK Duty Cycle
Data Setup Time
Data Hold Time
TRCT
TRCF/TRC
TRDPS
1
40
7
5
60
ns
%
ns
ns
TRDPH
7
TIMING DIAGRAM: Receive Waveforms (E3/DS3/STS-1)
RECEIVE LINE
INPUT (REF)
(LINP,LINN)
TRCF
TRC
TRCT
RCLK
RCLKP=LOW
TRCT
RCLK
RCLKP=HIGH
TRDPH
TRDPS
RPOS
RNEG
TRDNH
TRDNS
- 21 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
DS3 TRANSMITTER
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Measured at LOUTP/LOUTN pins
w/ 37.5Ω load and LBO pin held
high.
Transmitter Amplitude
700
800
850
mVpk
Ratio of amplitudes of positive
and negative pulses measured at
pulse peaks.
Transmitter Amplitude Mismatch
0.9
1.1
+5.7
-20
Transmitter Power
at 22.368 MHz
Harmonic Power
at 44.736 MHz
All ones pattern, 3kHz bandwidth
-1.8
dBm
dBm
All ones pattern
Power below fundamental at
22.368MHz
STS-1 TRANSMITTER
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at LOUTP/LOUTN pins
w/ 37.5Ω effective load and LBO
pin held high.
700
825
950
mVpk
Transmitter Amplitude Mismatch
Transmitter Power
Ratio of amplitudes of positive and
negative pulses measured at pulse
peaks.
PRBS15 pattern band-limited to
207.36MHz.
0.9
1.1
-2.7
+4.7
dBm
E3 – TRANSMITTER
PARAMETER
CONDITION (see timing diagram)
MIN
TYP
MAX
UNIT
Transmitter Amplitude
Measured at LOUTP/LOUTN pins
w/ 37.5Ω load.
900
1000
1100
mVpk
Ratio of amplitudes of positive and
negative pulses measured at pulse
centers
Ratio of widths of positive and
negative pulses measured at pulse
half amplitude
Transmitter Amplitude Mismatch
0.95
0.95
1.05
1.05
Transmitter Pulsewidth Mismatch
Transmitter Pulsewidth
Measured at LOUTP/LOUTN pins
14.8
ns
- 22 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
E3 TRANSMIT PULSE TEMPLATE
17 ns
0.2
0.1
1.0
8.65 ns
0.1
0.2
14.55 ns
0.5
12.1 ns
24.5 ns
0.1
0
0.1
0.1
0.1
0.2
29.1 ns
- 23 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
DS3 TRANSMIT PULSE TEMPLATE
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
Time axis range (UI)
Normalized amplitude equation
UPPER CURVE
-0.85 < T < -0.68
-0.68 < T < 0.36
0.36 < T < 1.4
0.03
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.08+0.407 e
-1.84(T-0.36)
LOWER CURVE
-0.85 < T < -0.36
-0.36 < T < 0.36
0.36 < T < 1.4
-0.03
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
-0.03
- 24 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
STS-1 TRANSMIT PULSE TEMPLATE
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
1.5
Time, Unit Intervals
STS-1 (Transmit template specs)
Time axis range (T)
Normalized amplitude equation (A)
UPPER CURVE
-0.85 < T < -0.68
-0.68 < T < 0.26
0.26 < T < 1.4
0.03
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
-2.4(T-0.26)
0.1+0.61 e
LOWER CURVE
-0.85 < T < -0.38
-0.38 < T < 0.36
0.36 < T < 1.4
-0.03
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
-0.03
- 25 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, Telcordia GR-499 CORE(I)
and GR-253-CORE, and ANSI T1.102-1993 for all supported rates. Transmit output jitter is guaranteed only if a
clean SONET quality transmit clock source is used.
Measured Jitter
Amplitude
Jitter
Detector
20dB/decade
Transmitter
Output
f1
f2
PARAMETER
Transmitter Output Jitter
CONDITION
10 Hz to 800 kHz
10 kHz to 800 kHz
MIN
NOM
MAX
0.15
0.08
UNIT
UIpp
UIpp
Note: Filters defined by standards are used for all testing
- 26 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
TRANSMIT MONITOR
The transmit monitor function looks at the signals on the LOUTP and LOUTN pins and checks for the existence
of a valid signal. The monitor detects the peak of the transmitted signal at the LOUTP and LOUTN pins and
checks that it is between VUNDER and VOVER at all times. If the peak level is within the voltage threshold window,
the TXOK signal is high (TXNW bit is low). If the peak level falls outside of the threshold limits for more than
approximately 32 bit times, the TXOK signal goes low (TXNW bit goes high).
VTPOS - VTNEG
VOVER
VPEAK
VUNDER
Time
PARAMETER
CONDITION
DS3 mode with LBO=1
STS-1 mode
MIN
TYP
MAX
UNIT
VUNDER
320
mVpk
E3 mode
VUNDER
VOVER
VOVER
400
1280
1600
mVpk
mVpk
mVpk
DS3 mode with LBO=0
DS3 mode with LBO=1
STS-1 mode
E3 mode
DS3 mode with LBO=0
- 27 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
DS3/STS-1 RECEIVER (Transformer-coupled)
PARAMETER
CONDITION
MON=0.
Signal at DSX is 360-850 mVpk.
See Notes 2, 3
MON=1
MIN
TYP
MAX
UNIT
90
850
mVpk
Peak Differential Input
Amplitude, LINPx and LINNx
25
90
80
mVpk
mVpk
MON=0.
DS3-HIGH
1200
MON=0.
Flat-loss Tolerance
Receive Clock Jitter
0
6
dB
All valid cable lengths.
DS3 mode with 10 Hz – 400 kHz
a) Normal receive mode
b) Remote loopback mode
0.1
0.06
UIpp
UIpp
Interfering Tone Tolerance
(see Note 5)
Maximum ratio of Interference Power
to Signal Power for BER < 10-8
a) With 0ft cable from DSX
-9
dB
dB
-10
b) With 450ft cable from DSX
Note 1: Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSI-
T102.1993 Figure 5. Loss characteristics of the WE728A or RG59B cable should be better than Figure
C2 of ANSI-T102.1993.
Note 2: Min spec corresponds to minimum DSX amplitude, 5.5dB of cable loss (450ft) and 6dB of flat
attenuation. Error-free receiver performance is guaranteed for up to 600ft of cable from DSX cross-
connect. Typical part can handle up to 900ft.
Note 3: Min spec corresponds to amplitude of 425mVpk at DSX, 5.5dB of cable loss (450ft) and 20dB of flat
attenuation. In monitor mode, interfering tone performance is not guaranteed.
Note 4: In this mode, no noise, jitter, or interfering tone impairments should be added for guaranteed receiver
performance.
Note 5: Interfering signal is a non-synchronous sinusoidal tone of 22.368MHz for DS3 or 25.92MHz for STS-1.
Data is a PRBS15 (215-1) pattern.
- 28 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
E3 – RECEIVER (Transformer-coupled)
PARAMETER
CONDITION
MON=0
(See Note 1)
MON=1
(See Note 2)
MON=0.
All valid cable lengths.
With 100Hz-800kHz filter:
a) Normal receive mode
b) Remote loopback mode
MIN
TYP
MAX
UNIT
120
1200
mVpk
Peak Differential Input
Amplitude, LINPx and LINNx
25
0
100
6
mVpk
dB
Flat-loss Tolerance
Receive Clock Jitter
0.1
0.06
UIpp
UIpp
Interfering Tone Tolerance
(see Note 3)
Maximum ratio of Interference Power
to Signal Power for BER < 10-8
a) With 0ft cable
-9
dB
dB
-10
b) With 900ft cable
Note 1: Min spec corresponds to signal amplitude of 950mVpk at source, 12dB of cable loss (1100ft) and 6dB
of flat attenuation. Error-free receiver performance is guaranteed for all cable less than 1100ft. Typical
part can handle up to 1350ft.
Note 2: Min spec corresponds to signal amplitude of 1000mVpk at source, 12dB of cable loss (1100ft) and
20dB of flat attenuation. In monitor mode, interfering tone performance is not guaranteed.
Note 3: Interfering signal is a non-synchronous E3 signal of the specified power level below the desired E3
signal. Both data and interfering signals are PRBS23 (223-1) pattern.
- 29 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TOLERANCE
The 78P2341JAT receive jitter tolerance exceeds all specifications as shown on the graph below.
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Receiver High Frequency Jitter
Tolerance
> 60 kHz
0.75
UIpp
Jitter Tolerance: 78P234x vs. Standards
104
103
102
101
100
10-1
10-2
78P234x
GR-499-CORE(I) [DS3]
GR-499-CORE(II) [DS3]
GR-253-CORE(II) [STS1]
-
ITU T G.823 [E3]
-
ITU T G.824 [DS3]
JAT enabled
101
102
103
104
105
106
107
Jitter Frequency (Hz)
- 30 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop characteristics are such that the receiver has the following transfer function.
When the Jitter Attenuator (JAT) is enabled in the receive or transmit path, the receiver or transmitter will
exhibit a jitter transfer as shown in the graph and table below. Jitter Attenuator operation is guaranteed through
digital scan testing. The actual jitter transfer is guaranteed by logic design and is not tested during production
testing.
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Receiver Jitter transfer function
Below Fc
At –3dB point
JABW= 0, E3 mode (default)
JABW= 1, E3 mode
0.1
dB
13
188
JABW= 0, DS3 mode (default)
JABW= 1, DS3 mode
17
245
Hz
Receiver Jitter Bandwidth, Fc
JABW= 0, STS1 mode
JABW= 1, STS1 mode (default)
20
283
JAEN= 0, JAT disabled
After Fc
55
dB per
Jitter transfer function roll-off
20
decade
10
27Hz
40kHz
40Hz
1kHz
59.6kHz
0
-10
-20
-30
-40
ETSI TBR 24 (E3)
E3 JAT
STS1 JAT
JAT Disabled
DS3 JAT
-50
10
100
1k
10k
100k
1M
Jitter Frequency
- 31 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
APPLICATION INFORMATION
EXTERNAL COMPONENTS:
COMPONENT
PIN(S)
VALUE
UNITS
TOLERANCE
LINP
Receiver Termination Resistor
Transmitter Termination Resistor
75
1%
Ω
LINN
LOUTP
LOUTN
402
1%
Ω
TRANSFORMER SPECIFICATIONS:
COMPONENT
Turns Ratio for the Receiver
VALUE
UNITS
1:1
TOLERANCE
Turns Ratio for the Transmitter (center-tapped)
Suggested Manufacturer: Pulse, TDK, Halo
1:2CT
SCHEMATICS
For the latest typical application schematics, please check TDK Semiconductor's website or contact your local
sales representative for the latest application note(s) and/or demo board manuals.
- 32 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PACKAGE INFORMATION
MECHANICAL SPECIFICATIONS
28-pin PLCC
Mechanical Specification
- 33 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PACKAGE INFORMATION
MECHANICAL SPECIFICATIONS
48-pin TQFP (JEDEC LQFP)
Mechanical Specification
- 34 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PACKAGE INFORMATION
PIN-OUT
(Top View)
4
3
2
1
28 27 26
SDIO
GND
5
25
24
23
22
21
20
19
RPOS
RNEG
RCLK
GNDD
MON
6
VCC
7
78P2341
GND
8
LOUTP
ICKP
9
10
11
ENDEC
LOUTN
CKREF
12 13 14 15 16 17 18
28-pin PLCC
- 35 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
PACKAGE INFORMATION
PIN-OUT
(Top View)
N/C
SDIO
GND
36
35
34
33
32
31
30
29
28
27
26
25
1
JAERR
RPOS
2
3
RNEG
RCLK
GNDD
GNDD
TXOK
N/C
GND
4
VCC
5
VCC
6
78P2341
GND
7
GND
8
LOUTP
ICKP
LOUTN
POR
9
MON
10
11
12
ENDEC
CKREF
N/C
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
48-pin JEDEC LQFP
78P2341JAT-IGT
78P2341J-IGT
28-pin PLCC
78P2341JAT-IH
78P2341J-IH
Tape & Reel option
Lead-free option
append ‘R’
append ‘/F’
n/a
append ‘/F
- 36 -
78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
REVISION HISTORY
Revision Date:
Revision Description:
ꢀ
ꢀ
ꢀ
ꢀ
Changes to 48-TQFP pinout (pins 14, 19, 23)
Additions to CKREF pin description
Corrected LPBK pin description and Intrinsic Transmit Jitter spec.
Marketing number change
June 24, 2002
Changed to Preliminary Status
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Updated Receive Jitter Tolerance and Jitter Transfer graphs
Removed SGHI bit definition
Updated Internal Power on Reset description
Updated timing diagrams & e-spec table values
August 06, 2003
Changed recommended Rx / Tx termination resistor values to 75 / 402 ohm respectively
Preliminary Data Sheet: This Preliminary Data Sheet describes a product not completely released to production. The specifications are
based on preliminary evaluations and may not be accurate. Samples of the described product are available and limited quantities can be
purchased. TDK Semiconductor Corporation should be consulted contacted for contacted to obtain the most current up-to-date information
about the product.
If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TDK Semiconductor Corporation
(TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a
data sheet is current before placing orders. TSC assumes no liability for applications assistance.
TDK Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com
08/06/03 – rev 1.3
© 2003 TDK Semiconductor Corporation
- 37 -
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