T89C51AC2(PLCC44) [TEMIC]
Microcontroller,;
| 型号： | T89C51AC2(PLCC44) |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Microcontroller, 微控制器 |
| 文件： | 总6页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T89C51AC2
8-bit MCU with 32K byte Flash, 10 bit A/D and EEPROM
1. Description
The T89C51AC2 is a high performance FLASH version The fully static design of the T89C51AC2 allows to
of the 80C51 single chip 8-bit microcontrollers. It reduce system power consumption by bringing the clock
contains a 32Kbyte Flash memory block for program frequency down to any value, even DC, without loss of
and data.
data.
The 32K byte FLASH memory can be programmed The T89C51AC2 has 2 software-selectable modes of
either in parallel mode or in serial mode with the ISP reduced activity and an 8 bit clock prescaler for further
capability or with software. The programming voltage reduction in power consumption. In the idle mode the
is internally generated from the standard VCC pin.
CPU is frozen while the peripherals and the interrupt
system are still operating. In the power-down mode the
RAM is saved and all other functions are inoperative.
The T89C51AC2 retains all features of the 80C52 with
256 bytes of internal RAM, a 7-source 4-level interrupt
controller and three timer/counters.
The added features of the T89C51AC2 make it more
powerful for applications that need A/D conversion,
pulse width modulation, high speed I/O and counting
capabilities such as industrial control, consumer goods,
alarms, motor control, ...
In addition, the T89C51AC2 has a 10 bit A/D converter,
a 2Kbytes Boot Flash memory, 2 Kbyte EEPROM for
data, a Programmable Counter Array, an XRAM of 1024
bytes, a Hardware Watchdog Timer and a more versatile
While remaining fully compatible with the 80C52 it
offers a superset of this standard microcontroller. In X2
mode a maximum external clock rate of 20 MHz reaches
a 300 ns cycle time.
serial
channel
that
facilitates
multiprocessor
communication (EUART).
2. Features
• 80C52 core architecture
•
•
Pulse Width Modulator
Watchdog Timer (Channel 4)
•
Double Data Pointer
• Hardware watchdog timer (One-time enabled with
•
256 bytes of on-chip RAM
Reset-out)
• 1Kbytes of on-chip XRAM
• 32 Kbytes of on-chip Flash memory
• A 10-bit resolution analog to digital converter (ADC)
with 8 multiplexed inputs
• 2 Kbytes of on-chip Flash for Bootloader
• 2 Kbytes of on-chip EEPROM
• 14 interrupt sources with 4 priority level
• Three 16-bit timer/counters
• Full duplex Enhanced UART
• High speed architecture
•
•
20 microsecond conversion time
Two conversion modes
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Power control modes:
•
Idle mode
•
•
40 MHz in standard mode
20 MHz in X2 mode (6 clocks/machine cycle)
•
Power down mode
• Power supply: 4.5V to 5.5V
• Temperature range: Industrial (-40 to +85C)
• Five ports: 32 + 2 digital I/O lines
• Programmable Counter Array with 5 16-bit channels :
• Packages: VQFP44 1,4 mm, PLCC44, CA-BGA64*
* on request
•
High-speed output
•
Compare / Capture
Rev.A - 11-Apr-01
1
Preliminary
T89C51AC2
3. Block Diagram
XTAL1
RAM
256x8
Flash Boot
32kx loader PROM
2kx8 2kx8
EE
XRAM
1kx8
PCA
UART
Timer2
XTAL2
8
ALE
C51
CORE
IB-bus
PSEN
CPU
EA
Timer 0
Timer 1
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 3
INT
Ctrl
10 bit
ADC
Watch
Dog
RD
Port 2
Port 4
WR
(1): 8 analog Inputs / 8 Digital I/O
(2): 2-bit I/O Port
2
Rev.A - 11-Apr-01
Preliminary
T89C51AC2
4. Pin Configuration
P1.4 / AN4 / CEX1
P1.5 / AN5 / CEX2
P1.6 / AN6 / CEX3
P1.7 / AN7 / CEX4 10
EA 11
7
8
9
39 ALE
38 PSEN
37 P0.7 / AD7
36 P0.6 / AD6
35 P0.5 / AD5
34 P0.4 / AD4
33 P0.3 / AD3
32 P0.2 / AD2
31 P0.1 / AD1
30 P0.0 / AD0
29 P2.0 / A8
P3.0 / RxD 12
P3.1 / TxD 13
P3.2 / INT0 14
P3.3 / INT1 15
P3.4 / T0 16
PLCC44
P3.5 / T1 17
44 43 42 41 40 39 38 37 36 35 34
P1.4 / AN4 / CEX1
P1.5 / AN5 / CEX2
P1.6 / AN6 / CEX3
P1.7 / AN7 / CEX4
EA
33
32
31
ALE
1
2
3
4
5
6
7
8
PSEN
P0.7 / AD7
P0.6 / AD6
P0.5 / AD5
P0.4 /AD4
P0.3 /AD3
P0.2 /AD2
P0.1 /AD1
P0.0 /AD0
P2.0 / A8
30
29
28
27
26
25
24
23
VQFP44
P3.0 / RxD
P3.1 / TxD
P3.2 / INT0
9
10
11
P3.3 / INT1
P3.4 / T0
P3.5 / T1
12 13 14 15 16 17 18 19 20 21 22
Rev.A - 11-Apr-01
3
Preliminary
T89C51AC2
Table 1. Pin Description
Pin Number
Pin Name
Type
Description
PLCC44 VQFP44
P0.0-P0.7
30-37
24-31
I/O
Port 0:
Port 0 is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to
them float, and in this state can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external Program and Data
Memory. In this application it uses strong internal pull-ups when emitting 1’s. Port 0 also
outputs the code bytes during program validation. External pull-ups are required during
program verification. In the T89C51AC2 Port 0 can sink or source 5mA. It can drive
CMOS inputs without external pull-ups.
P1.0-P1.7
3-10
41-44, 1-4
I/O
Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used
for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port
1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and
can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally
will be the source of current (IIL, on the datasheet) because of the internal pull-ups. Port
1 pins are assigned to be used as analog inputs via the ADCCF register.
As a secondary digital function, port 1 contains the Timer 2 external trigger and clock
input; the PCA external clock input and the PCA module I/O.
Port 1 receives the low-order address byte during FLASH programming and program
verification. In the T89C51AC2 Port 1 can sink or source 5mA. It can drive CMOS inputs
without external pull-ups.
3
4
41
42
43
44
1
I/O
I
P1.0 : Input / Output
AN0 : Analog input channel 0
T2 : External clock input for Timer/counter2
P1.1 : Input / Output
I
I/O
I
AN1 : Analog input channel 1
T2EX : Trigger input for Timer/counter2
P1.2 : Input / Output
I
5
I/O
I
AN2 : Analog input channel 2
ECI : PCA external clock input
P1.3 : Input / Output
I
6
I/O
I
AN3 : Analog input channel 3
CEX0 : PCA module 0 Entry of input/PWM output
P1.4 : Input / Output
O
I/O
I
7
AN4 : Analog input channel 4
CEX1 : PCA module 1 Entry of input/PWM output
P1.5 : Input / Output
O
I/O
I
8
2
AN5 : Analog input channel 5
CEX2 : PCA module 2 Entry of input/PWM output
P1.6 : Input / Output
O
I/O
I
9
3
AN6 : Analog input channel 6
CEX3 : PCA module 3 Entry of input/PWM output
P1.7 : Input / Output
O
I/O
I
10
4
AN7 : Analog input channel 7
CEX4 : PCA module 4 Entry of input/PWM output
O
4
Rev.A - 11-Apr-01
Preliminary
T89C51AC2
Pin Number
Pin Name
Type
Description
PLCC44 VQFP44
P2.0:7
29-22
23-16
I/O
Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s
written to them are pulled high by the internal pull-ups and can be used as inputs in this
state. As inputs, Port 2 pins that are being pulled low externally will be a source of current
(IIL, on the datasheet) because of the internal pull-ups. Port 2 emits the high-order address
byte during accesses to the external Program Memory and during accesses to external Data
Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong
internal pullups when emitting 1’s. During accesses to external Data Memory that use 8
bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register.
It also receives high-order addresses and control signals during program validation.
In the T89C51AC2 Port 2 can sink or source 5mA. It can drive CMOS inputs without
external pull-ups.
P3.0 - P3.7
12-19
6-13
I/O
Port 3:
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s
written to them are pulled high by the internal pull-up transistors and can be used as inputs
in this state. As inputs, Port 3 pins that are being pulled low externally will be a source
of current (IIL, on the datasheet) because of the internal pull-ups.
The output latch corresponding to a secondary function must be programmed to one for
that function to operate (except for TxD and WR).
In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without
external pull-ups.
The secondary functions are assigned to the pins of port 3 as follows:
12
13
6
7
I/O
I
P3.0 : Input / Output
Rxd :
Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
I/O
O
P3.1 : Input / Output
Txd :
Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
14
15
16
17
18
8
I/O
I
P3.2 : Input / Output
INT0: External interrupt 0 input / timer 0 gate control input
P3.3 : Input / Output
9
I/O
I
INT1: External interrupt 1 input / timer 1 gate control input
P3.4 : Input / Output
10
11
12
I/O
I
T0: Timer 0 counter input
P3.5 : Input / Output
I/O
I
T1: Timer 1 counter input
P3.6 : Input / Output
I/O
O
WR:
External Data Memory write strobe; latches the data byte from port 0 into the external
data memory
19
13
I/O
O
P3.7 : Input / Output
RD:
External Data Memory read strobe; Enables the external data memory. In the T89C51AC2
Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.
Port 4:
Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s
written to them are pulled high by the internal pull-ups and can be used as inputs in
this state. As inputs, Port 4 pins that are being pulled low externally will be a source
of current (IIL, on the datasheet) because of the internal pull-up transistor.
P4.0-P4.1
I/O
Rev.A - 11-Apr-01
5
Preliminary
T89C51AC2
Pin Number
Pin Name
Type
Description
PLCC44 VQFP44
Reset:
A high level on this pin during two machine cycles while the oscillator is running
resets the device. An internal pull-down resistor to VSS permits power-on reset using
only an external capacitor to VCC.
RESET
ALE
44
38
I/O
ALE:
An Address Latch Enable output for latching the low byte of the address during
accesses to the external memory. The ALE is activated every 1/6 oscillator periods
(1/3 in X2 mode) except during an external data memory access. When instructions
are executed from an internal FLASH (EA = 1), ALE generation can be disabled by
the software.
39
33
O
O
PSEN:
The Program Store Enable output is a control signal that enables the external program
memory of the bus during external fetch operations. It is activated twice each machine
cycle during fetches from the external program memory. (However, when executing
outside of the external program memory two activations of PSEN are skipped during
each access to the external Data memory). The PSEN is not activated during fetches
from the internal data memory.
PSEN
38
32
EA:
When External Access is held at the high level, instructions are fetched from the
internal FLASH when the program counter is less then 8000H. When held at the low
level, T89C51AC2 fetches all instructions from the external program memory.
EA
11
41
5
I
I
XTAL1:
Input of the inverting oscillator amplifier and input of the internal clock generator
circuits.
XTAL1
35
To drive the device from an external clock source, XTAL1 should be driven, while
XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle
of 50% should be maintained.
XTAL2
VAGND
VCC
40
1
34
39
36
37
40
O
I
XTAL2: Output from the inverting oscillator amplifier.
Reference Ground for ADC
42
43
2
I
Supply voltage during normal, idle, and power-down operation.
Circuit ground potential.
VSS
I
VAREF
I
Reference Voltage for ADC
6
Rev.A - 11-Apr-01
Preliminary
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