DG541DY [TEMIC]

Wideband/Video “T” Switches; 宽带/视频“ T”开关
DG541DY
型号: DG541DY
厂家: TEMIC SEMICONDUCTORS    TEMIC SEMICONDUCTORS
描述:

Wideband/Video “T” Switches
宽带/视频“ T”开关

复用器 开关 复用器或开关 信号电路 光电二极管
文件: 总10页 (文件大小:156K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DG540/541/542  
Wideband/Video “T” Switches  
Features  
Benefits  
Applications  
D Wide Bandwidth: 500 MHz  
D Flat Frequency Response  
D RF and Video Switching  
D Low Crosstalk: –85 dB  
D High Color Fidelity  
D RGB Switching  
D High Off-Isolation: –80 dB @ 5 MHz D Low Insertion Loss  
D Local and Wide Area Networks  
D Video Routing  
D “T” Switch Configuration  
D TTL Logic Compatible  
D Fast Switching—tON: 45 ns  
D Low rDS(on): 30 W  
D Improved System Performance  
D Reduced Board Space  
D Fast Data Acquisition  
D ATE  
D Reduced Power Consumption  
D Improved Data Throughput  
D Radar/FLR Systems  
D Video Multiplexing  
Description  
The DG540/541/542 are high performance monolithic To achieve TTL compatibility, low channel capacitances  
wideband/video switches designed for switching RF, video and fast switching times, the DG540 family is built on the  
and digital signals. By utilizing a “T” switch configuration Siliconix proprietary D/CMOS process. Each switch  
on each channel, these devices achieve exceptionally low conducts equally well in both directions when on.  
crosstalk and high off-isolation. The crosstalk and  
off-isolation of the DG540 are further improved by the  
introduction of extra GND pins between signal pins.  
Functional Block Diagrams and Pin Configurations  
DG540  
Dual-In-Line  
DG540  
PLCC  
IN  
D
IN  
D
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
1
2
2
3
2
1 20 19  
Truth Table  
GND  
GND  
3
Logic  
Switch  
4
5
6
7
8
18  
17  
16  
15  
14  
S
GND  
1
S
S
2
4
1
V–  
S
2
0
1
OFF  
ON  
V–  
V+  
5
GND  
V+  
GND  
GND  
6
S
4
GND  
Logic “0” v 0.8 V  
Logic “1” w 2 V  
GND  
S
3
S
S
3
7
4
GND  
GND  
8
9
10 11 12 13  
Top View  
D
D
9
4
3
IN  
IN  
10  
4
3
Top View  
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70055.  
Siliconix  
1
S-53694—Rev. E, 28-May-97  
DG540/541/542  
Functional Block Diagrams and Pin Configurations (Cont’d)  
DG541  
DualĆInĆLine and SOIC  
DG542  
Dual-In-Line and SOIC  
IN  
D
IN  
2
1
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
IN  
D
S
IN  
2
1
1
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
D
2
D
2
GND  
GND  
S
2
S
S
2
1
V–  
V+  
V–  
V+  
GND  
GND  
S
S
3
4
S
D
S
3
4
4
4
GND  
GND  
D
3
D
D
3
4
IN  
IN  
3
Top View  
Top View  
Truth Table  
-
DG541  
Truth Table  
-
DG542  
Logic  
Switch  
Logic  
SW1, SW  
2
SW3, SW  
4
0
1
OFF  
ON  
0
1
OFF  
ON  
ON  
OFF  
Logic “0” v 0.8 V  
Logic “1” w 2 V  
Logic “0” v 0.8 V  
Logic “1” w 2 V  
Ordering Information  
Temp Range  
DG540  
Package  
Part Number  
20-Pin Plastic DIP  
20-Pin PLCC  
DG540DJ  
–40t
o
to
8
5
85_C  
DG540DN  
DG540AP  
–55 to 125_C  
20-Pin Sidebraze  
DG540AP/883  
DG541  
16-Pin Plastic DIP  
DG541DJ  
–40 to 85_C  
16-Pin Narrow SOIC  
DG541DY  
DG541AP  
–55 to 125_C  
16-Pin Sidebraze  
DG541AP/883  
DG542  
16-Pin Plastic DIP  
DG542DJ  
–40 to 85_C  
16-Pin Narrow SOIC  
DG542DY  
DG542AP  
–55 to 125_C  
16-Pin Sidebraze  
DG542AP/883  
2
Siliconix  
S-53694—Rev. E, 28-May-97  
DG540/541/542  
Absolute Maximum Ratings  
V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V  
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 21 V  
V– to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –19 V to +0.3 V  
Power Dissipation (Package)a  
b
16-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW  
c
20-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW  
d
16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 mW  
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V+) +0.3 V  
or 20 mA, whichever occurs first  
d
20-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW  
e
16-, 20-Pin Sidebraze DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW  
V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –0.3 V to (V–) +14 V  
S
D
or 20 mA, whichever occurs first  
Notes:  
a. All leads welded or soldered to PC Board.  
b. Derate 6.5 mW/_C above 25_C  
c. Derate 7 mW/_C above 25_C  
d. Derate 10 mW/_C above 75_C  
e. Derate 12 mW/_C above 75_C  
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . 20 mA  
Current, S or D (Pulsed 1 ms, 10% duty cycle max) . . . . . . . . . . 40 mA  
Storage Temperature  
(AP Suffix) . . . . . . . . . . . . . . –65 to 150_C  
(DJ, DN, DY Suffixes) . . . . . –65 to 125_C  
Schematic Diagram (Typical Channel)  
V+  
GND  
V
REF  
S
+
IN  
D
V–  
Figure 1.  
Siliconix  
S-53694—Rev. E, 28-May-97  
3
DG540/541/542  
Specificationsa  
Test Conditions  
Unless Specified  
A Suffix  
D Suffixes  
–55 to 125_C  
–40 to 85_C  
V+ = 15 V, V– = –3 V  
f
V
= 2 V, V  
= 0.8 V  
Parameter  
Analog Switch  
Symbol  
Tempb Typc Mind Maxd Mind Maxd Unit  
INH  
INL  
Analog Signal Range  
V
V– = –5 V, V+ = 12 V  
Full  
–5  
5
–5  
5
V
ANALOG  
Drain-Source  
On-Resistance  
Room  
Full  
30  
60  
100  
60  
75  
r
DS(on)  
I
= –10 mA, V = 0 V  
W
S
D
r
Match  
Dr  
Room  
2
6
6
DS(on)  
DS(on)  
S(off)  
Source Off  
Leakage Current  
Room  
Full  
–0.05  
–10  
–500  
10  
500  
–10  
–100  
10  
100  
I
I
V
= 0 V, V = 10 V  
S
S
D
Drain Off  
Leakage Current  
Room  
Full  
–0.05  
–0.05  
–10  
–500  
10  
500  
–10  
–100  
10  
100  
V
= 10 V, V = 0 V  
nA  
D(off)  
D
Channel On  
Leakage Current  
Room  
Full  
–10  
–1000  
10  
1000  
–10  
–100  
10  
100  
I
V
= V = 0 V  
D(on)  
S
D
Digital Control  
Input Voltage High  
Input Voltage Low  
V
Full  
Full  
2
2
INH  
V
V
0.8  
0.8  
INL  
Room  
Full  
0.05  
–1  
–20  
1
20  
–1  
–20  
1
20  
Input Current  
I
V
= GND or V+  
IN  
mA  
IN  
Dynamic Characteristics  
e
On State Input Capacitance  
C
V
= V = 0 V  
Room  
Room  
Room  
Room  
14  
2
20  
4
20  
4
S(on)  
S(off)  
D(off)  
S
D
e
pF  
Off State Input Capacitance  
C
V
= 0 V  
= 0 V  
S
e
Off State Output Capacitance  
Bandwidth  
C
V
2
4
4
D
BW  
R
= 50 W, See Figure 5  
500  
45  
MHz  
L
DG540  
DG541  
Room  
Full  
70  
130  
70  
130  
Turn On Time  
Turn Off Time  
t
ON  
Room  
Full  
55  
20  
25  
100  
160  
100  
160  
R
C
= 1 kW  
= 35 pF  
50% to 90%  
See Figure 2  
L
DG542  
L
ns  
DG540  
DG541  
Room  
Full  
50  
85  
50  
85  
t
OFF  
Room  
Full  
60  
85  
60  
85  
DG542  
C
= 1000 pF, V = 0 V  
See Figure 3  
L
S
Charge Injection  
Off Isolation  
Q
Room  
–25  
pC  
dB  
DG540  
DG541  
DG542  
Room  
Room  
Room  
–80  
–60  
–75  
R
R
= 75 W  
= 75 W  
IN  
L
OIRR  
f = 5 MHz  
See Figure 4  
R
= 10 W, R = 75 W  
L
IN  
All Hostile Crosstalk  
Power Supplies  
X
Room  
–85  
TALK(AH)  
f = 5 MHz, See Figure 6  
Room  
Full  
3.5  
6
9
6
9
Positive Supply Current  
I+  
I–  
All Channels On or Off  
mA  
Room  
Full  
–3.2  
–6  
–9  
–6  
–9  
Negative Supply Current  
Notes:  
a. Refer to PROCESS OPTION FLOWCHART.  
b. Room = 25_C, Full = as determined by the operating temperature suffix.  
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.  
e. Guaranteed by design, not subject to production test.  
f.  
V
= input voltage to perform proper function.  
IN  
4
Siliconix  
S-53694—Rev. E, 28-May-97  
DG540/541/542  
Typical Characteristics  
Supply Curent vs. Temperature  
ID(off), IS(off) vs. Temperature  
6
100 nA  
10 nA  
1 nA  
5
4
I+  
3
2
1
100 pA  
10 pA  
I
GND  
0
–1  
–2  
–3  
–4  
–5  
I–  
1 pA  
0.1 pA  
–55 –35 –15  
5
25 45 65 85 105 125  
–55  
–25  
0
25  
50  
75  
100 125  
Temperature (_C)  
Temperature (_C)  
r
DS(on) vs. Drain Voltage  
V+ Constant  
V– Constant  
160  
140  
120  
100  
80  
42  
40  
38  
36  
34  
32  
30  
20  
18  
42  
40  
38  
36  
34  
32  
30  
20  
18  
V+ = 10 V  
V+ = 15 V  
V– = –3 V  
125_C  
V– = –5 V  
V+ = 12 V  
V+ = 15 V  
25_C  
V– = –3 V  
60  
–55_C  
40  
20  
V– = –1 V  
0
–3  
–1  
1
3
5
7
9
11  
–5 –4 –3 –2 –1  
0
10 11 12 13 14 15 16  
V+ – Positive Supply (V)  
V
– Drain Voltage (V)  
V– – Negative Supply (V)  
D
On Capacitance  
Off Isolation  
22  
20  
18  
16  
14  
12  
10  
8
–110  
–100  
–90  
–80  
–70  
–60  
–50  
–40  
–30  
–20  
–10  
DG540  
DG542  
DG541  
6
10  
100  
1
0
2
4
6
8
10  
12  
14  
V
– Drain Voltage (V)  
f – Frequency (MHz)  
D
Siliconix  
S-53694—Rev. E, 28-May-97  
5
DG540/541/542  
Typical Characteristics (Cont’d)  
Off Isolation vs. Frequency and Load Resistance  
All Hostile Crosstalk  
(DG540)  
–100  
–110  
–100  
–90  
R
L
= 75 W  
DG540  
–80  
–70  
–60  
–50  
–40  
–30  
–20  
–10  
0
–90  
–80  
–70  
–60  
–50  
–40  
–30  
–20  
–10  
180 W  
1 kW  
DG542  
10 kW  
DG541  
10  
100  
1
10  
100  
1
f – Frequency (MHz)  
f – Frequency (MHz)  
Switching Times vs. Temperature  
(DG540/541)  
Charge Injection vs. VS  
40  
30  
90  
80  
70  
60  
50  
40  
30  
20  
20  
10  
t
ON  
0
–10  
–20  
–30  
–40  
t
OFF  
C
L
= 1000 pF  
10  
0
–3 –2 –1  
0
1
2
3
4
5
6
7
8
–55 –25  
0
25  
50  
75  
100 125  
V
– Source Voltage (V)  
Temperature (_C)  
S
Switching and Break-Before-Make Time  
vs. Temperature (DG542)  
Operating Supply Voltage Range  
20  
18  
16  
14  
12  
10  
90  
80  
t
ON  
70  
60  
50  
40  
30  
20  
t
BBM  
Operating  
Voltage  
Area  
t
OFF  
10  
0
–55 –25  
0
25  
50  
75  
100 125  
0
–1  
–2  
–3  
–4  
–5  
–6  
Temperature (_C)  
V– – Negative Supply (V)  
6
Siliconix  
S-53694—Rev. E, 28-May-97  
DG540/541/542  
Test Circuits  
+15 V  
t <20 ns  
t <20 ns  
f
r
3 V  
V+  
Logic  
Input  
50%  
S
D
3
V
V
O
IN  
C
35 pF  
L
Switch  
Input  
R
1 kW  
L
V
S
GND  
V–  
90%  
Switch  
Output  
0
–3 V  
(includes fixture and stray capacitance)  
t
t
OFF  
ON  
C
L
R
L
V
= V  
S
O
R
L
+ r  
DS(on)  
Figure 2. Switching Time  
+15 V  
DV  
O
V+  
R
g
V
O
S
D
V
O
IN  
GND  
C
V
L
g
1000 pF  
3 V  
IN  
ON  
OFF  
ON  
X
V–  
DV = measured voltage error due to charge injection  
–3 V  
O
The charge injection in coulombs is DQ = C x DV  
L
O
Figure 3. Charge Injection  
+15 V  
+15 V  
C
C
V+  
V+  
V
R
V
O
O
S
D
V
S
D
S
V
S
R = 50 W  
g
R = 75 W  
g
R
L
L
IN  
75 W  
IN  
50 W  
0 V, 2.4 V  
0 V, 2.4 V  
GND  
V–  
GND  
V–  
C
C
–3 V  
–3 V  
V
S
Off Isolation = 20 log  
C = RF Bypass  
V
O
Figure 4. Off Isolation  
Figure 5. Bandwidth  
Siliconix  
S-53694—Rev. E, 28-May-97  
7
DG540/541/542  
Test Circuits (Cont’d)  
C
+15 V  
V+  
S
1
D
1
V
O
R
75 W  
L
10 W  
2.4 V  
IN  
X
S
D
D
2
2
3
S
3
R
L
S
4
D
4
R
L
GND  
V–  
R
L
C
–15 V  
VOUT  
VIN  
XTALK(AH) + 20 log10  
Figure 6. All Hostile Crosstalk  
Applications  
an attenuation effect on the analog signal – which is  
frequency dependent (like an RC low-pass filter). The  
–3-dB bandwidth of the DG540 is typically 500 MHz (into  
50 W). This measured figure of 500 MHz illustrates that  
the switch channel can not be represented by a two stage RC  
combination. The on capacitance of the channel is  
distributed along the on-resistance, and hence becomes a  
more complex multi stage network of R’s and C’s making  
Device Description  
The DG540/541/542 family of wideband switches offers  
true bidirectional switching of high frequency analog or  
digital signals with minimum signal crosstalk, low insertion  
loss, and negligible non-linearity distortion and group  
delay.  
Built on the Siliconix D/CMOS process, these “T” switches  
provide excellent off-isolation with a bandwidth of around  
500 MHz (350 MHz for DG541). Silicon-gate D/CMOS  
processing also yields fast switching speeds.  
up the total r  
and C  
. See Application Note AN502  
DS(on)  
S(on)  
for more details.  
An on-chip regulator circuit maintains TTL input  
compatibility over the whole operating supply voltage  
range, easing control logic interfacing.  
Off-Isolation and Crosstalk  
Off-isolation and crosstalk are affected by the load  
resistance and parasitic inter-electrode capacitances.  
Higher off-isolation is achieved with lower values of R .  
Circuit layout is facilitated by the interchangeability of  
source and drain terminals.  
L
However, low values of R increase insertion loss requiring  
L
gain adjustments down the line. Stray capacitances, even a  
fraction of 1 pF, can cause a large crosstalk increase. Good  
Frequency Response  
A single switch on-channel exhibits both resistance layout and ground shielding techniques can considerably  
[r ] and capacitance [C ]. This RC combination has improve your ac circuit performance.  
DS(on)  
S(on)  
8
Siliconix  
S-53694—Rev. E, 28-May-97  
DG540/541/542  
Applications (Cont’d)  
3. Capacitors  
characteristics  
should  
-
have  
good  
high  
frequency  
Power Supplies  
tantalum bead and/or monolithic  
A useful feature of the DG54X family is its power supply  
flexibility. It can be operated from a single positive supply  
(V+) if required (V– connected to ground).  
ceramic types are adequate.  
Suitable decoupling capacitors are m1FĆ  
to 10Ć  
tantalum bead, plus 10Ć to 100ĆnF ceramic.  
Note that the analog signal must not exceed V– by more  
than –0.3 V to prevent forward biasing the substrate p-n  
junction. The use of a V– supply has a number of  
advantages:  
+15 V  
+
C
1
C
2
1. It allows flexibility in analog signal handling, i.e.,  
with V-  
=
-5  
V
and V+ ="51Ć2V Va;c up to  
V+  
signals can be controlled.  
S
D
D
D
D
1
1
2
3
4
2. The value of on capacitance ] [Cmay be  
S(on)  
reduced.  
A
property known as `the bodyĆeffect' on  
S
2
the DMOS  
switch  
devices  
causes  
various  
DG540  
parametric effects to occur. One of these effects is  
S
3
the  
reduction  
in  
C
for  
an  
increasing  
V
S(on)  
S
body-source. Note, however, that to increase V-4  
normally requires V+ to be reduced (since V+ to  
GNDs  
V-  
=
21  
V
max.). Reduction in V+ causes an  
hence compromise has to be  
achieved. It is also useful to note that optimum  
V–  
increase in  
r
,
a
DS(on)  
C
1
C
2
C = 10 mF Tantalum  
1
video linearity performance (e.g., differential phase  
+
C = 0.1 mF Ceramic  
2
and gain) occurs when V- is around -3 V.  
–3 V  
3. V- eliminates the need to bias the analog signal  
using  
potential  
dividers  
and  
large  
coupling  
capacitors.  
Figure 7. Supply Decoupling  
Decoupling  
Board Layout  
PCB layout rules for good high frequency performance  
must be observed to achieve the performance boasted by the  
DG540. Some tips for minimizing stray effects are:  
It is an established RF design practice to incorporate  
sufficient bypass capacitors in the circuit to decouple the  
power supplies to all active devices in the circuit. The  
dynamic performance of the DG54X is adversely affected  
by poor decoupling of power supply pins. Also, of even  
more significance, since the substrate of the device is  
connected to the negative supply, adequate decoupling of  
this pin is essential.  
1. Use extensive ground planes on double sided PCB,  
separating adjacent signal paths. Multilayer PCB is  
even better.  
2. Keep signal paths as short as practically possible,  
with all channel paths of near equal length.  
Rules:  
3. Careful arrangement of ground connections is also  
1. Decoupling capacitors should be incorporated on  
very important. Star connected system grounds  
(See Figure 7.)  
eliminate signal current flowing through ground  
all power supply pins (V+, V-).  
2. They should be mounted as close as possible patoth thpearasitic resistance from coupling between  
device pins. channels.  
Siliconix  
S-53694—Rev. E, 28-May-97  
9
DG540/541/542  
Applications (Cont’d)  
Figure 8 shows a 4-channel video multiplexer using a DG540.  
+15 V  
V+  
CH  
1
CH  
2
Si582  
+
75 W  
CH  
75 W  
3
A = 2  
75 W  
CH  
4
DIS  
250 W  
75 W  
DG540  
V–  
250 W  
75 W  
–3 V  
TTL Channel Select  
Figure 8. 4 by 1 Video Multiplexing Using the DG540  
Figure 9 shows an RGB selector switch using two DG542s.  
+15 V  
V+  
R
1
Red Out  
75 W  
75 W  
R
2
75 W  
75 W  
G
1
Green Out  
G
2
DG542  
V–  
–3 V  
+15 V  
Si584  
V+  
B
1
Blue Out  
Sync Out  
75 W  
75 W  
B
2
75 W  
75 W  
Sync 1  
Sync 2  
DG542  
RGB Source Select  
V–  
–3 V  
Figure 9. RGB Selector Using Two DG542s  
10  
Siliconix  
S-53694—Rev. E, 28-May-97  

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