CLDP-67202AV-35 [TEMIC]
FIFO, 1KX9, 35ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28;
| 型号： | CLDP-67202AV-35 |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | FIFO, 1KX9, 35ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28 先进先出芯片 CD |
| 文件： | 总17页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M67201A/M67202A
512 ꢀ 9 & 1 K ꢀ 9 CMOS Parallel FIFO
Introduction
The M67201A/202A implement a first-in first-out Using an array of eigh transistors (8 T) memory cell and
algorithm, featuring asynchronous read/write operations. fabricated with the state of the art 1.0 µm lithography
The FULL and EMPTY flags prevent data overflow and named SCMOS, the M 67201A/202A combine an
underflow. The Expansion logic allows unlimited extremely low standby supply current (typ = 1.0
µA) with
expansion in word size and depth with no timing fast access time at 25 ns over the full temperature range.
a
penalties. Twin address pointers automatically generate All versions offer battery backup data retention capability
internal read and write addresses, and no external address with a typical power consumption at less than 5 µW.
information are required for the TEMIC FIFOs. Address
pointers are automatically incremented with the write pin
For military/space applications that demand superior
levels
of
performance
and
reliability
the
and read pin. The 9 bits wide data are used in data
communications applications where a parity bit for error
checking is necessary. The Retransmit pin reset the Read
pointer to zero without affecting the write pointer. This is
very useful for retransmitting data when an error is
detected in the system.
M 67201A/202A is processed according to the methods
of the latest revision of the MIL STD 883 (class B or S)
and/or ESA SCC 9000.
Features
D First-in first-out dual port memory
D 512 × 9 organisation (M 67201A)
D 1024 × 9 organisation (M 67202A)
D Fast access time
D Asynchronous read/write operations
D Empty, full and half flags in single device mode
D Retransmit capability
D Bi-directional applications
20*, 25, 35, 45, 55 ns, commercial, industrial and
automotive
D Battery back-up operation : 2 V data retention
D TTL compatible
20*, 25, 30, 40, 50 ns, military
D Wide temperature range :
D Single 5 V ± 10 % Power Supply (1)
D High performance SCMOS technology
– 55°C to + 125°C
(1) 3.3 V versions are also available. Please consult sales.
D 67201AL/202AL low power 67201AV/202AV very low
power
D Fully expandable by word width or depth
* Preview. Please Consult Sales.
MATRA MHS
1
Rev. D (11 April. 97)
M67201A/M67202A
Interface
Block Diagram
Pin Configuration
SO plastic 28 pin 300 mils(*)
DIL plastic 28 pin 300 mils
DIL ceramic 28 pin 300 mils
FP 28 pin 400 mils (Preview)
32 pin LCC and PLCC
SO/DIL (top view)
LCC (top view)
INDEX
W
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
I
8
I
3
I
2
I
1
I
0
2
I
I
I
I
4
4
3
2
32 31 30
1
I
I
I
5
6
7
8
9
29
I
I
3
2
1
0
6
5
6
7
28
27
26
25
24
23
22
21
4
7
NC
5
XI
FL/RT
RS
6
FL/RT
RS
XI
7
FF
FF
8
EF
10
11
12
13
Q
Q
EF
0
1
Q
9
XO/HF
XO/HF
0
Q
10
11
12
13
14
Q
NC
Q
1
7
7
Q
Q
Q
Q
2
6
2
6
14 15 16 17 18 19 20
Q
Q
Q
Q
R
3
8
5
4
GND
(*) On request only
.
2
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Pin Names
NAMES
DESCRIPTION
NAMES
FF
DESCRIPTION
I0–8
Q0–8
W
Inputs
Full Flag
Outputs
XO/HF
XI
Expansion Out/Half–Full Flag
Expansion IN
Write Enable
Read Enable
Reset
R
FL/RT
VCC
First Load/Retransmit
Power Supply
RS
EF
Empty Flag
GND
Ground
Signal Description
pointers to the first location. A reset is required after
power-up before a write operation can be enabled. Both
Data In (I0 - I8)
Data inputs for 9 - bit data
the Read Enable (R) and Write Enable (W
in the high state during the period shown in figure 1 (i.e.
before the rising edge of RS) and should not change
) inputs must be
t
RSS
RESET (RS)
until t
after the rising edge of RS. The Half-Full flag
RSR
(HF will be reset to high after Reset (RS).
Reset occurs whenever the Reset (RS) input is taken to a
low state. Reset returns both internal read and write
Figure 1. Reset.
Notes
:
1. EF, FF and HF may change status during reset, but flags will be valid at t
.
RSC
2. W and R = VIH around the rising edge of RS.
or equal to half of the total available memory in the
device. The Half-Full Flag (HF) is then reset by the rising
edge of the read operation.
Write Enable (W)
A write cycle is initiated on the falling edge of this input
if the Full Flag (FF) is not set. Data set-up and hold times
must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the
Ram array, regardless of any current read operation.
To prevent data overflow, the Full Flag (FF) will go low,
inhibiting further write operations. On completion of a
valid read operation, the Full Flag (FF) will go high after
TRFF, allowing a valid write to begin. When the FIFO
Once half of the memory is filled, and during the falling
edge of the next write operation, the Half-Full Flag (HF)
will be set to low and remain in this state until the
difference between the write and read pointers is less than
stack is full, the internal write pointer is blocked from W
so that external changes to W will have no effect on the
full FIFO stack.
,
MATRA MHS
3
Rev. D (11 April. 97)
M67201A/M67202A
Read Enable (R)
Full Flag (FF)
A read cycle is initiated on the falling edge of the Read
Enable (R) provided that the Empty Flag (EF) is not set.
The data is accessed on a first in/first out basis, not with
standing any current write operations. After Read Enable
(R) goes high, the Data Outputs (Q0 - Q8) will return to
a high impedance state until the next Read operation.
When all the data in the FIFO stack has been read, the
Empty Flag (EF) will go low, allowing the “final” read
cycle, but inhibiting further read operations whilst the
data outputs remain in a high impedance state. Once a
valid write operation has been completed, the Empty Flag
(EF) will go high after tWEF and a valid read may then
be initiated. When the FIFO stack is empty, the internal
read pointer is blocked from R, so that external changes
The Full Flag (FF) will go low, inhibiting further write
operations when the write pointer is one location less than
the read pointer, indicating that the device is full. If the
read pointer is not moved after Reset (RS), the Full Flag
(FF) will go low after 512/1024 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read
operations when the read pointer is equal to the write
pointer, indicating that the device is empty.
Expansion Out/Half-full Flag (XO/HF)
to
R will have no effect on the empty FIFO stack.
This is a dual-purpose output. In the single device mode,
when Expansion In (XI) is connected to ground, this
output acts as an indication of a half-full memory.
First Load/Retransmit (FL/RT)
This is a dual-purpose input. In the Depth Expansion
Mode, this pin is connected to ground to indicate that it
is the first loaded (see Operating Modes). In the Single
Device Mode, this pin acts as the retransmit input. The
Single Device Mode is initiated by connecting the
Expansion In (XI) to ground.
After half the memory is filled and on the falling edge of
the next write operation, the Half-Full Flag (HF) will be
set to low and will remain set until the difference between
the write and read pointers is less than or equal to half of
the total memory of the device. The Half-Full Flag (HF)
is then reset by the rising edge of the read operation.
The M 67201A/202A can be made to retransmit data
when the Retransmit Enable Control (RT) input is pulsed
low. A retransmit operation will set the internal read point
to the first location and will not affect the write pointer.
Read Enable (R) and Write Enable (W) must be in the
high state during retransmit. The retransmit feature is
intended for use when a number of writes equals to or less
than the depth of the FIFO have occured since the last RS
cycle. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag
(HF), in accordance with the relative locations of the read
and write pointers.
In the Depth Expansion Mode, Expansion In (XI) is
connected to Expansion Out (XO) of the previous device.
This output acts as a signal to the next device in the Daisy
Chain by providing a pulse to the next device when the
previous device reaches the last memory location.
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high
impedance condition whenever Read (R) is in a high state.
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is
connected to GND to indicate an operation in the single
device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth
Expansion or Daisy Chain modes.
4
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Functional Description
Operating Modes
The M 67201A/202A is in a Single Device Configuration
when the Expansion In (XI) control input is grounded (see
Single Device Mode
A single M 67201A/202A may be used when the Figure 2). In this mode the Half-Full Flag (HF), which is
application requirements are for 512/1024 words or less. an active low output, is shared with Expansion Out (XO).
Figure 2. Block Diagram of Single 512 × 9 and 1024 × 9.
HF
(HALF–FULL FLAG)
(W)
9
(R)
Q
READ
WRITE
9
DATA
DATA
OUT
IN
(I)
M
67201A
67202A
(EF)
(RT)
EMPTY FLAG
RETRANSMIT
FULL FLAG (FF)
(RS)
RESET
EXPANSION IN (XI)
Status flags (EF, FF and HF) can be detected from any
device. Figure 3 demonstrates an 18-bit word width by
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the using two M 67201A/202A. Any word width can be
corresponding input control signals of multiple devices. attained by adding additional M 67201A/202A.
Figure 3. Block Diagram of 512 / 1024 × 18 FIFO Memory Used in Width Expansion Mode.
HF
HF
9
18
9
DATA (1)
IN
(R) READ
(EF) EMPTY FLAG
(RT) RETRANSMIT
WRITE
(W)
M
M
FULL FLAG
(FF)
67201A/202A
67201A/202A
RESET
(RS)
9
9
XI
XI
18
(Q)DATA
OUT
Note
:
3. Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width
expansion configuration. Do not connect any output control signals together.
MATRA MHS
5
Rev. D (11 April. 97)
M67201A/M67202A
Table 1 : Reset and retransmit
Single Device Configuration/Width Expansion Mode
INPUTS
INTERNAL STATUS
Read Pointer Write Pointer
OUTPUTS
MODE
RS
0
RT
X
XI
0
EF
0
FF
1
HF
1
Reset
Location Zero
Location Zero
Unchanged
Retransmit
Read/Write
1
0
0
Location Zero
X
X
X
(4)
(4)
1
1
0
Increment
Increment
X
X
X
Note : 4. Pointer will increment if flag is high.
Table 2 : Reset and First Load Truth Table
Depth Expansion/Compound Expansion Mode
INPUTS
INTERNAL STATUS
OUTPUTS
MODE
RS
0
FL
0
XI
(5)
(5)
(5)
Read Pointer
Write Pointer
Location Zero
Location Zero
X
EF
FF
1
Reset First Device
Reset All Other Devices
Read/Write
Location Zero
Location Zero
X
0
0
0
1
1
1
X
X
X
Note : 5. XI is connected to XO of previous device.
See fig. 5.
Depth Expansion (Daisy Chain) Mode
Compound Expansion Module
It is quite simple to apply the two expansion techniques
described above together to create large FIFO arrays (see
figure 5).
The M 67201A/202A can be easily adapted for
applications which require more than 512/1024 words.
Figure 4 demonstrates Depth Expansion using three
M 67201A/202A. Any depth can be achieved by adding
additional 67201A/202A.
Bidirectional Mode
The M 67201A/202A operate in the Depth Expansion
configuration if the following conditions are met :
Applications which require data buffering between two
systems (each system being capable of Read and Write
operations) can be created by coupling M 67201A/202A
as shown in figure 6. Care must be taken to ensure that the
appropriate flag is monitored by each system (i.e. FF is
monitored on the device on which W is in use ; EF is
monitored on the device on which R is in use). Both Depth
Expansion and Width Expansion may be used in this
mode.
1. The first device must be designated by connecting the
First Load (FL) control input to ground.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be
connected to the Expansion In (XI) pin of the next
device. See figure 4.
4. External logic is needed to generate a composite Full
Flag (FF) and Empty Flag (EF). This requires that all
EF’s and all FFs be ØRed (i.e. all must be set to
generate the correct composite FF or EF). See figure 4.
Data Flow - Through Modes
Two types of flow-through modes are permitted : a read
flow-through and a write flow-through mode. In the read
flow-through mode (figure 17) the FIFO stack allows a
5. The Retransmit (RT) function and Half-Full Flag (HF)
are not available in the Depth Expansion Mode.
6
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
single word to be read after one word has been written to In the write flow-through mode (figure 18), the FIFO
an empty FIFO stack. The data is enabled on the bus at stack allows a single word of data to be written
(tWEF + tA) ns after the leading edge of W which is immediately after a single word of data has been read
known as the first write edge and remains on the bus until from a full FIFO stack. The R line causes the FF to be
the R line is raised from low to high, after which the bus reset, but the W line, being low, causes it to be set again
will go into a three-state mode after tRHZ ns. The EF line in anticipation of a new data word. The new word is
will show a pulse indicating temporary reset and then will loaded into the FIFO stack on the leading edge of W. The
be set. In the interval in which R is low, more words may
W line must be toggled when FF is not set in order to write
be written to the FIFO stack (the subsequent writes after new data into the FIFO stack and to increment the write
the first write edge will reset the Empty Flag) ; however, pointer.
the same word (written on the first write edge) presented
to the output bus as the read pointer will not be
incremented if R is low. On toggling R, the remaining
words written to the FIFO will appear on the output bus
in accordance with the read cycle timings.
Figure 4. Block Diagram of 1536 × 9 / 3072 × 9 FIFO Memory (Depth expansion).
XO
W
R
M
FF
9
EF
FL
6
9
67201A
67202A
9
Q
V
CC
FULL
EMPTY
FF
9
EF
FL
M
67201A
67202A
M
EF
FL
FF
9
67201A
67202A
RS
XI
Figure 5. Compound FIFO Expansion.
Q
0
– Q
Q
Q
– Q
– Q
Q
Q
– Q
– Q
8
9
17
17
(N–8)
N
N
Q
0
– Q
8
9
(N–8)
M
67201A/202A
M 67201A/202A
M 67201A/202A
R
. W . RS
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
I
0
– I
I – I
9 17
8
I
– I
N
(N–8)
I
0
– I
I
9
– I
I – I
(N–8) N
8
17
Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.
7. For Flag detection see section on Width Expansion and Figure 3.
MATRA MHS
7
Rev. D (11 April. 97)
M67201A/M67202A
Figure 6. Bidirectional FIFO Mode.
R
B
W
A
M
EF
B
FF
A
HF
M
67201A
B
M 67202A
I
Q
B 0–8
A 0–8
SYSTEM A
SYSTEM B
Q
A 0–8
I
B 0–8
M
R
A
M 67201A
M 67202A
W
B
HF
A
FF
B
EF
A
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC – GND) . . . . . . . . . . . . . . . . . . – 0.3 V to 7.0 V
Input or Output voltage applied : . . . . (GND – 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65 °C to + 150 °C
OPERATING RANGE
Military
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
– 55 °C to + 125 °C
Vcc = 5 V ± 10 %
Vcc = 5 V ± 10 %
Vcc = 5 V ± 10 %
Vcc = 5 V ± 10 %
Industrial
– 40 °C to + 85 °C
Commercial
0 °C to + 70 °C
Automotive
– 40 °C to + 125 °C
DC Parameters
M 67201A
M 67202A
M 67201A
M 67202A
M 67201A
M 67202A
M 67201A
M 67202A
– 20 (Preview)
– 25
– 30
– 35
VAL-
UE
IND
IND
UNIT
IND
AUTO
COM MIL COM MIL
MIL
COM
AUTO
150
150
1.5
AUTO
140
140
1.5
I
Operating
supply current
V
L
V
L
V
L
140
140
1.5
1.5
40
125
125
1.5
1.5
40
140
140
1.5
1.5
80
120
120
1.5
1.5
40
140
140
1.5
1.5
80
mA
mA
mA
mA
µA
Max
Max
Max
Max
Max
Max
CCOP (8)
I
Standby
supply current
CCSB (9)
1.5
1.5
I
Power down
current
80
80
CCPD (10)
400
800
400
800
800
400
800
µA
8
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
DC Parameters (continued)
M 67201A
M 67202A
M 67201A
M 67202A
M 67201A
M 67202A
M 67201A
M 67202A
– 40
– 45
– 50
– 55
VAL-
UE
Parameter
Description Version
UNIT
IND
IND
MIL
COM
MIL
COM
AUTO
120
120
1.5
AUTO
100
100
1.5
I
Operating
supply current
V
L
V
L
V
L
120
120
1.5
1.5
80
80
80
100
100
1.5
1.5
80
70
70
mA
mA
mA
mA
µA
Max
Max
Max
Max
Max
Max
CCOP (8)
I
Standby
supply current
1.5
1.5
40
1.5
1.5
40
CCSB (9)
1.5
1.5
I
Power down
current
80
80
CCPD (10)
800
400
800
800
400
800
µA
Notes : 8. Icc measurements are made with outputs open. F = F max
9. R = W = RS = FL/RT = VIH.
10. All input = Vcc.
M 67201A/M67202A
PARAMETER
DESCRIPTION
UNIT VALUE
– 20/– 25/– 30/
– 35/– 40/– 45/– 50/– 55
ILI (11)
Input leakage current
± 1
± 10
0.8
2.2
0.4
2.4
8
± 1
± 10
0.8
2.2
0.4
2.4
8
µA
µA
V
Max
Max
Max
Min
Max
Min
Max
Max
ILO (12)
Output leakage current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input capacitance
Output capacitance
VIL (13)
VIH (13)
VOL (14)
VOH (14)
C IN (15)
C OUT (15)
V
V
V
pF
pF
8
8
Notes : 11. 0.4 ≤ Vin ≤ Vcc.
12. R = VIH, 0.4 ≤ VOUT ≤ VCC.
13. VIH max = Vcc + 0.3 V. VIL min = –0.3 V or –1 V pulse width 50 ns.
14. Vcc min, IOL = 8 mA, IOH = –2 mA.
15. This parameter is sampled and not tested 100 % – TA = 25 °C – F = 1 MHz.
Figure 7. Output Load.
AC Test Conditions
5 V
500
Input pulse levels
Input rise/Fall times
: Gnd to 3.0 V
Ω
: 5 ns
TO
OUTPUT
PIN
Input timing reference levels
Output reference levels
Output load
: 1.5 V
: 1.5 V
: See figure 7
30 pF*
333 Ω
*
includes jig and scope capacitance
MATRA MHS
9
Rev. D (11 April. 97)
M67201A/M67202A
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
COM, IND, COM, IND, MIL ONLY COM, IND,
SYMBOL SYMBOL
PARAMETER (18) (22)
MIL, AUTO MIL, AUTO
– 20 – 25
AUTO
– 35
UNIT
(16)
(17)
– 30
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE
PREVIEW
TRLRL
TRLQV
TRHRL
TRLRH
TRLQX
TWHQX
TRHQX
TRHQZ
tRC
Read cycle time
30
–
–
20
–
35
–
–
25
–
40
–
–
30
–
45
–
–
35
–
ns
ns
ns
ns
ns
ns
ns
ns
tA
Access time
tRR
Read recovery time
10
20
5
10
25
5
10
30
5
10
35
5
tRPW
tRLZ
tWLZ
tDV
Read pulse width (19)
Read low to data low Z (20)
Write low to data low Z (20, 21)
Data valid from read high
Read high to data high Z (20)
–
–
–
–
–
–
–
–
5
–
5
–
10
5
–
10
5
–
5
–
5
–
–
–
tRHZ
–
15
–
18
–
20
–
20
WRITE CYCLE
PREVIEW
TWLWL
TWLWH
TWHWL
TDVWH
TWHDX
tWC
Write cycle time
Write pulse width (19)
Write recovery time
Data set–up time
Data hold time
30
20
10
12
0
–
–
–
–
–
35
25
10
15
0
–
–
–
–
–
40
30
10
18
0
–
–
–
–
–
45
35
10
18
0
–
–
–
–
–
ns
ns
ns
ns
ns
tWPW
tWR
tDS
tDH
RESET CYCLE
PREVIEW
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
tRSC
Reset cycle time
30
20
20
10
–
–
–
–
35
25
25
10
–
–
–
–
40
30
30
10
–
–
–
–
45
35
35
10
–
–
–
–
ns
ns
ns
ns
tRS
Reset pulse width (19)
Reset set–up time
Reset recovery time
tRSS
tRSR
RETRANSMIT CYCLE
PREVIEW
TRTLWL
TRTLRTH
TWHRTH
TRTHWL
FLAGS
tRTC
tRT
Retransmit cycle time
30
20
20
10
–
–
–
–
35
25
25
10
–
–
–
–
40
30
30
10
–
–
–
–
45
35
35
10
–
–
–
–
ns
ns
ns
ns
Retransmit pulse width (19)
Retransmit set–up time (20)
Retransmit recovery time
tRTS
tRTR
PREVIEW
TRSLEFL
TRSLFFH
TRLEFL
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
TFFHWH
tEFL
Reset to EF low
–
–
30
30
20
20
–
–
–
35
35
25
25
–
–
–
40
40
30
30
–
–
–
45
45
30
30
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFH, tFFH Reset to HF/FF high
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
Read low to EF low
–
–
–
–
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
Write width after FF high
–
–
–
–
20
–
25
–
30
–
35
–
20
20
30
30
–
25
25
35
35
–
30
30
40
40
–
30
30
45
45
–
–
–
–
–
–
–
–
–
–
–
–
–
20
25
30
35
10
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
MIL ONLY COM, IND, MIL ONLY COM, IND,
SYMBOL SYMBOL
MIL, AUTO
– 45
AUTO
– 55
PARAMETER (18) (22)
UNIT
(16)
(17)
– 40
– 50
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE
TRLRL
TRLQV
TRHRL
TRLRH
TRLQX
TWHQX
TRHQX
TRHQZ
tRC
Read cycle time
50
–
–
40
–
55
–
–
45
–
65
–
–
50
–
70
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
tA
Access time
tRR
Read recovery time
10
40
5
10
45
5
15
50
10
15
5
15
55
10
15
5
tRPW
tRLZ
tWLZ
tDV
Read pulse width (19)
Read low to data low Z (20)
Write low to data low Z (20, 21)
Data valid from read high
Read high to data high Z (20)
–
–
–
–
–
–
–
–
10
5
–
10
5
–
–
–
–
–
–
–
tRHZ
–
25
–
25
–
30
–
30
WRITE CYCLE
TWLWL
TWLWH
TWHWL
TDVWH
TWHDX
tWC
Write cycle time
Write pulse width (19)
Write recovery time
Data set–up time
Data hold time
50
40
10
20
0
–
–
–
–
–
55
45
10
20
0
–
–
–
–
–
65
50
15
30
0
–
–
–
–
–
70
55
15
30
0
–
–
–
–
–
ns
ns
ns
ns
ns
tWPW
tWR
tDS
tDH
RESET CYCLE
TRSLWL
TRSLRSH
TWHRSH
TRSHWL
tRSC
Reset cycle time
50
40
40
10
–
–
–
–
55
45
45
10
–
–
–
–
65
50
50
15
–
–
–
–
70
55
55
15
–
–
–
–
ns
ns
ns
ns
tRS
Reset pulse width (19)
Reset set–up time
Reset recovery time
tRSS
tRSR
RETRANSMIT CYCLE
TRTLWL
TRTLRTH
TWHRTH
TRTHWL
FLAGS
tRTC
tRT
Retransmit cycle time
50
40
40
10
–
–
–
–
55
45
45
10
–
–
–
–
65
50
50
15
–
–
–
–
70
55
55
15
–
–
–
–
ns
ns
ns
ns
Retransmit pulse width (19)
Retransmit set–up time (20)
Retransmit recovery time
tRTS
tRTR
TRSLEFL
TRSLFFH
TRLEFL
TRHFFH
TEFHRH
TWHEFH
TWLFFL
TWLHFL
TRHHFH
TFFHWH
tEFL
Reset to EF low
–
–
50
50
30
35
–
–
–
55
55
40
40
–
–
–
60
60
45
45
–
–
–
65
65
50
50
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFH, tFFH Reset to HF/FF high
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
Read low to EF low
–
–
–
–
Read high to FF high
Read width after EF high
Write high to EF high
Write low to FF low
Write low to HF low
Read high to HF high
Write width after FF high
–
–
–
–
40
–
45
–
50
–
55
–
35
35
50
50
–
40
40
55
55
–
45
45
60
60
–
50
50
65
65
–
–
–
–
–
–
–
–
–
–
–
–
–
40
45
50
55
MATRA MHS
11
Rev. D (11 April. 97)
M67201A/M67202A
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
COM, IND, COM, IND, MIL ONLY COM, IND,
SYMBOL SYMBOL
PARAMETER (18) (22)
MIL, AUTO MIL, AUTO
– 20 – 25
AUTO
– 35
UNIT
(16)
(17)
– 30
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION
TWLXOL
TWHXOH
TXILXIH
TXIHXIL
TXILRL
PREVIEW
tXOL
Read/Write to XO low
Read/Write to XO high
XI pulse width
–
20
20
–
–
25
25
–
–
30
30
–
–
35
35
–
ns
ns
ns
ns
ns
tXOH
tXI
–
–
–
–
20
10
10
25
10
10
30
10
10
35
10
10
tXIR
tXIS
XI recovery time
XI set–up time
–
–
–
–
–
–
–
–
M 67201A/202A M 67201A/202A M 67201A/202A M 67201A/202A
MIL ONLY COM, IND, MIL ONLY COM, IND,
SYMBOL SYMBOL
MIL, AUTO
– 45
AUTO
– 55
PARAMETER (18) (22)
UNIT
(16)
(17)
– 40
– 50
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION
TWLXOL
TWHXOH
TXILXIH
TXIHXIL
TXILRL
tXOL
Read/Write to XO low
Read/Write to XO high
XI pulse width
–
40
40
–
–
45
45
–
–
50
50
–
–
55
55
–
ns
ns
ns
ns
ns
tXOH
tXI
–
–
–
–
40
10
10
45
10
10
50
10
15
55
10
15
tXIR
tXIS
XI recovery time
XI set–up time
–
–
–
–
–
–
–
–
Notes : 16. STD symbol.
17. ALT symbol.
18. Timings referenced as in ac test conditions.
19. Pulse widths less than minimam value are not allowed.
20. Values guaranteed by design, not currently tested.
21. Only applies to read data flow-through mode.
22. All parameters tested only.
Figure 8. Asynchronous Write and Read Operation.
12
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Figure 9. Full Flag from Last Write to First Read.
Figure 10. Empty Flag from Last Read to First Write.
Figure 11. Retransmit.
Note
:
23. EF, FF and HF may change status during Retransmit, but flags will be valid at t
.
RTC
MATRA MHS
13
Rev. D (11 April. 97)
M67201A/M67202A
Figure 12. Empty Flag Timing
Figure 13. Full Flag Timing
Figure 14. Half-Full Flag Timing.
14
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Figure 15. Expansion Out.
Figure 16. Expansion In.
Figure 17. Read Data Flow – Through Mode.
MATRA MHS
15
Rev. D (11 April. 97)
M67201A/M67202A
Figure 18. Write Data Flow – Through Mode.
Ordering Information
TEMPERATURE RANGE
PACKAGE
3P
DEVICE
67201AL
SPEED
25
FLOW
C
M
M = 5 V version
L = 3.3 V version
20 ns
25 ns
30 ns
35 ns
40 ns
45 ns
50 ns
55 ns
blank
/883
P883
SB/SC
= MHS standards
= MIL STD 883 Class B or S
= MIL STD 883 + PIND test
= SCC 9000 level B/C
1P = 28 pin DIL ceramic 300 mils
3P = 28 pin DIL plastic 300 mils
*TI = 28 pin SOL plastic 300 mils
*UI = 28 pin SOJ plastic 300 mils
4J = 32 pin LCC rectangular
S1 = 32 pin PLCC
DP = 28 pin FP 400 mils (Preview)
CP = Side brazed 28 pins 300 mils
0 = Dice form
SHXXX = Special customer request
FHXXX = Flight models (space)
EHXXX = Engineering models (space)
MHXXX = Mechanical parts (space)
LHXXX = Life test parts (space)
: R
: RD
: D
= Tape and reel
= Tape and reel dry pack
= Dry pack
67201 = 512 × 9 FIFO
67202 = 1024 × 9 FIFO
AL = Low power
C = Commercial
I = Industrial
A = Automotive
M = Military
S = Space
0° to +70°C
–40° to +85°C
–40° to +125°C
–55° to +125°C
–55° to +125°C
AV = Very low power
* On request only
16
MATRA MHS
Rev. D (11 April. 97)
M67201A/M67202A
Military and Space Versions
The following tables give package/consumption/access time/process flow available combinations
Temp.
range
Packages
Consumption
Access Time (ns)
Std process
67201A
RT process
67201F
V
L
25
30
40
50
Mil flows
(including
Mil flows
Space flows
SMD5962–87531
SMD5962–89863)
M
S
1P
4J
CP
DP
0
1
1
1
1
X
D
D
D
D
D
X
X
X
X
X
D
D
D
D
D
D
D
X
D
D
D
X
D
D
D
D
X
D
D
D
X
X
X
X
4J
CP
DP
0
1
1
1
X
X
X
X
D
D
D
D
D
D
X
D
D
D
X
D
X
X
X
X
X
D
Temp.
range
Packages
Consumption
Access Time (ns)
Std process
67202A
RT process
67202F
V
L
25
30
40
50
Mil flows
(including
Mil flows
Space flows
(including
SMD5962–89536)
SCC9301032)
M
S
1P
4J
CP
DP
0
D
D
D
D
X
D
D
D
D
D
X
X
X
X
X
D
D
D
D
D
D
D
X
D
D
D
X
D
D
D
D
X
D
D
D
X
X
X
X
4J
CP
DP
0
D
D
D
X
X
X
X
X
D
D
D
D
D
D
X
D
D
D
X
D
X
X
X
X
D
D = product in production
X = call sales office for availibility
The information contained herein is subject to change without notice. No responsibility is assumed by TEMIC for using this publication and/or circuits
described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
MATRA MHS
17
Rev. D (11 April. 97)
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