80C52T-42D [TEMIC]
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller; CMOS 0至44 MHz的单芯片8位微控制器
| 型号： | 80C52T-42D |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller |
| 文件： | 总20页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MATRA MHS
80C32/80C52
CMOS 0 to 44 MHz Single-chip 8 Bit Microcontroller
Description
MHS’s 80C52 and 80C32 are high performance CMOS modes of reduced activity for further reduction in power
versions of the 8052/8032 NMOS single chip 8 bit µC.
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode the
RAM is saved and all other functions are inoperative.
The fully static design of the MHS 80C52/80C32 allows
to reduce system power consumption by bringing the
clock frequency down to any value, even DC, without loss
of data.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. MHS’s 80C52/80C32 are manufactured
using SCMOS process which allows them to run from 0
up to 44 MHz with Vcc = 5 V.
The 80C52 retains all the features of the 8052 : 8 K bytes
of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit
timers ; a 6-source, 2-level interrupt structure ; a full
duplex serial port ; and on-chip oscillator and clock MHS’s 80C52 and 80C32 are also available at 16 MHz
circuits. In addition, the 80C52 has 2 software-selectable with 2.7 V < V < 5.5 V.
CC
D 80C32 : Romless version of the 80C52
D 80C32/80C52-L16 : Low power version
D 80C32/80C52-36 : 0 to 36 MHz
D 80C32-40 : 0 to 40 MHz*
D 80C32-42 : 0 to 42 MHz*
D 80C32-44 : 0 to 44 MHz*
Vcc : 2.7 – 5.5 V
Freq : 0-16 MHz
D 80C32/80C52-12 : 0 to 12 MHz
D 80C32/80C52-16 : 0 to 16 MHz
D 80C32/80C52-20 : 0 to 20 MHz
D 80C32/80C52-25 : 0 to 25 MHz
D 80C32/80C52-30 : 0 to 30 MHz
* 0 to 70°C temperature range.
For other speed and temperature range availability please consult your
sales office.
Features
D Power control modes
D Fully static design
D 256 bytes of RAM
D 0.8µ CMOS process
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
Rev. E (31/08/95)
1
80C32/80C52
MATRA MHS
Interface
Figure 1. Block Diagram
2
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
Figure 2. Pin Configuration
P1.5
P1.6
P1.7
RST
P0.4/A4
P0.5/A5
P0.6/A6
P0.7/A7
EA
RxD/P3.0
NC
NC
ALE
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
PSEN
P2.7/A14
P2.6/A13
P2.5/A12
LCC
DIL
P
/A4
/A5
/A6
/A7
P
04
15
P
P
16
05
P
P
17
06
P
RST
07
RxD/P
EA
NC
30
NC
ALE
TxD/P
31
INT0/P
PSEN
32
INT1/P
P
/A15
33
27
T0/P
P
/A14
/A13
34
26
T1/P
P
25
35
Flat Pack
Diagrams are for reference only. Package sizes are not to scale.
Rev. E (31/08/95)
3
80C32/80C52
MATRA MHS
Pin Description
Memory that use 16 bit addresses (MOVX @DPTR). In
this application, it uses strong internal pullups when
emitting 1’s. During accesses to external Data Memory
that use 8 bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
VSS
Circuit ground potential.
VCC
It also receives the high-order address bits and control
signals during program verification in the 80C52. Port 2
can sink/source three LS TTL inputs. It can drive CMOS
inputs without external pullups.
Supply voltage during normal, Idle, and Power Down
operation.
Port 0
Port 3
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have 1’s written to them float, and in that state
can be used as high-impedance inputs.
Port 3 is an 8 bit bi-directional I/O port with internal
pullups. Port 3 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions
of various special features of the MHS 51 Family, as listed
below.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting 1’s. Port 0 also outputs the code bytes
during program verification in the 80C52. External
pullups are required during program verification. Port 0
can sink eight LS TTL inputs.
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
TD (Timer 0 external input)
T1 (Timer 1 external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 1
Port 1 is an 8 bit bi-directional I/O port with internal
pullups. Port 1 pins that have 1’s written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (IIL, on the data
sheet) because of the internal pullups.
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
Port 1 also receives the low-order address byte during
program verification. In the 80C52, Port 1 can sink/
source three LS TTL inputs. It can drive CMOS inputs
without external pullups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
2 inputs of PORT 1 are also used for timer/counter 2 :
P1.0 [T2] : External clock input for timer/counter 2. P1.1 pull-down resistor permits Power-On reset using only a
[T2EX] : A trigger input for timer/counter 2, to be capacitor connected to V . As soon as the Reset is
CC
reloaded or captured causing the timer/counter 2 applied (Vin), PORT 1, 2 and 3 are tied to one. This
interrupt.
operation is achieved asynchronously even if the
oscillator does not start-up.
Port 2
ALE
Port 2 is an 8 bit bi-directional I/O port with internal
pullups. Port 2 pins that have 1’s written to them are Address Latch Enable output for latching the low byte of
pulled high by the internal pullups, and in that state can the address during accesses to external memory. ALE is
be used as inputs. As inputs, Port 2 pins that are externally activated as though for this purpose at a constant rate of
being pulled low will source current (ILL, on the data 1/6 the oscillator frequency except during an external
sheet) because of the internal pullups. Port 2 emits the data memory access at which time on ALE pulse is
high-order address byte during fetches from external skipped. ALE can sink/source 8 LS TTL inputs. It can
Program Memory and during accesses to external Data drive CMOS inputs without an external pullup.
4
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
1 FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
PSEN
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
XTAL1
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator.
This pin should be floated when an external oscillator is
used.
EA
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds
Idle And Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
function, while the clock to the CPU is gated off.
Symbol
Position
Name and Function
SMOD
PCON.7
Double Baud rate bit. When set to
a 1, the baud rate is doubled when
the serial port is being used in
either modes 1, 2 or 3.
(Reserved)
(Reserved)
–
–
–
GF1
GF0
PD
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
These special modes are activated by software via the
Special Function Register, PCON. Its hardware address is
87H. PCON is not bit addressable.
(Reserved)
General-purpose flag bit.
General-purpose flag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
Figure 3. Idle and Power Down Hardware.
IDL
PCON.0
If 1’s are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(000X0000).
Idle Mode
The instruction that sets PCON.0 is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety : the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. Table 1 describes the status of the
external pins during Idle mode.
PCON : Power Control Register
(MSB)
SMOD
(LSB)
IDL
–
–
–
GF1
GF0
PD
Rev. E (31/08/95)
5
80C32/80C52
MATRA MHS
There are three ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware, terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote 1 to PCON.0.
Power Down Mode
The instruction that sets PCON.1 is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The hardware reset initiates the Special Fucntion
Register. In the Power Down mode, VCC may be lowered
to minimize circuit power consumption. Care must be
taken to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which freezes the
oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
Table 1 describes the status of the external pins while in
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the the power down mode. It should be noted that if the power
hardware reset needs to be active for only 2 machine down mode is activated while in external program
cycles (24 oscillator periods) to complete the reset memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the data is a 1, the port
pin is held high during the power down mode by the
strong pullup, T1, shown in Figure 4.
operation.
Table 1 : Status of the external pins during idle and power down modes.
MODE
Idle
PROGRAM MEMORY
ALE
PSEN
PORT0
Port Data
Floating
Port Data
Floating
PORT1
Port Data
Port Data
Port Data
Port Data
PORT2
Port Data
Address
PORT3
Port Data
Port Data
Port Data
Port Data
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Idle
Power Down
Power Down
Port Data
Port Data
Figure 4. I/O Buffers in the 80C52 (Ports 1, 2, 3).
Stop Clock Mode
Due to static design, the MHS 80C32/C52 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
I/O Ports
The I/O buffers for Ports 1, 2 and 3 are implemented as
shown in figure 4.
6
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
When the port latch contains a 0, all pFETS in figure 4 are
off while the nFET is turned on. When the port latch
makes a 0-to-1 transition, the nFET turns off. The strong
pFET, T1, turns on for two oscillator periods, pulling the
output high very rapidly. As the output line is drawn high,
pFET T3 turns on through the inverter to supply the IOH
source current. This inverter and T form a latch which
holds the 1 and is supported by T2.
Figure 5. Crystal Oscillator.
When Port 2 is used as an address port, for access to
external program of data memory, any address bit that
contains a 1 will have his strong pullup turned on for the
entire duration of the external memory access.
To drive the device from an external clock source,
XTAL1 should be driven while XTAL2 is left
unconnected as shown in figure 6. There are no
requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data Sheet
must be observed.
When an I/O pin on Ports 1, 2, or 3 is used as an input, the
user should be aware that the external circuit must sink
current during the logical 1-to-0 transition. The
maximum sink current is specified as ITL under the D.C.
Specifications. When the input goes below
approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical 1, T2 is the only internal
pullup that is on. This will result in a slow rise time if the
user’s circuit does not force the input line high.
Figure 6. External Drive Configuration.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output respectively,
of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in figure 5. Either a quartz
crystal or ceramic resonator may be used.
Hardware Description
Same as for the 80C51, plus a third timer/counter :
that a 1-to-0 transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H,
respectively, (RCAP2L and RCAP2H are new Special
Function Register in the 80C52). In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set,
and EXF2, like TF2, can generate an interrupt.
Timer/Event Counter 2
Timer 2 is a 16 bit timer/counter like Timers 0 and 1, it
can operate either as a timer or as an event counter. This
is selected by bit C/T2 in the Special Function Register
T2CON (Figure 1). It has three operating modes :
“capture”, “autoload” and “baud rate generator”, which
are selected by bits in T2CON as shown in Table 2.
Table 2 : Timer 2 Operating Modes.
RCLK +
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON; If EXEN2 = 0, then
Timer 2 is a 16 bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, which
can be used to generate an interrupt. If EXEN2 = 1, then
Timer 2 still does the above, but with the added feature
CP/RL2
TR2
MODE
TCLK
0
0
1
0
1
X
X
1
1
1
0
16 bit auto-reload
16 bit capture
baud rate generator
(off)
X
Rev. E (31/08/95)
7
80C32/80C52
MATRA MHS
The capture mode is illustrated in Figure 7.
with the 16 bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = 1, then Timer
2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX will also trigger
the 16 bit reload and set EXF2.
Figure 7. Timer 2 in Capture Mode.
The auto-reload mode is illustrated in Figure 8.
Figure 8. Timer in Auto-Reload Mode.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON.If
EXEN2 = 0, then when Timer 2 rolls over it does not only
set TF2 but also causes the Timer 2 register to be reloaded
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1.
Symbol
Position
Name and Significance
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 OR TCLK = 1.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer2 overflow pulses for its
receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2 overflows or
negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
8
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
80C52 with Secret ROM
80C52 with Secret TAG
Matra MHS offers 80C52 with the encrypted secret ROM
option to secure the ROM code contained in the 80C52
microcontrollers.
Matra MHS offers special 64-bit identifier called
“SECRET TAG” on the microcontroller chip.
The Secret Tag option is available on both ROMless and
masked microcontrollers.
The clear reading of the program contained in the ROM
is made impossible due to an encryption through several
random keys implemented during the manufacturing
process.
The Secret Tag feature allows serialization of each
microcontroller for identification of
a
specific
equipment. A unique number per device is implemented
in the chip during manufacturing process. The serial
number is a 64-bit binary value which is contained and
addressable in the Special Function Registers (SFR) area.
The keys used to do such encryption are selected
randomwise and are definitely different from one
microcontroller to another.
This encryption is activated during the following phases :
This Secret Tag option can be read-out by a software
routine and thus enables the user to do an individual
identity check per device. This routine is implemented
inside the microcontroller ROM memory in case of
masked version which can be kept secret (and then the
value of the Secret Tag also) by using a ROM Encryption.
–
–
–
Everytime a byte is addressed during a verify of the
ROM content, a byte of the encryption array is
selected.
MOVC instructions executed from external program
memory are disabled when fetching code bytes from
internal memory.
For further information, please refer to the application
note (ANM031) available upon request.
EA is sampled and latched on reset, thus all state
modification are disabled.
For further information please refer to the application
note (ANM053) available upon request.
Rev. E (31/08/95)
9
80C32/80C52
MATRA MHS
Electrical Characteristics
* Notice
Absolute Maximum Ratings*
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Ambiant Temperature Under Bias :
C = commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I = industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA = 0°C to 70°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 44 MHz
TA = –40°C + 85°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
VIL
PARAMETER
MIN
– 0.5
MAX
0.2 Vcc – 0.1
Vcc + 0.5
Vcc + 0.5
UNIT
TEST CONDITIONS
Input Low Voltage
V
V
V
VIH
Input High Voltage (Except XTAL and RST)
Input High Voltage (for XTAL and RST)
Output Low Voltage (Port 1, 2 and 3)
0.2 Vcc + 1.4
0.7 Vcc
VIH1
VOL
0.3
0.45
1.0
V
V
V
IOL = 100 µA
IOL = 1.6 mA (note 2)
IOL = 3.5 mA
VOL1
VOH
Output Low Voltage (Port 0, ALE, PSEN)
Output High Voltage Port 1, 2, 3
0.3
0.45
1.0
V
V
V
IOL = 200 µA
IOL = 3.2 mA (note 2)
IOL = 7.0 mA
Vcc – 0.3
Vcc – 0.7
Vcc – 1.5
V
V
V
IOH = – 10 µA
IOH = – 30 µA
IOH = – 60 µA
VCC = 5 V ± 10 %
VOH1
Output High Voltage (Port 0, ALE, PSEN)
Vcc – 0.3
Vcc – 0.7
Vcc – 1.5
V
V
V
IOH = – 200 µA
IOH = – 3.2 mA
IOH = – 7.0 mA
VCC = 5 V ± 10 %
IIL
ILI
Logical 0 Input Current (Ports 1, 2 and 3)
Input leakage Current
– 50
± 10
– 650
50
µA
µA
Vin = 0.45 V
0.45 < Vin < Vcc
Vin = 2.0 V
ITL
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
Power Down Current
µA
IPD
RRST
CIO
ICC
µA
Vcc = 2.0 V to 5.5 V (note 1)
RST Pulldown Resistor
50
200
10
KOhm
pF
Capacitance of I/O Buffer
fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
1.8
1
10
4
mA
mA
mA
mA
Freq ≥ 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
10
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
* Notice
Absolute Maximum Ratings*
Stresses above those listed under “ Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Ambient Temperature Under Bias :
A = Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA = –40°C + 125°C ; VSS = 0 V ; VCC = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
VIL
PARAMETER
MIN
– 0.5
MAX
0.2 Vcc – 0.1
Vcc + 0.5
Vcc + 0.5
UNIT
TEST CONDITIONS
Input Low Voltage
V
V
V
VIH
Input High Voltage (Except XTAL and RST)
Input High Voltage (for XTAL and RST)
Output Low Voltage (Port 1, 2 and 3)
0.2 Vcc + 1.4
0.7 Vcc
VIH1
VOL
0.3
0.45
1.0
V
V
V
IOL = 100 µA
IOL = 1.6 mA (note 2)
IOL = 3.5 mA
VOL1
VOH
Output Low Voltage (Port 0, ALE, PSEN)
Output High Voltage Port 1, 2 and 3
0.3
0.45
1.0
V
V
V
IOL = 200 µA
IOL = 3.2 mA (note 2)
IOL = 7.0 mA
Vcc – 0.3
Vcc – 0.7
Vcc – 1.5
V
V
V
IOH = – 10 µA
IOH = – 30 µA
IOH = – 60 µA
VCC = 5 V ± 10 %
VOH1
Output High Voltage (Port 0, ALE, PSEN)
Vcc – 0.3
Vcc – 0.7
Vcc – 1.5
V
V
V
IOH = – 200 µΑ
IOH = – 3.2 mA
IOH = – 7.0 mA
VCC = 5 V ± 10 %
IIL
ILI
Logical 0 Input Current (Ports 1, 2 and 3)
Input leakage Current
– 75
±10
– 750
75
µA
µA
Vin = 0.45 V
0.45 < Vin < Vcc
Vin = 2.0 V
ITL
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
Power Down Current
µA
IPD
RRST
CIO
ICC
µA
Vcc = 2.0 V to 5.5 V (note 1)
RST Pulldown Resistor
50
200
10
KOhm
pF
Capacitance of I/O Buffer
fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
1.8
1
10
4
mA
mA
mA
mA
Freq ≥ 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
Rev. E (31/08/95)
11
80C32/80C52
MATRA MHS
* Notice
Absolute Maximum Ratings*
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Ambient Temperature Under Bias :
M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA = –55°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
VIL
PARAMETER
MIN
– 0.5
MAX
0.2 Vcc – 0.1
Vcc + 0.5
Vcc + 0.5
0.45
UNIT
TEST CONDITIONS
Input Low Voltage
V
V
V
V
V
V
VIH
Input High Voltage (Except XTAL and RST)
Input High Voltage (for XTAL and RST)
Output Low Voltage (Port 1, 2 and 3)
Output Low Voltage (Port 0, ALE, PSEN)
Output High Voltage (Port 1, 2 and 3)
0.2 Vcc + 1.4
0.7 Vcc
VIH1
VOL
IOL = 1.6 mA (note 2)
IOL = 3.2 mA (note 2)
VOL1
VOH
0.45
2.4
IOH = – 60 µA
Vcc = 5 V ± 10 %
0.75 Vcc
0.9 Vcc
2.4
V
V
V
IOH = – 25 µA
IOH = – 10 µA
VOH1
Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
IOH = – 400 µA
Vcc = 5 V ± 10 %
0.75 Vcc
0.9 Vcc
V
V
IOH = – 150 µA
IOH = – 40 µA
IIL
ILI
Logical 0 Input Current (Ports 1, 2 and 3)
Input leakage Current
– 75
+/– 10
– 750
75
µA
µA
µA
µA
KΩ
pF
Vin = 0.45 V
0.45 < Vin < Vcc
Vin = 2.0 V
ITL
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
Power Down Current
IPD
RRST
CIO
ICC
Vcc = 2.0 V to 5.5 V (note 1)
RST Pulldown Resistor
50
200
Capacitance of I/O Buffer
10
fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
1.8
1
10
4
mA
mA
mA
mA
Freq ≥ 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
12
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
* Notice
Absolute Maximum Ratings*
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
Ambient Temperature Under Bias :
C = Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I
=
Industri.al .
.
.
.
.
.
.
.
.
.
.
.
. -.40 . to. .85.°C.
.
.
.
.
.
.
.
.
.
.
.
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Characteristics
TA = 0°C to 70°C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 16 MHz
TA = –40°C to 85°C ; Vcc = 2.7 V to 5.5 V
SYMBOL
VIL
PARAMETER
MIN
MAX
UNIT
TEST CONDITIONS
Input Low Voltage
– 0.5
0.2 V – 0.1
V
V
V
V
V
V
V
V
V
CC
VIH
Input High Voltage (Except XTAL and RST)
Input High Voltage to RST for Reset
Input High Voltage to XTAL1
0.2 V + 1.4
V
V
V
+ 0.5
+ 0.5
+ 0.5
CC
CC
CC
CC
VIH2
VIH1
VPD
0.7 V
0.7 V
2.0
CC
CC
Power Down Voltage to Vcc in PD Mode
Output Low Voltage (Ports 1, 2, 3)
Output Low Voltage Port 0, ALE, PSEN
Output High Voltage Ports 1, 2, 3
5.5
VOL
0.45
0.45
IOL = 0.8 mA (note 2)
IOL = 1.6 mA (note 2)
IOH = – 10 µA
VOL1
VOH
0.9 Vcc
0.9 Vcc
VOH1
Output High Voltage (Port 0 in External Bus
Mode), ALE, PSEN
IOH = – 40 µA
IIL
ILI
Logical 0 Input Current Ports 1, 2, 3
Input Leakage Current
– 50
± 10
µA
µA
µA
Vin = 0.45 V
0.45 < Vin < V
CC
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, 3)
– 650
Vin = 2.0 V
IPD
RRST
CIO
Power Down Current
50
200
10
µA
kΩ
pF
V
= 2.0 V to 5.5 V (note 1)
CC
RST Pulldown Resistor
Capacitance of I/O Buffer
50
fc = 1 MHz, T = 25_C
A
Maximum Icc (mA)
OPERATING (NOTE 1)
IDLE (NOTE 1)
FREQUENCY/Vcc
2.7 V
0.8 mA
4 mA
3 V
3.3 V
1.1 mA
6 mA
5.5 V
2.7 V
400 µA
1.5 mA
2.5 mA
3 mA
3 V
3.3 V
600 µA
2 mA
5.5 V
1 MHz
6 MHz
1 mA
5 mA
10 mA
12 mA
1.8 mA
10 mA
500 µA
1.7 mA
3 mA
1 mA
4 mA
12 MHz
8 mA
12 mA
14 mA
3.5 mA
4.5 mA
16 MHz
10 mA
3.8 mA
Freq > 12 MHz (Vcc = 5.5 V)
Icc (mA) = 1.25 × Freq (MHz) + 5
Icc Idle (mA) = 0.36 × Freq (MHz) + 2.7
Rev. E (31/08/95)
13
80C32/80C52
MATRA MHS
Note 1 : ICC is measured with all output pins
disconnected ; XTAL1 driven with TCLCH, TCHCL =
5 ns, VIL = VSS + .5 V, VIH = VCC –.5 V ; XTAL2
N.C. ; EA = RST = Port 0 = VCC. ICC would be slighty
higher if a crystal oscillator used.
Figure 9. ICC Test Condition, Idle Mode.
All other pins are disconnected.
Idle ICC is measured with all output pins disconnected ;
XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL =
VSS + 5 V, VIH = VCC –.5 V ; XTAL2 N.C ; Port 0 =
VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins
disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST = VSS.
Note 2 : Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins
when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
may exceed 0,45 V with maxi VOL peak 0.6 V. A Schmitt
Trigger use is not necessary.
Figure 10. ICC Test Condition, Active Mode.
All other pins are disconnected.
Figure 11. ICC Test Condition, Power Down Mode.
All other pins are disconnected.
Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
14
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
Explanation of the AC Symbol
Each timing symbol has 5 characters. The first character Example :
is always a “T” (stands for time). The other characters,
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
A : Address.
C : Clock.
D : Input data.
Q : Output data.
R : READ signal.
T : Time.
H : Logic level HIGH
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P : PSEN.
V : Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z : Float.
AC Parameters
TA = 0 to + 70°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 44 MHz
TA = 0 to +70°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz
TA = –40° to + 85°C ; Vss = 0 V ; 2.7 V < Vcc < 5.5 V ; F = 0 to 16 MHz
TA = –55° + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
(Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF)
External Program Memory Characteristics (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
min max min max min max min max min max min max min max min max
SYM-
BOL
PARAMETER
TLHLL ALE Pulse Width
110
40
90
30
35
70
20
35
60
15
35
50
10
35
40
9
35
8
30
7
TAVLL Address valid to ALE
TLLAX Address Hold After ALE
35
30
25
17
TLLIV
ALE to valid instr in
185
170
130
100
80
70
65
65
TLLPL ALE to PSEN
45
40
30
25
80
20
75
15
65
13
60
12
54
TPLPH PSEN pulse Width
165
130
100
TPLIV
TPXIX
TPXIZ
PSEN to valid instr in
125
50
110
45
85
35
65
30
50
25
45
20
40
15
35
10
Input instr Hold After PSEN
Input instr Float After PSEN
0
0
0
0
0
0
0
0
TPXAV PSEN to Address Valid
TAVIV Address to Valid instr in
TPLAZ PSEN low to Address Float
55
50
40
35
30
25
20
15
230
10
210
10
170
8
130
6
90
5
80
5
75
5
70
5
External Program Memory Read Cycle
Rev. E (31/08/95)
15
80C32/80C52
MATRA MHS
External Data Memory Characteristics (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
min max min max min max min max min max min max min max min max
SYM-
BOL
PARAMETER
TRLRH RD pulse Width
340
340
85
270
270
85
210
210
70
180
180
55
120
120
35
100
100
30
90
90
25
80
80
25
TWLWH WR pulse Width
TLLAX Address Hold After ALE
TRLDV RD to Valid in
240
210
175
135
110
90
80
70
TRHDX Data hold after RD
TRHDZ Data float after RD
TLLDV ALE to Valid Data In
TAVDV Address to Valid Data IN
TLLWL ALE to WR or RD
0
0
0
0
0
0
0
0
90
90
80
70
50
45
150
180
95
40
140
175
90
35
130
170
85
435
480
370
400
350
300
235
260
170
190
150 250 135 170 120 130 90 115 70 100 60
55
60
8
50
55
6
TAVWL Address to WR or RD
TQVWX Data valid to WR transition
TQVWH Data Setup to WR transition
TWHQX Data Hold after WR
TRLAZ RD low to Address Float
TWHLH RD or WR high to ALE high
180
35
180
35
140
30
115
20
75
15
65
10
380
40
325
35
250
30
215
20
170
15
160
10
150
8
140
6
0
0
0
0
0
0
0
0
35
90
35
60
25
45
20
40
20
40
15
35
13
33
13
33
External Data Memory Write Cycle
External Data Memory Read Cycle
16
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
Serial Port Timing – Shift Register Mode (values in ns)
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42 MHz 44 MHz
min max min max min max min max min max min max min max min max
SYM-
BOL
PARAMETER
TXLXL Serial Port Clock Cycle Time
750
563
600
480
480
380
400
300
330
220
250
170
230
150
227
140
TQVXH Output Data Setup to Clock
Rising Edge
TXHQX Output Data Hold after Clock
Rising Edge
63
0
90
0
65
0
50
0
45
0
35
0
30
0
25
0
TXHDX Input Data Hold after Clock
Rising Edge
TXHDV Clock Rising Edge to Input
Data Valid
563
450
350
300
250
200
180
160
Shift Register Timing Waveforms
Rev. E (31/08/95)
17
80C32/80C52
MATRA MHS
External Clock Drive Characteristics (XTAL1)
SYMBOL
FCLCL
PARAMETER
Oscillator Frequency
Oscillator period
High Time
MIN
MAX
UNIT
MHz
ns
44
TCLCL
TCHCX
TCLCX
TCLCH
TCHCL
22.7
5
ns
Low Time
5
ns
Rise Time
5
5
ns
Fall Time
ns
External Clock Drive Waveforms
AC Testing Input/Output Waveforms
AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45 V for a logic “0”. Timing measurements are
made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOH/VOL level occurs. Iol/IoH ≥ ± 20 mA.
18
Rev. E (31/08/95)
MATRA MHS
80C32/80C52
Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T = 25°C fully loaded) RD
A
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
Rev. E (31/08/95)
19
80C32/80C52
MATRA MHS
Ordering Information
xxx
-36
D
I
80C52C
S
Part Number
80C52 Rom 8 K × 8
–12 : 12 MHz version
–16 : 16 MHz version
–20 : 20 MHz version
–25 : 25 MHz version
–30 : 30 MHz version
–36 : 36 MHz version
–40 : 40 MHz version
–42 : 42 MHz version
–44 : 44 MHz version
–L16 : Low Power
80C32 External ROM
80C52C Secret ROM version
80C52T Secret Tag version
Temperature Range
blank : Commercial
I
A
M
: Industrial
: Automotive
: Military
(3)
(3)
(3)
(1)
Package Type
(2)
F1, F2 : Quad Flat Pack
P : Plastic DIL
(Vcc : 2.7-5.5 V
Freq : 0-16 MHz)
S : PLCC
V : V Quad Flat Pack (1.4 mm)
T : T Quad Flat Pack (1 mm)
Customer Rom Code
R : Tape and Reel
D : Dry Pack
(1) Ceramic of multi-layer packages : contact TEMIC sales office.
(2) See mechanical outlines available on Databook or on request.
(3) Only for 80C32 at commercial range.
20
Rev. E (31/08/95)
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