TC835CBU [TELCOM]
PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER; 个人计算机数据采集A / D转换器
| 型号： | TC835CBU |
| 厂家： | 
TELCOM SEMICONDUCTOR, INC |
| 描述： | PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER |
| 文件： | 总12页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3
TC835
PERSONAL COMPUTER DATA ACQUISITION A/D CONVERTER
GENERAL DESCRIPTION
FEATURES
■ Upgrade of Pin-Compatible TC7135, ICL7135,
MAX7135 and SI7135
■ Guaranteed 200 kHz Operation
■ Single 5V Operation With TC7660
■ Multiplexed BCD Data Output
■ UART and Microprocessor Interface
■ Control Outputs for Auto-Ranging
■ Input Sensitivity ............................................ 100 µV
■ No Sample and Hold Required
The TC835 is a low-power, 4-1/2 digit (0.005% resolu-
tion), BCD analog-to-digital converter (ADC) that has been
characterized for 200 kHz clock rate operation. The five
conversions per second rate is nearly twice as fast as the
ICL7135 or TC7135. The TC835 (like the TC7135) does
not use the external diode-resistor roll-over error compen-
sation circuits required by the ICL7135.
The multiplexed BCD data output is perfect for interfac-
ing to personal computers. The low-cost, greater than 14-
bit high-resolution, and 100 µV sensitivity makes the TC835
exceptionally cost-effective.
Microprocessor-based data acquisition systems are
supported by the BUSY and STROBE outputs, along with
the RUN/HOLD input of the TC835. The overrange, under-
range, busy, and run/hold control functions and multiplexed
BCD data outputs make the TC835 the ideal converter for
µP-based scales and measurement systems and intelligent
panel meters.*
The TC835 interfaces with full-function LCD and LED
display decoder/drivers. The UNDERRANGE and
OVERRANGE outputs may be used to implement an auto-
ranging scheme or special display functions.
APPLICATIONS
■ Personal Computer Data Acquisition
■ Scales, Panel Meters, Process Controls
■ HP-IL Bus Instrumentation
ORDERING INFORMATION
Temperature
Part No.
Package
Range
TC835CBU
TC835CKW
TC835CPI
64-Pin PQFP
0°C to +70°C
0°C to +70°C
0°C to +70°C
44-Pin PQFP
28-Pin Plastic DIP
NOTE: Tape and reel available for 44-pin PQFP packages.
*See Application Notes 16 and 17 for microprocessor interface tech-
niques.
TYPICAL APPLICATION
ADDRESS BUS
CONTROL
+
5V
+
DATA BUS
V
REF
CAP
BUF
AZ
GAIN: 10, 20, 50, 100
+15V –15V
DG529
POL
OR
UR
D5
B8
B4
PA0
PA1
PA2
1Y
2Y
3Y
1B
2B
3B
SEL
1A
2A
INT
11
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
+
8
3
TC835
+
D
A
157
10
LH0084
9
INPUT
3A
B2
D
B
14
–
16
6522
-VIA-
PA3
PA4
PA5
PA6
PA7
CA1
CA2
B1
D1
D2
D3
D4
STB
R/H
f
WR
15
V
R
REF
VOLTAGE
A
A
EN
0
1
–
INPUT
DIFFERENTIAL
MULTIPLEXER
ANALOG
COMMON
DGND
IN
f
IN
GAIN SELECTION
–
5V
PB5
PB4
PB0 PB1 PB2 PB3
CHANNEL SELECTION
TC835-8 11/5/96
TELCOM SEMICONDUCTOR, INC.
3-65
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
Package Power Dissipation (TA ≤ 70°C)
ABSOLUTE MAXIMUM RATINGS* (Note 1)
28-Pin Plastic DIP.............................................1.14W
44-Pin PQFP ....................................................1.00W
64-Pin PFP .......................................................1.14W
Positive Supply Voltage ............................................. +6V
Negative Supply Voltage............................................ - 9V
Analog Input Voltage (Pin 9 or 10) ........ V+ to V– (Note 2)
Reference Input Voltage (Pin 2) .......................... V+ to V–
Clock Input Voltage ............................................. 0V to V+
Operating Temperature Range .................... 0°C to +70°C
Storage Temperature Range ................ – 65°C to +150°C
Lead Temperature (Soldering, 10 sec) ................. +300°C
*Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS: TA = +25°C, fCLOCK = 200 kHz, V+ = +5V, V– = – 5V, unless otherwise specified.
Symbol Parameter
Analog
Test Conditions
Min
Typ
Max
Unit
Display Reading With
Zero Volt Input
Notes 3 and 4
–0.0000
±0.0000
0.5
+0.0000
Display
Reading
TCZ
Zero Reading
Temperature Coefficient
VIN = 0V
Note 5
—
—
2
5
µV/°C
TCFS
Full-Scale
VIN = 2V
—
ppm/°C
Temperature Coefficient
Notes 5 and 6
NL
Nonlinearity Error
Note 7
Note 7
—
—
0.5
0.01
1
—
Count
LSB
DNL
Differential Linearity Error
Display Reading in
Ratiometric Operation
VIN = VREF
Note 3
+0.9996
+0.9998
+1.0000
Display
Reading
±FSE
± Full-Scale Symmetry
Error (Roll-Over Error)
–VIN = +VIN
Note 8
—
0.5
1
Count
IIN
Input Leakage Current
Noise
Note 4
—
—
1
10
—
pA
eN
Peak-to-Peak Value Not Exceeded 95% of Time
15
µVP-P
Digital
IIL
Input Low Current
Input High Current
Output Low Voltage
VIN = 0V
—
—
—
10
0.08
0.2
100
10
µA
µA
V
IIH
VIN = +5V
IOL = 1.6 mA
VOL
VOH
0.4
Output High Voltage
B1, B2, B4, B8, D1–D5
Busy, Polarity, Overrange, IOH = 10 µA
IOH = 1 mA
2.4
4.9
4.4
4.99
5
5
V
V
Underrange, Strobe
fCLK
Clock Frequency
Note 10
0
200
1200
kHz
Power Supply
V+
V–
I+
Positive Supply Voltage
4
5
6
– 8
3
V
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
– 3
—
—
—
– 5
1
V
fCLK = 0 Hz
fCLK = 0 Hz
fCLK = 0 Hz
mA
mA
mW
I–
0.7
8.5
3
PD
30
7. – 2V ≤ VIN ≤ +2V. Error of reading from best fit straight
line.
NOTES: 1. Functional operation is not implied.
2. Limit input current to under 100 µA if input voltages exceed supply
8. |VIN| = 1.9959.
voltage.
9. Test circuit shown in Figure 1.
3. Full-scale voltage = 2V.
10. Specification related to clock frequency range over which
the TC835 correctly performs its various functions.
Increased errors result at higher operating frequencies.
4. VIN = 0V.
5. 0°C ≤ TA ≤ +70°C.
6. External reference temperature coefficient less than 0.01 ppm/°C.
3-66
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
3
TC835
PIN CONFIGURATIONS
–
UNDERRANGE
28
V
1
2
44 43 42 41 40 39 38 37 36 35 34
27 OVERRANGE
REF IN
NC
33
32
31
30
29
28
27
26
25
24
1
2
3
4
NC
NC
ANALOG
COM
26
25
24
23
22
21
20
19
18
17
16
STROBE
RUN/HOLD
DIGTAL GND
POLARITY
CLOCK IN
BUSY
3
INT OUT
AZ IN
INT OUT
4
RUN/HOLD
DGND
5
AZ IN
BUFF OUT
REF CAP–
BUFF OUT
–
6
5
6
POLARITY
CLK IN
BUSY
D1 (LSD)
D2
C
7
REF
TC835CPI
+
REF CAP+
–INPUT
C
8
TC835CKW
REF
7
–
9
D1 (LSD)
D2
INPUT
+INPUT
V+
8
+
10
11
12
13
14
INPUT
+
9
D3
V
NC
10
11
NC
D4
(MSD) D5
(LSB) B1
B2
NC
23 NC
B8 (MSD)
B4
15
19 20 21 22
12 13 14 15 16 17 18
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC
NC
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
NC
NC
NC
NC
NC
NC
3
4
D3
D4
5
6
B3
B4
7
OVERRANGE
8
UNDERRANGE
B2
SUB
B1
9
TC835CBU
SUB
10
11
12
13
14
15
16
V–
REF IN
NOTES 1 & 2
D5
ANALOG COM
NC
NC
NC
NC
NC
NC
NC
NC
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES:
1. NC = No internal connection.
2. Pins 9, 25, 40 and 56 are connected to the die substrate.
The potential at these pins is approximately V . No
external connections should be made.
+
TELCOM SEMICONDUCTOR, INC.
3-67
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
–5V
SET V
= 1V
REF
IN
1
2
3
4
V
REF
–
V
28
ANALOG
UNDERRANGE
OVERRANGE
STROBE
INPUT BUFFER
SW
I
100 kΩ
REF IN
27
26
25
24
23
22
21
20
19
C
R
INT
+
+
–
INT
IN
ANALOG
COMMON
–
+
SW
SW
RI
RI
ANALOG GND
C
RUN/HOLD
SZ
INT OUT
0.47
µF
1 µF
SW
SW
Z
5
6
IZ
DIGTAL GND
POLARITY
CLOCK IN
BUSY
AZ IN
–
+
C
COMPARATOR
SW
REF
R
+
REF
IN
BUFF OUT
100 kΩ
100
kΩ
7
8
9
–
CLOCK
INPUT
120 kHz
–
TO
C
REF
SIGNAL
INPUT
DIGITAL
SECTION
INTEGRATOR
1 µF
SW
SW
+
C
Z
Z
+
RI
–
REF
SW
SW
RI
–
INPUT
(LSD) D1
D2
ANALOG
COM
0.1 µF
10
11
12
13
14
+
INPUT
+
SW
TC835
18
1
SW
I
SWITCH OPEN
D3
+
5V
V
–
IN
SWITCH CLOSED
17
16
15
D5 (MSD)
D4
(MSB) B8
B4
B1 (LSB)
B2
Figure 3B. System Zero Phase
Figure 1. Test Circuit
ANALOG
INPUT BUFFER
+
SW
I
V
C
R
INT
INT
+
+
–
IN
–
+
RI
SW
SW
RI
C
SZ
SW
SW
Z
IZ
–
+
C
COMPARATOR
SW
REF
R
+
REF
IN
BUFFER
–
TO
DIGITAL
SECTION
INTEGRATOR
LOGIC
INPUT
SW
SW
Z
Z
+
RI
–
SW
SW
RI
ANALOG
COM
SW
1
SW
I
SWITCH OPEN
–
IN
SWITCH CLOSED
Figure 2. Digital Logic Input
Figure 3C. Input Signal Integration Phase
ANALOG
ANALOG
INPUT BUFFER
SW
SW
I
INPUT BUFFER
SW
I
C
R
INT
+
+
–
INT
IN
C
R
INT
+
+
–
IN
INT
–
+
SW
SW
RI
RI
–
+
RI
SW
SW
C
RI
SZ
C
SZ
SW
SW
Z
IZ
SW
SW
–
+
COMPARATOR
IZ
Z
C
REF
R
+
–
+
COMPARATOR
REF
IN
C
SW
REF
R
+
REF
IN
–
TO
DIGITAL
SECTION
–
INTEGRATOR
TO
DIGITAL
SECTION
SW
SW
Z
Z
INTEGRATOR
+
RI
–
SW
SW
SW
SW
Z
Z
RI
+
RI
–
SW
SW
ANALOG
COM
RI
ANALOG
COM
SW
1
SW
I
SWITCH OPEN
SW
1
SW
–
IN
SWITCH CLOSED
I
–
IN
Figure 3D. Reference Voltage Integration Cycle
Figure 3A. Analog Circuit Function Diagram
3-68
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
3
TC835
The dual-slope converter accuracy is unrelated to the
integratingresistorandcapacitorvalues, aslongastheyare
stable during a measurement cycle. An inherent benefit is
noiseimmunity. Noisespikesareintegrated, oraveraged, to
zero during the integration periods. Integrating ADCs are
immune to the large conversion errors that plague succes-
sive approximation converters in high-noise environments.
(See Figure 4.)
ANALOG
INPUT BUFFER
SW
I
C
R
Z
INT
+
+
INT
IN
–
–
+
SW
SW
C
RI
RI
C
SZ
SW
IZ
SW
–
+
COMPARATOR
SW
REF
R
+
REF
IN
–
TO
DIGITAL
SECTION
INTEGRATOR
SW
SW
Z
Z
+
RI
–
SW
SW
RI
TC835 Operational Theory
ANALOG
COM
The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced system
errors, fewer calibration steps, and a shorter overrange
recovery time result.
SW
1
SW
I
SWITCH OPEN
–
IN
SWITCH CLOSED
Figure 3E. Integrator Output Zero Phase
The TC835 measurement cycle contains four phases:
GENERAL THEORY OF OPERATION
(All Pin Designations Refer to 28-Pin DIP)
Dual-Slope Conversion Principles
(1) System zero
(2) Analog input signal integration
(3) Reference voltage integration
(4) Integrator output zero
The TC835 is a dual-slope, integrating analog-to-digital
converter. An understanding of the dual-slope conversion
technique will aid in following the detailed TC835 opera-
tional theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
Internal analog gate status for each phase is shown in
Table 1.
ANALOG
INPUT
(1) Input signal integration
(2) Reference voltage integration (deintegration)
INTEGRATOR
SIGNAL
–
COMPARATOR
–
+
The input signal being converted is integrated for a fixed
time period. Time is measured by counting clock pulses. An
opposite polarity constant reference voltage is then inte-
grateduntiltheintegratoroutputvoltagereturnstozero. The
referenceintegrationtimeisdirectlyproportionaltotheinput
signal.
Inasimpledual-slopeconverter,acompleteconversion
requires the integrator output to "ramp-up" and "ramp-
down."
+
SWITCH
DRIVER
CLOCK
PHASE
CONTROL
REF
VOLTAGE
CONTROL
LOGIC
POLARITY CONTROL
COUNTER
Asimplemathematicalequationrelatestheinputsignal,
reference voltage, and integration time:
DISPLAY
V
V
IN Ϸ
IN Ϸ
V
FULL SCALE
1/2 V
tSI
1
VR tRI
RC
,
FULL SCALE
VIN(t) dt =
∫
RC
0
FIXED VARIABLE
where:
VR = Reference voltage
tSI = Signal integration time (fixed)
SIGNAL REFERENCE
INTEGRATE INTEGRATE
TIME TIME
Figure 4. Basic Dual-Slope Converter
tRI = Reference voltage integration time (variable).
For a constant VIN:
tRI
VIN = VR
.
]
[
tSI
TELCOM SEMICONDUCTOR, INC.
3-69
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
Table 1. Internal Analog Gate Status
Conversion
Internal Analog Gate Status
Reference
Schematic
Cycle Phase
SWI
SWR+I
SWR–I
SWZ
SWR
SW1
SWIZ
System Zero
Closed
Closed
Closed
3B
3C
Input Signal
Integration
Closed
Reference Voltage
Integration
Closed*
Closed
Closed
3D
3E
Integrator
Closed
Output Zero
*NOTE: Assumes a positive polarity input signal. SWR–I would be closed for a negative input signal.
Analog Section Functional Description
System Zero (Figure 3B)
During this phase, errors due to buffer, integrator, and
comparator offset voltages are compensated for by charg-
ing CAZ (auto-zero capacitor) with a compensating error
voltage. With a zero input voltage the integrator output will
remain at zero.
The external input signal is disconnected from the
internal circuitry by opening the two SWI switches. The
internal input points connect to ANALOG COMMON. The
reference capacitor charges to the reference voltage poten-
tial through SWR. A feedback loop, closed around the
integrator and comparator, charges the CAZ capacitor with a
voltage to compensate for buffer amplifier, integrator, and
comparator offset voltages.
(In Reference to the 28-Pin Plastic Package)
Differential Inputs
(+INPUT, Pin 10 and –INPUT, Pin 9)
The TC835 operates with differential voltages within the
input amplifier common-mode range. The input amplifier
common-mode range extends from 0.5V below the positive
supply to 1V above the negative supply. Within this com-
mon-mode voltage range, an 86 dB common-mode rejec-
tion ratio is typical.
The integrator output also follows the common-mode
voltage. The integrator output must not be allowed to satu-
rate. A worst-case condition exists, for example, when a
large positive common-mode voltage with a near full-scale
negative differential input voltage is applied. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common-mode
voltage. For these critical applications the integrator swing
can be reduced to less than the recommended 4V full-scale
swing,withsomelossofaccuracy.Theintegratoroutputcan
swing within 0.3V of either supply without loss of linearity.
Analog Input Signal Integration (Figure 3C)
The TC835 integrates the differential voltage between
the +INPUT and –INPUT pins. The differential voltage must
be within the device common-mode range; - 1V from either
supply rail, typically.
The input signal polarity is determined at the end of this
phase.
Reference Voltage Integration (Figure 3D)
ANALOG COMMON Input (Pin 3)
The previously-charged reference capacitor is con-
nected with the proper polarity to ramp the integrator output
back to zero. The digital reading displayed is:
ANALOG COMMON is used as the –INPUT return
duringauto-zeroanddeintegrate. If–INPUTisdifferentfrom
ANALOG COMMON, a common-mode voltage exists in the
system. This signal is rejected by the excellent CMRR of the
converter.Inmostapplications,–INPUTwillbesetatafixed,
known voltage (power supply common, for instance). In this
application, ANALOG COMMON should be tied to the same
point, thus removing the common-mode voltage from the
converter. The reference voltage is referenced to ANALOG
COMMON.
Differential Input
Reading = 10,000
.
[
VREF
]
Integrator Output Zero (Figure 3E)
This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the true
system offset voltages are compensated for. This phase
normally lasts 100 to 200 clock cycles. If an overrange
conditionexists, thephaseisextendedto6200clockcycles.
REFERENCE Voltage Input (REF IN, Pin 2)
TheREFINinputmustbeapositivevoltagewithrespect
to ANALOG COMMON. Two reference voltage circuits are
shown in Figure 5.
3-70
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
3
TC835
+
POLARITY
D5
MSB
D4
D3
D2
D1
V
13 B1
14 B2
DIGIT
DRIVE
SIGNAL
LSB
+
V
DATA
OUTPUT
MULTIPLEXER
15 B4
16 B8
FROM
REF
IN
ANALOG
SECTION
6.8V
ZENER
LATCH
LATCH
LATCH
LATCH
LATCH
POLARITY
FF
TC835
I
Z
ANALOG
COMMON
COUNTERS
ZERO
CROSS
DETECT
CONTROL LOGIC
27
24
22
25
28
26
21
BUSY
–
V
DIGITAL CLOCK
GND IN
RUN/
HOLD
OVER–
RANGE
UNDER–
RANGE
STROBE
+
V
6.8 kΩ
Figure 6. Digital Section Functional Diagram
+
V
TC04
REF
IN
INTEGRATOR
OUTPUT
20
kΩ
1.25V REF
SIGNAL
INTE
10,000
COUNTS
(FIXED)
TC835
SYSTEM
ZERO
REFERENCE
INTEGRATE
20,001
10,001
COUNTS
COUNTS (MAX)
ANALOG
COMMON
FULL MEASUREMENT CYCLE
40,002 COUNTS
ANALOG
GROUND
BUSY
OVERRANGE
WHEN
APPLICABLE
Figure 5. Using an External Reference
UNDERRANGE
WHEN
Digital Section Functional Description
APPLICABLE
EXPANDED SCALE
BELOW
The major digital subsystems within the TC835 are
illustrated in Figure 6, with timing relationships shown in
Figure7. ThemultiplexedBCDoutputdatacanbedisplayed
on LCD or LED display with the TC7211A (LCD)
4-digit display driver.
DIGIT SCAN
D5
D4
D3
D2
The digital section is best described through a discus-
sion of the control signals and data outputs.
D1
100
COUNTS
FIRST D5 OF SYSTEM ZERO
AND REFERENCE INTEGRATE
ONE COUNT LONGER.
*
RUN/HOLD Input (Pin 25)
STROBE
When left open, this pin assumes a logic "1" level. With
a R/H = 1, the TC835 performs conversions continuously,
with a new measurement cycle beginning every 40,002
clock pulses.
When R/H changes to a logic "0," the measurement
cycle in progress will be completed, and data held and
displayed as long as the logic "0" condition exists.
A positive pulse (>300nsec) at R/H initiates a new
measurement cycle. The measurement cycle in progress
when R/H initially assumed the logic "0" state must be
completed before the positive pulse can be recognized as a
single conversion run command.
AUTO ZERO
REFERENCE
INTEGRATE
SIGNAL
INTEGRATE
*
DIGIT SCAN
FOR
OVERRANGE
D5
D4
D3
D2
*
D1
Figure 7. Timing Diagrams for Outputs
TELCOM SEMICONDUCTOR, INC.
3-71
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
The new measurement cycle begins with a 10,001-
count auto-zero phase. At the end of this phase the busy
signal goes high.
TC835
OUTPUTS
BUSY
END OF CONVERSION
STROBE Output (Pin 26)
*
B1–B8
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur in the
center of the digit drive signals (D1, D2, D3, D5, Figure 8).
D5 (MSD) goes high for 201 counts when the measure-
ment cycles end. In the center of the D5 pulse, 101 clock
pulses after the end of the measurement cycle, the first
STROBE occurs for one-half clock pulse. After the D5 digit
strobe, D4 goes high for 200 clock pulses. The STROBE
goeslow100clockpulsesafterD4 goeshigh.Thiscontinues
through the D1 digit drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE pulses are not repeated until a new
measurement is completed. The digit drive signals will not
continue if the previous signal resulted in an overrange
condition.
D3
D2
D1 (LSD)
DATA
D5
D5 (MSD)
DATA
D4
DATA
DATA
DATA
DATA
STROBE
NOTE ABSENCE
OF STROBE
200
COUNTS
201
COUNTS
200
COUNTS
D5
D4
D3
200
COUNTS
200
COUNTS
200
COUNTS
D2
D1
TheactivelowSTROBEpulsesaidBCDdatatransferto
UARTs, processors and external latches. (See Application
Note 16.)
200
COUNTS
*
DELAY BETWEEN BUSY GOING LOW AND FIRST STROBE
PULSE IS DEPENDENT ON ANALOG INPUT.
BUSY Output (Pin 21)
Figure 8. Strobe Signal Pulses Low Five Times per Conversion
At the beginning of the signal-integration phase, BUSY
goeshighandremainshighuntilthefirstclockpulseafterthe
integrator zero crossing. BUSY returns to the logic "0" state
after the measurement cycle ends in an overrange condi-
tion. The internal display latches are loaded during the first
clock pulse after BUSY, and are latched at the clock pulse
end. The BUSY signal does not go high at the beginning of
the measurement cycle, which starts with the auto-zero
cycle.
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal polarity
determined correctly. This is useful in null applications.
DIGIT Drive Outputs (Pins 12, 17, 18, 19 and 20)
Digit drive signals are positive-going signals. The scan
sequenceisD5 toD1.Allpositivepulsesare200clockpulses
wide, except D5, which is 201 clock pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE pulse until
the beginning of the next reference-integrate phase. The
scanning sequence is then repeated. This provides a blink-
ing visual display indication.
OVERRANGE Output (Pin 27)
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVERRANGE
output is set to a logic "1." The overrange output register is
setwhenBUSYgoeslow, andisresetatthebeginningofthe
next reference-integration phase.
BCD Data Outputs (Pins 13, 14, 15 and 16)
UNDERRANGE Output (Pin 28)
The binary coded decimal (BCD) bits B8, B4, B2, B1, are
positive-true logic signals. The data bits become active
simultaneously with the digit drive signals. In an overrange
condition, all data bits are at a logic "0" state.
If the output count is 9% of full scale or less (≤1800
counts), the underrange register bit is set at the end of
BUSY. Thebitissetlowatthenextsignal-integrationphase.
POLARITY Output (Pin 23)
Apositiveinputisregisteredbyalogic"1"polaritysignal.
The polarity bit is valid at the beginning of reference inte-
grate and remains valid until determined during the next
conversion.
3-72
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
3
TC835
APPLICATIONS INFORMATION
Component Value Selection
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this
reason, it is recommended that a high-quality reference be
used where high-accuracy absolute measurements are
being made. Suitable references are:
The integrating resistor is determined by the full-scale
input voltage and the output current of the buffer used to
chargetheintegratorcapacitor.Boththebufferamplifierand
the integrator have a class A output stage, with 100 µA of
quiescent current. A 20 µA drive current gives negligible
linearity errors. Values of 5 µA to 40 µA give good results.
The exact value of an integrating resistor for a 20 µA current
is easily calculated.
Part Type
Manufacturer
TC04A
TC9491
TelCom Semiconductor
TelCom Semiconductor
full-scale voltage
Conversion Timing
RINT
=
20 µA
Line Frequency Rejection
A signal integration period at a multiple of the 60 Hz line
frequency will maximize 60 Hz "line noise" rejection.
A 200 kHz clock frequency will reject 60 Hz and 400 Hz
noise. This corresponds to five readings per second.
Integrating Capacitor
The product of integrating resistor and capacitor should
beselectedtogivethemaximumvoltageswingthatensures
the tolerance buildup will not saturate the integrator swing
(approximately 0.3V from either supply). For ±5V supplies
and ANALOG COMMON tied to supply ground, a ±3.5V to
±4Vfull-scaleintegratorswingisadequate.A0.10µFto0.47
µFisrecommended.Ingeneral,thevalueofCINT isgivenby:
Conversion Rate vs Clock Frequency
Oscillator Frequency
(kHz)
Conversion Rate
(Conv/Sec)
[10,000 × clock period] × IINT
100
120
200
300
400
800
1200
2.5
3
5
7.5
10
20
30
CINT
=
=
Integrator output voltage swing
(10,000) (clock period) (20 µA)
Integrator output voltage swing
Averyimportantcharacteristicoftheintegratingcapaci-
tor is that it has low dielectric absorption to prevent rollover
or ratiometric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference. This
ratiometric condition should read half-scale 0.9999, any
deviation is probably due to dielectric absorption. Polypro-
pylene capacitors give undetectable errors at reasonable
cost.Polystyreneandpolycarbonatecapacitorsmayalsobe
used in less critical applications.
Line Frequency Rejection
Oscillator Frequency
(kHz)
60 Hz
50 Hz
400 Hz
50.000
53.333
•
•
—
—
—
•
•
•
•
•
•
•
•
•
•
•
•
—
•
66.667
80.000
—
—
•
83.333
Auto-Zero and Reference Capacitors
100.000
125.000
133.333
166.667
200.000
250.000
•
The size of the auto-zero capacitor has some influence
on the noise of the system. A large capacitor reduces the
noise. Thereferencecapacitorshouldbelargeenoughsuch
that stray capacitance to ground from its nodes is negligible.
The dielectric absorption of the reference capacitor and
auto-zero capacitor are only important at power-on, or when
thecircuitisrecoveringfromanoverload.Smallerorcheaper
capacitors can be used if accurate readings are not required
for the first few seconds of recovery.
—
—
—
•
•
—
—
—
•
—
The conversion rate is easily calculated:
Conversion Rate
Reference Voltage
Clock Frequency (Hz)
(Readings 1/sec) =
4000
Theanaloginputrequiredtogenerateafull-scaleoutput
is VIN = 2 VREF
.
TELCOM SEMICONDUCTOR, INC.
3-73
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
For many dedicated applications where the input signal
is always of one polarity, the delay of the comparator need
not be a limitation. Since the nonlinearity and noise do not
increase substantially with frequency, clock rates of up to
~1 MHz may be used. For a fixed clock frequency, the extra
count or counts caused by comparator delay will be a
constant and can be subtracted out digitally.
The clock frequency may be extended above 200 kHz
without this error, however, by using a low-value resistor in
series with the integrating capacitor. The effect of the
resistor is to introduce a small pedestal voltage on to the
integrator output at the beginning of the reference integrate
phase. By careful selection of the ratio between this resistor
and the integrating resistor (a few tens of ohms in the
recommended circuit), the comparator delay can be com-
pensated and the maximum clock frequency extended by
approximately a factor of 3. At higher frequencies, ringing
andsecond-orderbreakswillcausesignificantnonlinearities
in the first few counts of the instrument.
Power Supplies and Grounds
Power Supplies
The TC835 is designed to work from ±5V supplies. For
single +5V operation, a TC7660 can provide a – 5V supply.
Grounding
Systems should use separate digital and analog ground
systems to avoid loss of accuracy.
Displays and Driver Circuits
TelCom Semiconductor manufactures two display de-
coder/drivercircuitstointerfacetheTC835toanLCDorLED
display.Eachdrivehas28outputsfordrivingfour7-segment
digit displays.
Device
Package
Description
TC7211AIPL
40-Pin Epoxy
4-Digit LCD Driver/Decoder
Theminimumclockfrequencyisestablishedbyleakage
on the auto-zero and reference capacitors. With most de-
vices, measurement cycles as long as 10 seconds give no
measurable leakage error.
Several sources exist for LCD and LED display:
Display
Manufacturer
Address
Type
The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators are
shown in the applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.
Hewlett Packard
Components
640 Page Mill Rd.
Palo Alto, CA 94304
LED
Litronix, Inc.
19000 Homestead Rd.
Cupertino, CA 94010
LED
AND
720 Palomar Ave.
Sunnyvale, CA 94086
LCD and
LED
Zero-Crossing Flip-Flop
Epson America, Inc.
3415 Kanhi Kawa St.
Torrance, CA 90505
LCD
The flip-flop interrogates the data once every clock
pulse after the transients of the previous clock pulse and
half-clockpulsehavedieddown.Falsezero-crossingscaused
by clock pulses are not recognized. Of course, the flip-flop
delays the true zero-crossing by up to one count in every
instance, and if a correction were not made, the display
would always be one count too high. Therefore, the counter
is disabled for one clock pulse at the beginning of the
reference integrate (deintegrate) phase. This one-count
delay compensates for the delay of the zero-crossing flip-
flop, and allows the correct number to be latched into the
display. Similarly, a one-count delay at the beginning of
auto-zerogivesanoverloaddisplayof0000insteadof0001.
Nodelayoccursduringsignalintegrate,sothattrueratiometric
readings result.
High-Speed Operation
The maximum conversion rate of most dual-slope A/D
converters is limited by the frequency response of the
comparator. The comparator in this circuit follows the inte-
grator ramp with a 3 µsec delay, and at a clock frequency of
200 kHz (5 µsec period), half of the first reference integrate
clock period is lost in delay. This means that the meter
reading will change from 0 to 1 with a 50 µV input, 1 to 2 with
150 µV, 2 to 3 at 250 µV, etc. This transition at midpoint is
considered desirable by most users; however, if the clock
frequency is increased appreciably above 200 kHz, the
instrument will flash "1" on noise peaks even when the input
is shorted.
3-74
TELCOM SEMICONDUCTOR, INC.
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
3
TC835
TYPICAL APPLICATIONS DIAGRAMS
4-1/2 Digit ADC With Multiplexed Common Anode LED Display
+5V
20 19
18 17 12
D1 D2 D3 D4 D5
INT OUT
4
5
0.33µF
1 µF
AZ IN
4.7 kΩ
23
7
POL
6
BUFF
OUT
b
c
7
7
7
7
–
C
100 kΩ
REF
22
10
TC835
f
200 kHz
1 µF
IN
+
X7
8
C
BLANK MSD ON ZERO
6
REF
100 kΩ
+
+INPUT
9–15
5
ANALOG
16
15
14
13
1 µF
D
INPUT
B8
9
3
RBI
7447
–INPUT
2
1
7
–
C
B
A
B4
B2
B1
16
+5V
ANALOG
COMMON
REF
–
+
V
V
IN
1
2
11
6.8 kΩ
–5V
100 kΩ
TC04
Comparator Clock Circuits
RC Oscillator Circuit
+5V
R
R
2
1
C
16 kΩ
1 kΩ
f
O
56 kΩ
2
3
+
8
V
OUT
0.22 µF
GATES ARE 74C04
7
LM311
–
1
R1 R2
1
30 kΩ
1. fO =
, RP =
4
R1 + R2
16 kΩ
2 C(0.41 RP + 0.7 R1)
390 pF
a. If R1 = R2 = R1, f 0.55/RC
b. If R2 >> R1, f 0.45/R1C
c. If R2 << R1, f 0.72/R1C
+5V
R2
100 kΩ
R4
2 kΩ
2. Examples:
C2
a. f = 120 kHz, C = 420 pF
2
3
+
6
10 pF
7
R2
R1 = R2 ≈ 10.9 kΩ
V
LM311
OUT
100 kΩ
–
4
R3
b. f = 120 kHz, C = 420 pF, R2 = 50 kΩ
R1 = 8.93 kΩ
1
50 kΩ
C1
0.1 µF
c. f = 120 kHz, C = 220 pF, R2 = 5 kΩ
R1 = 27.3 kΩ
TELCOM SEMICONDUCTOR, INC.
3-75
PERSONAL COMPUTER
DATA ACQUISITION A/D CONVERTER
TC835
TYPICAL APPLICATIONS DIAGRAMS
4-1/2 Digit ADC with Multiplexed Common Cathode LED Display
+5V
+5V
SET V
= 1V
REF
–5V
6.8V
28
27
26
1
–
V
UR
OR
100
kΩ
2
3
TC04
1.22V
REF IN
150Ω
ANALOG
GND
STROBE
47
kΩ
10
11
9
8
7
6
5
4
3
2
1
ANALOG
GND
150Ω
25
24
23
22
21
20
4
5
6
7
8
9
INT
RUN/HOLD
DGND
OUT
1 µF
0.33 µF
12
13
14
15
AZ IN
BUFF
OUT
CD4513
BE
POLARITY
100 kΩ
+
C
CLK IN
BUSY
(LSD) D1
D2
REF
1 µF
100
kΩ
–
C
REF
+5V
16
17
+
–INPUT
+INPUT
SIG
0.1
µF
10
11
12
19
18
17
IN
–
18
+
+5V
D3
V
TC835
D4
D5 (MSD)
13
14
16
15
(MSB) B8
B4
B1 (LSB)
B2
f
= 200 kHz
OSC
+5V
4-1/2 DIGIT LCD
SEGMENT
DRIVE
1/2 CD4030
–5V
5
1
23
POL
BP
D1
–
20
V
CD4081
1/4 CD4030
31
32
33
34
D1
D2
D3
D4
4
INT OUT
19
18
17
0.33 µF
1 µF
D2
D3
D4
5
6
AZ IN
BUFF OUT
100 kΩ
16
CD4071
TC7211A
22
30
29
28
27
B8
200 kHz
+
f
B3
B2
B1
B0
IN
TC835
15
14
B4
B2
B1
100 kΩ
1
+
10
9
V
+INPUT
–INPUT
35
GND
ANALOG
INPUT
–
13
12
D
Negative Supply Voltage Generator
D5
Q
1/2
CD4013
CLK
1/4 CD4081
+5V
26
27
3
ANALOG
COMMON
STROBE
OR
11
+5V
+
S
R
1/4 CD4030
V
8
REF
IN
+
V
2
1
(–5V)
10 µF
5
–
6.8 kΩ
V
+5V
TC7660
100 kΩ
+
TC04
TC835
24
4
2
3
+
10 µF
3-76
TELCOM SEMICONDUCTOR, INC.
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