TPU3050PO [TDK]
Teletext Decoder, PDIP52, PLASTIC, DIP-52;
| 型号： | TPU3050PO |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | Teletext Decoder, PDIP52, PLASTIC, DIP-52 光电二极管 商用集成电路 |
| 文件： | 总72页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
TPU 3035,
TPU 3040,
TPU 3050
Teletext Processors
MICRONAS
Edition Feb. 23, 1999
6251-349-6PD
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
4
1.
Introduction
4
1.1.
Features
6
6
6
6
7
8
8
8
9
9
9
2.
Functional Description
Conceptional Overview
Teletext Acquisition
Teletext Page Management
Display Page Generation
WST Display Controller
Character Generator
OSD Layer
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
2.9.
2.10.
DRAM Interface
SRAM Interface
Applications
10
10
11
13
14
15
16
17
17
17
18
18
18
18
19
19
19
20
20
21
21
21
22
22
23
25
25
3.
Specifications
3.1.
Outline Dimensions
3.2.
Pin Connections and Short Descriptions
Pin Descriptions
3.3.
3.3.1.
3.4.
Pin Descriptions TPU 3050
Pin Configuration
3.5.
Pin Circuits
3.6.
Electrical Characteristics
3.6.1.
3.6.2.
3.6.3.
3.6.4.
3.6.5.
3.6.6.
3.6.7.
3.6.8.
3.6.9.
3.6.10.
3.6.11.
3.6.12.
3.6.13.
3.6.14.
3.6.15.
3.6.15.1.
3.6.15.2.
3.6.16.
3.6.16.1.
Absolute Maximum Ratings
Recommended Crystal Characteristics
General Operating Conditions
General Input Characteristics
Power Consumption
Timer, Interrupt and Watchdog Characteristics
Clock Generator Characteristics
Video Interface Characteristics
MAC Interface Characteristics
RGB Interface Characteristics
Prio and Color Interface Characteristics
H and V Sync Interface Characteristics
MSync Interface Characteristics
2
I C-Bus Interface Characteristics
DRAM Interface Characteristics
DRAM Fast Mode Timing
DRAM Slow Mode Timing
SRAM Interface Characteristics (TPU 3050 only)
SRAM Mode Timing
2
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
26
26
26
27
27
28
28
28
29
30
32
33
34
35
35
36
36
38
39
40
47
47
48
50
51
52
53
4.
Definitions
CPU
4.1.
4.1.1.
4.2.
Memory Mapping
2
I C-Bus Interface
4.2.1.
4.2.1.1.
4.2.1.2.
4.2.1.3.
4.2.1.4.
4.3.
Subaddressing
CPU Subaddressing
DRAM Subaddressing
Command Subaddressing
Data Subaddressing
Display Memory
4.4.
OSD Layer
4.5.
Character Set
4.6.
Font Structure
4.7.
Character Font
4.7.1.
4.7.2.
4.7.3.
4.7.4.
4.8.
Character Set 0
Character Set 1
Character Set 2
NTSC Character Sets
Character Mapping
Command Language
Memory Manager
Memory Organization
Page Table
4.9.
4.10.
4.11.
4.12.
4.13.
4.14.
4.15.
4.16.
Ghost Row Organization
Subpage Manager
I/O Page Definition
I/O Page Register
66
68
68
72
5.
6.
7.
8.
Application
Glossary of Abbreviations
References
Data Sheet History
MICRONAS INTERMETALL
3
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Multistandard Teletext Processor for Level 1 and 2
Release Note:
This data sheet describes functions and characteristics of TPU3040–A25 and TPU3050–C4.
If not otherwise designated, the pin numbers mentioned refer to the 44-pin PLCC package. For corresponding
PDIP and PSDIP numbers, see page 11. Revision bars indicate significant changes to the previous version.
1. Introduction
Table 1–1: Feature List
The TPU 3040 is a single chip World System Teletext
(WST) decoder for applications in analog and digital TV
sets. Based on a 65C02 core with RAM and ROM on
chip, an adaptive data slicer, a display controller, and a
number of interfaces, the TPU 3040 offers acquisition
and display of various teletext and data services such as
WST, PDC, VPS, and WSS.
TPU
3035
Acquisition
3040
3050
No. of analog comp. video
1
2
2
inputs
Clamping
x
x
x
x
x
x
–
–
x
x
x
x
x
x
–
x
x
x
x
x
x
x
–
–
AGC
1.1. Features
Sync. separation with PLL
Adaptive data slicer
Signal quality detection
PAL VBI acquisition
NTSC VBI acquisition
TheTPU3040isanintegratedcircuitdesignedinCMOS
technology. As a stand-alone system or in combination
with the DIGIT 3000 system, the TPU 3040 offers a wide
range of new and interesting features, some of them
unique in comparison with other products on the market.
The TPU 3035 is a stripped-down version of TPU 3040,
designed for low-cost applications. The basic chip archi-
tecture remains unchanged, whereas some of the more
sophisticated features are removed.
MAC VBI acquisition
(PLCC44 only)
MAC packet text acquisition
(PLCC44 only)
–
–
–
The TPU 3050 offers all features of the TPU 3040 plus
the possibility of connecting the SRAM instead of the
DRAM memory.
Full-field acquisition
–
x
–
x
–
x
Asynchronous acquisition and
display
This data sheet describes the full feature set of the
TPU 3040. Differences between TPU 3035, TPU 3040,
and TPU 3050 are denoted when necessary (see Table
1–1).
Ghost row acquisition
EPG support
x
–
–
x
x
x
x
x
x
Internal row 26 processing
(extended character sets)
FLOF/TOP s/w support on chip
PDC acquisition
x
x
x
–
–
x
x
x
x
x
x
x
x
x
x
x
x
x
VPS acquisition
WSS acquisition
US captioning
Software acquisition (ad-
vanced header, magazine
shuffle, ...)
Full parallel acquisition
x
x
x
4
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Table 1–1, continued
TPU
3035
Display
3040
3050
TPU
3035
x
3040
x
3050
x
OSD – layer independent
Display priority via
software-ID
D3000
D3000
D3000
No. of different characters
512
512
16
512
16
No. of national language
character sets
16
RGB input from SCART and
Fast Blank interface
x
x
x
Character matrix size
No. of display rows
Pixel graphics
10x10
> 26
–
10x10
10x10
Hardware cursor
–
–
–
> 26
> 26
Memory
–
x
–
x
No. of pages on-chip
No. of pages off-chip
Minimum DRAM (ext.)
Maximum DRAM (ext.)
DRAM organization
–
–
–
16:9 display
(25% shrink)
–
112
2032
2032
1/2 screen display
(50% shrink)
–
–
x
x
x
x
256 Kbit
1 Mbit
1 bit
256 Kbit
16 Mbit
1 bit
256 Kbit
16 Mbit
1 bit
1/2 screen 16:9 display
(62.5% shrink)
32 kHz mode
–
x
x
–
x
–
x
x
–
x
x
x
x
x
–
x
x
–
x
x
x
x
x
–
x
x
–
DRAM access time
(page mode)
90 ns
90 ns
90 ns
Non-interlace display
50/60 Hz display
Minimum SRAM (ext.)
Maximum SRAM (ext.)
SRAM organization
SRAM access time
–
–
–
–
x
–
–
–
–
x
256 Kbit
1 Mbit
8 bit
100/120 Hz display
Scrolling vertical
100 ns
x
Scrolling horizontal
Double height page display
Status row single height
Automatic memory/config.
check
Variable no. of subpages
(internal subpage manage-
ment)
x
x
x
Two page display side by
side
Constant page access time
x
x
x
Stable (line locked) display
with noisy video
x
x
x
Dyn. pg. storage (datacom-
pression)
–
–
–
Display synchronized by
input video
–
–
–
General Product Info
75 Ohm output
–
x
–
–
x
–
–
x
–
Supply voltage [V]
5
5
5
Half contrast RGB out
Power dissipation [mW]
Control bus
250
250
300
2
2
2
RGB level adjustable
(externally)
I C
I C
I C
IR decoder and control
Software macro interface
System clock [MHz]
Package
–
x
–
x
–
x
Level 3
Level 2
Level 2
Level 2
Level 2
DRCS
–
–
–
CLUT
D3000
D3000
D3000
20.25
PDIP40
20.25
20.25
double width
double height
full screen color
x
x
x
x
x
x
x
x
x
PLCC44 PSDIP52
PDIP40
Technology
0.8 µm
CMOS
0.8 µm
CMOS
0.8 µm
CMOS
MICRONAS INTERMETALL
5
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
2. Functional Description
2.1. Conceptional Overview
2.2. Teletext Acquisition
Theonlytaskoftheslicercircuitistoextractteletextlines
from the incoming composite video signal and to store
them into the acquisition scratch buffer of the external
DRAM. No page selection is done at this hardware level.
The basic idea behind the TPU 3040 concept is the re-
placement of random logic by software. The still existing
hardware supports the on-chip CPU in tasks with high
data rates and ineffective software solutions. Typical
tasks of a teletext decoder are listed below (realization
on TPU 3040 in brackets):
Two analog sources can be connected, thus it is pos-
sible to receive text from one channel while watching
another on the screen. After clamping and AGC amplifi-
er the analog video signal is converted into binary data.
Syncseparation is done by a sync slicer and a horizontal
PLL, which generate the horizontal and vertical timing.
By these means no external sync signals are needed
and any available signal source can be used for teletext
reception.
– teletext data acquisition
– teletext data decoding
– page generation
(hardware)
(software)
(software)
(software)
(hardware)
(software)
– page memory management
– page display
The teletext information itself is acquired using adaptive
slicers on bit and byte level with soft error detection to
decrease the bit error rate under bad reception condi-
tions. The slicer can be programmed to different bit rates
for reception of PAL, NTSC or MAC world system tele-
text as well as VPS,WSS, or CAPTION signals.
– user interface
Fig. 2–1 shows the functional block diagram of the
TPU 3040. The software approach is realized using a
65C02 core with RAM and program ROM on chip. Via
the I/O, the CPU is connected to a DRAM interface. The
DRAM contains an acquisition scratch buffer which is
filled automatically by the teletext slicer circuit. After pro-
cessing this scratch buffer, the CPU stores reorganized
teletext lines into the page memory which takes up the
greatest space in the DRAM capacity. A third part of the
DRAM holds WST level 2 display data, which are read
out by the WST layer. The CPU has to generate the dis-
play data by decoding teletext information from the page
memory.
2.3. Teletext Page Management
As a state-of-the-art teletext decoder the TPU 3040 is
able to store and manage a sufficient number of teletext
pages to absorb the annoying transmission cycle times.
The number of available pages is only limited by the
memory size. With an intelligent software and a 16 Mbit
DRAM it is possible to store and to control more than
2000 teletext pages.
Apart from the WST layer, there is also one additional
on-chip OSD layer. The OSD layer accesses the on-chip
memory to read text and character font information. The
RGB outputs of the OSD layer can have higher priority
thantheWSTlayeroutputs. Thusitispossibletooverlay
the teletext display with an additional layer for user guid-
ance.
The management of such a data base is a typical soft-
ware task and is therefore performed by the 65C02. Us-
ingafixedlengthpagetablewithoneentryforeverypos-
sible page, the software distributes the content of the
acquisition scratch buffer among the page memory. The
page size is fixed to 1 KByte, only ghost rows are
chained in 128-byte segments to avoid unused memory
space.
The CPU memory contains RAM, program ROM and
character ROM. The character ROM holds the font data
and is separated from the program ROM to save CPU
time. The CPU can still access the character ROM via
a DMA interface including wait cycles. The WST layer
and the additional OSD layer can also access the CPU
memory via the same DMA interface.
The CPU is supported by some glue logic such as timer,
watchdog and interrupt controller and communicates
2
with the outside world via the I C-Bus.
6
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
43
1
22
24
23
TPU 3040
42
MUX
ADC
Slicer
7–18
Clamping
AGC
44
3
4
5
6
19
20
2
I C-Bus
Program
RAM
Program
ROM
DRAM
Interface
65C02
Interface
21
2
Timer
Interrupt
Watchdog
Skew
Delay
DMA
Interface
WST
Layer
29
36
37
38
39
27
28
RGB &
PRIO
Interface
Sync
Interface
Character
ROM
OSD
Layer
Clock
Generator
25
26
30 31
32
33
41
40
34
35
Fig. 2–1: Functional block diagram of the TPU 3040
2.4. Display Page Generation
non-spacing attributes. This is done by using a slightly
modified stack model, in which one pointer bit for every
character location indicates the presence of additional
parallelattributes. Fig. 2–2showstheorganizationofthe
stack row buffer. In this stack model the number of non-
spacing attributes per row is limited to 40, which agrees
with the WST and CEPT specification.
A stored teletext page cannot be displayed directly, be-
cause of the row-adaptive transmission and the level 2
enhancements (row 26–29). Therefore the CPU has to
generate a display page buffer, separated into level 1
datasuchascharactercodesandspacingattributesand
into level 2 data, such as character set extension and
MICRONAS INTERMETALL
7
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Level 2 Buffer
Pointer
Level 1 Buffer
– 1-bit italics
– 1-bit shadow
1
1
1
0
1
1
0
1
1
1
Char 3 Attr.
Char 3 Attr.
Char 3 Attr.
Char 3 Attr.
Char 6 Attr.
Char 6 Attr.
Char 6 Attr.
Char 10 Attr.
Char 10 Attr.
Char 10 Attr.
0
0
1
0
0
1
0
0
0
1
Char 1
Char 2
Char 3
Char 4
Char 5
Char 6
Char 7
Char 8
Char 9
Char 10
The display controller delivers 5-bit digital color informa-
tion, a shadow signal for contrast reduction and a fast
blank signal. The color bus can be used to address ex-
ternal color-look-up-tables (CLUT) which are part of
modern digital TV systems, such as the DIGIT 3000. By
this means, the full level 2 color spectrum can be dis-
played. For simple level 1 applications only 3 bits of the
color bus are converted into analog RGB signals on
chip.
2.6. Character Generator
Characters are displayed with a 10x10 pixel resolution
in PAL and 10x8 pixel resolution in NTSC mode. Pixel
clock is 10.125 MHz, derived from the main clock of
20.25 MHz. To get 10-bit pixel information two memory
cycles are needed. The character font is part of the
mask-programmable ROM, but supplied with its own
bus structure (see Fig. 4–1). By this means the data
transfer between character ROM and teletext display
controller does not stop the CPU, which is important in
the case of doubled line frequency.
0
0
0
0
0
Char 36 Attr.
1
0
0
0
0
Char 36
Char 37
Char 38
Char 39
Char 40
Fig. 2–2: Stack Row Buffer
Both bus structures are connected via a memory inter-
face which allows cross-connections using DMA or wait
cycles. As the number of addressable characters is
1024, the maximum character font size is 12800 byte. In
this case part of the character font can be shifted into the
program ROM which causes DMA cycles. Therefore
only less frequently used characters should be placed
into the program ROM. Vice versa seldom used CPU
code can be put into the character ROM.
2.5. WST Display Controller
The display controller includes two row buffers. The first
row buffer holds a copy of a teletext row from the display
page buffer. This decreases the data rate through the
DRAM interface by a factor of 10 or 8, because new tele-
text row data is needed only after 10 lines in PAL or 8
lines in NTSC mode. The second row buffer stores all
display attributes in parallel, to allow level 2 display with-
out additional decoding.
The WST specification defines a number of 7-bit code
tables, which are filled with 96 characters only. In the G0
code table some characters have several language de-
pendent variations. Additionally characters from the G0
code table can be combined with diacritical marks from
the G2 code table (row 26). Thus it is not possible to sim-
ply transform the code tables into a continuous font
ROM without getting unused ROM space and multiple
defined character fonts.
To present a WST level 2 display, the teletext display
controller has to evaluate the following attributes in par-
allel, that is for every character location:
– 10-bit character code
– 5-bit foreground color
– 5-bit background color
– 2-bit size
The character ROM is optimized by reorganizing the
code table structure of the WSTspecification. Thewhole
character font is subdivided into blocks of 32 characters
which are mapped to the WST character sets via a mask
programmable mapping ROM (see Fig. 4–5). The char-
acter set selection is done via software.
– 5-bit flash
– 1-bit invert
2.7. OSD Layer
– 1-bit separated
– 1-bit conceal
Apart from the WST layer, there is also one additional
OSD layer on chip. The OSD layer accesses the CPU
memory via DMA to read text and character font infor-
mation. The RGB outputs of the OSD layer can have
higher priority than the WST layer outputs. Thus it is pos-
sible to overlay the teletext display with an additional lay-
er for user guidance (see Fig. 2–3).
– 1-bit underline
– 1-bit boxing/window
Additional attributes are defined to improve the display
of CAPTION and OSD text:
8
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
2.9. SRAM Interface
Full Screen Layer
The TPU 3050 is able to address either DRAM or SRAM
memories. The DRAM interface can be switched into
2
SRAM mode via I C-Bus. The SRAM interface is in-
serted between the DRAM interface and the actual
memory and demultiplexes the DRAM addresses into a
single SRAM address and arranges the serial DRAM
data into parallel data. Therefore, there is no gain in
speed when SRAM is connected and slow SRAM types
(100 ns) can be used. The internal, as well as the exter-
nal controller software, does not see any difference be-
tween DRAM and SRAM mode.
WST Layer
OSD Layer
2.10. Applications
The field of applications covers analog and digital TV
sets, set-top satellite decoders, video recorders and
home computers. For example, Fig. 2–4 shows how the
TPU 3040 fits into an analog environment. Two analog
sources are connected and the output is analog RGB,
synchronized with an external sync signal or self-timed.
Page selection and other user actions are sent to the
Fig. 2–3: Display Layer
2.8. DRAM Interface
The DRAM interface connects a standard DRAM to the
internal bus structure. The address bus is 12 bit wide,
addressing DRAMs up to 16 Mbit. Smaller DRAMs can
alsobeconnected. Themaximumdatathroughputofthe
DRAM interface is 8.82 Mbit/s. This fast mode timing is
adapted to DRAMS with page mode cycle time faster
than 85 ns. In slow mode the data rate is 6.1 Mbit/s and
the timing is adapted to DRAMS with a page mode cycle
time faster than 120 ns. The data rate calculation al-
ready takes into account the required refresh cycles.
2
TPU 3040 via I C-Bus using a high level command lan-
guage.
DRAM
The DRAM interface has to handle 3 asynchronous data
streams. The CPU needs access to every memory loca-
tion of the DRAM. During VBI the slicer writes up to 22
teletext lines of 43 bytes into the acquisition scratch
memory. Alternatively the slicer can store MAC packets
of 90 bytes into the acquisition scratch. During text dis-
play the display controller copies teletext rows from dis-
play memory into its internal row buffer.
Tuner 1
Tuner 2
R
G
B
TPU 3040
Sync
2
I C-Bus
The lower data rate of the slow mode makes some re-
strictions necessary. With 6.1 Mbit/s it is no longer possi-
ble to run slicer and display in parallel. Only MAC packet
teletext can still be acquired asynchronously because of
the lower bit rate. VBI teletext can only be acquired while
the display controller is inactive (synchronous acquisi-
tion and display).
Controller
Fig. 2–4: Stand-Alone Application
MICRONAS INTERMETALL
9
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3. Specifications
3.1. Outline Dimensions
D001/3E
SPGS0015-1/2E
40
1
21
52
1
27
20
26
±0.15
15.6
±0.1
15.6
±0.1
52
±0.1
±0.1
14
47
5±1°
6±5°
±0.1
0.27
±0.06
0.27
0°...15°
15.24
±0.1
1
±0.1
±0.1
1.25
0.5
0.457
±0.05
1.778
19 x 2.54 = 48.26
±0.1
25 x 1.778 = 44.47
Fig. 3–1:
40-pin Plastic Dual-Inline Package
(PDIP40)
Weight approx. 6 g
Dimensions in mm
Fig. 3–2:
52-Pin Plastic Shrink Dual-Inline Package
(PSDIP52)
Weight approximately 5.5 g
Dimensions in mm
± 0.1
10 x 1.27 = 12.7
±0.1
1.27
1.2 x 45°
1.1 x 45 °
6
1
40
7
39
1.6
6
2
2
8.6
5
17
29
1.9
4.05
18
28
± 0.125
± 0.1
16.5
17.525
0.1
±0.15
4.75
SPGS7003-2/3E
Fig. 3–3:
44-Pin Plastic Leaded Chip Carrier Package
(PLCC44)
Weight approximately 2.5 g
Dimensions in mm
10
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.2. Pin Connections and Short Descriptions
Pin No.
PLCC44
Pin No.
PDIP40
Pin No.
PSDIP52
Signal Name
Type
Symbol
TPU 3040
TPU 3035
TPU 3040
TPU 3040
TPU 3050
1
–
1
–
3
2
Reference Voltage Top
SRAM Data 0
Supply
VRT
D0
Input/Output
Input/Output
Input/Output
Input
–
–
1
SRAM Data 1
D1
–
–
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
–
SRAM Data 2
D2
2
40
39
38
37
36
–
Test Mode
TEST
DATA / D3
WE
3
DRAM Data / SRAM Data 3
DRAM/SRAM Write Enable
DRAM Row Address Strobe / SRAM Data 4
DRAM Column Address Strobe / SRAM Data 5
SRAM Data 6
Input/Output
Output
4
5
Output
RAS / D4
CAS / D5
D6
6
Output
–
Input/Output
Input/Output
Output
–
–
SRAM Data 7
D7
7
35
34
33
32
31
30
29
28
27
26
25
–
DRAM/SRAM Address 0
DRAM/SRAM Address 1
DRAM/SRAM Address 2
DRAM/SRAM Address 3
DRAM/SRAM Address 4
DRAM/SRAM Address 5
DRAM/SRAM Address 6
DRAM/SRAM Address 7
DRAM/SRAM Address 8
DRAM/SRAM Address 9
DRAM/SRAM Address 10
Pad Supply Voltage
Pad Ground
A0
8
Output
A1
9
Output
A2
10
11
12
13
14
15
16
17
–
Output
A3
Output
A4
Output
A5
Output
A6
Output
A7
Output
A8
Output
A9
Output
A10
PVSUP
PGND
A11
Supply
–
–
Supply
18
–
24
–
DRAM/SRAM Address 11
SRAM Address 12
Output
Output
A12
A13
A14
A15
SCL
SDA
A16
A17
A18
A19
–
–
SRAM Address 13
Output
–
–
SRAM Address 14
Output
–
–
SRAM Address 15
Output
19
20
–
23
22
–
IIC Bus Clock
Input/Output
Input/Output
Output
IIC Bus Data
SRAM Address 16
–
–
–
SRAM Address 17
Output
–
–
–
SRAM Address 18
Output
–
–
–
SRAM Address 19
Output
MICRONAS INTERMETALL
11
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Pin Connections and Short Descriptions, continued
Pin No.
PLCC44
Pin No.
PDIP40
Pin No.
PSDIP52
Signal Name
Type
Symbol
TPU 3040
TPU 3035
TPU 3040
TPU 3040
TPU 3050
–
21
22
23
24
25
–
21
–
–
–
SRAM Address 20
Infrared
Output
Input
Input
Input
Input
A20
IR
–
MAC Paket Data
MAC VBI Data
MAC Sync
MAC_PAK
MAC_VBI
MAC_SYNC
–
–
–
–
20
23
Horizontal Sync
Composite Sync 1
Main Sync
Input/Output
Output
Input
HSYNC
CSYNC1
MSYNC
26
19
22
Vertical Sync
Composite Sync 2
Input/Output
Output
VSYNC
CSYNC2
27
28
18
17
21
20
Crystal Oscillator Output
Output
XTAL2
Crystal Oscillator Input
Main Clock
Input
Input
XTAL1
CLK20
29
30
16
15
19
18
Reset
Input/Output
RESET
Fast Blank Input
Shadow
Priority Bus 0
Input
Output
Input/Output
FBIN
SHADOW
PRIO0
31
32
33
14
13
12
17
16
15
Analog Blue Input
Priority Bus 1
Input
Input/Output
BIN
PRIO1
Analog Green Input
Priority Bus 2
Input
Input/Output
GIN
PRIO2
Analog Red Input
Color Address Bus 4
Input
Output
RIN
COLOR4
34
35
36
11
10
9
14
13
12
Digital Supply Voltage
Digital Ground
Supply
Supply
DVSUP
DGND
Fast Blank Output
Color Address Bus 3
Output
Output
FBOUT
COLOR3
37
38
39
8
7
6
11
10
9
Analog Blue Output
Color Address Bus 2
Output
Output
BOUT
COLOR2
Analog Green Output
Color Address Bus 1
Output
Output
GOUT
COLOR1
Analog Red Output
Color Address Bus 0
Output
Output
ROUT
COLOR0
40
41
42
43
44
5
4
3
2
–
8
7
6
5
4
Analog Ground
Supply
Supply
Input
AGND
AVSUP
VIN1
Analog Supply Voltage
Analog Composite Video 1
Analog Signal Ground
Analog Composite Video 2
Supply
Input
SGND
VIN2
12
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.3. Pin Descriptions
Pin 25 – HSYNC Horizontal Synchronization (Fig. 3–9)
Via this input, the TPU 3040 receives the horizontal syn-
chronization signal. Either the falling or the rising edge
of this signal will start the internal horizontal timing gen-
eration.
Pin 1 – VRT Reference Voltage Top (Fig. 3–7)
This pin is connected to the internally-stabilized refer-
ence voltage of the A/D converter which is derived from
the V
supply. Pin 1 must be decoupled externally to
ASUP
Pin 26 – VSYNC Vertical Synchronization (Fig. 3–9)
Via this input, the TPU 3040 receives the vertical syn-
chronization signal. Either the falling or the rising edge
of this signal will start the internal vertical timing genera-
tion.
prevent high and low frequency noise.
Pin 2 – TEST Test Input (Fig. 3–8)
This pin is used for switching the TPU 3040 into test
mode. For normal operation this pin has to be connected
to ground.
Pin 27 and 28 – XTAL1 and XTAL2 (Fig. 3–13)
These oscillator pins are used to connect a 20.25MHz
crystal, which determines the internal clock signal. Alter-
natively, an 20.25MHz clock signal may be fed to pin 28.
Pin 3 – DATA DRAM Data Input/Output (Fig. 3–9)
This pin serves as an output for writing data into the ex-
ternal DRAM and as an input for reading data from the
external DRAM.
Pin 29 – RESET Reset Input/Output (Fig. 3–11)
This pin is used for hardware reset. The TPU 3040
watchdog generates a reset pulse which can be used to
reset external circuits.
Pin 4 – WE DRAM Write Enable Output (Fig. 3–9)
This pin supplies the Write Enable signal to the external
DRAM.
Pin 30 – FBIN Fast Blanking Input (Fig. 3–14)
This pin serves for enabling the analog RGB inputs.
Pin 5 – RAS DRAM Row Address Strobe Output
(Fig. 3–9)
This pin supplies the Row Address Strobe signal to the
external DRAM.
Pin 31 to 33 – RIN, GIN, BIN RGB Inputs (Fig. 3–15)
Via these inputs, the TPU 3040 receives analog RBG
signals, e.g. OSD or video recorder (SCART), which are
fed to the analog RBG outputs. The specified level of
these signals is 0 V to 0.7 V. For other DC levels, an AC
coupling has to be used and the internal clamping circuit
will adjust the DC level.
Pin 6 – CAS DRAM Column Address Strobe Output
(Fig. 3–9)
This pin supplies the Column Address Strobe signal to
the external DRAM.
Pins 7 to 18 – A0 to A11 DRAM Address Outputs
(Figs. 3–9 and 3–10)
These pins are used for addressing the external DRAM.
The addressing is compatible to all DRAM sizes from
64K to 16M, therefore the correct connection of pins A8
to A11 to the corresponding DRAM pins is necessary.
Pin 34 – DVSUP Digital Supply Voltage
This pin supplies all digital stages and has to be con-
nected with the positive supply voltage.
Pin 35 – DGND Digital Ground
This pin is the common ground connection of all digital
stages and has to be connected with the ground of the
power supply.
Pins 19 and 20 – SCL and SDA IIC Bus (Fig. 3–11)
Via these pins, the TPU 3040 communicates with exter-
nal devices.
Pin 36 – FBOUT Fast Blanking Output (Fig. 3–10)
This output supplies a fast switching signal, indicating
the presence of RBG output signals.
Pin 21 – IR Infrared (Fig. 3–12)
This pin has to be connected to ground.
Pin 37 to 39 – ROUT, GOUT, BOUT RGB Outputs
(Fig. 3–15)
These outputs either supply the analog RGB signals,
which have been received via the analog RGB input pins
31 to 33, or the internally generated RGB signals.
Pin 22 – MAC_PAK MAC Paket Data (Fig. 3–12)
Via this pin, the TPU 3040 receives MAC packets from
the DMA 2381 or from the DMA 2386.
Pin 23 – MAC_VBI MAC VBI Data (Fig. 3–12)
By means of this input, the TPU 3040 receives MAC VBI
data from the DMA 2381 or from the DMA 2386.
Pin 40 – AGND Analog Ground
This pin is the common ground connection of all analog
stages and has to be connected with the ground of the
power supply.
Pin 24 – MAC_SYNC MAC Synchronization (Fig. 3–12)
By means of this input, the TPU 3040 receives the re-
quired MAC synchronization pulse from the DMA 2381.
This sync pulse is used both as line sync and frame sync
for the MAC teletext acquisition.
Pin 41 – AVSUP Analog Supply Voltage
This pin supplies all analog stages and has to be con-
nected with the positive supply voltage.
MICRONAS INTERMETALL
13
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Pin 42 and 44 – VIN1 and VIN2 Analog Video Inputs
(Fig. 3–16)
The analog input signals carrying text data are fed to the
TPU 3040 via a clamping capacitor of 33 nF to these
pins.
Pin 43 – SGND Signal Ground
The lower end of the internal reference chain of the A/D
converter is internally connected to the pin 43.
3.3.1. Pin Descriptions TPU 3050
(pin numbers refer to 52-pin PSDIP package)
Pin 33 – PVSUP Pad Supply Voltage
This pin supplies all SRAM interface pads and has to be
connected with the positive supply voltage.
Pin 32 – PGND Pad Ground
This pin is the common ground connection of all SRAM
interface pads and has to be connected with the ground
of the power supply.
Pin 1, 2, 45 to 48, 50, 52 – D0 to D7 SRAM Data Input/
Output (Fig. 3–9)
Thesepinsserveasoutputforwritingdataintotheexter-
nalSRAMandasinputforreadingdatafromtheexternal
SRAM.
Pins 7 to 18 – A0 to A16 SRAM Address Outputs
(Figs. 3–9 and 3–10)
These pins are used for addressing the external SRAM.
The addressing is compatible to all SRAM sizes from
64K to 1M. Therefore, the correct connection of pinsA11
to A16 to the corresponding SRAM pins is necessary.
14
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.4. Pin Configuration
VRT
TEST
DATA
WE
RAS
CAS
VIN2
SGND
VIN1
AVSUP
AGND
1
VRT
SGND
40 TEST
6
5
4
3
2
1 44 43 42 41 40
DATA
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
7
39
A0
A1
A2
ROUT / COLOR0
GOUT / COLOR1
BOUT / COLOR2
FBOUT / COLOR3
DGND
3
VIN1
WE
RAS
CAS
A0
38
37
36
35
34
33
32
31
30
29
8
AVSUP
4
9
AGND
5
10
11
12
13
14
15
16
17
A3
A4
ROUT / COLOR0
GOUT / COLOR1
BOUT / COLOR2
FBOUT / COLOR3
DGND
6
7
A1
A5
A6
DVSUP
TPU 3040
A2
8
RIN / COLOR4
GIN / PRIO2
BIN / PRIO1
FBIN / PRIO0
RESET
A3
9
A7
A4
10
11
A8
DVSUP
A5
A9
RIN / COLOR4 12
GIN / PRIO2 13
A6
A10
A7
18 19 20 21 22 23 24 25 26 27 28
14
15
16
BIN / PRIO1
FBIN / PRIO0
RESET
A8
XTAL1 / CLK20
XTAL2
A11
SCL
SDA
A9
A10
A11
SCL
SDA
IR
24
23
22
21
VSYNC / CSYNC
HSYNC / MSYNC
XTAL1 / CLK20 17
XTAL2 18
IR
MAC_PAK
VSYNC / CSYNC 19
HSYNC / MSYNC 20
MAC_SYNC
MAC_VBI
Fig. 3–6: TPU 3040 in 44-pin PLCC package
Fig. 3–4: TPU 3040 in 40-pin PDIP package
1
D1
D0
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
D2
2
TEST
3
VRT
D3 / DATA
WE
VIN2
4
SGND
5
D4 / RAS
D5 / CAS
D6
VIN1
6
AVSUP
7
AGND
8
D7
A0
A1
A2
A3
A4
A5
ROUT / COLOR0
GOUT / COLOR1
BOUT / COLOR2
FBOUT / COLOR3
DGND
9
10
11
12
13
14
15
16
DVSUP
RIN / COLOR4
GIN / PRIO2
A6
A7
A8
36
35
BIN / PRIO1
FBIN / PRIO0
RESET
17
18
19
20
21
22
23
24
25
26
A9
34 A10
PVSUP
33
32
31
XTAL1 / CLK20
XTAL2
PGND
A11
VSYNC / CSYNC
HSYNC / MSYNC
A16
30 A12
29 A13
A14
A15
SDA
28
27
SCL
Fig. 3–5: TPU 3050 in 52-pin PSDIP package
MICRONAS INTERMETALL
15
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
P
off
3.5. Pin Circuits
The following figures schematically show the circuitry at
the various pins. The integrated protection structures
arenotshown. Theletter“P”meansP-channel, theletter
“N” N-channel.
Fig. 3–12:
Input Pins 22 to 24
–
+
=
V
Ref
Fig. 3–7:
Supply Pin 1
Fig. 3–13:
Output/Input Pins 27, 28
P
off
V
SUP
P
N
Fig. 3–8:
Input Pins 2 and 21
GND
=
0.7 V
Fig. 3–14: Input Pin 30
V
SUP
P
P
N
=
=
0.7 V
0.46 V
Fig. 3–9:
N
Input/Output Pins 3 to
14, 18, 25, 26
GND
Fastblank
Clamp
V
SUP
P
Fig. 3–15: Input/Output Pins 31 to 33 and 37 to 39
Fig. 3–10:
N
Output Pins 15 to 17
and 36
GND
Fig. 3–11:
Input/Output Pins 19, 20
and 29
Fig. 3–16:
Input Pins 42 and 44
16
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6. Electrical Characteristics
All voltages refer to ground.
3.6.1. Absolute Maximum Ratings
Symbol
Parameter
Pin No.
Min.
0
Max.
65
125
6
Unit
°C
°C
V
T
A
Ambient Operating Temperature
Storage Temperature
Digital Supply Voltage
Analog Supply Voltage
Digital Input Voltage
Analog Input Voltage
Output Current
–
T
–
*40
*0.3
*0.3
*0.3
*0.3
*10
S
V
DSUP
34
41
V
ASUP
6
V
V
DI
V
DSUP
)0.3
)0.3
V
V
AI
V
ASUP
V
I
O
10
mA
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the
“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi-
mum ratings conditions for extended periods may affect device reliability.
3.6.2. Recommended Crystal Characteristics
Symbol
Parameter
Pin No.
Min.
Typ.
–
Max.
65
Unit
°C
Test Conditions
T
A
Ambient Operating Temperature
Parallel Resonance Frequency
27, 28
0
–
–
f
0
20.25
–
–
MHz
ppm
C = 30 pF, T = 25 °C
L
A
∆f
Frequency Tolerance
± 50
T = 25 °C
A
f
0
∆f
f
Frequency Deviation versus
Temperature
–
–
± 50
ppm
over operating temperature
range with respect to fre-
quency at 25 °C
R
C
C
Series Resistance
–
–
30
8
Ω
r
Static Capacitance
–
–
pF
fF
0
1
D
Dynamic Capacitance
Rated Drive Level
10
–
–
30
–
P
0.2
–
mW
dB
f
f
Spurious Frequency Attenuation
3
–
0
H
MICRONAS INTERMETALL
17
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.3. General Operating Conditions
Symbol
Parameter
Pin No.
all
Min.
0
Typ.
20
Max.
65
Unit
Test Conditions
T
A
Ambient Operating Temperature
Digital Supply Voltage
Analog Supply Voltage
Clock Frequency
°C
V
V
DSUP
34
4.75
4.75
20.20
5.0
5.25
5.25
20.30
V
41
5.0
V
ASUP
CLK
f
27, 28
20.25
MHz
correct slicer operation
3.6.4. General Input Characteristics
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
I
I
Input Leakage Current
all inputs
±1
µA
V
GND ≤ V ≤ V
I SUP
C
Input Capacitance
20
pF
I
3.6.5. Power Consumption
Symbol
Parameter
Pin No.
34
Min.
Typ.
40
Max.
60
Unit
mA
Test Conditions
I
I
Digital Supply Current
Analog Supply Current
Total Power Consumption
–
–
–
DSUP
ASUP
41
20
30
mA
P
T
34,41
300
500
mW
3.6.6. Timer, Interrupt, and Watchdog Characteristics
Symbol
Parameter
Pin No.
Min.
–
Typ.
Max.
1.5
–
Unit
V
Test Conditions
V
V
V
Reset Input Low Voltage
Reset Input High Voltage
Reset Output Low Voltage
Reset Output Pulse Width
Test Input Low Voltage
Test Input High Voltage
Infrared Input Low Voltage
Infrared Input High Voltage
29
–
IL
3.0
–
–
V
IH
OL
–
0.4
–
V
I = 3mA
L
15
t
OL
–
1.618
ms
V
2
/ f
CLK
V
IL
V
IH
V
IL
V
IH
2
–
–
–
–
–
0.8
–
2.0
–
V
21
0.8
–
V
2.0
V
18
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.7. Clock Generator Characteristics
Symbol
Parameter
Pin No.
Min.
1.0
Typ.
–
Max.
3.0
Unit
Test Conditions
C = 10 nF
C
V
Clock Input Amplitude
Clock Input Frequency
Generated Clock Frequency
28
V
PP
CLK
CLK
CLK
f
f
20.20
20.20
20.25
20.25
20.30
20.30
MHz
MHz
27,28
recommended crystal
3.6.8. Video Interface Characteristics
Symbol
Parameter
Pin No.
Min.
2.6
–
Typ.
2.8
–
Max.
3.0
100
1.3
–
Unit
Test Conditions
V
V
V
I
Voltage Reference Top
Voltage Reference Top Noise
Video Input Voltage
1
V
C = 100 nF || 10 µF
L
VRT
VRTN
I
mV
C = 100 nF || 10 µF
L
PP
42, 44
0.7
–
1
V
PP
R = 75 Ω
D
Positive Clamping Current
235
6
µA
µA
V
IN
V
IN
= 0V
CLP
CLN
CR
I
I
Negative Clamping Current
Clamping Current Ratio
–
–
= V
ASUP
35
–
40
33
45
–
C
R
Recommended Coupling
Capacitance
nF
C
D
Recommended Drive Impedance
–
75
100
Ω
3.6.9. MAC Interface Characteristics
Symbol
Parameter
Pin No.
Min.
–
Typ.
Max.
0.8
–
Unit
V
Test Conditions
V
V
Input Low Voltage
Input High Voltage
22, 23, 24
–
–
IL
2.0
V
IH
MICRONAS INTERMETALL
19
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.10. RGB Interface Characteristics
Symbol
Parameter
Pin No.
Min.
0
Typ.
Max.
1.5
Unit
Test Conditions
V
I
RGB Input Voltage
External Coupling Capacitance
31, 32, 33
0 to 0.7
V
R = 75 Ω
L
C
R
100
–
-
1000
100
nF
Ω
R > 100k Ω
L
C
RGB Input Resistance during
Clamping
–
clamp window = 64 µs
CL
V
V
V
V
V
Fast Blank Input Low Voltage
Fast Blank Input High Voltage
RGB Output Low Voltage
30
–
–
0.5
–
V
R = 75 Ω
L
IL
0.9
0
–
V
R = 75 Ω
L
IH
37, 38, 39
–
50
770
513
50
10
10
10
mV
mV
mV
mV
ns
%
V
= 5.0 V, I = 0.5 mA
OL
ASUP L
RGB Output High Voltage
630
420
–
700
467
–
V
= 5.0 V, I = *0.5 mA
OH100
OH66
ASUP L
RGB Output High Voltage
V
= 5.0 V, I = *0.5 mA
ASUP L
∆V
Differential RGB Output Voltage
RGB Output Transition Time
RGB Output Positive Overshoot
V
= 5.0 V, ∆I t10 µA
O
ASUP L
t
T
–
–
V
= 5.0 V, C = 20 pF
ASUP L
V
OHO
V
OLO
V
= 5.0 V, C = 20 pF
ASUP L
RGB Output Negative Over-
shoot
%
V
= 5.0 V, C = 20 pF
ASUP L
R
Resistance from RGB Inputs to
RGB Outputs
31, 32, 33,
37, 38, 39
–
–
150
Ω
ext. RGB on
on
V
V
Fast Blank Output Low Voltage
Fast Blank Output High Voltage
36
–
–
–
–
0.4
–
V
I = 1.6 mA
L
OL
3.0
–
V
I =*0.5 mA
L
OH
t
T
Fast Blank Output Transition
Time
10
ns
C = 20 pF
L
VOL(max) ↔ V
OH(min)
t
D
Differential RGB & FB Timing
36
10
ns
C = 20 pF
L
37,38,39
3.6.11. Prio and Color Interface Characteristics
Symbol
Parameter
Pin No.
Min.
–
Typ.
–
Max.
0.8
–
Unit
V
Test Conditions
V
V
Prio Input Low Voltage
Prio Input High Voltage
30 to 32
IL
1.5
–
–
V
IH
V
OL
Prio & Color Output Low Voltage
30 to 33
36 to 39
0.25
0.5
V
I = 8mA, strength 3
L
I = 6mA, strength 2
L
I = 4mA, strength 1
L
I = 2mA, strength 0
L
V
Prio & Color Output High Voltage
1.8
1.3
2.0
1.5
–
–
V
I = *0.01 mA
L
OH
I
t
t
Prio & Color Output Pull-up
Current
mA
V
OL
= 0 V
O
Prio & Color Output Transition
Time
–
–
10
10
ns
ns
C = 20 pF
L
T
Differential Prio & Color Timing
C = 20 pF
L
D
20
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.12. H and V Sync Interface Characteristics
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
V
Input Trigger Level
High → Low
25, 26
1.5
–
2.0
V
ITF
ITR
V
Input Trigger Level
Low → High
2.5
–
3.0
V
V
V
V
Input Trigger Hysteresis
Output Low Voltage
Output High Voltage
Output Transition Time
0.5
–
–
–
–
–
–
V
ITH
0.4
–
V
I = 1.6 mA
L
OL
2.4
–
V
I =*0.1 mA
L
OH
t
T
10
ns
C = 20 pF
L
3.6.13. MSync Interface Characteristics
Symbol
Parameter
Pin No.
Min.
–
Typ.
Max.
0.8
–
Unit
V
Test Conditions
V
V
Input Low Voltage
Input High Voltage
25
–
–
–
–
IL
1.5
10
0
V
IH
t
IS
t
IH
Input Setup Time
Input Hold Time
–
ns
ns
C = 20 pF
L
–
C = 20 pF
L
2
3.6.14. I C-Bus Interface Characteristics
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
V
Input Trigger Level
High → Low
19, 20
1.5
–
2.0
V
ITF
ITR
V
Input Trigger Level
Low → High
2.5
–
3.0
V
V
V
Input Trigger Hysteresis
Output Low Voltage
Input Rise Time
0.5
–
–
–
–
–
–
–
V
ITH
0.4
1000
300
400
V
I = 3 mA
L
OL
t
t
f
–
ns
ns
kHz
R
Output Fall Time
–
C = 400 pF
L
F
Clock Frequency
19
0
SCL
MICRONAS INTERMETALL
21
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.15. DRAM Interface Characteristics
Symbol
Parameter
Pin No.
Min.
–
Typ.
Max.
0.8
–
Unit
Test Conditions
V
V
Input Low Voltage
Input High Voltage
3
–
–
–
–
5
V
IL
2.0
–
V
IH
V
V
Output Low Voltage
Output High Voltage
Output Transition Time
3 to 18
0.4
–
V
I = 1.6 mA
L
OL
2.4
–
V
I = *0.5 mA
L
OH
t
T
10
ns
C = 15 pF
L
V
OL(max) ↔ V
OH(min)
3.6.15.1. DRAM Fast Mode Timing at f
= 20.25 MHz
CLK
Symbol
Parameter
Pin No.
Min.
Typ.
98.8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
t
t
Page Mode Cycle Time
CAS Pulse Width
6
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
>
>
>
>
>
55
25
10
80
25
PC
PC
60
CAS
CAS
CP
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CAS Precharge Time
10
90
40
110
45
55
55
15
105
55
5
CP
RAS Precharge Time
5
RP
RP
RAS Hold Time
5, 6
RSH
CSH
RCD
CRP
ASR
RAH
AR
RSH
CSH
RCD
CRP
ASR
RAH
AR
CAS Hold Time
> 100
RAS to CAS Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Hold Time
Column Address Lead Time
Column Address Setup Time
Column Address Hold Time
Read Command Hold Time
Read Command Hold Time
Write Command Hold Time
Write Command Setup Time
DATA Output Hold Time RAS
DATA Output Setup Time
DATA Output Hold Time
DATA Input Setup Time
DATA Input Hold Time
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
<
25
10
0
5, 7 to 18
15
75
50
0
RAL
ASC
CAH
RRH
RCH
WCH
WCS
DOHR
DOS
DOH
DIS
RAL
ASC
CAH
RRH
RCH
WCH
WCS
DHR
DS
6, 7 to 18
60
80
50
90
30
105
0
20
0
4, 5
4, 6
0
20
0
3, 5
3, 6
75
0
60
20
0
20
25
30
DH
CAC
OFF
DIH
22
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.15.2. DRAM Slow Mode Timing at f
= 20.25 MHz
CLK
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
t
t
Page Mode Cycle Time
CAS Pulse Width
6
148
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
DRAM:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
> 120
PC
PC
60
>
>
>
>
60
25
90
60
CAS
CAS
CP
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CAS Precharge Time
60
90
60
140
65
85
55
15
155
105
35
60
80
50
90
50
155
30
60
20
0
CP
RAS Precharge Time
5
RP
RP
RAS Hold Time
5, 6
RSH
CSH
RCD
CRP
ASR
RAH
AR
RSH
CSH
RCD
CRP
ASR
RAH
AR
CAS Hold Time
> 120
RAS to CAS Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Hold Time
Column Address Lead Time
Column Address Setup Time
Column Address Hold Time
Read Command Hold Time
Read Command Hold Time
Write Command Hold Time
Write Command Setup Time
DATA Output Hold Time RAS
DATA Output Setup Time
DATA Output Hold Time
DATA Input Setup Time
DATA Input Hold Time
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
<
<
25
10
0
5, 7 to 18
15
80
80
0
RAL
ASC
CAH
RRH
RCH
WCH
WCS
DOHR
DOS
DOH
DIS
RAL
ASC
CAH
RRH
RCH
WCH
WCS
DHR
DS
6, 7 to 18
20
20
0
4, 5
4, 6
30
0
3, 5
3, 6
90
0
30
60
35
DH
CAC
OFF
DIH
MICRONAS INTERMETALL
23
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
V
V
OH
WE
OL
t
t
RRH
RAL
t
t
CSH
t
WCH
V
V
OH
t
PC
t
RSH
t
RAS
CAS
AR
RP
OL
t
t
t
t
CAS
RCH
RCD
CP
V
V
OH
t
WCS
OL
t
CRP
t
t
ASC
RAH
t
CAH
t
ASR
V
OH
A[0...11]
ROW ADDR.
COLUMN ADDR. 0
COLUMN ADDR. 1
VALID DATA
COLUMN ADDR. 7
VALID DATA
ROW ADDR.
V
OL
t
DOHR
t
DOS
t
DOH
V
V
OH
DOUT
VALID DATA
OL
t
t
DIH
DIS
V
V
OH
DIN
VALID DATA
VALID DATA
VALID DATA
OL
Fig. 3–17: DRAM page mode waveforms
24
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
3.6.16. SRAM Interface Characteristics (TPU 3050 only)
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
PSDIP 52
V
V
Input Low Voltage
Input High Voltage
1,2
45 to 48
50,52
–
–
–
–
0.8
–
V
V
V
IL
2.0
–
IH
V
V
Output Low Voltage
Output High Voltage
Output Transition Time
1,2,24
27 to 31
34 to 50
52
0.4
I = 1.6 mA
L
OL
2.4
–
–
5
–
V
I = *0.5 mA
L
OH
t
T
10
ns
C = 15 pF
L
V
OL(max) ↔ V
OH(min)
3.6.16.1. SRAM Mode Timing at f
= 20.25 MHz
CLK
Symbol
Parameter
Pin No.
Min.
Typ.
Max.
Unit
Test Conditions
PSDIP 52
t
t
Read / Write Cycle Time
24
27 to 31
34 to 44
889
ns
SRAM:
SRAM:
t
t
> 100
> 100
RC
RC
WC
WC
t
t
t
t
t
t
t
t
t
t
t
Address Setup Time
24
444
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM:
SRAM:
SRAM:
SRAM:
SRAM:
SRAM:
SRAM:
SRAM:
SRAM:
SRAM:
t
t
t
t
t
t
t
t
t
t
>
>
>
>
>
<
>
>
0
90
5
AS
AS
27 to 31
34 to 44
49
Address Valid to End of Write
Write Recovery Time
543
593
98.8
0
AW
AW
WR
WP
OW
WHZ
DW
DH
WR
WP
WHZ
OW
DOS
DOH
DIS
DIH
DIL
Write Pulse Width Time
Write to Output High–Z
Write to Output Active
Data Output Setup Time
Data Output Hold Time
Data Input Setup Time
Data Input Hold Time
Data Input Latch Time
49
70
10
50
40
0
1,2
45 to 50
52
25
98.8
0
1,2,24
20
< 100
10
AA
27 to 31
34 to 48
50,52
0
>
OH
198
t
t
WC
RC
V
OH
A[0...16]
VALID ADDRESS
V
OL
t
AW
t
t
t
WR
AS
WP
V
V
OH
WE
OL
t
t
WHZ
OW
t
t
DOS
DOH
V
V
OH
DOUT
VALID DATA
OL
t
DIL
t
AA
t
t
DIH
t
DIS
OH
V
V
OH
DIN
VALID DATA
OL
Fig. 3–18: SRAM mode waveforms
MICRONAS INTERMETALL
25
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4. Definitions
4.1. CPU
4.1.1. Memory Mapping
Table 4–1: 65C02 memory map
Zero Page
Stack Page
I/O Page
Interrupt Vector
Absolute Address
(high byte, low byte)
IRQ
FFFF, FFFE
FFFD, FFFC
FFFB, FFFA
FFF9
Reset
NMI
Control Word
Memory Segment
Program RAM
Zero Page
Stack Page
OSD Buffer
I/O Page
8K
Character ROM
Absolute Address
0000 – 01FF
0000 – 00FF
0100 – 01FF
0100 – 019F
0200 – 02FF
6000 – 7FFF
E000 – FFFF
8K
Program ROM
DMA
Interface
Character ROM
Program ROM
ADR
DATA
DATA
ADR
BE
65C02
Display
RDY
BUSREQ
Fig. 4–1: 65C02 memory environment
26
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
2
2
4.2. I C Bus Interface
The time required to process the I C buffer depends on
other processes running inside the TPU 3040 firmware.
2
Thus the following I C telegram addressing the TPU can
Communication between TPU 3040 and host controller
be held after the slave address byte until the old tele-
gram is completely processed.
2
2
is done via I C-bus. For detailed information on the I C-
2
bus please refer to the Philips manual ‘I C-bus Specifi-
cation’.
4.2.1. Subaddressing
The TPU 3040 acts as a slave transmitter/receiver and
uses clock synchronization to slow down the data trans-
fer if necessary. General call address will not be ac-
knowledged.
Access to all memory locations and to the command in-
terface is achieved by subaddressing. Both the external
DRAM and the internal CPU memory can be addressed
completely. The TPU 3040 acknowledges 6 different
subaddresses following the slave address (see Table
4–2).
Different memories and functions of TPU 3040 can be
accessed by subaddressing. The byte following the
slave address byte is defined as the subaddress byte.
2
The following symbols are used to describe the I C ex-
ample telegrams:
2
Maximum length of an I C telegram is 256 bytes follow-
ing slave address and subaddress byte. The interface
supports data transfer with autoincrement.
<
>
start condition
stop condition
address bank byte
address high byte
address low byte
command byte
data byte
status byte
0 – n continuation bytes
2
The I C-bus interface is interrupt-driven and uses an in-
ab
ah
al
cc
dd
ss
..
2
ternal 48-byte buffer to collect I C data in real-time with-
out disturbing internal processes. This is done to avoid
clock synchronization as far as possible. When the TPU
2
2
3040 has to process the I C buffer and the I C telegram
2
has not yet been stopped, the I C clock line will be held
down.
2
Table 4–2: I C-bus Subaddresses
Name
TPU
Binary Value
0010 001x
0111 1000
0111 1001
0111 1010
0111 1011
0111 1100
0111 1101
Hex Value
Mode
W, R
W
Function
22, 23
78
TPU slave address
Sub 1
Sub 2
Sub 3
Sub 4
Data
subaddressing CPU (static)
79
W
subaddressing CPU (autoincrement)
subaddressing DRAM (autoincrement)
subaddressing command language
subaddressing data register
7A
W
7B
W
7C
R/W
R
Status
7D
status register
bit 7 = command wait
bit 6 = command invalid
bit 5 = command found no data
bit 4 = not used
bit 3 = not used
bit 2 = not used
bit 1 = 0
bit 0 = 0
MICRONAS INTERMETALL
27
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.2.1.1. CPU Subaddressing
When reading the DRAM, the first data byte the TPU
3040 returns is a dummy byte, which has to be ignored.
There are 2 CPU subaddresses to access CPU
memory: either with static memory address or with auto-
incrementing memory address. The main purpose of
CPU subaddressing is to write text into the OSD buffer
and to access the I/O page (see chapter 4.15.). The stat-
ic CPU subaddress can be used to write more than 1
byte into the same I/O page register.
< 22 7A ab ah al dd .. >
< 22 7A ab ah al > < 22 7C dd .. >
< 22 7A ab ah al > < 22 7C < 23 dd ..>
Data written to the DRAM subaddress is collected first
2
in the I C buffer of TPU 3040 and is copied to DRAM
when the buffer is full (48 bytes) or after stop condition.
During the time the buffer is copied to DRAM the TPU
2
The CPU subaddress has to be followed by 2 address
bytes defining the CPU memory address. The following
data byte is written into this address. In the case of auto-
increment the continuation bytes are written into incre-
menting memory addresses.
3040 will hold the I C clock line down.
Reading data from the DRAM subaddress is also buff-
ered internally. Reading the first byte will only empty the
2
I C buffer. Every time the buffer is empty, the TPU 3040
2
will copy 48 bytes from DRAM into the I C buffer. During
this time the TPU 3040 will hold the I C clock line down.
2
The CPU telegram can be stopped after the 2 memory
2
address bytes. The following I C telegram subaddres-
sing the data register will continue data transfer to or
from the CPU memory. The data transfer will always
start at the CPU memory address (autoincrement is not
saved).
4.2.1.3. Command Subaddressing
TPU 3040 supports a command language, allowing the
host controller to start complex processing inside the
TPU 3040 with simple commands (see chapter 4.9.).
Commands have to be sent to the command subad-
dress.
< 22 78 ah al dd .. >
< 22 79 ah al dd .. >
< 22 79 ah al > < 22 7C dd .. >
Data is directly written into CPU memory without using
the I C buffer of TPU 3040 and without waiting for a stop
condition.
2
The command subaddress has to be followed by the
command code. The following data bytes are taken as
command parameters.
The execution time for commands depends on other
processes running inside the TPU 3040 firmware, there-
fore the host controller has to read the status register to
get information about the running command before
reading command parameter or starting other com-
mands.
4.2.1.2. DRAM Subaddressing
DRAM access is necessary to generate level 2 displays.
TheexternalDRAMcanbeaddressedonbytelevel. The
maximum DRAM size of 16 Mbit requires a 21-bit
memory address pointer. The format of the DRAM ad-
dress pointer is shown in Fig. 4–2.
The status register returns information about the com-
mand interface. The ‘command wait’ bit is set during
execution of a command and is reset when a command
is executed completely and read parameters are avail-
able. If a non-existing command is sent to the TPU 3040,
the ‘command invalid’ bit is set. If a command could not
be executed successfully, the ‘command found no data’
bit is set. In this case the read parameters of this com-
mand are not valid.
5-bit Bank
8-bit High
8-bit Low
Fig. 4–2: DRAM Address Pointer
Reading status from TPU 3040 is done by subaddres-
sing the status register followed by repeated start condi-
tion and slave read address (see Fig. 4–3).
The DRAM subaddress has to be followed by 3 address
bytes defining the DRAM address pointer. The following
data byte is written into this address.
< 22 7B cc dd ..
< 22 7D < 23 ss .. >
< 22 7C < 23 dd .. >
>
DRAMsubaddressingalwaysusesautoincrement. Sep-
arate read and write DRAM address pointers are saved
for autoincrement.
Telegrams subaddressing the command interface are
buffered and processed after receiving the stop condi-
tion. Therefore the command code and all necessary
command parameters have to be included in a single
telegram.
The DRAM telegram can be stopped after the 3 address
pointerbytes. ThefollowingI Ctelegramsubaddressing
the data register will continue data transfer to or from the
DRAM.
2
28
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.2.1.4. Data Subaddressing
Writing data to TPU 3040 memory is possible by subad-
dressing the data register directly. The data is then writ-
ten into memory addressed by the foregoing telegram.
< 22 7C dd .. >
Reading data from TPU 3040 is done by subaddressing
the data register followed by a repeated start condition
and slave read address (see Fig. 4–3). The returned
data depend on the subaddress selected in the preced-
ing TPU telegram.
< 22 7C < 23 dd .. >
S
S
S
S
S
S
0010001
0010001
0010001
0010001
0010001
0010001
W
W
W
W
W
W
Ack
Ack
Ack
Ack
Ack
Ack
0111 1000
0111 1001
0111 1010
0111 1011
0111 1100
0111 1100
Ack
Ack
Ack
Ack
Ack
Ack
n byte Sub 1
n byte Sub 2
n byte Sub 3
n byte Sub 4
n byte Data
0010001
Ack
Ack
Ack
Ack
Ack
R
P
P
P
P
P
S
S
Ack n–1 byte Data Ack
last byte Data Nak
P
P
S
0010001
W
Ack
0111 1101
Ack
0010001
R
Ack
Status
Status
Ack
Nak
W
R
Ack =
Nak =
S
P
=
=
0
1
0
1
1
0
SDA
SCL
S
P
=
=
=
=
Start
Stop
Interrupt
Data from TPU
2
Fig. 4–3: I C-bus Protocol
MICRONAS INTERMETALL
29
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.3. Display Memory
The TPU 3040 supports a variable number of display
memories, each 4 KByte large. One bank is used to
store the display information of the selected teletext
page. The bank location can be defined with the com-
mand DISPLAY_TTX_POINTER. Other banks can be
used to store any kind of display data in level 1 or level
2 format. Switching between these banks is fast and can
be programmed with the command DISPLAY_POINT-
ER. Bank switching allows generation of OSD menus
without affecting the teletext display.
autoincrement
40 byte level 1
40 byte level 1
40-bit pointer
40-bit pointer
40 byte level 2
40 byte level 2
full row attr.
full row attr.
Row 0
Row 1
Display Bank
Row 46
40 byte level 1
40-bit pointer
40 byte level 2
full row attr.
40 byte level 1
40 byte level 1
40-bit pointer
40-bit pointer
40 byte level 2
40 byte level 2
full row attr.
full row attr.
Row 0
Row 1
TTX Display Bank
Row 25
40 byte level 1
40-bit pointer
40 byte level 2
full row attr.
DRAM
Fig. 4–4: Display Memory Organization
30
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Table 4–3: Full Row Attribute
Table 4–5: Level 2 Parallel Attributes
7
P
P
P
P
P
P
P
P
P
P
P
6
0
0
1
1
1
1
1
1
1
1
1
5
0
1
0
1
1
1
1
1
1
1
1
4
3
2
1
0
Function
+ 55H
Bit
R/W
Full Row Attribute
Function
Color
Foreground Color
Background Color
Flash Mode
Reset
Color
Flash
7
–
–
–
–
1 = row is displayed blank
0 = row is displayed using row data
0
0
0
0
1
1
1
1
0
1
1
1
0
0
0
0
L
0
1
1
0
0
1
1
Set
Character Set
DH DW Size
6
1 = row is displayed in double height
0 = row is displayed in normal height
0
1
0
1
0
1
U
I
Underline/Separated
Inverted
5
1 = row is displayed in level 2 mode
0 = row is displayed in level 1 mode
C
W
S
IT
Conceal
Window/Boxing
Shadow
4 to 0
5-bit value defining full row back-
ground color
Italic
Table 4–6: Flash Modes
Table 4–4: Level 1 Spacing Attributes
4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
3
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
2
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
x
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
Function
Code
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
Function
Action
Notes
Off
Alpha Black
set alpha
Normal
mode and
foreground
color of fol-
lowing alpha
characters
Normal Fast Phase 1
Normal Fast Phase 2
Normal Fast Phase 3
Inverted
Alpha Red
Alpha Green
Alpha Yellow
Alpha Blue
Inverted Fast Phase 1
Inverted Fast Phase 2
Inverted Fast Phase 3
Color Table
select G0
set
Alpha Magenta
Alpha Cyan
Alpha White
Flash Normal
Flash Off
Color Table Phase 1
Color Table Phase 2
Color Table Phase 3
Incremental
set at
Boxing Off
set at double
set at double
set at
Boxing On
x
x
Decremental
Size Normal
Size Double Height
Size Double Width
Size Double
Mosaic Black
Mosaic Red
Table 4–7: Color Look-Up Table
set mosaic
mode and
color of fol-
lowing
mosaic
characters
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
Display Color
Black
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Mosaic Green
Mosaic Yellow
Mosaic Blue
Mosaic Magenta
Mosaic Cyan
Mosaic White
Conceal
Red
Green
Yellow
Blue
select G1
character
set
Magenta
Cyan
White
set at
set at
set at
Transparent
Reduced Red
Reduced Green
Reduced Yellow
Reduced Blue
Reduced Magenta
Reduced Cyan
Reduced White
Programmable
Contiguous Mosaic
Separated Mosaic
ESC
Black Background
New Background
Hold Mosaic
Release Mosaic
set at
set at
set at
Shaded attributes are default at start of each display row.
MICRONAS INTERMETALL
31
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.4. OSD Layer
Table 4–8: OSD Layer Control Codes
Code
01
Function
Underline On
Underline Off
Flash On
Notes
only for 13 scanlines/character
02
03
04
Flash Off
05
Italics On
06
Italics Off
07
Transparent
Shadow
layer becomes transparent
08
layer becomes transparent and
contrast is reduced to 66%
0C
END
CR
end of layer
0D
end of text line
0E – 7F
80 – FF
ASCII Character using font 1 or font 2
Color Control only one control code per charac-
ter is allowed
bit 0 = foreground color blue
bit 1 = foreground color green
bit 2 = foreground color red
bit 3 = background color blue
bit 4 = background color green
bit 5 = background color red
bit 6 = replace white by
transparent
bit 7 = 1
Shaded attributes are default at start of each text line.
32
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.5. Character Set
10-bit Character Code = 2–bit Character Set (level 2) + 8–bit Character Value (level 1)
000H
Set = 0
G0
G0
G0
080H
National
National
National
National
Character ROM
PAL = 5200 byte
100H
180H
G0
G0
Set = 1
G1
G0
G0
G1
G1
National
National
National
National
G1
User
National
National
National
National
G2
Mapping ROM
32 x 5 bit
Set = 2
200H
280H
G2
G2
G2
G2
G2
User
User
User
User
NTSC = 2240 byte
NTSC G0
NTSC G0
NTSC G0
NTSC G1
300H
380H
Set = 3
NTSC G1
G3
G3
NTSC User
NTSC National
G3
User
User
User
User
32 char
Fig. 4–5: Character Set Organization
MICRONAS INTERMETALL
33
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.6. Font Structure
MSB
9
LSB
0
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Character Font
ROM_Adr = Char x 10 + Line + Font_Adr
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 1
Line 2
Line 3
Line 4
Char
Line
Font_Adr
16
ROM_Adr
16
10
4
4
Σ
16-bit
2
Σ
14-bit
Σ
12-bit
‘A‘
‘A‘
‘A‘
‘A‘
Extension Font
ROM_Adr = Char / 4 x 10 + Line +Ext_ Font_Adr
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 1
Line 2
Line 3
Line 4
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘@‘
‘D‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘A‘
‘E‘
‘E‘
‘E‘
‘E‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘B‘
‘F‘
‘F‘
‘F‘
‘F‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘C‘
‘G‘
‘G‘
‘G‘
‘G‘
Char
8
Line
Ext_Font_Adr
16
ROM_Adr
16
4
4
Σ
16-bit
2
Σ
Σ
10-bit
12-bit
‘D‘
‘D‘
‘D‘
Fig. 4–6: Character Font Structure
34
MICRONAS INTERMETALL
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PRELIMINARY DATA SHEET
4.7. Character Font
4.7.1. Character Set 0
Table 4–9: G0 font
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
= National Option
Table 4–10: National font
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
MICRONAS INTERMETALL
35
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.7.2. Character Set 1
Table 4–11: G1 font
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
= National Option
4.7.3. Character Set 2
Table 4–12: G2 font
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
36
MICRONAS INTERMETALL
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PRELIMINARY DATA SHEET
Table 4–13: User font TPU 3035/3040
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
Table 4–14: User font TPU 3050
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
MICRONAS INTERMETALL
37
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.7.4. NTSC Character Sets
NTSC character sets G0 and G1 are identical to PAL character sets. There is no G2 character set for NTSC.
Table 4–15: NTSC national font
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
Table 4–16: NTSC user font
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8
9
10
11
12
13
14
15
38
MICRONAS INTERMETALL
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PRELIMINARY DATA SHEET
4.8. Character Mapping
Table 4–17: Character set options
Option Bits
Character Set
C14,C13,C12
6
38
40
English (US)
French
55
70
000
001
010
011
100
101
110
111
English
French
Swedish
Czech
Polish
English
French
Swedish
Turkish
German
Spanish
Italian
English (US)
Slovakian
Hungarian
Serbian
French
Swedish
Czech
German
Serbian
Italian
Swedish
Czech
German
Spanish
Italian
German
Spanish
Italian
Albanian
Polish
Turkish
English
English
English
English
Rumanian
Table 4–18: National option mapping
Language
G0/G1 Table Position
2/3
5/15
5/15
2/3
2/4
2/4
4/0
13/12
13/13
4/0
5/11
5/12
12/12
12/13
5/12
13/5
9/7
5/13
12/3
12/11
5/13
15/4
8/2
5/14
11/12
8/4
5/15
9/1
6/0
7/11
13/3
8/3
7/12
12/13
12/0
7/12
15/6
9/8
7/13
13/1
9/2
7/14
Albanian
Czech
13/2
10/11
5/11
14/4
9/1
13/13
9/3
11/13
11/13
7/14
15/7
9/0
12/9
2/4
15/13
5/15
13/0
5/15
13/0
11/15
5/15
9/4
English
5/14
14/6
8/8
6/0
7/11
14/5
8/7
7/13
15/5
8/9
English (US)
French
5/15
9/3
2/4
4/0
14/7
9/5
8/1
8/5
German
Hungarian
Italian
5/15
5/15
2/3
2/4
15/0
9/14
9/3
8/13
8/4
8/14
8/14
9/0
8/15
10/1
5/13
15/8
14/11
12/3
12/11
8/4
14/6
12/15
5/14
13/3
10/6
11/12
8/4
14/0
9/3
8/10
9/4
8/11
8/11
9/6
8/12
8/3
9/10
8/12
8/6
9/2
2/4
14/0
13/8
10/5
13/2
10/11
8/3
8/2
8/5
9/5
Polish
5/15
5/15
5/15
5/15
9/0
14/3
14/1
2/4
13/15
10/14
13/12
13/13
9/15
9/14
10/8
12/7
14/14
12/12
12/13
9/3
10/9
10/15
13/13
9/3
13/9
8/7
13/7
14/15
12/13
12/0
9/11
8/11
8/11
15/9
12/5
13/1
9/2
13/11
8/8
Rumanian
Serbian
Slovakian
Spanish
Swedish
Turkish
15/1
13/0
15/13
9/2
13/3
8/3
11/13
11/13
8/5
12/9
2/4
9/4
9/9
8/12
8/10
14/15
9/5
5/15
13/6
14/1
10/13
8/13
14/14
8/14
8/14
9/13
8/0
8/15
8/15
13/0
10/12
9/3
9/12
9/0
8/12
8/12
15/1
MICRONAS INTERMETALL
39
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.9. Command Language
Table 4–19: Command Table
Code Code
Command Name
Dummy
No. Write Parameter
No. Read Parameter
Status Register
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x000 0000
x000 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x0x0 0000
x000 0000
x000 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x0x0 0000
x0x0 0000
x0x0 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x0x0 0000
x000 0000
x0x0 0000
x0x0 0000
x0x0 0000
x000 0000
x000 0000
x000 0000
x000 0000
x0x0 0000
x000 0000
x000 0000
x0x0 0000
x0x0 0000
x0x0 0000
x000 0000
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
00
01
02
03
04
05
06
07
08
09
0a
0b
0c
0d
0e
0f
0
0
Reset
0
0
Escape
0
0
Version
0
2
Test
0
0
Test
0
0
DRAM Mode
3
0
Acquisition Mode
Display Mode
5
2
3
0
Display TTX Pointer
Display Pointer
Display Clear
2
0
3
0
2
0
Page Request
Display Time Pointer
Read DRAM Size
Read VPS
8
3
2
0
0
3
0
15
10
11
12
13
14
15
16
17
18
19
1a
1b
1c
1d
1e
1f
Read Quality
0
4
Read Display Mode
Read Reset Source
Read Rolling Header
Read Page Info
Read Page Row
Change Page Info
Search MPET
Read Display Page
Page Memory
0
3
0
1
0
24
2
7
5
40
3
0
0
1 + (n*4)
0
4
2
0
Display Page Request
Page Table Reset
Search Next Page
Read Page Cycle
Read TOP Code
Read Rolling Time
Copy Page Row
Copy Data
5
0
0
0
3
6
0
9
2
2
0
8
20
21
22
23
24
25
26
27
28
29
2a
2b
2c
2d
2e
2f
8
0
7
0
Search Next TOP Code
Read Ghost Row
Read 8/30 Row
Read Priority
3
4
6
40
1
40
0
5
Page Priority
2
0
Search AIT
0
1 + (n*4)
Read TOP Status
Search AIT Title
Reset Ghost Row Status
Search MPT
0
2
2
17
0
0
0
1 + (n*4)
Copy AIT Title
Search Direct Choice
Read Hamming
Read Hamming 2
Display Column
Display Fill
5
17
1
1 + (n*2)
1
1
3
3
30
31
32
33
34
35
36
37
38
3+length
0
4
0
2
1
0
0
0
5
0
Read BTTL
9
Read Next Page
Change BTT magazine
Read WSS
2
0
15
7
Read CAPTION 1
Read CAPTION 2
OSD Font Pointer
7
0
40
MICRONAS INTERMETALL
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PRELIMINARY DATA SHEET
Note:
Ifnototherwisedesignated, allparametersinthefollowingtablearespecifiedassinglebytes. Aswriteparame-
ter magazine numbers 8 and 0 have the same meaning, as read parameter the magazine number is a true 4-bit
number (e.g. magazine 8 = 00001000). For write parameters the values in parentheses indicate default values
after reset (in hex notation). For compatibility reasons every undefined bit in a write parameter should be set to
‘0’. Undefined bits in a read parameter should be treated as “don’t care”.
Table 4–20: Command Codes
Code
Function
Write Parameter
Read Parameter
Notes
Operational & Test Commands
00
01
02
03
Dummy
Reset
no action
software reset of 65C02
escape to other codes
Escape
Version
CPU pointer high
CPU pointer low
show version in OSD layer
CPU pointer to text in ROM
04
05
06
Test
reserved for testing
reserved for testing
Test
DRAM Mode
dram mode
flash inc
control enable
(06)
(05)
(FF)
dram mode = I/O page register 028EH
flash freq = flash inc / (256 * 0.00324)
control enable:
bit0 = C4 erase page
bit1 = C5 news flash
bit2 = C6 subtitle
bit3 = C7 suppress header
bit4 = C8 update indicator
bit5 = C9 interrupted sequence
bit6 = C10 inhibit display
bit7 = C11 magazine parallel
07
Acquisition Mode
acquisition mode
init subcode high
init subcode low
gain max
(00)
(FF)
(FF)
(1F)
(1F)
gain
filter
acquisition mode:
bit0 = no slicer adaption
bit1 = no bit error in framing code
bit2 = limit slicer adaption
init subcode:
filter max
automatic subcode request after
page table reset
gain max: only used if bit2 = 1
filter max: only used if bit2 = 1
Memory Management Commands
14
Read DRAM Size
dram size high
dram size low
dram mode
dram size:
0080H = 256Kbit (slow mode)
0200H = 1Mbit
0800H = 4Mbit
(fast mode)
(fast mode)
2000H = 16Mbit (fast mode)
dram mode:
(only in TPU 3050)
see I/O page register 028EH
25
27
Page Memory
dram bank
dram high
(00)
(40)
start of page memory
execute page table reset
Page Table Reset
reset page table
reset ghost row status
reset data service status
reset cycle count
reset memory count
reset ghost count
reset priorities
clear rolling header
clear VPS data
clear WSS data
42
Reset Ghost Row Status
ghost row status:
bit0 = row 24 in cycle
bit1 = row 25 in cycle
bit2 = row 26 in cycle
bit3 = row 27 in cycle
bit4 = row 28 in cycle
bit5 = row 29 in cycle
bit6 = row 30 in cycle
bit7 = row 31 in cycle
MICRONAS INTERMETALL
41
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Command Codes, continued
Code
Function
Write Parameter
Read Parameter
Notes
29
Read Page Cycle
ghost row status
2 byte cycle count
2 byte memory count
2 byte ghost count
data service status
memory status
= number of pages in cycle
= number of pages in memory
= number of ghost blocks in memory
data service status:
bit0 = 8/30 format 1 updated
bit1 = 8/30 format 2 updated
bit2 = VPS updated
bit3 = WSS updated
bit4 = CAPTION 1st field updated
bit5 = CAPTION 2nd field updated
memory status:
bit0 = memory full
38
37
Page Priority
Read Priority
enable
border
(00)
(FF)
enable:
bit0 = enable priority manager
border:
min/max border for page priorities
highest priority
lowest priority
border priority
magazine number
page number
= max priority in page memory
= min priority in page memory
= min/max border for page priorities
= page with lowest priority
Page Related Commands
12
Page Request
magazine number
page number
page subcode high
page subcode low
priority
number of open requests
removed magazine num-
ber
remove pages from memory beginning at
start page if page priority is disabled,
ignores start page if page priority is en-
abled
removed page number
magazine number:
quantity
start magazine number
start page number
bit0–3= magazine number
bit4 = not used
bit5 = hex request
bit6 = backward request
bit7 = forced request = ignore
cycle flag
20
22
Read Page Info
magazine number
page number
page pointer high
page pointer low
subpage count
ghost row count
ring buffer index
page subcode high
page subcode low
= pointer from page table
= number of subpages in chain
= number of ghost rows in chain
if page request with subcode F1xx
Change Page Info
magazine number
page number
page table flags
page table flags:
bit0 = protection
bit1 = update
bit2 = not used
bit3 = not used
bit4 = not used
bit5 = subpage
bit6 = memory
bit7 = cycle
28
Search Next Page
magazine number
page number
search code
magazine number
page number
page pointer high
page pointer low
subpage count
ghost row count
search in page table for cycle flag
magazine number:
bit0–3= magazine number
bit4 = take search code
bit5 = hex search
bit6 = backward search
bit7 = include start page
search code:
bit0 = search protection flag
bit1 = search update flag
bit2–4= not used
bit5 = search subpage flag
bit6 = search memory flag
bit7 = search cycle flag
51
Read Next Page
magazine number
page number
magazine number
page number
calculate next page number
magazine number:
bit0–3= magazine number
bit4 = not used
bit5 = hex calculation
bit6 = backward calculation
bit7 = not used
42
MICRONAS INTERMETALL
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PRELIMINARY DATA SHEET
Command Codes, continued
Code
Function
Write Parameter
Read Parameter
Notes
21
Read Page Row
magazine number
page number
40 byte row data
row 0 – 24
subpage number high
subpage number low
row number
32
Copy Page Row
magazine number
page number
copy 40byte text row from page memory
into DRAM
subpage number high
subpage number low
row number
destination dram bank
destination dram high
destination dram low
35
40
Read Ghost Row
Read TOP Status
magazine number
page number
subpage number high
subpage number low
row number
40 byte row data
row 25 – 28
designation code
TOP Commands
TOP status 1
TOP status 2
TOP status 1:
bit0 = not used
bit1 = MPT link in PLT
bit2 = MPET link in PLT
bit3 = AIT link in PLT
bit4 = BTT in memory
bit5 = MPT in memory
bit6 = MPET in memory
bit7 = AIT in memory
TOP status 2:
bit0–5 = not used
bit6 = all MPET in memory
bit7 = all AIT in memory
30
50
Read TOP Code
Read BTTL
magazine number
page number
BTT code
MPT code
code:
bit0–3= data
bit6 = hamming error
BTTL error
8 byte BTTL data
BTTL error:
bit6 = hamming error in BTTL
BTTL data:
bit0–3= data
bit6 = hamming error
52
43
Change BTT magazine
Search MPT
magazine number (01)
all TOP commands then refer to this
magazine
number of MPTs
magazine number
page number
subpage number high
subpage number low
...
search in PLT
search in PLT
search in PLT
23
39
41
Search MPET
Search AIT
number of MPETs
magazine number
page number
subpage number high
subpage number low
...
number of AITs
magazine number
page number
subpage number high
subpage number low
...
Search AIT Title
magazine number
page number
5 byte data
12 byte title
search in AIT
magazine number:
bit0–3= magazine number (0#8)
bit4–6= not used
bit7 = ignore title language
data:
bit0–3= data
bit6 = hamming error
MICRONAS INTERMETALL
43
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Command Codes, continued
Code
Function
Write Parameter
Read Parameter
Notes
44
Copy AIT Title
magazine number
page number
5 byte data
12 byte title
search in AIT and copy title into dram
magazine number:
destination dram bank
destination dram high
destination dram low
bit0–3= magazine number (0#8)
bit4–6= not used
bit7 = ignore title language
data:
bit0–3= data
bit6 = hamming error
34
Search Next TOP Code
magazine number
page number
code condition
magazine number
page number
code
search in BTT
magazine number:
bit0–3= magazine number
bit4–5= not used
code flag
bit6 = backward search
bit7 = include start page
code condition:
low nibble = BTT code
high nibble = search condition
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
= BTT code in low nibble
= BTT code # 0
= block page
= group page
= normal page
= subtitle page
= TV page
= block/TV page
= group/block/TV page
= subpage
= block/TV subpage
= group/block/TV subpage
= title page
= future page
= future page
= future page
code:
bit0–3= BTT code
bit6 = hamming error
code flag:
bit0 = subtitle page found
bit1 = TV page found
bit2 = block page found
bit3 = group page found
bit4 = normal page found
bit5 = future page found
bit6 = title page found
bit7 = subpage found
45
Search Direct Choice
direct choice code
number of AIT entries
magazine number
page number
...
search in AIT
44
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Command Codes, continued
Code
Function
Write Parameter
Read Parameter
Notes
Miscellaneous Data Commands
36
Read 8/30 Row
designation code
40 byte row data
only format 1 and 2 are supported
1st byte of row data is already hamming
decoded
15
53
Read VPS
Read WSS
framing code
counter
13 byte VPS data
= 51H
= incremented every VPS reception
= biphase decoded VPS bytes 3–15
framing code
counter
13 byte WSS data
= 78H
= incremented every WSS reception
= 102 WSS elements from group 1 on
54
55
Read CAPTION 1
Read CAPTION 2
counter
6 byte CAPTION data
= incremented every reception in field 1
= 3x oversampling
counter
6 byte CAPTION data
= incremented every reception in field 2
= 3x oversampling
19
31
16
Read Rolling Header
Read Rolling Time
Read Quality
24 byte rolling header
8 byte rolling time
every row 0 in cycle
using time pointer
updated every VBI
text lines
hamming errors
parity errors
soft errors
18
Read Reset Source
reset source
reset source:
bit0 = clock supervision
bit1 = voltage supervision
bit2 = watchdog
all bits in reset source are reset after read
46
47
Read Hamming
hamming (8,4) byte
data
hamming byte:
bit0–3= data
bit6 = hamming error
Read Hamming 2
hamming (24,18) 1st byte
hamming (24,18) 2nd byte
hamming (24,18) 3rd byte
address
mode
data
address:
bit0–5= address
bit7 = hamming error
mode:
bit0–4= mode
data:
bit0–6= data
33
Copy Data
source dram bank
source dram high
source dram low
length
copy data from DRAM to DRAM
destination dram bank
destination dram high
destination dram low
MICRONAS INTERMETALL
45
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
Command Codes, continued
Code
Function
Write Parameter
Read Parameter
Display Commands
Notes
17
Read Display Mode
display mode
character set
font
display mode:
bit0 = forced boxing
bit1 = reveal
bit2 = box
bit3 = time hold
bit4 = page hold
bit5 = row 24 hold
bit6 = row 25 hold
bit7 = row 26 hold
08
Display Mode
display mode
character set
font
(00)
(06)
(00)
display mode: see above
character set: 6,38,40,55,70
font:
0=PAL
1=NTSC
09
10
Display TTX Pointer
Display Pointer
dram high
dram low
(20)
(00)
page memory is copied to TTX pointer
dram high
dram low
scroll counter
(20)
(00)
(00)
display starts at pointer using scroll
counter as line offset
11
13
26
Display Clear
dram high
dram low
clear display bank beginning at pointer
(26 rows * 86 bytes)
Display Time Pointer
Display Page Request
dram high
dram low
(20)
(20)
8byte time string from packet x/00 is
copied to time pointer
magazine number
page number
subpage number high
subpage number low
magazine number:
bit0–3= magazine number
bit4 = change display delay
bit5 = display clear (on update)
bit6–7= not used
display delay
(1E)
subpage number:
F0xx for rolling subpages
display delay:
delay after row 0 reception in steps
of 3.24ms (255 = no update)
only used if bit4 = 1
24
48
Read Display Page
Display Column
magazine number
page number
subpage number high
subpage number low
current page in display
dram high
dram low
length
write to dram with increment of 86 byte
= number of bytes in list
byte list
...
49
56
Display Fill
dram high
dram low
length
repeated write of 1 character to dram
= number of repeated writes
character
OSD Font Pointer
font mode
font pointer high
font pointer low
extension font pointer high
extension font pointer low
(00)
font mode:
bit0 = 0 = reset OSD font 2 pointer
bit0 = 1 = load OSD font 2 pointer
withfollowingparameters
46
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.10. Memory Manager
4.11. Memory Organization
The Memory manager is the core of the internal
TPU 3040 software. Most of the acquisition and display
related functions are controlled by this management.
The upper end of the memory is defined by the DRAM
size, the lower end can be defined with the
PAGE_MEMORY command. Default memory organiza-
tion is shown in Fig. 4–8.
20 00 00 = 16Mbit
DRAM
08 00 00 = 4Mbit
02 00 00 = 1Mbit
Page Memory
n x 1 KByte
00 80 00 = 256Kbit
Acquisition
00 40 00
Display Bank
Scratch
Memory
4 KByte
00 30 00
TTX Display Bank
Page
Table
Memory
Manager
Page
Memory
4 KByte
00 20 00
Acquisition
Scratch
Display
Memory
4 KByte
00 10 00
Page Table
Display
Controller
4 KByte
00 00 00
Fig. 4–7: Memory Manager
Fig. 4–8: Memory Organization
MICRONAS INTERMETALL
47
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.12. Page Table
The cycle flag will be set as soon as this page is detected
in the transmission cycle even if it cannot be stored in
memory. Only if the page is really stored in memory, the
memory flag will be set. The subpage flag will be set for
every page in cycle if the page subcode is different from
0000H or 3F7FH. The update flag is set every time a
page is stored and will be reset only for the display page
after updating the display memory. A page with protec-
tion flag set will never be removed from memory.
The memory management is based on a fixed size page
table, which has entries for every hexadecimal page
number from 100 to 8FF. The page table starts with page
800 and contains a 2-byte page pointer for every page.
The page table can be read with the command
READ_PAGE_INFO sending the page number and
reading the 2-byte page pointer containing:
– DRAM pointer
– cycle flag
The memory manager uses page priorities to decide
which pages should be stored or removed from memory.
If no more memory is available, pages with lowest prior-
ity are removed automatically and the higher priority
pagesarestoredattheirplace. Bysettingthepageprior-
ity the programmer has control over the memory man-
agement.
– memory flag
– subpage flag
– update flag
– protection flag
The page table is fully controlled by the memory manag-
er and should never be written by external software. To
change the page table flags the command
CHANGE_PAGE_INFO can be used.
The DRAM pointer gives the location where the page is
stored in memory. The page size is fixed to 1 KByte, only
ghost rows are allocated dynamically.
Table 4–21: Page Table Format
Index
000
001
...
2-byte Page Pointer
start magazine 8
Cycle
Flag
Memory Subpage
Flag Flag
Update
Flag
Protect
Flag
11-bit DRAM Pointer
100
...
hexadecimal pages (e.g. TOP)
1F0
...
7FE
7FF
end magazine 7
48
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
control language
row flag row flag row flag row flag
ghost row pointer subpage pointer
priority status
subcode req
subcode in
8 byte
4–11
12–14
0–7
8–15
16–23
24–31
packet x/00
packet x/01
8 byte
1 KByte page data
packet x/24
24 byte
subcode subcode
high low
mag
page
index
Fig. 4–9: Page Format
MICRONAS INTERMETALL
49
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.13. Ghost Row Organization
Table 4–22: Ghost Row Identification
Page-related ghost rows are stored in blocks of 128
byte. These ghost blocks are linked together using 2
byte ghost row pointers. The first pointer can be found
in the basic page, all following pointers are part of the
block header. A zero pointer indicates the end of the
chain.
Row Number Tag
Row
000
001
010
011
100
101
110
111
empty
row 25
row 26
row 27
row 28
row 29
row 30
row 31
ghost
pointer
Page Table
page pointer
page 100
ghost
pointer
4-bit designation code
3-bit row number
ghost block
0000
‘aa’
‘aa’
‘aa’
row 1
row 2
row 3 ghost row pointer
ghost block
Fig. 4–10: Ghost Row Organization
8 byte block header
Every ghost block contains 3 ghost rows which can be
identified by 3 row identification bytes in the block
header. The row identification contains designation
code and row number. The row number is reduced to a
3-bit tag. All ghost rows in one block belong to the same
page. If the memory manager removes a page from
memory, the linked ghost blocks will also be removed.
40 byte row 1 data
40 byte row 2 data
40 byte row 3 data
Fig. 4–11: Ghost Block Structure
50
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.14. Subpage Manager
subpage
pointer
Page Table
page 100
subcode 0003
Any page in cycle can have a number of subpages, iden-
tifiedbysubcode. Innormalmodethesubpagemanager
will acquire only one subpage of every requested page.
This subpage can be any if subcode FFFF is requested
oritwillbeselectedaccordingtotherequestedsubcode.
page pointer
AfteraPAGE_REQUESTcommandwithsubcodeF0xx,
the subpage manager will acquire all subpages of the
requested page. The subpages will be chained in the
same order as they are transmitted, i.e. every new sub-
code will be added at the end of chain. The page table
entry points to the subpage which was transmitted first
after the page request. The READ_PAGE_INFO com-
mand will reply the page table pointer and the actual
number of subpages in chain.
subpage
pointer
page 100
subcode 0001
0000
AfteraPAGE_REQUESTcommandwithsubcodeF1xx,
thesubpagemanagerwillacquireallsubpagesofthere-
quested page but will allocate only a limited amount of
memory to store these subpages. The parameter “page
subcode low” will define the length (in number of sub-
pages) of a ring buffer in page memory which will hold
the recently received subpages. In this case, the
READ_PAGE_INFO command will return an index
pointing to the most recently updated subpage in chain,
together with the subcode of this page.
page 100
subcode 0002
Fig. 4–12: Subpage Organization
The DISPLAY_PAGE_REQUEST command searches
and displays a page according to the requested display
subcode. The search starts from page table and contin-
ues through the subpage chain if there is any. A rolling
header will be displayed if the requested subpage can-
not be found in memory.
ArequesteddisplaysubcodeFFFF(don’tcaresubcode)
will only search and display the first subpage in chain,
thus there is no rolling subpage anymore. A DIS-
PLAY_PAGE_REQUEST command with subcode F0xx
(follow subcode) will search and display the last re-
ceived subpage in chain, thus it is possible to request all
subpages in background while still showing rolling sub-
pages in display.
MICRONAS INTERMETALL
51
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.15. I/O Page Definition
Most hardware related functions of the TPU 3040 are
controlled by memory mapped I/O of the 65C02. The fol-
lowing table lists all available registers. For a more de-
tailed description of the I/O page registers see next sec-
tion.
Reset values are written by TPU during initialization. Ap-
plication software should only write into registers with
user label ‘Appl’!
Most of the I/O page registers are only write registers
and will not return useful data when read by application
software.
The application software has access to the I/O page reg-
2
isters via I C-bus using the CPU subaddresses SUB1
and SUB 2.
Table 4–23: I/O Page Register
Addr.
Mode
R/W
W
User
Test
Test
Appl
TPU
Test
Reset Name
Addr.
Mode
W
User
Test
Test
TPU
Test
Reset Name
0200 H
0201 H
0202 H
0203 H
0204 H
00 H Control Register
00 H Test Mode
00 H Standby
0271 H
0272 H
0273 H
0274 H
00 H Display Test 1
00 H Display Test 2
00 H Display Mode 5
00 H Display Test 4
W
W
W
W
6C H Watchdog
07 H Supervision
W
R/W
0280 H
0281 H
0282 H
0283 H
0284 H
0285 H
0286 H
0287 H
0288 H
0289 H
028A H
028B H
028C H
028D H
028E H
0290 H
0291 H
0292 H
0293 H
0294 H
0295 H
0296 H
0297 H
0298 H
0299 H
029A H
029B H
029C H
029D H
029E H
029F H
02A0 H
02A1 H
02A2 H
02A3 H
02A4 H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
TPU
Appl
Appl
Appl
Appl
TPU
TPU
TPU
TPU
TPU
Test
Test
TPU
TPU
Appl
Appl
TPU
Test
Test
Appl
Appl
00 H DRAM Display Pointer Low
20 H DRAM Display Pointer Medium
00 H DRAM Display Pointer High
00 H DRAM Slicer Pointer Low
10 H DRAM Slicer Pointer Medium
00 H DRAM Slicer Pointer High
0210 H
0211 H
0212 H
0213 H
0220 H
0221 H
0222 H
0223 H
0224 H
0225 H
0226 H
0250 H
0251 H
0252 H
0253 H
0254 H
0255 H
0256 H
025A H
025B H
0260 H
0261 H
0262 H
0264 H
0265 H
0266 H
0267 H
0268 H
0269 H
026A H
026B H
026C H
026D H
026E H
026F H
0270 H
R/W
R/W
R
TPU
TPU
TPU
Appl
TPU
TPU
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Appl
Test
Appl
Appl
Appl
Appl
TPU
Appl
TPU
–
Interface Data
00 H Interface Status
Interface Address
–
W
R/W
W
W
R
01 H Interface Mode
FF H Interrupt Source
3B H Interrupt Enable
0F H Interrupt & Timer Mode
–
–
–
–
–
–
–
–
DRAM CPU Write Pointer Low
DRAM CPU Write Pointer Medium
DRAM CPU Write Pointer High
DRAM CPU Read Pointer Low
DRAM CPU Read Pointer Medium
DRAM CPU Read Pointer High
DRAM Data
–
–
–
–
Timer Latch Low
Timer Latch High
Timer Count Low
Timer Count High
R
R
R
W
W
W
W
W
W
W
W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
04 H Clamping Start
07 H Blanking Stop
DRAM Hamming Data
06 H DRAM Mode
00 H Blanking Start
W
01 H ACQ Soft Slicer
37 H Halfline Code
W
BE H ACQ TTX Bitslicer Frequency Low
0A H ACQ TTX Bitslicer Frequency High
FA H ACQ VPS Bitslicer Frequency Low
09 H ACQ VPS Bitslicer Frequency High
07 H ACQ Filter Coefficient
60 H Display Mode 1
W
4D H Display Mode 2
W
07 H Clamping Stop
W
35 H PRIO Mode
W
00 H FB Mode
W
0D H ACQ Data Slicer
0060 H OSD Layer Vertical Start
0128 H OSD Layer Vertical Stop
16 H OSD Layer Horizontal Start
version OSD Layer Text Pointer
0138 H OSD Layer 2nd Color Start
0C H OSD Layer 2nd Color
0024 H WST Layer Vertical Start
0F H WST Layer Horizontal Start
00 H OSD Test
W
04 H ACQ Accumulator Mode
R
–
–
ACQ AC Accumulator
ACQ FLT Accumulator
R
W
00 H ACQ Packet Header Low
00 H ACQ Packet Header High
W
R
–
ACQ Soft Error Counter
0F H ACQ Sync Slicer
ACQ Sync Status
W
R
–
W
18 H ACQ Standard
0128 H WST Layer Vertical Stop
011E H WST Layer Last Row
00 H RGB Mode
W
50 H ACQ Analog Mode
00 H ACQ Test Mode
00 H ACQ Test Observe
00 H ACQ Video Input
W
W
00 H Sync Mode
W
pal font Display Font Pointer
8F H Display Mode 3
R
–
ACQ HSync Counter
00 H Display Mode 4
52
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
4.16. I/O Page Register
Note:
For compatibility reasons, every undefined bit of a write register should be set to ‘0’. Undefined bits of a read
register should be treated as “don’t care”.
0200 H
R/W
Reset
00 H
CONTROL REGISTER
Bit
all
Function
During reset the control register is loaded with the contents of the address FFF9H, but it can be read and
written via software.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1 = CPU disable
0 = CPU enable
1 = program RAM disable
0 = program RAM enable
1 = program ROM disable
0 = program ROM enable
1 = character ROM disable
0 = character ROM enable
1 = DMA interface disable
0 = DMA interface enable
1 = I/O page disable
0 = I/O page enable
1 = test mode on
0 = test mode off
write: 1 = burnin test mode (only if test pin high)
0 = normal test mode
read: 1 = burnin test mode
0 = normal test mode
0202 H
Write
Reset
0
STANDBY
Bit
2
Function
1 = digital circuitry power off
0 = digital circuitry power on
(CPU still active with slow clock)
1
0
0
0
1 = analog circuitry power off
0 = analog circuitry power on
1 = character ROM power off
0 = character ROM power on
0203 H
Write
Reset
6C H
WATCHDOG
Bit
all
Function
reset watchdog if 8-bit value= 0x6c is written into this register
all other values or time out will reset the chip
MICRONAS INTERMETALL
53
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
0204 H
R/W
Reset
0
SUPERVISION
Bit
4
Function
write enable only if test pin high
write: 1 = short reset pulse
0 = long reset pulse
(15-bit FOSC)
3
2
1
0
0
1
1
1
write enable only if test pin high
write: 1 = short watchdog period
0 = long watchdog period
(19-bit PH2)
write enabled per mask option
write: 1 = watchdog enable
0 = watchdog disable
reset after read
read: 1 = watchdog alarm
0 = watchdog sleeping
write disabled per mask option
write: 1 = voltage supervision enable
0 = voltage supervision disable
reset after read
read: 1 = voltage supervision alarm
0 = voltage supervision sleeping
write disabled per mask option
write: 1 = clock supervision enable
0 = clock supervision disable
reset after read
read: 1 = clock supervision alarm
0 = clock supervision sleeping
0210 H
R/W
Reset
–
INTERFACE DATA
Function
Bit
all
8-bit value
0211 H
R/W
INTERFACE STATUS
Bit
7
Reset
Function
–
–
–
–
–
–
–
–
write:
read: 1 = stop condition
read: 1 = write data telegram
read: 1 = read data telegram
read: 1 = sub 4 telegram
read: 1 = sub 3 telegram
read: 1 = sub 2 telegram
read: 1 = sub 1 telegram
read: 1 = start condition
6
write:
5
write:
4
write:
3
write:
2
write:
1
write: 1 = reset interface (static)
write: 0 = clear status
0
0212 H
Read
Reset
–
INTERFACE ADDRESS
Function
Bit
all
8-bit value
54
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
0213 H
Write
Reset
0
INTERFACE MODE
Bit
2
Function
1 = IIM Bus test enable (if normal test mode)
0 = IIM Bus test disable
1
0
0
1
1 = standby enable
0 = standby disable
(if bit 2 of register 0202H = 1)
1 = IIC Bus
0 = IIM Bus
0220 H
R/W
Reset
FF H
INTERRUPT SOURCE
Bit
all
Function
write: 1 = reset interrupt source
0 = no action
read: 1 = pending interrupt
0 = no pending interrupt
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
IR input falling edge
IR input rising edge
timer
12
(bit 2 from timer = every 3.24ms)
vertical sync display
slave interface
(bus write of address or read/write of data register)
master interface
TTX acquisition start
TTX acquisition stop
0221 H
Write
Reset
3B H
INTERRUPT ENABLE
Bit
all
Function
for bit mapping see register 0220 H
1 = interrupt enable
0 = interrupt disable
0222 H
Write
Reset
1
INTERRUPT & TIMER MODE
Bit
3
Function
1 = timer not latched by falling edge of IR input (see Fig. 2–5)
0 = timer latched by falling edge of IR input
2
1
0
1
1
1
1 = timer not latched by rising edge of IR input (see Fig. 2–5)
0 = timer latched by rising edge of IR input
1 = IRQ generated by falling edge of IR input
0 = NMI generated by falling edge of IR input
1 = IRQ generated by rising edge of IR input
0 = NMI generated by rising edge of IR input
MICRONAS INTERMETALL
55
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
0223 H
0224 H
0225 H
0226 H
Read
TIMER LATCH LOW
TIMER LATCH HIGH
TIMER COUNT LOW
TIMER COUNT HIGH
Bit
all
Reset
–
Function
8-bit value
(see Fig. 2–5)
Timer
Interrupt
IR
Interrupt
12
2
fosc
%16
16 bit counter
IR
8
8
D ...D
0
7
Fig. 2–5: Timer Structure
0250 H
Write
Reset
04 H
CLAMPING START
Bit
all
Function
horizontal start of clamping pulse in character increments
(see Fig. 2–6)
correct clamping pulse cannot be guaranteed if clamping start = clamping stop
0251 H
Write
Reset
07 H
BLANKING STOP
Bit
all
Function
horizontal stop of blanking pulse in character increments
(see Fig. 2–6)
correct blanking pulse cannot be guaranteed if blanking start = blanking stop
0252 H
Write
Reset
00 H
BLANKING START
Bit
all
Function
horizontal start of blanking pulse or self-timed HSYNC in character increments (see Fig. 2–6)
correct blanking pulse cannot be guaranteed if blanking start = blanking stop
0256 H
Write
Reset
07 H
CLAMPING STOP
Bit
all
Function
horizontal stop of clamping pulse in character increments
(see Fig. 2–6)
correct clamping pulse cannot be guaranteed if clamping start = clamping stop
56
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
HSYNC
Clamping
Blanking
Fig. 2–6: Internal Timing
0253 H
Write
HALFLINE CODE
Bit
all
Reset
Function
37 H
horizontal position to reset HSYNC flip-flop in normal sync mode (in character)
horizontal position of halfline HSYNC in self-timed interlaced mode (in character)
0254 H
Write
Reset
0
DISPLAY MODE 1
Bit
7
Function
1 = OSD layer always uses FONT 1
0 = OSD layer changes from FONT 1 to FONT 2 if ASCII≥20H
6
5
1
1
0
0
1 = enable OSD layer
0 = disable OSD layer
1 = active flash phase of OSD layer
0 = inactive flash phase of OSD layer
4
1 = 13 scanlines/character
0 = 8 scanlines/character
3 to 0
With this scan line the OSD layer starts display of the first text line. By slow incrementing of this value soft
scroll begins.
0255 H
Write
Reset
1
DISPLAY MODE 2
Bit
6
Function
1 = skew delay enable
0 = skew delay disable
5
4
3
2
1
0
0
0
1
1
0
1
1 = VSYNC active high
0 = VSYNC active low
1 = HSYNC active high
0 = HSYNC active low
1 = 10.125MHz display clock
0 = 20.25MHz display clock
1 = font pointer offset 10 scanlines/character
0 = font pointer offset 8 or 16 scanlines/character (depending on bit 1)
1 = font pointer offset 16 scanlines/character
0 = font pointer offset 8 scanlines/character
1 = 10 scanlines/character
0 = 8 or 13 scanlines/character (depending on bit 4 in register 0254 H)
MICRONAS INTERMETALL
57
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
025A H
Bit
Write
Reset
00
PRIO MODE
Function
7 to 6
prio output strength:
3 = 8 mA output pull-down current
2 = 6 mA output pull-down current
1 = 4 mA output pull-down current
0 = 2 mA output pull-down current
5 to 3
2 to 0
110
101
prio code for shadow pixel
prio code for normal pixel
025B H
R/W
Reset
00 H
0
FB Mode
Function
write:
Bit
all
7
read: every read resets status
color bit 4
color bit 3
(color output of OSD layer)
(color output of OSD layer)
6
0
5
0
1 = inverted shadow output / enable fastblank input
0 = normal shadow output / disable fastblank input
4
3
2
1
0
0
0
0
0
0
1 = inverted color output
0 = normal color output
1 = inverted fastblank output
0 = normal fastblank output
1 = shadow output on pin 30
0 = fastblank input on pin 30
1 = invert fastblank input
0 = normal fastblank input
read: dynamic fastblank status
read: static fastblank status
1 = fastblank input with high priority
0 = fastblank input with low priority
0260 H
Write
OSD LAYER VERTICAL START
Function
Bit
all
Reset
00 H
60 H
9-bit value defining vertical position (in scanline)
1st write:
2nd write:
bit 0 = MSB
bit7 to 0 = 8 LSBs
0261 H
Write
OSD LAYER VERTICAL STOP
Function
Bit
all
Reset
01 H
28 H
9-bit value defining vertical position (in scanline)
1st write:
2nd write:
bit 0 = MSB
bit7 to 0 = 8 LSBs
0262 H
Write
Reset
16 H
OSD LAYER HORIZONTAL START
Function
Bit
all
8-bit value defining horizontal start position (in character)
58
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
0264 H
Write
Reset
–
OSD LAYER TEXTPOINTER
Bit
all
Function
16-bit value defining memory address of text
1st write:
2nd write:
bit7 to 0 = 8 MSBs
bit7 to 0 = 8 LSBs
0265 H
Write
OSD LAYER 2nd COLOR START
Function
Bit
all
Reset
01 H
38 H
9-bit value defining vertical start for 2nd color (in scanline)
1st write:
2nd write:
bit 0 = MSB
bit7 to 0 = 8 LSBs
0266 H
Bit
Write
Reset
0C H
OSD LAYER 2nd COLOR
Function
6 to 0
7-bit value defining 2nd color
2nd color is used during 1 text row (8, 10 or 13 scanlines) after 2nd color start
0267 H
Write
WST LAYER VERTICAL START
Function
Bit
all
Reset
00 H
24 H
9-bit value defining vertical position (in scanline)
1st write:
2nd write:
bit 0 = MSB
bit7 to 0 = 8 LSBs
0268 H
Write
Reset
0F H
WST LAYER HORIZONTAL START
Function
Bit
all
8-bit value defining horizontal start position (in character)
026A H
Write
WST LAYER VERTICAL STOP
Function
Bit
all
Reset
01 H
28 H
9-bit value defining vertical position (in scanline)
1st write:
2nd write:
bit 0 = MSB
bit7 to 0 = 8 LSBs
026B H
Write
WST LAYER LAST ROW
Bit
all
Reset
Function
01 H
1E H
9-bit value defining last scanline of the last row to display level 1 double height
after this scanline the level 1 double height attribute will not be decoded anymore
1st write:
2nd write:
bit 0 = MSB
bit7 to 0 = 8 LSBs
MICRONAS INTERMETALL
59
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
026C H
Write
Reset
0
RGB MODE
Bit
6
Function
1 = inverted CLK20 input
0 = normal CLK20 input
5
0
0
1 = WST layer mixed mode
0 = WST layer normal mode
4 to 3
11 = WST layer top
10 = WST layer opaque bottom
01 = WST layer transparent bottom
00 = WST layer disable
2
0
0
1 = OSD layer mixed mode
0 = OSD layer normal mode
1 to 0
11 = OSD layer top
10 = OSD layer opaque bottom
01 = OSD layer transparent bottom
00 = OSD layer disable
026D H
Write
Reset
0
SYNC MODE
Bit
7
Function
1 = MSYNC enable
0 = HSYNC & VSYNC enable
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1 = CSYNC enable
0 = CSYNC disable
(for self-timed mode only)
1 = double scan enable
0 = double scan disable
1 = blanking disable
0 = blanking enable
1 = NTSC self-timed mode
0 = PAL self-timed mode
1 = digital color mode enable
0 = digital color mode disable
1 = self-timed mode enable
0 = self-timed mode disable
1 = interlace enable = 312/313
0 = interlace disable = 312/312
(for self-timed mode only)
026E H
Write
Reset
–
DISPLAY FONT POINTER
Bit
all
Function
4 x 16 value defining memory address of related font
WST layer always uses font 1
order of loading:
extension font 1
extension font 2
font 1
font 2
for every fontpointer:
1st write:
2nd write:
bit7 to 0 = 8 MSBs
bit7 to 0 = 8 LSBs
60
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
026F H
Write
Reset
1
DISPLAY MODE 3
Bit
7
Function
1 = 10 pixel/character
0 = 8 pixel/character
6
5
0
0
1 = double dot size in vertical direction
0 = normal dot size in vertical direction
(OSD layer only)
(OSD layer only)
(OSD layer only)
1 = double dot size in horizontal direction
0 = normal dot size in horizontal direction
4
0
1 = black colors replaced by transparent & shadow
0 = black colors displayed black
3 to 0
F H
4-bit value defining delay of horizontal start for both layers (in pixel)
delay = mod (character_width – 2 – value)
(leftmost position should not be used!)
16
0270 H
Write
Reset
0
DISPLAY MODE 4
Bit
2
Function
1 = boxing enable
0 = boxing disable
1
0
0
0
1 = reveal enable
0 = reveal disable
This bit is taken as flash clock for the WST layer, the frequency should be around 6 Hz.
0273 H
Bit
Write
DISPLAY MODE 5
Reset
Function
4
0
0
WST layer scan line counter preset (LSB for zoom mode)
WST layer scan line counter preset
3 to 0
0280 H
0283 H
0286 H
0289 H
R/W
DRAM DISPLAY POINTER LOW
DRAM SLICER POINTER LOW
DRAM CPU WRITE POINTER LOW
DRAM CPU READ POINTER LOW
Bit
Reset
–
Function
7 to 0
8 least significant bits of 21 bit address pointer
12 LSBs of 21 bit address pointer are running with autoincrement
read value is only specified when pointer is not incrementing
0281 H
0284 H
0287 H
028A H
R/W
DRAM DISPLAY POINTER MEDIUM
DRAM SLICER POINTER MEDIUM
DRAM CPU WRITE POINTER MEDIUM
DRAM CPU READ POINTER MEDIUM
Bit
all
Reset
–
Function
8 medium bits of 21 bit address pointer
12 LSBs of 21 bit address pointer are running with autoincrement
read value is only specified when pointer is not incrementing
writing this register clears all lower bits of related pointer
MICRONAS INTERMETALL
61
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
0282 H
0285 H
0288 H
028B H
R/W
DRAM DISPLAY POINTER HIGH
DRAM SLICER POINTER HIGH
DRAM CPU WRITE POINTER HIGH
DRAM CPU READ POINTER HIGH
Bit
Reset
–
Function
4 to 0
5 most significant bits of 21 bit address pointer
static (no autoincrement)
writing this register clears all lower bits of related pointer
028C H
R/W
Reset
–
DRAM DATA
Function
Bit
all
8 bit value
028D H
R/W
Reset
–
DRAM HAMMING DATA
Bit
all
Function
8 bit value
writing this register resets hamming decoder
028E H
Write
Reset
0
DRAM MODE
Bit
5
Function
1 = SRAM mode enable
0 =DRAM mode enable
(only available in TPU 3050)
4
3
2
1
0
0
0
1
1
0
1 = next CPU write without WEQ but with address increment
0 = normal CPU write mode
1 = reset address pointer and switch off refresh during standby
0 = keep address pointer and refresh during standby
1 = display channel enable
0 = display channel disable
1 = slicer channel enable
0 = slicer channel disable
1 = slow mode timing
0 =fast mode timing
0290 H
Bit
Write
Reset
01 H
ACQ SOFT SLICER
Function
4 to 0
5 bit binary soft slicer level is compared with ABS[data]
(*32≤data≤)31)
0291 H
0293 H
Write
ACQ TTX BITSLICER FREQUENCY LOW
ACQ VPS BITSLICER FREQUENCY LOW
Bit
all
Reset
–
Function
8 LSBs of bitslicer frequency
62
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
0292 H
0294 H
Write
ACQ TTX BITSLICER FREQUENCY HIGH
ACQ VPS BITSLICER FREQUENCY HIGH
Bit
3
Reset
1
Function
1 = PHINC enable
0 = PHINC disable
phase inc = Freq*(1)1/8) before framing code
phase inc = Freq*(1)1/16) after framing code
phase inc = Freq
11
2 to 0
–
3 MSBs of bitslicer frequency
Freq = 2 * Bitfreq / 20.25MHz
= 702 for PAL
= 579 for NTSC
= 506 for VPS or WSS
= 153 for CAPTION
0295 H
Bit
Write
Reset
07 H
ACQ FILTER COEFFICIENT
Function
5 to 0
high pass filter coefficient in 2’s complement
100000 = not allowed
100001 = *31
000000 =
0
011111 = )31
0296 H
Bit
Write
Reset
0D H
ACQ DATA SLICER
Function
5 to 0
6-bit binary data slicer level is compared with ABS[data]
(*32≤data≤)31)
0297 H
Write
Reset
0
ACQ ACCUMULATOR MODE
Bit
3
Function
1 = soft error correction disable
0 = soft error correction enable
2
1
0
1
0
0
1 = AC & FLT accu disable
0 = AC & FLT accu enable
(only during VPS&CAPTION line)
1 = DC accu disable
0 = DC accu enable
1 = reset DC & AC & FLT accu
0 = no action
(one shot)
0298 H
0299 H
Read
ACQ AC ACCUMULATOR
ACQ FLT ACCUMULATOR
Bit
all
Reset
–
Function
8 MSBs of 16bit accu
accu increment is 6-bit binary ABS[data-slicer_level]
these 8 MSBs are reset after read
(*32≤data≤)31)
read must occur when accu is not active
029A H
Write
Reset
00 H
ACQ PACKET HEADER LOW
Function
Bit
all
8 LSBs of MAC packet address
MICRONAS INTERMETALL
63
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
029B H
Bit
Write
Reset
6
ACQ PACKET HEADER HIGH
Function
7 to 4
4-bit framing code window
every detected clock-runin loads window counter with 4-bit value * 2 (e.g. 6 → 12-bit window)
window counter is clocked down to 0 with teletext bit rate
slicer will ignore text line if no framing code is found inside framing code window
0000 = disable framing code window
3
2
0
0
0
1 = subframe 2 MAC packet acquisition enable
0 = subframe 2 MAC packet acquisition disable
1 = subframe 1 MAC packet acquisition enable
0 = subframe 1 MAC packet acquisition disable
1 to 0
2 MSBs of MAC packet address
029C H
Bit
Read
Reset
–
ACQ SOFT ERROR COUNTER
Function
5 to 0
6-bit soft error counter
counts number of soft error corrected bytes
counter stops at 63
reset after read
029D H
Write
Reset
0
ACQ SYNC SLICER
Bit
7
Function
1 = vertical sync window disable
0 = vertical sync window enable
6 to 0
00 H
7-bit binary sync slicer level is compared with binary data
(0≤data≤127)
029E H
Read
Reset
–
ACQ SYNC STATUS
Bit
7
Function
1 = field 1
0 = field 2
set at line 624 (PAL) or line 524 (NTSC)
reset at line 313 (PAL) or line 263 (NTSC)
6
–
1 = vertical retrace
0 = vertical window
set at line 628 (PAL) or line 528 (NTSC)
reset at line 624 (PAL) or line 524 (NTSC)
64
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
029F H
Write
ACQ STANDARD
Bit
7
Reset
0
Function
1 = CAPTION enable in field 2
0 = CAPTION disable in field 2
6
5
0
0
0
1 = CAPTION enable in field 1
0 = CAPTION disable in field 1
1 = VPS enable
0 = VPS disable
7 to 5
VPS and CAPTION cannot be used at the same time, therefore these combinations are used to enable
WSS reception on a PAL+ signal
0 =
1 = VPS
2 = CAPTION field 1
3 = WSS & VPS
4 = CAPTION field 2
5 = WSS & VPS
6 = CAPTION field 1&2
7 = WSS
4
1
1
0
0
0
0
1 = TTX enable
0 = TTX disable
3
1 = MAC VBI channel A
0 = MAC VBI channel B
2
1
1 = MAC packet acquisition enable
0 = MAC VBI acquisition enable
1 = NTSC mode
0 = PAL mode
0
1 = MAC mode
0 = composite video mode
1 to 0
MAC and NTSC cannot be used at the same time, therefore this combination is used to enable full VBI data
reception in Caption mode
02A0 H
Write
ACQ ANALOG MODE
Bit
7
Reset
0
Function
1 = full N clamping
0 = half N clamping
(*150 µA)
(* 75 µA)
6
5
1
0
1 = N clamping disable
0 = N clamping enable
(*150 µA if data < sync slicer level)
(+225 µA if data = 0, *6 µA static)
1 = clamping disable
0 = clamping enable
4 to 0
10 H
5 bit analog gain of AGC
31 = 12dB
16 = 6dB
00 = 0dB
02A3 H
Write
Reset
0
ACQ VIDEO INPUT
Bit
0
Function
1 = video input 2
0 = video input 1
(pin 44)
(pin 42)
02A4 H
Read
ACQ HSYNC COUNTER
Bit
Reset
0
Function
7 to 0
number of detected horizontal sync pulses per frame divided by 4
sync pulse is detected if within horizontal window of HPLL
counter is latched with vertical sync, the register can be read at any time
MICRONAS INTERMETALL
65
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
5. Application
22pF 22pF
256Kbit – 16Mbit DRAM
10nF
12
20.25Mhz
XTAL2 XTAL1
RIN
A[0...11] CAS RAS
WE DATA TEST
33nF
33nF
100nF
100nF
100nF
VIN1
VIN2
VRT
GIN
100nF 10 µF
BIN
2 x 75Ω
FBIN
SGND
4 x 75 Ω
TPU 3040
HSYNC
VSYNC
+5 V
AVSUP
AGND
DVSUP
DGND
100nF
100nF
FBOUT
ROUT
GOUT
BOUT
+5 V
RESET
IR
SDA SCL
10k
1k
1k
1k
100nF
+5 V
+5 V
Fig. 5–1: TPU 3040 Application with DRAM
66
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
22pF 22pF
10nF
OE
CE
256K/1Mbit SRAM
17
A[0...16]
8
20.25Mhz
WE
DATA
TEST
XTAL2 XTAL1
RIN
33nF
33nF
100nF
100nF
100nF
VIN1
VIN2
VRT
GIN
100nF 10 µF
BIN
2 x 75Ω
FBIN
SGND
4 x 75 Ω
TPU 3050
HSYNC
VSYNC
+5 V
AVSUP
AGND
DVSUP
DGND
100nF
100nF
FBOUT
ROUT
GOUT
BOUT
+5 V
RESET
SDA SCL
PGND
PVSUP
10k
1k
1k
1k
100nF
100nF
+5 V
+5 V
+5 V
Fig. 5–2: TPU 3050 Application with SRAM
MICRONAS INTERMETALL
67
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
7. References
6. Glossary of Abbreviations
AIT
Additional Information Table
Basic TOP Table
1) “World System Teletext and Data Broadcasting
System”. Technical Specification. February 1990.
BTT
BTTL
CEPT
Basic TOP Table List
2) “Teletext Specification”. Interim Technical Docu-
ment SPB 492. European Broadcasting Union.
December 1992.
Conférence Européene des Administra-
tions des Postes et Télécommunication
CLUT
CPU
CRI
Color Look Up Table
3) “8R2 Video-Programm-System (VPS)”.
Technische Richtlinie ARD/ZDF.
Central Processing Unit
Clock Runin
4) “8R4 Fernsehtext-Spezifikation”. Technische
Richtlinie ARD/ZDF.
DRAM
DRCS
FLOF
FRC
MAC
MPT
MPET
OSD
PDC
PLT
Dynamic Random Access Memory
Dynamically Redefinable Character Set
Full Level One Features
Framing Code
5) “8R5 TOP-Verfahren für Fernsehtext”.
Technische Richtlinie ARD/ZDF.
6) “Specification of the domestic video Programme
Delivery Control system (PDC)”. European
Broadcasting Union. August 1990.
Multiplexed Analogue Components
Multipage Table
7) “Television systems; 625-Line television Wide
Screen Signalling (WSS)”. ETSI.
November 1993.
Multipage Extension Table
On Screen Display
Programme Delivery Control
Page Linking Table
8) “Television Captioning for the Deaf”. Signal and
Display Specifications. May 1980.
RAM
ROM
SRAM
TOP
TPU
Random Access Memory
Read Only Memory
Static Random Access Memory
Table Of Pages
Teletext Processing Unit
Teletext
TTX
VBI
Vertical Blanking Interval
Video-Programm-System
Wide Screen Signalling
World System Teletext
VPS
WSS
WST
68
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
69
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
70
MICRONAS INTERMETALL
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
71
TPU 3035, TPU 3040, TPU 3050
PRELIMINARY DATA SHEET
8. Data Sheet History
1. Preliminary data sheet: “TPU 3040”, Nov. 27, 1992,
6251-349-1PD.
5. Preliminary data sheet: “TPU 3035, TPU 3040”,
Dec. 9, 1996, 6251-349-5PD.
First release of the preliminary data sheet.
Fifth release of the preliminary data sheet.
Major changes:
2. Preliminary data sheet: “TPU 3040”, June 28, 1993,
6251-349-2PD.
Second release of the preliminary data sheet.
– section 4.14.: subpage manager extension
– section 4.16.: RGB mode bit 6 added
6. Preliminary data sheet: “TPU 3035, TPU 3040, TPU
3050”, Feb. 23, 1998, 6251-349-6PD.
Sixth release of the preliminary data sheet.
Major changes:
3. Preliminary data sheet: “TPU 3040”, Dec. 20, 1993,
6251-349-3PD.
Third release of the preliminary data sheet.
4. Preliminary data sheet: “TPU 3035, TPU 3040”,
Sept. 20, 1995, 6251-349-4PD.
Fourth release of the preliminary data sheet.
Major changes:
– Combined data sheet for TPU 3035, TPU 3040,
TPU 3050.
– SRAM interface for TPU 3050
– Combined data sheet for TPU 3035 and TPU 3040.
– section 3.1.: Outline Dimensions changed
MICRONAS INTERMETALL GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
All information and data contained in this data sheet are with-
out any commitment, are not to be considered as an offer for
conclusion of a contract nor shall they be construed as to
create any liability. Any new issue of this data sheet invalidates
previous issues. Product availability and delivery dates are ex-
clusively subject to our respective order confirmation form; the
same applies to orders based on development samples deliv-
ered. By this publication, MICRONAS INTERMETALL GmbH
does not assume responsibility for patent infringements or
other rights of third parties which may result from its use.
Reprinting is generally permitted, indicating the source. How-
ever, our prior consent must be obtained in all cases.
E-mail: docservice@intermetall.de
Internet: http://www.intermetall.de
Printed in Germany
Order No. 6251-349-6PD
72
MICRONAS INTERMETALL
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