ICM-20690 [TDK]
IMU (惯性测量设备);
TDK ELECTRONICS 
ICM-20690
ICM-20690 Datasheet
This document contains information on a pre-
production product. InvenSense Inc. reserves the
right to change specifications and information
herein without notice.
InvenSense Inc.
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
Document Number: DS-000178
Revision: 1.0
Rev. Date: 10/11/2016
www.invensense.com
ICM-20690
TABLE OF CONTENTS
Table of Figures............................................................................................................................................................... 7
Table of Tables................................................................................................................................................................ 7
1
2
3
Introduction......................................................................................................................................................... 8
1.1 Purpose and Scope....................................................................................................................................8
1.2 Product Overview......................................................................................................................................8
1.3 Applications...............................................................................................................................................8
Features ............................................................................................................................................................... 9
2.1 Gyroscope Features ..................................................................................................................................9
2.2 Accelerometer Features............................................................................................................................9
2.3 Additional Features...................................................................................................................................9
Electrical Characteristics.................................................................................................................................... 10
3.1 Gyroscope Specifications ........................................................................................................................10
3.2 Accelerometer Specifications..................................................................................................................11
3.3 Electrical Specifications...........................................................................................................................12
3.4 I2C Timing Characterization.....................................................................................................................15
3.5 SPI Timing Characterization – 4-Wire SPI Mode .....................................................................................16
3.6 SPI Timing Characterization – 3-Wire SPI Mode .....................................................................................17
3.7 Absolute Maximum Ratings ....................................................................................................................18
Applications Information ................................................................................................................................... 19
4.1 Pin Out Diagram and Signal Description .................................................................................................19
4.2 Typical Operating Circuit.........................................................................................................................20
4.3 Bill of Materials for External Components ..............................................................................................21
4.4 Block Diagram .........................................................................................................................................22
4.5 Overview .................................................................................................................................................22
4.6 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ...............................................22
4.7 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning.........................................23
4.8 I2C and SPI Host Interface .......................................................................................................................23
4.9 SPI OIS Interface and Auxiliary I2C Interface ...........................................................................................23
4
4.10
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
Self-Test ..............................................................................................................................................23
Clocking...............................................................................................................................................23
Sensor Data Registers .........................................................................................................................24
FIFO.....................................................................................................................................................24
Interrupts............................................................................................................................................24
Digital-Output Temperature Sensor ...................................................................................................24
Bias and LDOs .....................................................................................................................................24
Charge Pump ......................................................................................................................................24
Standard Power Modes ......................................................................................................................24
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ICM-20690
5
6
Programmable Interrupts .................................................................................................................................. 25
5.1 Wake-on-Motion Interrupt .....................................................................................................................26
Digital Interface ................................................................................................................................................. 27
6.1 I2C and SPI Serial Interfaces ....................................................................................................................27
6.2 I2C Interface.............................................................................................................................................27
6.3 I2C Communications Protocol .................................................................................................................28
6.4 I2C Terms .................................................................................................................................................30
6.5 SPI Interface ............................................................................................................................................31
Assembly............................................................................................................................................................ 32
7.1 Orientation of Axes .................................................................................................................................32
7.2 Package Dimensions................................................................................................................................33
Part Number Package Marking.......................................................................................................................... 35
Environmental Compliance................................................................................................................................ 36
Use Notes........................................................................................................................................................... 37
7
8
9
10
10.1
Valid Combinations Of UI And OIS Datapath Settings ........................................................................37
FIFO Watermark Threshold ................................................................................................................37
FIFO Watermark Interrupt..................................................................................................................37
Accelerometer-Only Low-Noise Mode ...............................................................................................37
Accelerometer Low-Power Mode.......................................................................................................38
Sensor Mode Change..........................................................................................................................38
Temp Sensor during Gyroscope Standby Mode .................................................................................38
Gyroscope Mode Change....................................................................................................................38
Power Management 1 Register Setting ..............................................................................................38
Unlisted Register Locations ................................................................................................................38
Clock Transition When Gyroscope is Turned Off ................................................................................38
Sleep Mode.........................................................................................................................................38
No special operation needed for FIFO read in low power mode........................................................38
Gyroscope Standby Procedure ...........................................................................................................39
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
11
12
Register Map...................................................................................................................................................... 40
11.1 Registers Specific To Secondary Interface In OIS Mode .....................................................................43
Register Descriptions ......................................................................................................................................... 44
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Registers 0 to 2 – Gyroscope Self-Test Registers................................................................................44
Registers 13 to 15 – Accelerometer Self-Test Registers .....................................................................45
Register 19 – Gyro Offset Adjustment Register..................................................................................45
Register 20 – Gyro Offset Adjustment Register..................................................................................45
Registers 21 – Gyro Offset Adjustment Register ................................................................................46
Registers 22 – Gyro Offset Adjustment Register ................................................................................46
Registers 23 – Gyro Offset Adjustment Register ................................................................................46
Register 24 – Gyro Offset Adjustment Register..................................................................................46
Register 25 – Sample Rate Divider......................................................................................................47
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ICM-20690
12.10
12.11
12.12
12.13
12.14
12.15
12.16
12.17
12.18
12.19
12.20
12.21
12.22
12.23
12.24
12.25
12.26
12.27
12.28
12.29
12.30
12.31
12.32
12.33
12.34
12.35
12.36
12.37
12.38
12.39
12.40
12.41
12.42
12.43
12.44
12.45
12.46
12.47
12.48
12.49
Register 26 – Configuration ................................................................................................................47
Register 27 – Gyroscope Configuration ..............................................................................................48
Register 28 – Accelerometer Configuration .......................................................................................49
Register 29 – Accelerometer Configuration 2.....................................................................................49
Register 30 – Gyroscope Low Power Mode ConfiguratioN ................................................................50
Register 32 – Wake-On Motion Threshold (X-Axis Accelerometer) ...................................................50
Register 33 – Wake-On Motion Threshold (Y-Axis Accelerometer)....................................................51
Register 34 – Wake-On Motion Threshold (Z-Axis Accelerometer)....................................................51
Register 35 – FIFO Enable ...................................................................................................................51
Register 36 – I2C Master Control ........................................................................................................52
Register 37 – I2C Slave 0 Physical Address..........................................................................................52
Register 38 – I2C Slave 0 Register Address..........................................................................................53
Register 39 – I2C Slave 0 Control.........................................................................................................53
Register 40 – I2C Slave 1 Physical Address..........................................................................................53
Register 41 – I2C Slave 1 Register Address..........................................................................................54
Register 39 – I2C Slave 1 Control.........................................................................................................54
Register 43 – I2C Slave 2 Physical Address..........................................................................................54
Register 44 – I2C Slave 2 Register Address..........................................................................................55
Register 45 – I2C Slave 2 Control.........................................................................................................55
Register 46 – FSYNC ODR Delay Enable ..............................................................................................55
Register 54 – FSYNC Interrupt Status..................................................................................................56
Register 55 – INT Pin Configuration....................................................................................................56
Register 56 – Interrupt Enable............................................................................................................56
Register 57 – FIFO Watermark Interrupt Status .................................................................................57
Register 58 – Interrupt Status.............................................................................................................57
Register 59 – High Byte Of Accelerometer X-Axis Data ......................................................................57
Register 60 – Low Byte Of Accelerometer X-Axis Data.......................................................................57
Register 61 – High Byte Of Accelerometer Y-Axis Data ......................................................................58
Register 62 – Low Byte Of Accelerometer Y-Axis Data .......................................................................58
Register 63 – High Byte Of Accelerometer Z-Axis Data ......................................................................58
Register 64 – Low Byte Of Accelerometer Z-Axis Data .......................................................................58
Register 65 – High Byte Of Temperature Sensor Data........................................................................58
Register 66 – Low Byte Of Temperature Sensor Data ........................................................................59
Register 67 – High Byte Of Gyroscope X-Axis Data.............................................................................59
Register 68 – Low Byte Of Gyroscope X-Axis Data..............................................................................59
Register 69 – High Byte Of Gyroscope Y-Axis Data.............................................................................59
Register 70 – Low Byte Of Gyroscope Y-Axis Data..............................................................................59
Register 71 – High Byte Of Gyroscope Z-Axis Data.............................................................................60
Register 72 – Low Byte Of Gyroscope Z-Axis Data..............................................................................60
Register 73 – Sensor Data From External I2C devices .........................................................................60
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ICM-20690
12.50
12.51
12.52
12.53
12.54
12.55
12.56
12.57
12.58
12.59
12.60
12.61
12.62
12.63
12.64
12.65
12.66
12.67
12.68
12.69
12.70
12.71
12.72
12.73
12.74
12.75
12.76
12.77
Register 74 – Sensor Data From External I2C devices .........................................................................60
Register 75 – Sensor Data From External I2C devices .........................................................................60
Register 76 – Sensor Data From External I2C devices .........................................................................61
Register 77 – Sensor Data From External I2C devices .........................................................................61
Register 78 – Sensor Data From External I2C devices .........................................................................61
Register 79 – Sensor Data From External I2C devices .........................................................................61
Register 80 – Sensor Data From External I2C devices .........................................................................61
Register 81 – Sensor Data From External I2C devices .........................................................................62
Register 82 – Sensor Data From External I2C devices .........................................................................62
Register 83 – Sensor Data From External I2C devices .........................................................................62
Register 84 – Sensor Data From External I2C devices .........................................................................62
Register 95 – FSYNC ODR Delay Counter High Byte............................................................................63
Register 96 – FSYNC ODR Delay Counter Low Byte ............................................................................63
Register 97 – FIFO Watermark Threshold In Number Of Bytes ..........................................................63
Register 99 – Slave 0 Data Out ...........................................................................................................63
Register 100 – Slave 1 Data Out .........................................................................................................63
Register 101 – Slave 2 Data Out .........................................................................................................64
Register 103 – I2C Master Delay Control............................................................................................64
Register 104 – Signal Path Reset.........................................................................................................64
Register 105 – Accelerometer Intelligence Control............................................................................65
Register 106 – User Control................................................................................................................65
Register 107 – Power Management 1 ................................................................................................66
Register 108 – Power Management 2 ................................................................................................67
Register 112 – OIS Enable...................................................................................................................67
Registers 114 and 115 – FIFO Count Registers ...................................................................................68
Register 116 – FIFO Read Write..........................................................................................................68
Register 117 – WHO AM I ...................................................................................................................69
Register 119 to 126 – Accelerometer Offset Registers.......................................................................70
13
Description Of Registers Specific To Secondary Interface In OIS Mode ............................................................ 71
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
13.11
Register 0 – High Byte Of Accelerometer X-Axis OIS Data..................................................................71
Register 1 – Low Byte Of Accelerometer X-Axis OIS Data...................................................................71
Register 2 – High Byte Of Accelerometer Y-Axis OIS Data..................................................................71
Register 3 – Low Byte Of Accelerometer Y-Axis OIS Data...................................................................71
Register 4 – High Byte Of Accelerometer Z-Axis OIS Data ..................................................................71
Register 5 – Low Byte Of Accelerometer Z-Axis OIS Data...................................................................72
Register 6 – High Byte Of Temperature Sensor OIS Data ...................................................................72
Register 7 – Low Byte Of Temperature Sensor OIS Data ....................................................................72
Register 8 – High Byte Of Gyroscope X-Axis OIS Data ........................................................................72
Register 9 – Low Byte Of Gyroscope X-Axis OIS Data .........................................................................72
Register 10 – High Byte Of Gyroscope Y-Axis OIS Data.......................................................................73
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Document Number: DS-000178
Revision: 1.0
ICM-20690
13.12
13.13
13.14
Register 11 – Low Byte Of Gyroscope Y-Axis OIS Data .......................................................................73
Register 12 – High Byte Of Gyroscope Z-Axis OIS Data.......................................................................73
Register 13 – Low Byte Of Gyroscope Z-Axis OIS Data .......................................................................73
14
15
Reference........................................................................................................................................................... 74
Document Information ...................................................................................................................................... 75
15.1
Revision History ..................................................................................................................................75
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Document Number: DS-000178
Revision: 1.0
ICM-20690
TABLE OF FIGURES
Figure 1. I2C Bus Timing Diagram ........................................................................................................................................15
Figure 2. 4-Wire SPI Bus Timing Diagram............................................................................................................................16
Figure 3. 3-Wire SPI Bus Timing Diagram............................................................................................................................17
Figure 4. Pin Out Diagram for ICM-20690 2.5x3.0x0.91 mm LGA .......................................................................................19
Figure 5. ICM-20690 Application Schematic (I2C Interface to Host & OIS Operation).........................................................20
Figure 6. ICM-20690 Application Schematic (SPI Interface to Host & OIS Operation) ........................................................20
Figure 7. ICM-20690 Block Diagram.....................................................................................................................................22
Figure 8. START and STOP Conditions ...............................................................................................................................28
Figure 9. Acknowledge on the I2C Bus .................................................................................................................................28
Figure 10. Complete I2C Data Transfer.................................................................................................................................29
Figure 11. Typical SPI Master/Slave Configuration ..............................................................................................................31
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation ..................................................................................32
TABLE OF TABLES
Table 1. Gyroscope Specifications .......................................................................................................................................10
Table 2. Accelerometer Specifications.................................................................................................................................11
Table 3. D.C. Electrical Characteristics ................................................................................................................................12
Table 4. A.C. Electrical Characteristics.................................................................................................................................13
Table 5. Other Electrical Specifications ................................................................................................................................14
Table 6. I2C Timing Characteristics.......................................................................................................................................15
Table 7. SPI Timing Characteristics (10-MHz Operation).....................................................................................................16
Table 8. SPI Timing Characteristics (20-MHz Operation).....................................................................................................17
Table 9. Absolute Maximum Ratings ....................................................................................................................................18
Table 10. Signal Descriptions ...............................................................................................................................................19
Table 11. Bill of Materials......................................................................................................................................................21
Table 12. Standard Power Modes for ICM-20690 ................................................................................................................24
Table 13. Table of Interrupt Sources ....................................................................................................................................25
Table 14. Serial Interface......................................................................................................................................................27
Table 15. I2C Terms ..............................................................................................................................................................30
Table 16. ICM-20690 Register Map......................................................................................................................................42
Table 17. Registers Specific to Secondary Interface in OIS Mode.......................................................................................43
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Document Number: DS-000178
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ICM-20690
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on the ICM-20690
Dual-Interface MotionTracking device. The device is housed in a small 2.5x3x0.91 mm 14-pin LGA package.
1.2 PRODUCT OVERVIEW
The ICM-20690 is a 6-axis MotionTracking device with a main Interface for UI and an Auxiliary interface configurable as SPI slave for
Optical Image Stabilization (OIS) applications or as I2C Master to support other sensors such as a compass or pressure sensor. It
combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 2.5x3x0.91 mm (14-pin LGA) package. The device supports
independent data paths for UI and OIS, with independent control for full-scale range (FSR), output data rate (ODR).
ICM-20690 also features a 1K-byte FIFO that can lower the traffic on the serial bus interface, and reduce power consumption by
allowing the system processor to burst read sensor data and then go into a low-power mode. ICM-20690, with its 6-axis integration,
enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices,
guaranteeing optimal motion performance for consumers.
The gyroscope and accelerometer support the following independently programmable full-scale range settings:
Signal Path
UI Path
Gyroscope
Accelerometer
±31.25, ±62.5, ±125, ±250, ±500,
±1000, and ±2000 degrees/sec
±31.25, ±62.5, ±125, ±250, ±500,
±1000, and ±2000 degrees/sec
±2, ±4, ±8, ±16g
OIS Path
±1, ±2, ±4, ±8g
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71 V to 3.45 V, and a separate
digital IO supply, VDDIO from 1.71 V to 3.45 V.
The host interface can be configured to support SPI slave or I2C slave modes. The SPI interface supports speeds up to 10 MHz and
the I2C interface supports speeds up to 400 kHz. A secondary interface can be configured to support SPI slave mode (3-wire) for
interfacing to OIS controllers, or I2C master mode for interfacing to external sensors. The SPI interface supports speeds up to
20 MHz and the I2C interface supports speeds up to 400 kHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
2.5x3x0.91 mm (14-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness
by supporting 20,000g shock reliability.
1.3 APPLICATIONS
Smartphones and Tablets
Head Mounted Displays
Wearable Sensors
Page 8 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-20690 includes a wide range of features:
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with independently programmable full-scale range of
±31.25, ±62,5, ±125, ±250, ±500, ±1000, and ±2000 degrees/sec for UI and OIS paths
Integrated 16-bit ADCs per axis
Digitally-programmable low-pass filters
Low-power gyroscope operation
Factory calibrated sensitivity scale factor
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-20690 includes a wide range of features:
Digital-output X-, Y-, and Z-axis accelerometer with independently programmable full-scale range of ±2g, ±4g, ±8g and ±16g
for UI path and ±1g, ±2g, ±4g and ±8g for OIS path
Integrated 16-bit ADCs per axis
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 ADDITIONAL FEATURES
The ICM-20690 includes the following additional features:
Smallest and thinnest LGA package for portable devices: 2.5x3x0.91 mm (14-pin LGA)
1K byte FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope, accelerometer, and temp sensor
20,000 g shock tolerant
Main interface: 10 MHz SPI / 400 kHz I2C slave host interface
Auxiliary interface: 20 MHz SPI slave OIS controller interface / 400 kHz I2C master interface for external sensors
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Page 9 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
FS_SEL=5
FS_SEL=6
FS_SEL=7
±250
±500
±1000
±2000
±31.25
±62.5
±125
16
º/s
º/s
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
º/s
Full-Scale Range
º/s
º/s
º/s
º/s
Gyroscope ADC Word Length
Sensitivity Scale Factor
bits
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
FS_SEL=5
FS_SEL=6
FS_SEL=7
25°C
131
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
%
65.5
32.8
16.4
1048.6
524.3
262
Sensitivity Scale Factor Initial Tolerance
±1
Sensitivity Scale Factor Variation Over
Temperature
-40°C to +85°C
±0.01
%/ºC
1
Nonlinearity
Best fit straight line; 25°C
±0.1
±1
%
%
1
1
Cross-Axis Sensitivity
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
±1
º/s
1
1
ZRO Variation vs. Temperature
-40°C to +85°C
±0.01
º/s/ºC
OTHER PARAMETERS
Rate Noise Spectral Density
Total RMS Noise
@ 10 Hz
0.004
0.04
27
º/s/√Hz
º/s-rms
KHz
1
1, 4
2
Bandwidth = 100 Hz
Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start-Up Time
25
5
29
Programmable Range
Time from gyro enable to gyro drive ready
Low-Noise Mode
250
Hz
ms
Hz
3
1, 5
3
80
3.91
3.91
32k
Output Data Rate
3
Low-Power Mode
333.33
Hz
Table 1. Gyroscope Specifications
Notes:
1. Target spec. Subject to update.
2. Tested in production.
3. Guaranteed by design.
4. For low-noise mode.
5. The gyroscope output will be stable if ~200 ms are provided between a disable and the subsequent enable of the sensor.
Page 10 of 76
Document Number: DS-000178
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ICM-20690
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
±2
±4
g
g
2
2
2
2
2
2
2
2
2
1
1
1
1
Full-Scale Range
±8
g
±16
g
ADC Word Length
Output in two’s complement format
AFS_SEL=0
16
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
16,384
8,192
4,096
2,048
±1
AFS_SEL=1
Sensitivity Scale Factor
AFS_SEL=2
AFS_SEL=3
Component-level
Sensitivity Scale Factor Initial Tolerance
Sensitivity Change vs. Temperature
Nonlinearity
-40°C to +85°C
±0.008
±0.3
±1
%/ºC
%
Best Fit Straight Line
Cross-Axis Sensitivity
%
ZERO-G OUTPUT
Initial Tolerance
Board-level, all axes
±40
±0.5
±1
mg
1
1
1
X & Y-axis (-40°C to +85°C)
Z-axis (-40°C to +85°C)
mg/ºC
mg/ºC
Zero-G Level Change vs. Temperature
OTHER PARAMETERS
Power Spectral Density
RMS Noise
@ 10 Hz
100
1
µg/√Hz
1
Bandwidth = 100 Hz
mg-rms
1, 3
Low-Pass Filter Response
Accelerometer Startup Time
Programmable Range
From sleep mode to valid data
Low-Noise Mode
5
218
Hz
ms
Hz
Hz
2
2
2
2
10
3.91
3.91
4000
500
Output Data Rate
Low-Power Mode
Table 2. Accelerometer Specifications
Notes:
1. Target spec. Subject to update.
2. Guaranteed by design.
3. For low-noise mode.
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Document Number: DS-000178
Revision: 1.0
ICM-20690
3.3 ELECTRICAL SPECIFICATIONS
3.3.1 D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
MIN
TYP
MAX
UNITS
NOTES
VDD
1.71
1.71
1.8
1.8
3.45
3.45
V
V
2
2
VDDIO
SUPPLY CURRENTS
6-Axis Gyroscope + Accelerometer
Low-Noise Mode
3.1
440
2.9
mA
µA
1
1
1
3-Axis Accelerometer
3-Axis Gyroscope
mA
Accelerometer Low -Power Mode
(Gyroscope disabled)
100Hz ODR, 1x averaging
100Hz ODR, 1x averaging
50
µA
1
1
Gyroscope Low-Power Mode
(Accelerometer disabled)
1.40
mA
6-Axis Low-Power Mode (Gyroscope
Low-Power Mode; Accelerometer Low-
Noise Mode)
100Hz ODR, 1x averaging
At 25ºC
1.66
6
mA
µA
1
1
Full-Chip Sleep Mode
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
°C
1
Table 3. D.C. Electrical Characteristics
Notes:
1. Target spec. Subject to update.
2. Derived from validation or characterization of parts, not guaranteed in production.
Page 12 of 76
Document Number: DS-000178
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ICM-20690
3.3.2 A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Monotonic ramp. Ramp rate is 10% to 90% of
the final value
Supply Ramp Time
0.01
3
ms
1
1
mV
peak-peak
Power Supply Noise
10
TEMPERATURE SENSOR
Operating Range
25°C Output
ADC Resolution
Ambient
-40
85
°C
LSB
bits
Hz
Hz
°C
µs
LSB/°C
%
1
3
2
2
2
3
2
1
1
0
16
8000
Without Filter
With Filter
25°C
ODR
3.91
-15
1000
15
14000
Room Temperature Offset
Stabilization Time
Sensitivity
Untrimmed
326.8
Sensitivity Error
-2.5
+2.5
1
POWER-ON RESET
I2C ADDRESS
Start-up time for register read/write
From power-up
ms
1
1
1
AD0 = 0
AD0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, AD0, SCLK, SDI, CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
V
V
0.3*VDDIO
< 10
pF
DIGITAL OUTPUT (SDO, INT1, INT2)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
RLOAD=1 MΩ;
RLOAD=1 MΩ;
0.9*VDDIO
V
V
V
0.1*VDDIO
0.1
OPEN=1, 0.3 mA sink
Current
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
100
50
nA
µs
LATCH_INT_EN=0
I2C I/O (SCL, SDA)
-0.5 V
VIL, LOW-Level Input Voltage
VIH, HIGH-Level Input Voltage
0.3*VDDIO
V
V
0.7*VDDIO
VDDIO +
0.5 V
Vhys, Hysteresis
0.1*VDDIO
V
V
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3 mA sink current
0
0.4
1
VOL=0.4 V
VOL=0.6 V
3
6
mA
mA
Output Leakage Current
100
nA
ns
tof, Output Fall Time from VIHmax to VILmax
Cb bus capacitance in pf
20+0.1Cb
300
INTERNAL CLOCK SOURCE
FCHOICE_B=1,2,3; SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=0 or 7
SMPLRT_DIV=0
FCHOICE_B=0;
32
8
kHz
kHz
2
2
Sample Rate
DLPFCFG=1,2,3,4,5,6;
1
kHz
2
SMPLRT_DIV=0
CLK_SEL=0, 6 or gyro inactive; 25°C
-3
-1
+3
+1
±2
±2
%
%
%
%
1
1
1
1
Clock Frequency Initial Tolerance
CLK_SEL=1,2,3,4,5 and gyro active; 25°C
CLK_SEL=0,6 or gyro inactive. (-40°C to +85°C)
CLK_SEL=1,2,3,4,5 and gyro active
Frequency Variation over Temperature
Table 4. A.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
3. Production tested.
Page 13 of 76
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Revision: 1.0
ICM-20690
3.3.3 Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SERIAL INTERFACE
Low Speed Characterization
High Speed Characterization
OIS Mode Characterization
100
0.2
100 ±10%
1
kHz
MHz
MHz
1,3
SPI Operating Frequency, All Registers
Read/Write
10
20
1, 2, 3
1, 2, 3
SPI Modes
0 and 3
All registers, Fast-mode
100
400
100
kHz
kHz
1
1
I2C Operating Frequency
All registers, Standard-mode
Table 5. Other Electrical Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. SPI clock duty cycle between 45% and 55% should be used for 10-MHz/20-MHz operation.
3. Minimum SPI/I2C clock rate is dependent on ODR. If ODR is below 4 kHz, minimum clock rate is 100 kHz. If ODR is greater than 4 kHz, minimum clock rate is
200 kHz.
Page 14 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
3.4
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
I2C TIMING CHARACTERIZATION
Parameters
I2C TIMING
Conditions
I2C FAST-MODE
Min
Typical
Max
Units
Notes
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
100
0.6
400
kHz
µs
1
1
tLOW, SCL Low Period
1.3
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
0.6
0
100
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
20+0.1Cb
20+0.1Cb
0.6
300
300
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
tBUF, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
< 400
pF
µs
µs
1
1
1
0.9
0.9
tVD.ACK, Data Valid Acknowledge Time
Table 6. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf
tSU.DAT
tr
SDA
SCL
70%
30%
70%
30%
continued below at
9th clock cycle
A
tf
tr
tVD.DAT
70%
30%
70%
30%
tHD.DAT
tHD.STA
1/fSCL
tLOW
1st clock cycle
S
tHIGH
tBUF
SDA
SCL
70%
30%
A
tSU.STO
tSU.STA
tHD.STA
tVD.ACK
70%
30%
9th clock cycle
S
P
Sr
Figure 1. I2C Bus Timing Diagram
Page 15 of 76
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Revision: 1.0
ICM-20690
3.5 SPI TIMING CHARACTERIZATION – 4-WIRE SPI MODE
The following section is applicable to 4-wire SPI mode for the Main Interface.
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
2
56
56
2
tHD.CS, CS Hold Time
63
3
tSU.SDI, SDI Setup Time
tHD.SDI, SDI Hold Time
tVD.SDO, SDO Valid Time
tHD.SDO, SDO Hold Time
tDIS.SDO, SDO Output Disable Time
tFall, SCLK Fall Time
7
Cload = 20 pF
Cload = 20 pF
40
6
20
6.5
6.5
tRise, SCLK Rise Time
Table 7. SPI Timing Characteristics (10-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
tHD;CS
tSU;CS
70%
tHIGH
1/fCLK
SCLK
30%
tSU;SDI
tHD;SDI
tLOW
70%
30%
SDI
LSB IN
MSB IN
tDIS;SDO
tVD;SDO
tHD;SDO
70%
30%
SDO
MSB OUT
LSB OUT
Figure 2. 4-Wire SPI Bus Timing Diagram
Page 16 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
3.6 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
The following section is applicable to 3-wire SPI mode for the Auxiliary Interface.
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
2
30
30
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
14.5
9
tHD.CS, CS Hold Time
tSU.SDIO, SDOI Input Setup Time
tHD.SDIO, SDIO Input Hold Time
tVD.SDIO, SDIO Output Valid Time
tHD.SDIO, SDIO Output Hold Time
tDIS.SDIO, SDIO Output Disable Time
tFall, SCLK Fall Time
3.5
8.5
Cload = 20 pF
Cload = 20 pF
21
19
41
8
tRise, SCLK Rise Time
8
Table 8. SPI Timing Characteristics (20-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
tHD;CS
tSU;CS
70%
tHIGH
1/fCLK
SCLK
30%
tSU;SDIO
tHD;SDIO
tLOW
70%
30%
I
LSB IN
MSB IN
tDIS;SDIO
tVD;SDIO
tHD;SDIO
70%
30%
O
MSB OUT
LSB OUT
Figure 3. 3-Wire SPI Bus Timing Diagram
Page 17 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
3.7 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
Parameter
Rating
-0.5 V to +4 V
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
-0.5 V to +4 V
-0.5 V to 2 V
Input Voltage Level (AD0, FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
-0.5 V to VDDIO + 0.5 V
20,000g for 0.2 ms
-40°C to +85°C
-40°C to +125°C
2 kV (HBM);
250 V (MM)
Electrostatic Discharge (ESD) Protection
Latch-up
JEDEC Class II (2),125°C
±100 mA
Table 9. Absolute Maximum Ratings
Page 18 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Number
Pin Name
Pin Description
Application Processor (AP) Interface: AP I2C slave address LSB (AP_AD0); AP
SPI serial data output (AP_SDO)
1
AP_AD0 / AP_SDO
2
3
OIS_SDIO / AUX_DA
OIS_SCLK / AUX_CL
INT1
OIS SPI serial data IO (OIS_SDIO); I2C master serial data (AUX_DA)
OIS SPI serial clock (OIS_SCLK); I2C master serial clock (AUX_CL)
Interrupt digital output (totem pole or open-drain)
Digital I/O supply voltage
4
5
VDDIO
6
GND
Power supply ground
7
RESV
Reserved, connect to ground
8
VDD
Power supply voltage
9
INT2
Interrupt digital output (totem pole or open-drain)
Frame synchronization digital input; OIS SPI chip select (OIS_CS)
Regulator filter capacitor connection
10
11
12
13
14
FSYNC / OIS_CS
REGOUT
AP_CS
AP SPI Chip select (SPI mode only)
AP_SCL / AP_SCLK
AP_SDA / AP_SDI
AP I2C serial clock (AP_SCL); AP SPI serial clock (AP_SCLK)
AP I2C serial data (AP_SDA); AP SPI serial data input (AP_SDI)
Table 10. Signal Descriptions
Note: Power up with AP_SCL / AP_SCLK and AP_CS pins held low is not a supported use case. In case this power up approach is used, software
reset is required using the PWR_MGMT_1 register, prior to initialization.
AP_AD0 / AP_SDO
1
2
3
4
11
10
9
REGOUT
FSYNC / OIS_CS
INT2
+Z
OIS_SDIO / AUX_DA
OIS_SCLK / AUX_CL
INT1
I
C
M
ICM-20690
-
2
0
6
9
0
8
VDD
+Y
+X
Orientation of Axes of and Polarity of Rotation
LGA Package (Top view)
Figure 4. Pin Out Diagram for ICM-20690 2.5x3.0x0.91 mm LGA
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ICM-20690
4.2 TYPICAL OPERATING CIRCUIT
SCL
SDA
VDDIO
14
13
12
AP_AD0
AD0
REGOUT
11
10
9
1
2
C1, 0.1 mF
OIS_SDIO
OIS_CS
INT2
ICM-20690
OIS_SCLK
INT1
3
4
1.71 – 3.45VDC
C4, 2.2 mF
VDD
8
5
6
7
C2, 0.1 mF
1.71 – 3.45VDC
C3, 10 nF
Figure 5. ICM-20690 Application Schematic (I2C Interface to Host & OIS Operation)
Note: I2C lines are open drain and pull-up resistors (e.g. 10 kΩ) are required.
SDI SCLK
nCS
12
14
13
AP_SDO
REGOUT
SDO
11
10
9
1
2
C1, 0.1 mF
OIS_SDIO
OIS_SCLK
INT1
OIS_CS
INT2
ICM-20690
3
4
1.71 – 3.45VDC
C4, 2.2 mF
VDD
8
5
6
7
C2, 0.1 mF
1.71 – 3.45VDC
C3, 10 nF
Figure 6. ICM-20690 Application Schematic (SPI Interface to Host & OIS Operation)
Page 20 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component
Label
Specification
Quantity
REGOUT Capacitor
C1
X7R, 0.1µF ±10%
1
C2
C4
X7R, 0.1µF ±10%
X7R, 2.2µF ±10%
1
1
VDD Bypass Capacitors
VDDIO Bypass Capacitor
C3
X7R, 10nF ±10%
1
Table 11. Bill of Materials
Page 21 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
4.4 BLOCK DIAGRAM
M2: filter
M2: filter
Accel Digital
Filters (UI)
CV
CV
MUX
MUX
3x Accel
3x Gyro
3x ADC
I2C/SPI
M1: raw
M1: raw
To Host
Select ODR &
FSR
Sensor
Slave
Registers
Interface
Gyro Digital
Filters (UI)
CV
CV
3x ADC
1x ADC
SRAM/FIFO
1 Kbyte
Temp Sensor
Digital Filters
(UI)
Temp
Sensor
M2: filter
1x FSYNC
Input
CV
CV
MUX
M1: raw
OIS FSR & ODR
selection
Select ODR & FSR
SPI Slave mode
for OIS
I2C Master mode for
external sensors
Sensor Registers
SPI Slave
I2C Master Interface
M: OIS Modes
1x OIS Controller
(SPI Master) OR External
Sensors (I2C Slaves)
Figure 7. ICM-20690 Block Diagram
4.5 OVERVIEW
The ICM-20690 is comprised of the following key blocks and functions:
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20690 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.
When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff.
The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage
is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro
sensors may be digitally programmed to ±31.25, ±62.5, ±125, ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC
sample rate is programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters
enable a wide range of cut-off frequencies.
Page 22 of 76
Document Number: DS-000178
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ICM-20690
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20690’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The ICM-20690’s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g for UI mode or to ±1g, ±2g, ±4g, or ±8g for OIS
mode.
4.8 I2C AND SPI HOST INTERFACE
The ICM-20690 communicates to the application processor using either a SPI or an I2C serial interface. The ICM-20690 always acts as
a slave when communicating to the application processor. The LSB of the I2C slave address is set by pin 1 (AD0).
4.9 SPI OIS INTERFACE AND AUXILIARY I2C INTERFACE
The ICM-20690 has an SPI interface for communicating to OIS controllers. This interface supports 3-wire SPI. The ICM-20690 always
acts as a slave when communicating to OIS controllers over this interface. The SPI interface is multiplexed with an auxiliary I2C bus
that can be used for communicating to off-chip sensors. This bus has two operating modes:
I2C Master Mode: The ICM-20690 acts as a master to any external sensors connected to the auxiliary I2C bus. The ICM-
20690 can directly access the data registers of external digital sensors. In this mode, the ICM-20690 directly obtains data
from auxiliary sensors without intervention from the application processor. The I2C Master can be configured to read up to
12 bytes from up to 3 auxiliary sensors.
Pass-Through Mode: The ICM-20690 directly connects the primary and auxiliary I2C buses together, allowing the application
processor to directly communicate with any external sensors connected to the auxiliary I2C interface. Pass-through mode is
useful for configuring external sensors.
4.10 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
Self-test response = Sensor output with self-test enabled – Sensor output with self-test disabled
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-
test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
4.11 CLOCKING
The ICM-20690 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. An on-chip
PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be used.
Page 23 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
4.12 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
4.13 FIFO
The ICM-20690 contains a 1K-byte FIFO register that is accessible via the Serial Interface. The FIFO configuration register determines
which data is written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, and FSYNC input.
A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads. The
interrupt function may be used to determine when new data is available.
The ICM-20690 allows FIFO read in low-power accelerometer mode.
4.14 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be
read from the Interrupt Status register.
4.15 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-20690 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
4.16 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-20690. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
4.17 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.18 STANDARD POWER MODES
The following table lists the user-accessible power modes for ICM-20690.
Mode Name
Gyro
Off
Drive On
Off
Off
Duty-Cycled
On
Accel
Off
Off
Duty-Cycled
1
2
3
4
5
6
7
8
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Power Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode
On
Off
Off
On
On
On
6-Axis Low-Power Mode
Duty-Cycled
Table 12. Standard Power Modes for ICM-20690
Notes:
1. Power consumption for individual modes can be found in section 3.3.1.
Page 24 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
5 PROGRAMMABLE INTERRUPTS
The ICM-20690 has a programmable interrupt system that can generate an interrupt signal on the INT pins. Status flags indicate the
source of an interrupt. Interrupt sources may be enabled and disabled individually.
Interrupt Name
Motion Detection
FIFO Overflow
FIFO Watermark
Data Ready
Interrupt Pin
INT2
INT2
INT1
INT1
FSYNC
INT2
Table 13. Table of Interrupt Sources
Page 25 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
5.1 WAKE-ON-MOTION INTERRUPT
The ICM-20690 provides motion detection capability. A qualifying motion sample is one where the high passed sample from any axis
has an absolute value exceeding a user-programmable threshold. The following steps explain how to configure the Wake-on-Motion
Interrupt.
Step 1: Ensure that Accelerometer is running
In PWR_MGMT_1 register (0x6B) set CYCLE = 0, SLEEP = 0, and GYRO_STANDBY = 0
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0, and STBY_XG = STBY_YG = STBY_ZG = 1
Step 2: Accelerometer Configuration
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 1 and A_DLPF_CFG[2:0] = 1 (b001)
Step 3: Enable Motion Interrupt
In INT_ENABLE register (0x38) set WOM_X_INT_EN = WOM_Y_INT_EN = WOM_Z_INT_EN = 1 to enable motion interrupt for
X, Y, and Z axis
Step 4: Set Motion Threshold
Set the motion threshold for X-axis in ACCEL_WOM_X_THR register (0x20)
Set the motion threshold for Y-axis in ACCEL_WOM_Y_THR register (0x21)
Set the motion threshold for Z-axis in ACCEL_WOM_Z_THR register (0x22)
Step 5: Set Interrupt Mode
In ACCEL_INTEL_CTRL register (0x69) clear bit 0 (WOM_TH_MODE) to select the motion interrupt as an OR of the enabled
interrupts for X, Y, Z-axes and set bit 0 to make the interrupt an AND of the enabled interrupts for X, Y, Z axes)
Step 6: Enable Accelerometer Hardware Intelligence
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = ACCEL_INTEL_MODE = 1; Ensure that bit 0 is set to 0.
Step 7: Set Frequency of Wake-Up
In register (0x19) set SMPLRT_DIV for a sample rate as indicated in the register map
Step 8: Enable Cycle Mode (Accelerometer Low-Power Mode)
In PWR_MGMT_1 register (0x6B) set CYCLE = 1
Page 26 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20690 can be accessed using either I2C at 400 kHz or SPI at 10 MHz. SPI operates in
four-wire mode.
Pin Number
Pin Name
Pin Description
Application Processor (AP) Interface: AP I2C slave address LSB (AP_AD0); AP SPI serial
data output (AP_SDO)
1
AP_AD0 / AP_SDO
12
13
14
AP_CS
AP SPI Chip select (SPI mode only)
AP_SCL / AP_SCLK
AP_SDA / AP_SDI
AP I2C serial clock (AP_SCL); AP SPI serial clock (AP_SCLK)
AP I2C serial data (AP_SDA); AP SPI serial data input (AP_SDI)
Table 14. Serial Interface
Note:
To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit.
Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write”
in Section 6.3.
For further information regarding the I2C_IF_DIS bit, please refer to sections 11 and 12 of this document.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-20690 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20690 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level
on pin AD0. This allows two ICM-20690s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin AD0 is logic low) and the address of the other should be b1101001 (pin AD0 is logic high).
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ICM-20690
6.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
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ICM-20690
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Figure 10. Complete I2C Data Transfer
To write the internal ICM-20690 registers, the master transmits the start condition (S), followed by the I2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the ICM-20690 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the ICM-20690 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM-
20690 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
P
ACK
ACK
To read the internal ICM-20690 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the ICM-20690, the master transmits a start signal
followed by the slave address and read bit. As a result, the ICM-20690 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
AD+R
AD+R
NACK
P
ACK
ACK
ACK
DATA
Burst Read Sequence
Master AD+W
S
S
ACK
NACK
P
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ICM-20690
Slave
ACK
ACK
ACK DATA
DATA
6.4 I2C TERMS
Signal
S
Description
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
AD
W
R
ACK
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock
cycle
NACK
RA
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-20690 internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 15. I2C Terms
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ICM-20690
6.5 SPI INTERFACE
The ICM-20690 support 4-wire SPI for host interface and 3-wire SPI for the OIS interface. 4-wire SPI is a synchronous serial interface
that uses two control lines and two data lines. 3-wire SPI is a synchronous serial interface that uses two control lines and one data
line. The ICM-20690 always operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO) and the Serial Data Input (SDI) for 4-wire SPI
(or Serial Data IO (SDOI) for 3-wire SPI) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (nCS)
line from the master.
nCS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one nCS line is active at a time,
ensuring that only one slave is selected at any given time. The nCS lines of the non-selected slave devices are held high, causing their
SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 10 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
LSB
D7
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
SCLK
SDI
SPI Master
SPI Slave 1
SDO
nCS
CS1
CS2
SCLK
SDI
SDO
nCS
SPI Slave 2
Figure 11. Typical SPI Master/Slave Configuration
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ICM-20690
7 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) gyros packaged in
LGA package.
7.1
ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the
figure.
+Z
+Y
+Z
I
C
+Y
M
-
2
0
6
9
0
+X
+X
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation
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ICM-20690
7.2
PACKAGE DIMENSIONS
14 Lead LGA (2.5x3x0.91) mm NiAu pad finish
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ICM-20690
DIMENSIONS IN MILLIMETERS
NOM
SYMBOLS
MIN
MAX
Total Thickness
Substrate Thickness
Mold Thickness
A
A1
A2
0.85
0.91
0.105
0.8
0.97
REF
REF
D
E
2.5
3
BSC
BSC
0.3
Body Size
Lead Width
Lead Length
W
0.2
0.25
L
e
n
0.425
0.475
0.5
14
0.525
BSC
Lead Pitch
Lead Count
D1
1.5
BSC
Edge Pin Center to Center
E1
SD
1
0.25
BSC
BSC
Body Center to Contact Pin
Package Edge Tolerance
aaa
bbb
ddd
0.1
0.2
0.08
Mold Flatness
Coplanarity
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ICM-20690
8 PART NUMBER PACKAGE MARKING
The part number package marking for ICM-20690 devices is summarized below:
Part Number
ICM-20690
Part Number Package Marking
I2690
TOP VIEW
I2690
XXXXXX
YYWW
Part Number
Lot Traceability Code
YY = Year Code
WW = Work Week
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Revision: 1.0
ICM-20690
9 ENVIRONMENTAL COMPLIANCE
The ICM-20690 is RoHS and Green compliant.
The ICM-20690 is in full environmental compliance as evidenced in report HS-ICM-20690A, Materials Declaration Data Sheet.
Environmental Declaration Disclaimer:
InvenSense believes this environmental information to be correct but cannot guarantee accuracy or completeness. Conformity documents for the above component
constitutes are on file. InvenSense subcontracts manufacturing and the information contained herein is based on data received from vendors and suppliers, which has
not been validated by InvenSense.
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ICM-20690
10 USE NOTES
10.1 VALID COMBINATIONS OF UI AND OIS DATAPATH SETTINGS
When the device is being used with UI and OIS datapaths active, certain combinations of settings are valid and others are invalid.
These are summarized in the tables below. The device is in low-noise mode for these configurations.
Gyroscope Configurations:
UI Mode
FCHOICE_B =
00; DLPFCFG =
1 to 6
FCHOICE_B =
00; DLPFCFG = 7 00; DLPFCFG = 0
FCHOICE_B =
Filter Settings
FCHOICE_B = 01
FCHOICE_B = 10
ODR
32kHz
32kHz
Valid
32kHz
Valid
8kHz
Valid
8kHz
Valid
≤1kHz
Valid
FCHOICE_OIS_B = 11
FCHOICE_OIS_B =
10; FCHOICE_B = 10
FCHOICE_OIS_B =
10; FCHOICE_B = 00
FCHOICE_OIS_B =
01; FCHOICE_B = 00
FCHOICE_OIS_B =
01; FCHOICE_B = 00;
DLPF_CFG = 1 to 6
32kHz
8kHz
8kHz
Invalid
Invalid
Invalid
Valid
Invalid
Invalid
Invalid
Valid
Invalid
Valid
Invalid
Valid
OIS Mode
Valid
Valid
Valid
≤1kHz
Invalid
Invalid
Invalid
Invalid
Valid
Accelerometer Configurations:
UI Mode
ACCEL_FCHOICE_B =
0; A_DLPF_CFG = 0 to
ACCEL_FCHOICE_B =
0; A_DLPF_CFG = 7
Filter Settings
ACCEL_FCHOICE_B = 1
6
ODR
4kHz
4kHz
Valid
≤1kHz
Valid
≤1kHz
Valid
OIS Mode
ACCEL_FCHOICE_OIS_B = 11
ACCEL_FCHOICE_OIS_B = 10;
ACCEL_FCHOICE_B = 0
≤1kHz
Invalid
Valid
Valid
ACCEL_FCHOICE_OIS_B = 01;
ACCEL_FCHOICE_B = 0;
≤1kHz
Invalid
Invalid
Valid
A_DLPF_CFG = 0 to 6
10.2 FIFO WATERMARK THRESHOLD
FIFO watermark threshold, FIFO_WM_TH, is limited to 8 bits but the FIFO size is 1Kbytes. This limits the use of FIFO watermark to
256 out of a possible 1024 bytes.
10.3 FIFO WATERMARK INTERRUPT
For FIFO watermark interrupt, FIFO_WM_INT, to receive future interrupts after a first interrupt, the host must clear the status
register with a read.
10.4 ACCELEROMETER-ONLY LOW-NOISE MODE
The first output sample in Accelerometer-Only Low-Noise Mode after wake up from sleep always has 1 ms delay, independent of
ODR.
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ICM-20690
10.5 ACCELEROMETER LOW-POWER MODE
Changing the value of SMPLRT_DIV register in Accelerometer Low-Power mode will take effect after up to one sample at the old
ODR.
10.6 SENSOR MODE CHANGE
When switching from low-power modes to low-noise modes, unsettled output samples may be observed at the gyroscope or
accelerometer outputs due to filter switching and settling. The number of unsettled output samples depends on the filter and ODR
settings. The number of unsettled output samples is minimized by selecting the widest low-noise-mode filter bandwidth consistent
with the chosen ODR.
10.7 TEMP SENSOR DURING GYROSCOPE STANDBY MODE
During transition from Gyro Low power mode (GYRO_CYCLE=1), to Gyro Standby mode, in addition to the Gyro axis (axes) being
turned off, the Temp Sensor will also be turned off if the Accel is disabled. In order to keep the temp sensor on during Gyroscope
standby mode when Accel is disabled, the following procedure should be followed:
Set GYRO_CYCLE = 0 at least one ODR cycle prior to entering Standby mode
At least one of the Gyro axis is ON prior to entering Standby mode
Set GYRO_STANDBY = 1
10.8 GYROSCOPE MODE CHANGE
Gyroscope will take one ODR clock period to switch from Low-Noise to Low-Power mode after GYRO_CYCLE bit is set.
If GYRO_CYCLE is set to 1 prior to turning on the gyroscope, the first sample will be from low-noise mode, which may not be a
settled value. It is therefore recommended to ignore the first reading in this case.
10.9 POWER MANAGEMENT 1 REGISTER SETTING
It is required to set CLKSEL[2:0] to 001 (auto-select) for full performance.
10.10 UNLISTED REGISTER LOCATIONS
Do not read unlisted register locations in Sleep mode as this may cause the device to hang up, requiring power cycle to restore
operation.
10.11 CLOCK TRANSITION WHEN GYROSCOPE IS TURNED OFF
When the gyroscope is on, the on-chip master clock source will be the gyroscope clock (assuming CLKSEL[2:0] = 001 for auto-select
mode); otherwise, the master clock source will be the internal oscillator as long as the part is not in Sleep mode. During a power
mode transition, whenever the gyroscope is disabled and the part enters a mode other than Sleep, the on-chip master clock source
will transition from the gyroscope clock to the internal oscillator. It will take about 20 ms for this transition to complete.
10.12 SLEEP MODE
The part will only enter Sleep mode when the SLEEP bit in PWR_MGMT_2 is set to ‘1’. If SLEEP bit is ‘0’ and bit STBY_[X,Y,Z]A and
STBY_[X,Y,Z]G are all set to ‘1’, accelerometer and gyroscope will be turned off, but the on-chip master clock will still be running and
consuming power.
10.13 NO SPECIAL OPERATION NEEDED FOR FIFO READ IN LOW POWER MODE
The use of FIFO is enabled in all modes including low power mode.
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ICM-20690
10.14 GYROSCOPE STANDBY PROCEDURE
The follow precaution and procedure must be followed while using the Gyroscope Standby mode:
Precaution to follow while entering Standby Mode:
The user will ensure that at least one gyro axis is ON when setting gyro_standby = 1.
Procedure to transition from Gyro Standby to Gyro off:
The user should set gyro_standby = 0 first
Next, turn off gyro x/y/z.
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Document Number: DS-000178
Revision: 1.0
ICM-20690
11 REGISTER MAP
The following table lists the register map for the ICM-20690. Note that all registers are accessible in all modes of device operation.
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
READ/
WRITE
00
01
02
0D
00
01
02
13
SELF_TEST_X_GYRO
XG_ST_DATA[7:0]
READ/
WRITE
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
SELF_TEST_X_ACCEL
YG_ST_DATA[7:0]
ZG_ST_DATA[7:0]
XA_ST_DATA[7:0]
READ/
WRITE
READ/
WRITE
READ/
WRITE
0E
0F
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
20
21
22
23
24
25
26
27
28
29
2A
2B
14
15
19
20
21
22
23
24
25
26
27
28
29
30
32
33
34
35
36
37
38
39
40
41
42
43
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
XG_OFFS_USRH
XG_OFFS_USRL
YG_OFFS_USRH
YG_OFFS_USRL
ZG_OFFS_USRH
ZG_OFFS_USRL
SMPLRT_DIV
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
X_OFFS_USR [15:8]
X_OFFS_USR [7:0]
Y_OFFS_USR [15:8]
Y_OFFS_USR [7:0]
Z_OFFS_USR [15:8]
Z_OFFS_USR [7:0]
SMPLRT_DIV[7:0]
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
READ/
WRITE
FIFO_
MODE
CONFIG
-
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
READ/
WRITE
GYRO_CONFIG
ACCEL_CONFIG
ACCEL_CONFIG 2
LP_MODE_CONFIG
ACCEL_WOM_X_THR
ACCEL_WOM_Y_THR
ACCEL_WOM_Z_THR
FIFO_EN
XG_ST
XA_ST
YG_ST
YA_ST
ZG_ST
ZA_ST
FS_SEL [2:0]
FCHOICE_B[1:0]
READ/
WRITE
AFS_SEL[1:0]
-
AFS_SEL_OIS[1:0]
READ/
WRITE
ACCEL_FC
HOICE_B
FIFO_SIZE
DEC2_CFG
A_DLPF_CFG
READ/
WRITE
GYRO_CYCL
E
GYRO_AVGCFG[2:0]
-
READ/
WRITE
WOM_X_TH[7:0]
READ/
WRITE
WOM_Y_TH[7:0]
WOM_Z_TH[7:0]
READ/
WRITE
READ/
WRITE
ACCEL_XY
Z_OUT
TEMP_OUT
GYRO_XOUT
GYRO_YOUT
GYRO_ZOUT
-
READ/
WRITE
MULT_MST
_EN
I2C_MST_P_N
SR
I2C_MST_CTRL
I2C_SLV0_ADDR
I2C_SLV0_REG
-
I2C_MST_CLK[3:0]
READ/
WRITE
I2C_SLV0_R
NW
I2C_ID_0[6:0]
READ/
WRITE
I2C_SLV0_REG[7:0]
READ/
WRITE
I2C_SLV0_E
N
I2C_SLV0_BY
TE_SW
I2C_SLV0_RE
G_DIS
I2C_SLV0_GR
P
I2C_SLV0_CTRL
I2C_SLV1_ADDR
I2C_SLV1_REG
I2C_SLV0_LENG[3:0]
I2C_SLV1_LENG[3:0]
READ/
WRITE
I2C_SLV1_R
NW
I2C_ID_1[6:0]
READ/
WRITE
I2C_SLV1_REG[7:0]
READ/
WRITE
I2C_SLV1_E
N
I2C_SLV1_BY
TE_SW
I2C_SLV1_RE
G_DIS
I2C_SLV1_GR
P
I2C_SLV1_CTRL
I2C_SLV2_ADDR
READ/
WRITE
I2C_SLV2_R
NW
I2C_ID_2[6:0]
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ICM-20690
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
I2C_SLV2_REG
I2C_SLV2_CTRL
ODR_DELAY_EN
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
READ/
WRITE
2C
2D
2E
44
45
46
I2C_SLV2_REG[7:0]
I2C_SLV2_GR
READ/
WRITE
I2C_SLV2_E
N
I2C_SLV2_BY
TE_SW
I2C_SLV2_RE
G_DIS
I2C_SLV2_LENG[3:0]
P
READ/
WRITE
ODR_DELAY
_EN
-
-
READ to
CLEAR
36
37
54
55
FSYNC_INT
FSYNC_INT
INT_LEVEL
FSYNC
READ/
WRITE
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_IN
T_LEVEL
INT_PIN_CFG
INT_OPEN
_INT_MODE_
EN
-
FIFO
_OFLOW
_EN
READ/
WRITE
WOM_X_IN
T_EN
WOM_Y_INT
_EN
WOM_Z_INT
_EN
GDRIVE_INT_
EN
DATA_RDY_I
NT_EN
38
39
3A
56
57
58
INT_ENABLE
FIFO_WM_INT_STATUS
INT_STATUS
-
-
-
READ to
CLEAR
FIFO_WM_IN
T
-
-
FIFO
_OFLOW
_INT
READ to
CLEAR
WOM_X_IN
T
DATA
_RDY_INT
WOM_Y_INT
WOM_Z_INT
-
GDRIVE_INT
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
ACCEL_XOUT_H
ACCEL_XOUT_L
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
ACCEL_XOUT[15:8]
ACCEL_XOUT[7:0]
ACCEL_YOUT[15:8]
ACCEL_YOUT_H
ACCEL_YOUT_L
ACCEL_YOUT[7:0]
ACCEL_ZOUT_H
ACCEL_ZOUT[15:8]
ACCEL_ZOUT_L
ACCEL_ZOUT[7:0]
TEMP_OUT_H
TEMP_OUT[15:8]
TEMP_OUT_L
TEMP_OUT[7:0]
GYRO_XOUT_H
GYRO_XOUT[15:8]
GYRO_XOUT_L
GYRO_XOUT[7:0]
GYRO_YOUT_H
GYRO_YOUT[15:8]
GYRO_YOUT_L
GYRO_YOUT[7:0]
GYRO_ZOUT_H
GYRO_ZOUT[15:8]
GYRO_ZOUT_L
GYRO_ZOUT[7:0]
EXT_SLV_SENS_DATA_00
EXT_SLV_SENS_DATA_01
EXT_SLV_SENS_DATA_02
EXT_SLV_SENS_DATA_03
EXT_SLV_SENS_DATA_04
EXT_SLV_SENS_DATA_05
EXT_SLV_SENS_DATA_06
EXT_SLV_SENS_DATA_07
EXT_SLV_SENS_DATA_08
EXT_SLV_SENS_DATA_09
EXT_SLV_SENS_DATA_10
EXT_SLV_SENS_DATA_11
EXT_SLV_SENS_DATA_00[7:0]
EXT_SLV_SENS_DATA_01[7:0]
EXT_SLV_SENS_DATA_02[7:0]
EXT_SLV_SENS_DATA_03[7:0]
EXT_SLV_SENS_DATA_04[7:0]
EXT_SLV_SENS_DATA_05[7:0]
EXT_SLV_SENS_DATA_06[7:0]
EXT_SLV_SENS_DATA_07[7:0]
EXT_SLV_SENS_DATA_08[7:0]
EXT_SLV_SENS_DATA_09[7:0]
EXT_SLV_SENS_DATA_10[7:0]
EXT_SLV_SENS_DATA_11[7:0]
READ/
WRITE
5F
60
61
63
64
65
67
68
95
96
ODR_DLY_CNT_HI
ODR_DLY_CNT_LO
FIFO_WM_TH
ODR_DLY_CNT[15:8]
ODR_DLY_CNT[7:0]
FIFO_WM_TH[7:0]
I2C_SLV0_DO[7:0]
I2C_SLV1_DO[7:0]
I2C_SLV2_DO[7:0]
READ/
WRITE
READ/
WRITE
97
READ/
WRITE
99
I2C_SLV0_DO
READ/
WRITE
100
101
103
104
I2C_SLV1_DO
READ/
WRITE
I2C_SLV2_DO
READ/
WRITE
DELAY_ES_
SHADOW
I2C_SLV2_DE
LAY_EN
I2C_SLV1_DE
LAY_EN
I2C_SLV0_DE
LAY_EN
I2C_MST_DELAY_CTRL
SIGNAL_PATH_RESET
-
READ/
WRITE
ACCEL
_RST
TEMP
_RST
FS_SEL_OIS[2:0]
FCHOICE_OIS_B[1:0]
GYRO_RST
Page 41 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
ACCEL_INTEL_CTRL
USER_CTRL
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
READ/
WRITE
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
WOM_INT_
MODE
69
6A
6B
6C
70
105
106
107
108
112
ACCEL_FCHOICE_OIS_B
-
READ/
WRITE
FIFO
_RST
SIG_COND
_RST
-
FIFO_EN
SLEEP
-
I2C_MST_EN
I2C_IF_DIS
I2C_MST_RST
CLKSEL[2:0]
STBY_YG
READ/
WRITE
DEVICE_RES
ET
GYRO_
STANDBY
PWR_MGMT_1
PWR_MGMT_2
OIS_ENABLE
CYCLE
TEMP_DIS
STBY_ZA
READ/
WRITE
LP_DIS
STBY_XA
STBY_YA
STBY_XG
STBY_ZG
-
READ/
WRITE
-
OIS_ENABLE
72
73
114
115
FIFO_COUNTH
FIFO_COUNTL
READ
READ
FIFO_COUNT[15:8]
FIFO_COUNT[7:0]
FIFO_DATA[7:0]
WHOAMI[7:0]
READ/
WRITE
74
75
77
116
117
119
FIFO_R_W
WHO_AM_I
XA_OFFSET_H
READ
READ/
WRITE
XA_OFFS[14:7]
READ/
WRITE
78
7A
7B
7D
7E
120
122
123
125
126
XA_OFFSET_L
YA_OFFSET_H
YA_OFFSET_L
ZA_OFFSET_H
ZA_OFFSET_L
XA_OFFS[6:0]
-
-
-
READ/
WRITE
YA_OFFS[14:7]
READ/
WRITE
YA_OFFS[6:0]
READ/
WRITE
ZA_OFFS[14:7]
READ/
WRITE
ZA_OFFS[6:0]
Table 16. ICM-20690 Register Map
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
The reset value is 0x00 for all registers other than the registers below; also, the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
Registers 00 – 02: Trim values
Registers 13 – 15: Trim values
Register 105 ACCEL_INTEL_CTRL value: 0x10
Register 107 Power Management 1 value: 0x41
Register 117 WHO_AM_I value: 0x20
Registers 119, 120, 122, 123, 125, 126: Trim values
Page 42 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
11.1 REGISTERS SPECIFIC TO SECONDARY INTERFACE IN OIS MODE
The following registers are accessible from the secondary interface in OIS mode only. OIS controller should only read this data in SPI
burst mode to avoid OIS sensor data update during reading. SPI single byte read mode should not be used.
Addr
(Hex)
Addr
(Dec.)
Serial
I/F
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00
01
02
03
00
01
02
03
ACCEL_XOUT_OIS_H
ACCEL_XOUT_OIS_L
ACCEL_YOUT_OIS_H
ACCEL_YOUT_OIS_L
READ
READ
READ
READ
ACCEL_XOUT_OIS[15:8]
ACCEL_XOUT_OIS[7:0]
ACCEL_YOUT_OIS[15:8]
ACCEL_YOUT_OIS[7:0]
04
05
06
07
08
09
0A
0B
0C
0D
04
05
06
07
08
09
10
11
12
13
ACCEL_ZOUT_OIS_H
ACCEL_ZOUT_OIS_L
TEMP_OUT_OIS_H
TEMP_OUT_OIS_L
GYRO_XOUT_OIS_H
GYRO_XOUT_OIS_L
GYRO_YOUT_OIS_H
GYRO_YOUT_OIS_L
GYRO_ZOUT_OIS_H
GYRO_ZOUT_OIS_L
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
ACCEL_ZOUT_OIS[15:8]
ACCEL_ZOUT_OIS[7:0]
TEMP_OUT_OIS[15:8]
TEMP_OUT_OIS[7:0]
GYRO_XOUT_OIS[15:8]
GYRO_XOUT_OIS[7:0]
GYRO_YOUT_OIS[15:8]
GYRO_YOUT_OIS[7:0]
GYRO_ZOUT_OIS[15:8]
GYRO_ZOUT_OIS[7:0]
Table 17. Registers Specific to Secondary Interface in OIS Mode
Page 43 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12 REGISTER DESCRIPTIONS
This section describes the function and contents of the registers within the ICM-20690.
Note: The device powers up in Sleep Mode.
12.1 REGISTERS 0 TO 2 – GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Register Type: READ/WRITE
Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)
REGISTER
BIT
NAME
FUNCTION
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
SELF_TEST_X_GYRO
[7:0] XG_ST_DATA[7:0]
[7:0] YG_ST_DATA[7:0]
[7:0] ZG_ST_DATA[7:0]
SELF_TEST_Y_GYRO
SELF_TEST_Z_GYRO
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _OTP (2620/2FS )*1.01(ST _code1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
log(ST _ FAC /(2620/2FS ))
ST _ code round(
) 1
log(1.01)
Page 44 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.2 REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Register Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, OE, OF (Hex)
REGISTER
BITS
NAME
FUNCTION
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
SELF_TEST_X_ACCEL
[7:0]
XA_ST_DATA[7:0]
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
The value in this register indicates the self-test output
generated during manufacturing tests. This value is to be used
to check against subsequent self-test outputs performed by
the end user.
SELF_TEST_Y_ACCEL
SELF_TEST_Z_ACCEL
[7:0]
[7:0]
YA_ST_DATA[7:0]
ZA_ST_DATA[7:0]
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _OTP (2620/2FS )*1.01(ST _code1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
log(ST _ FAC /(2620/2FS ))
ST _ code round(
) 1
log(1.01)
12.3 REGISTER 19 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
X_OFFS_USR[15:8]
12.4 REGISTER 20 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
X_OFFS_USR[7:0]
Page 45 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.5 REGISTERS 21 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Y_OFFS_USR[15:8]
12.6 REGISTERS 22 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Y_OFFS_USR[7:0]
12.7 REGISTERS 23 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT
NAME
FUNCTION
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Z_OFFS_USR[15:8]
12.8 REGISTER 24 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT
NAME
FUNCTION
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s complement). This
register is used to remove DC bias from the sensor output. The value in
this register is added to the gyroscope sensor value before going into
the sensor register.
[7:0]
Z_OFFS_USR[7:0]
Page 46 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.9 REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
NAME
FUNCTION
[7:0]
SMPLRT_DIV[7:0]
Divides the internal sample rate (see register CONFIG) to generate the
sample rate that controls sensor data output rate, FIFO sample rate.
NOTE: This register is only effective when FCHOICE_B register bits are
2’b00, and (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1kHz
SMPLRT_DIV values of 0 and 1 are not supported in low-power mode.
12.10 REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
[6]
NAME
FIFO_MODE
FUNCTION
-
Default configuration value is 1. User should set it to 0.
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO,
replacing the oldest data.
[5:3] EXT_SYNC_SET[2:0]
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
FSYNC bit location
function disabled
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
ACCEL_XOUT_L[0]
ACCEL_YOUT_L[0]
ACCEL_ZOUT_L[0]
0
1
2
3
4
5
6
7
FSYNC will be latched to capture short strobes. This will be done such that if FSYNC
toggles, the latched value toggles, but won’t toggle again until the new latched value
is captured by the sample rate strobe.
[2:0] DLPF_CFG[2:0]
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See the tables below.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and temperature sensor are filtered
according to the value of DLPF_CFG and FCHOICE_B as shown in the table below.
Page 47 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
UI path gyroscope DLPF configuration:
FCHOICE_B
DLPF_CFG
Filter BW (Hz)
Filter Delay (ms)
ODR (kHz)
<1>
X
1
0
0
0
0
0
0
<0>
1
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
7
8800
3600
250
184
92
41
20
10
5
0.064
0.11
0.97
2.9
3.9
5.9
32
32
8
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
8
9.9
17.85
33.48
0.17
0
0
0
0
3600
Temperature sensor DLPF configuration:
DLPF_CFG
Filter BW (Hz)
NA
Filter Delay (ms)
0
1
2
3
4
5
6
7
NA
1.9
2.8
4.8
8.3
13.4
18.6
NA
188
98
42
20
10
5
NA
12.11 REGISTER 27 – GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
BIT
[7]
[6]
[5]
NAME
XG_ST
YG_ST
ZG_ST
FUNCTION
1: Enable X Gyro self-test
1: Enable Y Gyro self-test
1: Enable Z Gyro self-test
UI Path Gyro Full Scale Select:
000 = ±250dps
001= ±500dps
010 = ±1000dps
011 = ±2000dps
101= ±31.25dps
110 = ±62.5dps
111 = ±125dps
Used to bypass DLPF as shown in table above
[4:2]
[1:0]
FS_SEL[2:0]
FCHOICE_B[1:0]
Page 48 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.12 REGISTER 28 – ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT
[7]
[6]
[5]
NAME
XA_ST
YA_ST
ZA_ST
FUNCTION
1: Enable X Accel self-test
1: Enable Y Accel self-test
1: Enable Z Accel self-test
UI Path Accel Full Scale Select:
00 = ±2g
[4:3]
[2]
AFS_SEL[1:0]
01 = ±4g
10 = ±8g
11 = ±16g
Reserved
-
OIS Path Accel Full Scale Select:
00 = ±2g
[1:0]
AFS_SEL_OIS[1:0]
01= ±4g
10 = ±8g
11 = ±1g
12.13 REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
NAME
FUNCTION
Controls FIFO size as follows:
00 = 128bytes
01 = 256 bytes
10 = 512 bytes
11 = 1024 bytes
[7:6]
FIFO_SIZE
Averaging filter settings for Low Power Accelerometer mode as explained in
the second table below
[5:4]
DEC2_CFG[1:0]
[3]
[2:0]
ACCEL_FCHOICE_B
A_DLPF_CFG
Used to bypass DLPF as shown in the table below
UI path accelerometer low pass filter setting as shown in the table below
ACCEL_FCHOICE_B
A_DLPF_CFG
Filter BW (Hz)
Filter Delay (ms)
ODR (kHz)
1
0
0
0
0
0
0
0
0
X
0
1
2
3
4
5
6
7
1046.00
218.10
218.10
99.00
44.80
21.20
10.20
5.05
4
0.50
1.88
1.88
2.88
4.88
8.87
16.80
32.50
1.38
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1
420.00
Page 49 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
Low Power accelerometer mode averaging filter settings:
ACCEL_FCHOICE_B A_DLPF_CFG DEC2_CFG Averaging Filter
1
0
0
0
0
X
7
7
7
7
0
0
1
2
3
1x
4x
8x
16x
32x
12.14 REGISTER 30 – GYROSCOPE LOW POWER MODE CONFIGURATION
Register Name: LP_MODE_CONFIG
Register Type: READ/WRITE
Register Address: 30 (Decimal); 1E (Hex)
BIT
NAME
FUNCTION
[7]
GYRO_CYCLE
When set to ‘1’ low-power gyroscope mode is enabled. Default setting is ‘0’
Averaging filter configuration for low-power gyroscope mode. Default
setting is ‘000’
The following list shows averaging filter configurations for different settings:
000 = 1x
001 = 2x
010 = 4x
011 = 8x
100 = 16x
101 = 32x
110 = 64x
111 = 128x
Reserved
[6:4]
[3:0]
GYRO_AVGCFG[2:0]
-
To operate in gyroscope low-power mode or 6-axis low-power mode, GYRO_CYCLE should be set to ‘1.’ Gyroscope filter
configuration is determined by GYRO_AVGCFG[2:0] that sets the averaging filter configuration. It is not dependent on
DLPF_CFG[2:0].
12.15 REGISTER 32 – WAKE-ON MOTION THRESHOLD (X-AXIS ACCELEROMETER)
Register Name: ACCEL_WOM_X_THR
Register Type: READ/WRITE
Register Address: 32 (Decimal); 20 (Hex)
BIT
NAME
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for X-axis
accelerometer.
[7:0]
WOM_X_TH[7:0]
Page 50 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.16 REGISTER 33 – WAKE-ON MOTION THRESHOLD (Y-AXIS ACCELEROMETER)
Register Name: ACCEL_WOM_Y_THR
Register Type: READ/WRITE
Register Address: 33 (Decimal); 21 (Hex)
BIT
NAME
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for Y-axis
accelerometer.
[7:0]
WOM_Y_TH[7:0]
12.17 REGISTER 34 – WAKE-ON MOTION THRESHOLD (Z-AXIS ACCELEROMETER)
Register Name: ACCEL_WOM_Z_THR
Register Type: READ/WRITE
Register Address: 34 (Decimal); 22 (Hex)
BIT
NAME
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for Z-axis
accelerometer.
[7:0]
WOM_Z_TH[7:0]
12.18 REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
NAME
FUNCTION
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate. If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled.
[7]
TEMP_OUT
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate. If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled.
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate. If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled.
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate. If
enabled, buffering of data occurs even if data path is in standby.
0 – Function is disabled.
[6]
[5]
[4]
GYRO_XOUT
GYRO_YOUT
GYRO_ZOUT
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,
ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate.
0 – Function is disabled.
[3]
ACCEL_XYZ_OUT
-
[2:0]
Reserved
Page 51 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.19 REGISTER 36 – I2C MASTER CONTROL
Register Name: I2C_MST_CTRL
Register Type: READ/WRITE
Register Address: 36 (Decimal); 24 (Hex)
BIT
[7]
NAME
FUNCTION
1 – Enables multi-master capability
0 – Function is disabled
Reserved
MULT_MST_EN
-
[6:5]
This bit controls the I2C master’s transition from one slave read to the next slave
read
1 – There is a stop between reads
0 – There is a restart between reads
Sets I2C master clock according to the table below
[4]
I2C_MST_P_NSR
I2C_MST_CLK
[3:0]
I2C_MST_CLK[3:0]
Slowest Frequency (kHz)
Duty Cycle
0
1
341
341
42%
50%
2
315
38%
3
315
46%
4
293
43%
5
293
50%
6
273
40%
7
273
47%
8
256
38%
9
Invalid
Invalid
Invalid
410
410
372
Invalid
Invalid
Invalid
40%
40%
45%
10
11
12
13
14
15
372
45%
12.20 REGISTER 37 – I2C SLAVE 0 PHYSICAL ADDRESS
Register Name: I2C_SLV0_ADDR
Register Type: READ/WRITE
Register Address: 37 (Decimal); 25 (Hex)
BIT
[7]
NAME
FUNCTION
1 – Transfer is a read
0 – Transfer is a write
Physical address of I2C slave 0
I2C_SLV0_RNW
I2C_ID_0
[6:0]
Page 52 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.21 REGISTER 38 – I2C SLAVE 0 REGISTER ADDRESS
Register Name: I2C_SLV0_REG
Register Type: READ/WRITE
Register Address: 38 (Decimal); 26 (Hex)
BIT
[7:0]
NAME
I2C_SLV0_REG
FUNCTION
I2C slave 0 register address from where to begin data transfer
12.22 REGISTER 39 – I2C SLAVE 0 CONTROL
Register Name: I2C_SLV0_CTRL
Register Type: READ/WRITE
Register Address: 39 (Decimal); 27 (Hex)
BIT
NAME
FUNCTION
[7]
I2C_SLV0_EN
1 – Enable reading data from this slave at the sample rate and storing data at the
first available EXT_SENS_DATA register, which is always EXT_SENS_DATA_00 for I2C
slave 0.
0 – Function is disabled for this slave
[6]
I2C_SLV0_BYTE_SW 1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV0_REG[0] = 1, or if the last
byte read has a register address lsb = 0.
For example, if I2C_SLV0_REG = 0x1, and I2C_SLV0_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_00,
2) The second and third bytes will be read and swapped, so the data read from
address 0x2 will be stored at EXT_SENS_DATA_02, and the data read from address
0x3 will be stored at EXT_SENS_DATA_01,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_03
0 – No swapping occurs, bytes are written in order read.
[5]
[4]
I2C_SLV0_REG_DIS
I2C_SLV0_GRP
When set, the transaction does not write a register value, it will only read data, or
write data
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc..
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
3:0
I2C_SLV0_LENG
Number of bytes to be read from I2C slave 0
12.23 REGISTER 40 – I2C SLAVE 1 PHYSICAL ADDRESS
Register Name: I2C_SLV1_ADDR
Register Type: READ/WRITE
Register Address: 40 (Decimal); 28 (Hex)
BIT
[7]
NAME
FUNCTION
1 – Transfer is a read
0 – Transfer is a write
Physical address of I2C slave 1
I2C_SLV1_RNW
I2C_ID_1
[6:0]
Page 53 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.24 REGISTER 41 – I2C SLAVE 1 REGISTER ADDRESS
Register Name: I2C_SLV1_REG
Register Type: READ/WRITE
Register Address: 41 (Decimal); 29 (Hex)
BIT
[7:0]
NAME
I2C_SLV1_REG
FUNCTION
I2C slave 1 register address from where to begin data transfer
12.25 REGISTER 39 – I2C SLAVE 1 CONTROL
Register Name: I2C_SLV1_CTRL
Register Type: READ/WRITE
Register Address: 42 (Decimal); 2A (Hex)
BIT
NAME
FUNCTION
[7]
I2C_SLV1_EN
1 – Enable reading data from this slave at the sample rate and storing data at the
first available EXT_SENS_DATA register, which is always EXT_SENS_DATA_00 for I2C
slave 0.
0 – Function is disabled for this slave.
[6]
I2C_SLV1_BYTE_S
W
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV1_REG[0] = 1, or if the last
byte read has a register address lsb = 0.
For example, if I2C_SLV1_REG = 0x1, and I2C_SLV1_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_00,
2) The second and third bytes will be read and swapped, so the data read from
address 0x2 will be stored at EXT_SENS_DATA_02, and the data read from address
0x3 will be stored at EXT_SENS_DATA_01,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_03
0 – No swapping occurs; bytes are written in the order read.
[5]
[4]
I2C_SLV1_REG_DIS When set, the transaction does not write a register value, it will only read data, or
write data
I2C_SLV1_GRP
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc..
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
3:0
I2C_SLV1_LENG
Number of bytes to be read from I2C slave 1.
12.26 REGISTER 43 – I2C SLAVE 2 PHYSICAL ADDRESS
Register Name: I2C_SLV2_ADDR
Register Type: READ/WRITE
Register Address: 43 (Decimal); 2B (Hex)
BIT
[7]
NAME
FUNCTION
1 – Transfer is a read.
0 – Transfer is a write.
Physical address of I2C slave 2.
I2C_SLV2_RNW
I2C_ID_2
[6:0]
Page 54 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.27 REGISTER 44 – I2C SLAVE 2 REGISTER ADDRESS
Register Name: I2C_SLV2_REG
Register Type: READ/WRITE
Register Address: 44 (Decimal); 2C (Hex)
BIT
[7:0]
NAME
I2C_SLV2_REG
FUNCTION
I2C slave 2 register address from where to begin data transfer.
12.28 REGISTER 45 – I2C SLAVE 2 CONTROL
Register Name: I2C_SLV2_CTRL
Register Type: READ/WRITE
Register Address: 45 (Decimal); 2D (Hex)
BIT
NAME
FUNCTION
[7]
I2C_SLV2_EN
1 – Enable reading data from this slave at the sample rate and storing data at the
first available EXT_SENS_DATA register, which is always EXT_SENS_DATA_00 for I2C
slave 0.
0 – Function is disabled for this slave.
[6]
I2C_SLV2_BYTE_S
W
1 – Swap bytes when reading both the low and high byte of a word. Note there is
nothing to swap after reading the first byte if I2C_SLV2_REG[0] = 1, or if the last
byte read has a register address lsb = 0.
For example, if I2C_SLV2_REG = 0x1, and I2C_SLV2_LENG = 0x4:
1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_00,
2) The second and third bytes will be read and swapped, so the data read from
address 0x2 will be stored at EXT_SENS_DATA_02, and the data read from address
0x3 will be stored at EXT_SENS_DATA_01,
3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_03
0 – No swapping occurs; bytes are written in the order read.
[5]
[4]
I2C_SLV2_REG_DIS When set, the transaction does not write a register value, it will only read data, or
write data.
I2C_SLV2_GRP
External sensor data typically comes in as groups of two bytes. This bit is used to
determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc..,
or if the groups are address 1 and 2, 3 and 4, etc..
0 indicates slave register addresses 0 and 1 are grouped together (odd numbered
register ends the group). 1 indicates slave register addresses 1 and 2 are grouped
together (even numbered register ends the group). This allows byte swapping of
registers that are grouped starting at any address.
3:0
I2C_SLV2_LENG
Number of bytes to be read from I2C slave 2.
12.29 REGISTER 46 – FSYNC ODR DELAY ENABLE
Register Name: ODR_DELAY_EN
Register Type: READ/WRITE
Register Address: 46 (Decimal); 2E (Hex)
BIT
[7]
NAME
FUNCTION
1 – Enables FSYNC ODR delay counter.
0 – Function is disabled.
Reserved
ODR_DELAY_EN
-
[6:0]
Page 55 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.30 REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
[7]
NAME
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been generated. The
bit clears to 0 after the register has been read.
Reserved
FSYNC_INT
-
[6:0]
12.31 REGISTER 55 – INT PIN CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
NAME
FUNCTION
1 – The logic level for INT pin is active low.
0 – The logic level for INT pin is active high.
[7]
INT_LEVEL
1 – INT pin is configured as open drain.
0 – INT pin is configured as push-pull.
[6]
[5]
[4]
[3]
INT_OPEN
1 – INT pin level held until interrupt status is cleared.
0 – INT pin indicates interrupt pulse’s width is 50 µs.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register.
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it
transitions to the level specified by FSYNC_INT_LEVEL.
When this bit is equal to 0, the FSYNC pin is disabled from causing an
interrupt.
LATCH_INT_EN
INT_RD_CLEAR
FSYNC_INT_LEVEL
[2]
FSYNC_INT_MODE_EN
-
[1:0]
Reserved
12.32 REGISTER 56 – INTERRUPT ENABLE
Register Name: INT_ENABLE
Register Type: READ/WRITE
Register Address: 56 (Decimal); 38 (Hex)
BIT
[7]
[6]
[5]
NAME
FUNCTION
WOM_X_INT_EN
WOM_Y_INT_EN
WOM_Z_INT_EN
1 – Enable WoM interrupt on X-axis accelerometer. Default setting is 0.
1 – Enable WoM interrupt on Y-axis accelerometer. Default setting is 0.
1 – Enable WoM interrupt on Z-axis accelerometer. Default setting is 0.
1 – Enables a FIFO buffer overflow to generate an interrupt.
0 – Function is disabled.
[4]
FIFO_OFLOW_EN
[3]
[2]
[1]
[0]
-
Reserved
GDRIVE_INT_EN
-
DATA_RDY_INT_EN
Gyroscope Drive System Ready interrupt enable
Reserved
Data ready interrupt enable
Page 56 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.33 REGISTER 57 – FIFO WATERMARK INTERRUPT STATUS
Register Name: FIFO_WM_INT_STATUS
Register Type: READ to CLEAR
Register Address: 57 (Decimal); 39 (Hex)
BIT
[7]
NAME
-
FUNCTION
Reserved
[6]
[5:0]
FIFO_WM_INT
-
FIFO Watermark interrupt status. Cleared on Read.
Reserved
12.34 REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT
NAME
FUNCTION
[7]
WOM_X_INT
X-axis accelerometer WoM interrupt status. Cleared on Read.
[6]
[5]
WOM_Y_INT
WOM_Z_INT
Y-axis accelerometer WoM interrupt status. Cleared on Read.
Z-axis accelerometer WoM interrupt status. Cleared on Read.
This bit automatically sets to 1 when a FIFO buffer overflow has been
generated. The bit clears to 0 after the register has been read.
Reserved
Gyroscope Drive System Ready interrupt.
Reserved
[4]
FIFO_OFLOW_INT
[3]
[2]
[1]
-
GDRIVE_INT
-
This bit automatically sets to 1 when a Data Ready interrupt is generated. The
bit clears to 0 after the register has been read.
[0]
DATA_RDY_INT
12.35 REGISTER 59 – HIGH BYTE OF ACCELEROMETER X-AXIS DATA
Register Name: ACCEL_XOUT_H
Register Type: READ
Register Address: 59 (Decimal); 3B (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT[15:8]
High byte of accelerometer x-axis data.
12.36 REGISTER 60 – LOW BYTE OF ACCELEROMETER X-AXIS DATA
Register Name: ACCEL_XOUT_L
Register Type: READ
Register Address: 60 (Decimal); 3C (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT[7:0]
Low byte of accelerometer x-axis data.
Page 57 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.37 REGISTER 61 – HIGH BYTE OF ACCELEROMETER Y-AXIS DATA
Register Name: ACCEL_YOUT_H
Register Type: READ
Register Address: 61 (Decimal); 3D (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT[15:8]
High byte of accelerometer y-axis data.
12.38 REGISTER 62 – LOW BYTE OF ACCELEROMETER Y-AXIS DATA
Register Name: ACCEL_YOUT_L
Register Type: READ
Register Address: 62 (Decimal); 3E (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT[7:0]
Low byte of accelerometer y-axis data.
12.39 REGISTER 63 – HIGH BYTE OF ACCELEROMETER Z-AXIS DATA
Register Name: ACCEL_ZOUT_H
Register Type: READ
Register Address: 63 (Decimal); 3F (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT[15:8]
High byte of accelerometer z-axis data.
12.40 REGISTER 64 – LOW BYTE OF ACCELEROMETER Z-AXIS DATA
Register Name: ACCEL_ZOUT_L
Register Type: READ
Register Address: 64 (Decimal); 40 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT[7:0]
Low byte of accelerometer z-axis data.
12.41 REGISTER 65 – HIGH BYTE OF TEMPERATURE SENSOR DATA
Register Name: TEMP_OUT_H
Register Type: READ
Register Address: 65 (Decimal); 41 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT[15:8]
High byte of the temperature sensor output.
Page 58 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.42 REGISTER 66 – LOW BYTE OF TEMPERATURE SENSOR DATA
Register Name: TEMP_OUT_L
Register Type: READ
Register Address: 66 (Decimal); 42 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT[7:0]
Low byte of the temperature sensor output.
TEMP_OUT may be converted to temperature in degrees C by using the following formula:
TEMP_degC = (TEMP_OUT[15:0]/Temp_Sensitivity) + RoomTemp_Offset
where Temp_Sensitivity = 326.8 LSB/ºC and RoomTemp_Offset = 25ºC
12.43 REGISTER 67 – HIGH BYTE OF GYROSCOPE X-AXIS DATA
Register Name: GYRO_XOUT_H
Register Type: READ
Register Address: 67 (Decimal); 43 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_XOUT[15:8]
High byte of gyroscope x-axis data.
12.44 REGISTER 68 – LOW BYTE OF GYROSCOPE X-AXIS DATA
Register Name: GYRO_XOUT_L
Register Type: READ
Register Address: 68 (Decimal); 44 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_XOUT[7:0]
Low byte of gyroscope x-axis data.
12.45 REGISTER 69 – HIGH BYTE OF GYROSCOPE Y-AXIS DATA
Register Name: GYRO_YOUT_H
Register Type: READ
Register Address: 69 (Decimal); 45 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_YOUT[15:8]
High byte of gyroscope y-axis data.
12.46 REGISTER 70 – LOW BYTE OF GYROSCOPE Y-AXIS DATA
Register Name: GYRO_YOUT_L
Register Type: READ
Register Address: 70 (Decimal); 46 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_YOUT[7:0]
Low byte of gyroscope y-axis data.
Page 59 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.47 REGISTER 71 – HIGH BYTE OF GYROSCOPE Z-AXIS DATA
Register Name: GYRO_ZOUT_H
Register Type: READ
Register Address: 71 (Decimal); 47 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_ZOUT[15:8]
High byte of gyroscope z-axis data.
12.48 REGISTER 72 – LOW BYTE OF GYROSCOPE Z-AXIS DATA
Register Name: GYRO_ZOUT_L
Register Type: READ
Register Address: 72 (Decimal); 48 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_ZOUT[7:0]
Low byte of gyroscope z-axis data.
12.49 REGISTER 73 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_00
Register Type: READ
Register Address: 73 (Decimal); 49 (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
00
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.50 REGISTER 74 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_01
Register Type: READ
Register Address: 74 (Decimal); 4A (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
01
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.51 REGISTER 75 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_02
Register Type: READ
Register Address: 75 (Decimal); 4B (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
02
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
Page 60 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.52 REGISTER 76 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_03
Register Type: READ
Register Address: 76 (Decimal); 4C (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
03
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.53 REGISTER 77 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_04
Register Type: READ
Register Address: 77 (Decimal); 4D (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
04
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.54 REGISTER 78 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_05
Register Type: READ
Register Address: 78 (Decimal); 4E (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
05
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.55 REGISTER 79 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_06
Register Type: READ
Register Address: 79 (Decimal); 4F (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
06
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.56 REGISTER 80 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_07
Register Type: READ
Register Address: 80 (Decimal); 50 (Hex)
BIT
[7:0]
NAME
EXT_SLV_SENS_DATA_
07
FUNCTION
Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
Page 61 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.57 REGISTER 81 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_08
Register Type: READ
Register Address: 81 (Decimal); 51 (Hex)
BIT
[7:0]
NAME
FUNCTION
EXT_SLV_SENS_DATA_08 Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.58 REGISTER 82 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_09
Register Type: READ
Register Address: 82 (Decimal); 52 (Hex)
BIT
[7:0]
NAME
FUNCTION
EXT_SLV_SENS_DATA_09 Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.59 REGISTER 83 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_10
Register Type: READ
Register Address: 83 (Decimal); 53 (Hex)
BIT
[7:0]
NAME
FUNCTION
EXT_SLV_SENS_DATA_10 Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
12.60 REGISTER 84 – SENSOR DATA FROM EXTERNAL I2C DEVICES
Register Name: EXT_SLV_SENS_DATA_11
Register Type: READ
Register Address: 84 (Decimal); 54 (Hex)
BIT
[7:0]
NAME
FUNCTION
EXT_SLV_SENS_DATA_11 Sensor data read from external I2C devices via the I2C master interface. The
data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and
I2C_SLV(0-4)_CTRL registers
Page 62 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.61 REGISTER 95 – FSYNC ODR DELAY COUNTER HIGH BYTE
Register Name: ODR_DLY_CNT_HI
Register Type: READ/WRITE
Register Address: 95 (Decimal); 5F (Hex)
BIT
NAME
FUNCTION
[7:0]
ODR_DLY_TIME_CNT[15:8]
High byte of FSYNC ODR delay counter.
12.62 REGISTER 96 – FSYNC ODR DELAY COUNTER LOW BYTE
Register Name: ODR_DLY_CNT_LO
Register Type: READ/WRITE
Register Address: 96 (Decimal); 60 (Hex)
BIT
NAME
FUNCTION
[7:0]
ODR_DLY_TIME_CNT[7:0] Low byte of FSYNC ODR delay counter.
12.63 REGISTER 97 – FIFO WATERMARK THRESHOLD IN NUMBER OF BYTES
Register Name: FIFO_WM_TH
Register Type: READ/WRITE
Register Address: 97 (Decimal); 61 (Hex)
BIT
NAME
FUNCTION
[7:0]
FIFO_WM_TH
FIFO watermark threshold in number of bytes. If zero then watermark
interrupt is disabled.
12.64 REGISTER 99 – SLAVE 0 DATA OUT
Register Name: I2C_SLV0_DO
Register Type: READ/WRITE
Register Address: 99 (Decimal); 63 (Hex)
BIT
[7:0]
NAME
I2C_SLV0_DO
FUNCTION
Data out when slave 0 is set to write.
12.65 REGISTER 100 – SLAVE 1 DATA OUT
Register Name: I2C_SLV1_DO
Register Type: READ/WRITE
Register Address: 100 (Decimal); 64 (Hex)
BIT
NAME
FUNCTION
[7:0]
I2C_SLV1_DO
Data out when slave 1 is set to write.
Page 63 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.66 REGISTER 101 – SLAVE 2 DATA OUT
Register Name: I2C_SLV2_DO
Register Type: READ/WRITE
Register Address: 101 (Decimal); 65 (Hex)
BIT
NAME
FUNCTION
[7:0]
I2C_SLV2_DO
Data out when slave 2 is set to write.
12.67 REGISTER 103 – I2C MASTER DELAY CONTROL
Register Name: I2C_MST_DELAY_CTRL
Register Type: READ/WRITE
Register Address: 103 (Decimal); 67 (Hex)
BIT
[7]
[6:3]
[2]
NAME
DELAY_ES_SHADOW
-
FUNCTION
Delays shadowing of external sensor data until all data is received.
Reserved
When enabled, slave 2 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
I2C_SLV2_DELAY_EN
[1]
[0]
I2C_SLV1_DELAY_EN
I2C_SLV0_DELAY_EN
When enabled, slave 1 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG.
When enabled, slave 0 will only be accessed 1/(1+I2C_SLC4_DLY) samples as
determined by I2C_MST_ODR_CONFIG
12.68 REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT
NAME
FUNCTION
OIS Path Gyro Full Scale Select:
000 = ±250 dps
001 = ±500 dps
010 = ±1000 dps
011 = ±2000 dps
[7:5]
FS_SEL_OIS
101 = ±31.25 dps
110 = ±62.5 dps
111 = ±125 dps
[4:3]
[2]
FCHOICE_OIS_B
GYRO_RST
Used for OIS path gyroscope DLPF configuration as shown in the table below.
Reset gyroscope digital signal path.
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor
registers.
Reset accelerometer digital signal path.
[1]
[0]
ACCEL_RST
TEMP_RST
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor
registers.
Reset temperature sensor digital signal path.
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor
registers.
Page 64 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
FCHOICE_OIS_B
FCHOICE_B
DLPF_CFG
Filter BW (Hz) Filter Delay (ms)
ODR (kHz)
32
11
10
10
01
00
00
00
00
00
00
xx
10
00
00
00
00
00
00
00
00
x
x
x
8800
3600
3600
250
184
92
0.064
0.11
0.17
0.97
2.9
32
8
8
x
1
2
3
4
5
6
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
3.9
41
5.9
20
9.9
10
5
17.85
33.48
12.69 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
NAME
FUNCTION
[7]
ACCEL_INTEL_EN
This bit enables the Wake-on-Motion detection logic.
0 – Do not use.
1 – Compare the current sample with the previous sample,
[6]
ACCEL_INTEL_MODE
Used for OIS path accelerometer DLPF configuration as shown in the table
below.
Reserved
[5:4]
[3:1]
ACCEL_FCHOICE_OIS_B
-
0 – Set WoM interrupt on the OR of all enabled accelerometer thresholds.
1 – Set WoM interrupt on the AND of all enabled accelerometer threshold.
Default setting is 0
[0]
WOM_INT_MODE
ACCEL_FCHOICE_OIS_B ACCEL_FCHOICE_B A_DLPF_CFG
Filter BW (Hz)
Filter Delay (ms)
ODR (kHz)
11
10
01
01
01
01
01
01
01
X
0
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
1046.00
420.00
218.10
218.10
99.00
44.80
21.20
10.20
5.05
0.50
1.38
1.88
1.88
2.88
4.88
8.87
16.80
32.50
4
1
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
1/(1+SMPLRT_DIV)
12.70 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
NAME
FUNCTION
[7]
-
Reserved
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
[6]
FIFO_EN
Page 65 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
BIT
NAME
FUNCTION
1 – Enable the I2C master interface module: Pins AUX_DA and AUX_CL are
isolated from pins AP_SDA/AP_SDI and AP_SCL/AP_SCLK.
0 – Disable the I2C master interface module: Pins AUX_DA and AUX_CL are
driven by pins AP_SDA/AP_SDI and AP_SCL/AP_SCLK.
Disable I2C slave interface to host and put the interface in SPI mode.
Reserved
[5]
I2C_MST_EN
[4]
[3]
I2C_IF_DIS
-
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one
clock cycle of the internal 20MHz clock.
Reserved
[2]
[1]
FIFO_RST
-
1 – Reset gyroscope digital signal path, accelerometer digital signal path, and
temperature sensor digital signal path. This bit also clears all the sensor
registers.
[0]
SIG_COND_RST
12.71 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
[7]
[6]
NAME
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit
automatically clears to 0 once the reset is done.
When set to 1, the chip is set to sleep mode.
DEVICE_RESET
SLEEP
When set to 1, and SLEEP and GYRO_STANDBY are not set to 1, the chip will
cycle between sleep and taking a single accelerometer sample at a rate
determined by SMPLRT_DIV.
NOTE: When all accelerometer axes are disabled via PWR_MGMT_2 register
bits and cycle is enabled, the chip will wake up at the rate determined by the
respective registers above, but will not take any samples.
When set, the gyro drive and PLL circuitry are enabled, but the sense paths are
disabled. This is a low power mode that allows quick enabling of the gyros.
When set to 1, this bit disables the temperature sensor.
Code Clock Source
[5]
CYCLE
[4]
[3]
GYRO_STANDBY
TEMP_DIS
0
1
Internal 20 MHz oscillator
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
2
3
4
5
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
[2:0]
CLKSEL[2:0]
Auto selects the best available clock source – PLL if ready, else use
the Internal oscillator
6
7
Internal 20MHz oscillator
Stops the clock and keeps timing generator in reset
Page 66 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.72 REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT
NAME
FUNCTION
When gyroscope is disabled, this bit controls accelerometer duty cycling
operation mode.
1 – System will not enter sleep when gyroscope is disabled and accelerometer is
off while duty cycling.
0 - System will enter sleep when gyroscope is disabled and accelerometer is off
while duty cycling.
[7]
LP_DIS
This bit should be set to 1 when reading from SRAM/FIFO.
Reserved
[6]
[5]
-
1 – X accelerometer is disabled.
0 – X accelerometer is on.
1 – Y accelerometer is disabled.
0 – Y accelerometer is on.
1 – Z accelerometer is disabled.
0 – Z accelerometer is on.
1 – X gyro is disabled.
0 – X gyro is on.
1 – Y gyro is disabled.
0 – Y gyro is on.
1 – Z gyro is disabled.
STBY_XA
[4]
[3]
[2]
[1]
[0]
STBY_YA
STBY_ZA
STBY_XG
STBY_YG
STBY_ZG
0 – Z gyro is on.
12.73 REGISTER 112 – OIS ENABLE
Register Name: OIS_ENABLE
Register Type: READ/WRITE
Register Address: 112 (Decimal); 70 (Hex)
BIT
NAME
FUNCTION
[7:2]
-
Reserved
1 - Configures auxiliary interface as SPI slave (for connection to OIS controller).
[1]
[0]
OIS_ENABLE
-
0 – Configures auxiliary interface as I2C master (for connection to external
sensors).
Reserved
Page 67 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.74 REGISTERS 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ
Register Address: 114 (Decimal); 72 (Hex)
BIT
NAME
FUNCTION
High Bits, count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
[7:0]
FIFO_COUNT[15:8]
Register Name: FIFO_COUNTL
Register Type: READ
Register Address: 115 (Decimal); 73 (Hex)
BIT
NAME
FUNCTION
Low Bits, count indicates the number of written bytes in the FIFO.
Note: Must read FIFO_COUNTL to latch new data for both FIFO_COUNTH and
FIFO_COUNTL.
[7:0]
FIFO_COUNT[7:0]
12.75 REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT
NAME
FUNCTION
[7:0]
FIFO_DATA
Read/Write command provides Read or Write operation for the FIFO.
Description:
This register is used to read and write data from the FIFO buffer.
Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are
enabled, the contents of registers 59 through 72 will be written in order at the Sample Rate.
The contents of the sensor data registers (registers 59 to 72) are written into the FIFO buffer when their corresponding FIFO
enable flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in INT_STATUS
(Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO
unless register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data is available.
Normal data is precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty.
Page 68 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.76 REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ
Register Address: 117 (Decimal); 75 (Hex)
BIT
NAME
FUNCTION
[7:0]
WHOAMI
Register to indicate to user which device is being accessed.
Description:
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of
the register is 0x20. This is different from the I2C address of the device as seen on the slave I2C controller by the applications
processor. The I2C address of the ICM-20690 is 0x68 or 0x69 depending upon the value driven on AD0 pin.
Page 69 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
12.77 REGISTER 119 TO 126 – ACCELEROMETER OFFSET REGISTERS
Register Name: XA_OFFSET_H
Register Type: READ/WRITE
Register Address: 119 (Decimal); 77 (Hex)
BIT
NAME
FUNCTION
Upper bits of the X accelerometer offset cancellation. +/- 16g Offset
cancellation in all Full Scale modes, 15 bit 0.98-mg steps.
[7:0]
XA_OFFS[14:7]
Register Name: XA_OFFSET_L
Register Type: READ/WRITE
Register Address: 120 (Decimal); 78 (Hex)
BIT
[7:1]
[0]
NAME
FUNCTION
Lower bits of the X accelerometer offset cancellation. +/- 16g Offset
cancellation in all Full Scale modes, 15 bit 0.98-mg steps.
Reserved
XA_OFFS[6:0]
-
Register Name: YA_OFFSET_H
Register Type: READ/WRITE
Register Address: 122 (Decimal); 7A (Hex)
BIT
NAME
FUNCTION
Upper bits of the Y accelerometer offset cancellation. +/- 16g Offset
cancellation in all Full Scale modes, 15 bit 0.98-mg steps.
[7:0]
YA_OFFS[14:7]
Register Name: YA_OFFSET_L
Register Type: READ/WRITE
Register Address: 123 (Decimal); 7B (Hex)
BIT
[7:1]
[0]
NAME
FUNCTION
Lower bits of the Y accelerometer offset cancellation. +/- 16g Offset
cancellation in all Full Scale modes, 15 bit 0.98-mg steps.
Reserved
YA_OFFS[6:0]
-
Register Name: ZA_OFFSET_H
Register Type: READ/WRITE
Register Address: 125 (Decimal); 7D (Hex)
BIT
NAME
FUNCTION
Upper bits of the Z accelerometer offset cancellation. +/- 16g Offset
cancellation in all Full Scale modes, 15 bit 0.98-mg steps.
[7:0]
ZA_OFFS[14:7]
Register Name: ZA_OFFSET_L
Register Type: READ/WRITE
Register Address: 126 (Decimal); 7E (Hex)
BIT
[7:1]
[0]
NAME
FUNCTION
Lower bits of the Z accelerometer offset cancellation. +/- 16g Offset
cancellation in all Full Scale modes, 15 bit 0.98-mg steps.
Reserved
ZA_OFFS[6:0]
-
Page 70 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
13 DESCRIPTION OF REGISTERS SPECIFIC TO SECONDARY INTERFACE IN OIS MODE
The following registers are accessible from the secondary interface in OIS mode only. OIS controller should only read this data in SPI
burst mode to avoid OIS sensor data update during reading. SPI single byte read mode should not be used.
13.1 REGISTER 0 – HIGH BYTE OF ACCELEROMETER X-AXIS OIS DATA
Register Name: ACCEL_XOUT_OIS_H
Register Type: READ
Register Address: 00 (Decimal); 00 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_OIS[15:8] High byte of accelerometer x-axis OIS data.
13.2 REGISTER 1 – LOW BYTE OF ACCELEROMETER X-AXIS OIS DATA
Register Name: ACCEL_XOUT_OIS_L
Register Type: READ
Register Address: 01 (Decimal); 01 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_XOUT_OIS[7:0]
Low byte of accelerometer x-axis OIS data.
13.3 REGISTER 2 – HIGH BYTE OF ACCELEROMETER Y-AXIS OIS DATA
Register Name: ACCEL_YOUT_OIS_H
Register Type: READ
Register Address: 02 (Decimal); 02 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_OIS[15:8] High byte of accelerometer y-axis OIS data.
13.4 REGISTER 3 – LOW BYTE OF ACCELEROMETER Y-AXIS OIS DATA
Register Name: ACCEL_YOUT_OIS_L
Register Type: READ
Register Address: 03 (Decimal); 03 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_YOUT_OIS[7:0]
Low byte of accelerometer y-axis OIS data.
13.5 REGISTER 4 – HIGH BYTE OF ACCELEROMETER Z-AXIS OIS DATA
Register Name: ACCEL_ZOUT_OIS_H
Register Type: READ
Register Address: 04 (Decimal); 04 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT_OIS[15:8] High byte of accelerometer z-axis OIS data.
Page 71 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
13.6 REGISTER 5 – LOW BYTE OF ACCELEROMETER Z-AXIS OIS DATA
Register Name: ACCEL_ZOUT_OIS_L
Register Type: READ
Register Address: 05 (Decimal); 05 (Hex)
BIT
NAME
FUNCTION
[7:0]
ACCEL_ZOUT_OIS[7:0]
Low byte of accelerometer z-axis OIS data.
13.7 REGISTER 6 – HIGH BYTE OF TEMPERATURE SENSOR OIS DATA
Register Name: TEMP_OUT_OIS_H
Register Type: READ
Register Address: 06 (Decimal); 06 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT_OIS[15:8]
High byte of temperature sensor OIS data.
13.8 REGISTER 7 – LOW BYTE OF TEMPERATURE SENSOR OIS DATA
Register Name: TEMP_OUT_OIS_L
Register Type: READ
Register Address: 07 (Decimal); 07 (Hex)
BIT
NAME
FUNCTION
[7:0]
TEMP_OUT_OIS[7:0]
Low byte of temperature sensor OIS data.
13.9 REGISTER 8 – HIGH BYTE OF GYROSCOPE X-AXIS OIS DATA
Register Name: GYRO_XOUT_OIS_H
Register Type: READ
Register Address: 08 (Decimal); 08 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_XOUT_OIS[15:8] High byte of gyroscope x-axis OIS data.
13.10 REGISTER 9 – LOW BYTE OF GYROSCOPE X-AXIS OIS DATA
Register Name: GYRO_XOUT_OIS_L
Register Type: READ
Register Address: 09 (Decimal); 09 (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_XOUT_OIS[7:0]
Low byte of gyroscope x-axis OIS data.
Page 72 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
13.11 REGISTER 10 – HIGH BYTE OF GYROSCOPE Y-AXIS OIS DATA
Register Name: GYRO_YOUT_OIS_H
Register Type: READ
Register Address: 10 (Decimal); 0A (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_YOUT_OIS[15:8] High byte of gyroscope y-axis OIS data.
13.12 REGISTER 11 – LOW BYTE OF GYROSCOPE Y-AXIS OIS DATA
Register Name: GYRO_YOUT_OIS_L
Register Type: READ
Register Address: 11 (Decimal); 0B (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_YOUT_OIS[7:0]
Low byte of gyroscope y-axis OIS data.
13.13 REGISTER 12 – HIGH BYTE OF GYROSCOPE Z-AXIS OIS DATA
Register Name: GYRO_ZOUT_OIS_H
Register Type: READ
Register Address: 12 (Decimal); 0C (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_ZOUT_OIS[15:8] High byte of gyroscope z-axis OIS data.
13.14 REGISTER 13 – LOW BYTE OF GYROSCOPE Z-AXIS OIS DATA
Register Name: GYRO_ZOUT_OIS_L
Register Type: READ
Register Address: 13 (Decimal); 0D (Hex)
BIT
NAME
FUNCTION
[7:0]
GYRO_ZOUT_OIS[7:0]
Low byte of gyroscope z-axis OIS data.
Page 73 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
14 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
Manufacturing Recommendations
o
o
o
o
Assembly Guidelines and Recommendations
PCB Design Guidelines and Recommendations
MEMS Handling Instructions
ESD Considerations
o
Reflow Specification
o
Storage Specifications
o
o
o
Package Marking Specification
Tape & Reel Specification
Reel & Pizza Box Label
o
Packaging
o
Representative Shipping Carton Label
Compliance
o
o
o
Environmental Compliance
DRC Compliance
Compliance Declaration Disclaimer
Page 74 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
15 DOCUMENT INFORMATION
15.1 REVISION HISTORY
Revision Date
Revision
Description
10/11/2016
1.0
Initial Release
Page 75 of 76
Document Number: DS-000178
Revision: 1.0
ICM-20690
This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use, or for any
infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves the right
to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes no
warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any
claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to,
claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any
patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the
property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or
mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2016 InvenSense, Inc. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, Digital Motion Processor,
AAR, and the InvenSense logo are trademarks of InvenSense, Inc. Other company and product names may be trademarks of the respective companies with which they
are associated.
©2016 InvenSense, Inc. All rights reserved.
Page 76 of 76
Document Number: DS-000178
Revision: 1.0
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