VN4012_13 [SUPERTEX]
N-Channel Enhancement-Mode Vertical DMOS FET;
| 型号： | VN4012_13 |
| 厂家： | 
Supertex, Inc |
| 描述： | N-Channel Enhancement-Mode Vertical DMOS FET |
| 文件： | 总3页 (文件大小：568K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
VN4012
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
General Description
► Free from secondary breakdown
► Low power drive requirement
► Ease of paralleling
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
► Low CISS and fast switching speeds
► Excellent thermal stability
► Integral source-drain diode
► High input impedance and high gain
Applications
► Motor controls
► Converters
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
► Amplifiers
► Switches
► Power supply circuits
► Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
Ordering Information
Product Summary
RDS(ON)
(max)
12Ω
VGS(TH)
(max)
1.8V
IDSS
(min)
Part Number
Package Option
Packing
BVDSS/BVDGS
VN4012L-G
TO-92
1000/Bag
400V
150mA
VN4012L-G P002
VN4012L-G P003
VN4012L-G P005
VN4012L-G P013
VN4012L-G P014
Pin Configuration
TO-92
2000/Reel
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
DRAIN
SOURCE
Absolute Maximum Ratings
Parameter
Value
GATE
TO-92
Drain-to-source voltage
Drain-to-gate voltage
BVDSS
BVDGS
±20V
Gate-to-source voltage
Product Marking
Operating and storage temperature
-55OC to +150OC
Si VN
4 0 1 2 L
YYWW
YY = Year Sealed
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
Typical Thermal Resistance
TO-92
Package
θja
TO-92
132OC/W
Doc.# DSFP-VN4012
B082013
Supertex inc.
www.supertex.com
VN4012
Thermal Characteristics
ID
ID
Power Dissipation
†
Package
IDR
IDRM
@TC = 25OC
(continuous)†
(pulsed)
TO-92
160mA
650mA
1.0W
160mA
650mA
Notes:
†
ID (continuous) is limited by max rated Tj .
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym
BVDSS
VGS(th)
IGSS
Parameter
Min
400
0.6
-
Typ
Max Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
Gate body leakage
-
-
-
-
-
V
V
VGS = 0V, ID = 100µA
VGS = VDS, ID = 1.0mA
VGS = ±20V, VDS = 0V
1.8
10
1
nA
-
VGS = 0V, VDS = 0.8 Max Rating
DS = 0.8 Max Rating,
IDSS
Zero gate voltage drain current
On-state drain current
µA
V
-
-
100
VGS = 0V, TA = 125°C
ID(ON)
0.15
0.3
-
A
VGS = 4.5V, VDS = 10V
-
9.5
12
30
-
VGS = 4.5V, ID = 100mA
VGS = 4.5V, ID = 100mA, TA = 125OC
Static drain-to-source on-state
resistance
RDS(ON)
Ω
-
17
GFS
CISS
COSS
CRSS
tr
Forward transductance
Input capacitance
125
350
mmho VDS = 15V, ID = 100mA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
110
30
10
20
20
65
65
1.2
VGS = 0V,
VDS = 25V,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Rise time
pF
VDD = 25V,
ID = 100mA,
RGEN = 25Ω
td(ON)
tf
td(OFF)
VSD
Turn-on delay time
ns
V
Fall time
Turn-off delay time
Diode forward voltage drop
VGS = 0V, ISD = 160mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
VDD
90%
INPUT
0V
Pulse
RL
10%
Generator
OUTPUT
t(ON)
td(ON)
t(OFF)
td(OFF)
RGEN
tf
tr
VDD
OUTPUT
0V
INPUT
D.U.T.
10%
10%
90%
90%
Doc.# DSFP-VN4012
B082013
Supertex inc.
www.supertex.com
2
VN4012
3-Lead TO-92 Package Outline (L)
D
A
Seating
Plane
1
2
3
L
c
b
e1
e
Side View
Front View
E
E1
1
3
2
Bottom View
Symbol
A
.170
-
b
.014†
-
c
D
.175
-
E
.125
-
E1
.080
-
e
e1
.045
-
L
.500
-
MIN
NOM
MAX
.014†
-
.095
-
Dimensions
(inches)
.210
.022†
.022†
.205
.165
.105
.105
.055
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-VN4012
B082013
3
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