VN2410L-GP014 [SUPERTEX]

SMALL SIGNAL, FET;


型号：	VN2410L-GP014
厂家：	Supertex, Inc
描述：	SMALL SIGNAL, FET
文件：	总3页 (文件大小：544K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Supertex inc.

VN2410

N-Channel Enhancement-Mode

Vertical DMOS FET

Features

General Description

► Free from secondary breakdown

► Low power drive requirement

► Ease of paralleling

This enhancement-mode (normally-off) transistor utilizes

a vertical DMOS structure and Supertex’s well-proven,

silicon-gate manufacturing process. This combination

produces a device with the power handling capabilities

of bipolar transistors and the high input impedance and

positive temperature coefﬁcient inherent in MOS devices.

Characteristic of all MOS structures, this device is free

from thermal runaway and thermally-induced secondary

breakdown.

► Low C_ISSand fast switching speeds

► Excellent thermal stability

► Integral source-drain diode

► High input impedance and high gain

Applications

► Motor controls

► Converters

Supertex’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications where

very low threshold voltage, high breakdown voltage, high

input impedance, low input capacitance, and fast switching

speeds are desired.

► Ampliﬁers

► Switches

► Power supply circuits

► Drivers (relays, hammers, solenoids, lamps, memories,

displays, bipolar transistors, etc.)

Ordering Information

Product Summary

R_DS(ON)

(max)

10Ω

Part Number

Package Option

Packing

I_DSS

(min)

BV_DSS/BV_DGS

VN2410L-G

TO-92

1000/Bag

240V

1.0A

VN2410L-G P002

VN2410L-G P003

VN2410L-G P005

VN2410L-G P013

VN2410L-G P014

Pin Conﬁguration

TO-92

2000/Reel

-G denotes a lead (Pb)-free / RoHS compliant package.

Contact factory for Wafer / Die availablity.

Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.

DRAIN

SOURCE

Absolute Maximum Ratings

Parameter

Value

GATE

TO-92

Drain-to-source voltage

Drain-to-gate voltage

BV_DSS

BV_DGS

±20V

Gate-to-source voltage

Product Marking

Operating and storage temperature

-55^OC to +150^OC

Si VN

2 4 1 0 L

YYWW

YY = Year Sealed

Absolute Maximum Ratings are those values beyond which damage to the device may

occur. Functional operation under these conditions is not implied. Continuous operation

of the device at the absolute rating level may affect device reliability. All voltages are

referenced to device ground.

WW = Week Sealed

= “Green” Packaging

Package may or may not include the following marks: Si or

Typical Thermal Resistance

TO-92

Package

θ_ja

TO-92

132^OC/W

Doc.# DSFP-VN2410

C081913

Supertex inc.

www.supertex.com

VN2410

Thermal Characteristics

I_D

Power Dissipation

†

Package

I_DR

I_DRM

@T_C= 25^OC

(continuous)^†

(pulsed)

TO-92

190mA

1.7A

1.0W

190mA

1.7A

Notes:

†

I_D(continuous) is limited by max rated T_j.

Electrical Characteristics (T_A= 25^OC unless otherwise speciﬁed)

Sym

BV_DSS

V_GS(th)

I_GSS

Parameter

Min

240

0.8

Typ

Max Units Conditions

Drain-to-source breakdown voltage

Gate threshold voltage

Gate body leakage

V_GS= 0V, I_D= 100µA

2.0

100

V_GS= V_DS, I_D= 1.0mA

V_GS= 20V, V_DS= 0V

V_GS= 0V, V_DS= 120V

I_DSS

Zero gate voltage drain current

On-state drain current

µA

_GS= 0V, V_DS= 120V,

500

T_A= 125°C

I_D(ON)

1.0

1.4

V_GS= 10V, V_DS= 15V

V_GS= 2.5V, I_D= 100mA

V_GS= 10V, I_D= 500mA

R_DS(ON)Static drain-to-source on-state resistance

ΔR_DS(ON)Change in R_DS(ON)with temperature

1.0

%/^OC V_GS= 10V, I_D= 500mA

G_FS

C_ISS

C_OSS

C_RSS

t_r

Forward transductance

Input capacitance

300

mmho V_DS= 10V, I_D= 500mA

125

8.0

V_GS= 0V,

V_DS= 25V,

f = 1.0MHz

Common source output capacitance

Reverse transfer capacitance

Rise time

V_DD= 60V,

I_D= 400mA,

R_GEN= 25Ω

t_d(ON)

t_f

t_d(OFF)

V_SD

Turn-on delay time

Fall time

Turn-off delay time

Diode forward voltage drop

1.2

V_GS= 0V, I_SD= 190mA

Notes:

1. All D.C. parameters 100% tested at 25^OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)

2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

10V

VDD

90%

INPUT

Pulse

R_L

10%

Generator

OUTPUT

t_(ON)

t_d(ON)

t_(OFF)

t_d(OFF)

R_GEN

t_f

t_r

VDD

OUTPUT

INPUT

D.U.T.

10%

90%

Doc.# DSFP-VN2410

C081913

Supertex inc.

www.supertex.com

VN2410

3-Lead TO-92 Package Outline (L)

Seating

Plane

Side View

Front View

Bottom View

Symbol

.170

.014^†

.175

.125

.080

.045

.500

MIN

NOM

MAX

.014^†

.095

Dimensions

(inches)

.210

.022^†

.205

.165

.105

.055

.610*

JEDEC Registration TO-92.

* This dimension is not speciﬁed in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

Doc.# DSFP-VN2410

C081913

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