LN100 [SUPERTEX]
1200V Cascoded N-Channel MOSFET;
| 型号： | LN100 |
| 厂家： | 
Supertex, Inc |
| 描述： | 1200V Cascoded N-Channel MOSFET |
| 文件： | 总6页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
LN100
1200V Cascoded
N-Channel MOSFET
Features
General Description
The LN100 is a 1200V cascoded N-channel MOSFET
with an integrated high value high voltage resistor divider.
Multiple devices can be used in series for voltages
greater than 1200V. A resistor divider ratio of 1000:1 is
provided. High value resistors are used to minimize power
consumption.
► 1200V breakdown voltage
► Low threshold, 1.6V max.
► High input impedance
► Low input capacitance
► Integrated high voltage resistor divider
► Integrated 1000:1 resistor divider
► Compact 3x3 LFGA package
The maximum Gate-to-Source threshold voltage is 1.6V.
This allows the Gate to be controlled by low voltage
circuitry. The LN100 can be used as a high voltage low
power pulser. It can also be used in a high voltage low
current amplifier application where it is used to charge and
discharge a small capacitive load.
Applications
► High voltage shunt regulator
► High voltage linear amplifier
► High voltage digital pulsers
► High voltage sensing circuit
Ordering Information
Product Summary
BVDSS
min (V)
RDS(ON)
max (kΩ)
ID(ON)
min (mA)
Part Number
Package Option Packing
LN100LA-G
6-Lead LFGA 3000/Reel
1200
3.0
3.0
Pin Configuration
ESD Sensitive Device
6
5
V1
DRAIN
Absolute Maximum Ratings
Parameter
Value
1200V
1200V
5.0V
Drain-to-Source voltage
V1 - V2 differential voltage
V2 - V3 differential voltage
Operating temperature range
Power dissipation, TA = 25°C
V2
V3
GATE SOURCE
1
2
3
4
-25°C to +125°C
350mW1
6-Lead LFGA
(top view)
Pads are at bottom of package.
Absolute Maximum Ratings are those values beyond which damage
to the device may occur. Functional operation under these conditions
is not implied. Continuous operation of the device at the absolute
rating level may affect device reliability. All voltages are referenced
to device ground.
Product Marking
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
Note:
L 1 0 0
YWLL
1. Device mounted on a 25mm x 25mm x 1.57mm board.
Typical Thermal Resistance
Package
Package may or may not include the following marks: Si or
θja
6-Lead LFGA
6-Lead LFGA
186°C/W
Doc.# DSFP-LN100
A031414
Supertex inc.
www.supertex.com
LN100
Electrical Characteristics
(Tj = 25ºC unless otherwise specified)
Symbol
Parameter
Min
Typ
Max Unit Conditions
MOSFET M1 and M2
BVDSS1
BVDSS2
Drain-to-Source breakdown voltage of M1
600
600
-
-
-
-
V
V
VGS = 0V, ID = 1.0μA
Drain-to-Source breakdown voltage of M2
Gate-to-Source threshold voltage
VGS = 0V, ID = 1.0μA
VGS = VDS, ID = 10μA
See test circuit
VGS(th)
0.5
-
-
-
1.6
3.0
V
VGS = 2.8V, ID = 2.0mA
See test circuit
RDS(ON)
Static Drain-to-Source On-State resistance
kΩ
mA
VGS = 2.8V, VDS = 25V
See test circuit
ID(ON)
CISS
On-State Drain current
Input capacitance
3.0
-
-
-
-
50
pF VGS = 0V, VDS = 25V
Zener Diode
VZ
IGS
IZ
M2 Gate-to-Source Zener diode clamp
6.5
-
-
12
100
-
V
IGS = 1.0mA, VS = 0V
Gate-to-Source Zener diode leakage
Maximum Zener current
-
-
nA VGS = 4.5V
mA ---
10
Resistors R1, R2, and R3
R1 + R2
R1
Resistor divider R1 + R2
54
27
27
54
-
-
-
-
-
-
-
MΩ V1 = 0 to 1000V, V2 = 0V
MΩ VR1 = 0 to 500V
MΩ VR2 = 0 to 500V
kΩ VR3 = 0 to 5.0V
Resistor R1
-
R2
Resistor R2
-
-
R3
Resistor R3
ΔR
R1, R2, and R3 matching
±18
%
---
Block Diagram
V1
V2
DRAIN
R1
M1
R2
R3
M2
V3
D
GATE
SOURCE
Doc.# DSFP-LN100
A031414
Supertex inc.
www.supertex.com
2
LN100
Test Circuits
10V
10µA
V1
DRAIN
R1
R2
R3
VGS(th)
M1
M2
V2
V3
D
SOURCE
GATE
LN100
Gate-to-Source Threshold Voltage
10V
2.0mA
V1
DRAIN
R1
R2
R3
VDS
M1
M2
V2
V3
VDS
2.0mA
RDS(ON)
=
2.8V
D
SOURCE
GATE
LN100
Drain-to-Source On-Resistance
25V
ID(ON)
V1
DRAIN
R1
R2
R3
M1
M2
V2
V3
2.8V
D
SOURCE
GATE
LN100
On-State Drain Current
Doc.# DSFP-LN100
A031414
Supertex inc.
www.supertex.com
3
LN100
Typical Application Circuits
R3 divides the output voltage by approximately 1000. V2 is
the feedback voltage for the op-amp. If the reference voltage,
VREF, is 1.0V, the output voltage will be shunted to 1000V.
High Voltage, Low Current Shunt Regulator
The LN100 can be used as a high voltage, low current shunt
regulator as shown in Figure 1. Resistor divider R1, R2, and
HVOUT
=
1000 x VREF
COUT
1000V
V1
Charge
Pump
DRAIN
R1
M1
M2
R2
V2
R3
V3
D
SOURCE
+
A
VIN
-
GATE
LN100
Figure 1: High Voltage, Low Current, Shunt Regulator
The Gate is driven with a low voltage op-amp. V2 is the
High Voltage, Low Current Linear Amplifier
In Figure 2, the two LN100’s are used as the main output
stage for a 1000V low frequency amplifier to drive capacitive
loads. The top LN100 is used to actively charge the load up
to the desired voltage. The bottom LN100 is used to actively
discharge the load to the desired voltage.
feedback voltage for the op-amp setting it to a gain of 60dB.
A 0 to 1.0V sinusoidal waveform on VIN will create a 0 to
1000V sinusoidal waveform on HVOUT. Output frequency
only needs to go up to 300Hz.
C
V1
DRAIN
R1
M1
R2
V2
M2
R3
V3
D
SOURCE
GATE
LN100
HVOUT
=
1000 x VIN
COUT
V1
DRAIN
R1
R2
R3
M1
M2
V2
V3
D
SOURCE
+
A
VIN
-
GATE
LN100
Figure 2: High Voltage Low Current Linear Amplifier
Doc.# DSFP-LN100
A031414
Supertex inc.
www.supertex.com
4
LN100
Typical Application Circuits (cont.)
three LN100s are used to discharge the load back to ground.
The integrated resistors in each of the LN100 allows the
3000V to be divided into thirds. Each LN100 will only need
to hold off 1000V.
High Voltage, Low Current Digital Pulser
In Figure 3, the six LN100’s are used as the main output
stage for a 3000V low frequency digital pulser. The first three
LN100s are used to charge the load up to 3000V. The next
HV = 3000V
HVOUT
=
0 to 3000V
COUT
C
V1
V1
DRAIN
DRAIN
R1
R2
R3
R1
R2
R3
M1
M2
M1
M2
V2
V3
V2
V3
D
D
SOURCE
DRAIN
SOURCE
DRAIN
GATE
V1
GATE
V1
LN100
LN100
R1
R2
R3
R1
R2
R3
M1
M2
M1
M2
V2
V3
V2
V3
D
D
SOURCE
SOURCE
DRAIN
GATE
GATE
V1
LN100
LN100
V1
DRAIN
R1
R2
R3
R1
R2
R3
M1
M2
M1
M2
V2
V3
V2
V3
D
D
SOURCE
SOURCE
GATE
GATE
LN100
LN100
V
=
0INto 3.0V
Figure 3: High Voltage Low Current 3000V Digital Pulser
Doc.# DSFP-LN100
A031414
Supertex inc.
www.supertex.com
5
LN100
6-Lead LFGA Package Outline (LA)
3.00x3.00mm body, 0.85mm height (max), 0.65mm pitch
D
6
d1
5
6
E
d2
Note 1
(Index Area
D/2 x E/2)
Solder Mask
(hatch area)
4
3
2
1
1
b
e
Top View
Side View
Bottom View
A
Seating
Plane
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
A
b
D
E
d1
d2
e
MIN
NOM
MAX
0.75
0.80
0.85
0.30
0.35
0.40
2.925
3.000
3.075
2.925
3.000
3.075
0.225
0.325
0.425
Dimension
(mm)
2.00
BSC
0.65
BSC
Drawings not to scale
Supertex Doc. #: DSPD-6LFGALA3X3P065, Version A110811
(The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2014 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-LN100
A031414
6
相关型号：
©2020 ICPDF网 联系我们和版权申明