HV528 [SUPERTEX]
16-Channel Serial to Parallel Converter with High Voltage Backplane Driver and Push-Pull Outputs; 16通道串行到并行转换器与高压背板驱动器和推挽输出
| 型号： | HV528 |
| 厂家： | 
Supertex, Inc |
| 描述： | 16-Channel Serial to Parallel Converter with High Voltage Backplane Driver and Push-Pull Outputs |
| 文件： | 总8页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV528
16-Channel Serial to Parallel Converter
with High Voltage Backplane Driver and Push-Pull Outputs
Features
General Description
The HV528 is a 200V, 16-channel serial to parallel converter.
The high voltage outputs and the backplane driver are
designed to source and sink 1.0mꢀ.
► HVCMOS® technology
► Output voltage up to +200V
► Shift register speed 500kHz @ VDD = 1.7V
► 16 high voltage outputs
► High voltage backplane driver
► CMOS input levels
The high voltage outputs are controlled by a 16-bit serial shift
register, followed by a 16-bit latch. Data is shifted through
the shift registers during the low to high clock transition. ꢀ
data output buffer is provided for cascading multiple devices.
Data is transferred to the 16-bit latch when a logic level low is
applied to the LE input. Data is stored in the latch when LE is
high. Output states are controlled by the data in the latch and
by the POL pin.
Applications
► Multiple segment EL display
► Piezoelectric transducer driver
► Braille driver
Typical Application Circuit
Low Voltage
Power Supply
High Voltage
Power Supply
VBIꢀS
HVOUT
1
EL
DIN
Segment
Panel
High
Voltage
Low
Voltage
CLK
Micro
Processor
LE
16
Level
Translators
&
Push-Pull
Output
Shift
Register
Latches
HVOUT16
BP
POL
DOUT
Supertex HV528
to DIN of another HV528 for cascading (if needed)
HV528
Ordering Information
Pin Configuration
32
Package Option
32-Lead QFN
Device
5x5mm body,
1
1.0mm height (max), 0.50mm pitch
HV528
HV528K6-G
-G indicates package is RoHS compliant (‘Green’)
32-Lead QFN (K6)
Absolute Maximum Ratings
Parameter
(top view)
(Bottom side exposed center pad is at VPP potential)
Value
-0.5V to 7.0V
Logic supply, VDD
High voltage supply, VPP
Translator supply voltage, VBIꢀS
Logic input levels
215V
Product Marking
-0.5V to 7.0V
L = Lot Number
-0.5V to VDD +0.5V
-40°C to +125°C
-65°C to +150°C
YY = Year Sealed
WW = Week Sealed
ꢀ = ꢀssembler ID
C = Country of Origin
= “Green” Packaging
HV528
Operating junction temperature
LLLLLL
YYWW
Storage temperature range
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
AAACCC
32-Lead QFN (K6)
Operating Supply Voltages and Conditions
Sym Parameter
Min
1.7
5.4
50
Typ Max Units Conditions
VDD
Logic supply voltage
3.0
5.5
6.6
200
VDD
V
V
---
---
---
---
---
---
VBIꢀS Level translator supply voltage
-
-
-
-
-
VPP
VIH
VIL
Positive high voltage supply
High-level input voltage
Low-level input voltage
Operating temperature
V
0.9VDD
0
V
V
Tꢀ
0
+70
°C
Notes:
1. External ground noise reduction circuit will be provided by design upon characterization.
Power-up sequence should be the following*:
1. ꢀpply ground
2. ꢀpply VDD
3. Set all inputs (DIN, CLK, LE , POL) to a known state
4. ꢀpply VBIꢀS
5. ꢀpply VPP
Power-down sequence should be the reverse of the above
*This power up sequence requires an external high voltage diode between VDD and VPP. Without the diode, power up VPP to a VDD level first to bias the
silicon substrate. ꢀfter all other signals are powered, finish raising the VPP to its final level.
2
HV528
DC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted)
Sym Parameter
Min
Typ Max Units Conditions
IDD
VDD supply current
-
-
-
-
1.0
10
mꢀ
µꢀ
fCLK = 500kHz
IDDQ
Quiescent VDD supply current
ꢀll logic inputs = VDD or 0V
ꢀll HVOUTS switching at 1.0kHz.
Peak IBIꢀS = 200mꢀ with all channels
switching
IBIꢀS
VBIꢀS supply current
-
-
100
µꢀ
IBIꢀSQ Quiescent VBIꢀS current
-
-
-
-
-
-
-
-
-
-
-
-
10
100
10
-10
-
µꢀ
µꢀ
µꢀ
µꢀ
V
No HVOUT switching
IPPQ
IIH
Quiescent VPP supply current
High-level logic input current
Low-level logic input current
-
VPP = 200V, outputs are static
-
VIH = VDD
IIL
-
VIL = 0V
VPP -30V
IHVOUT = -1.0mꢀ, 50V ≤ VPP ≤ 100V
HVOUT & BP
VOH
High level output
VPP -16V
-
V
IHVOUT = -1.0mꢀ, 100V < VPP ≤ 200V
DOUT
VDD -1.0V
-
V
IDOUT = -1.0mꢀ
IHVOUT = 1.0mꢀ
IDOUT = 1.0mꢀ
---
HVOUT & BP
Low level output
DOUT
-
-
-
-
6.0
1.0
10
10
V
VOL
V
CDIN Logic input capacitance
CDOUT Logic output capacitance
pF
pF
---
AC Electrical Characteristics (Over operating supply voltages and temperature, unless otherwise noted)
Sym Parameter
fCLK Clock frequency
tC
Min
0
Typ Max Units Conditions
-
-
-
-
-
-
500
kHz ---
Clock high / low pulse width
Data setup time before clock rises
Data hold time after clock rises
LE from CLK setup time
LE pulse width
1.0
50
-
-
-
-
-
µs
ns
ns
ns
ns
---
---
---
---
---
tSU
tH
50
tCLE
tWLE
15
100
CLDOUT = 50pF,
tDD
Clock negative edge to DOUT delay
-
-
-
-
150
500
ns
ns
(CLDOUT includes CDIN and CDOUT
)
Delay time from inputs for
HVOUT / BP to start rise/fall
tPHV
VPP = 200V, VBIꢀS = 5.4V
CL = 1500pF, VPP = 200V
tOR
tOF
tOC
HVOUTPUT / BP rise time
HVOUTPUT / BP fall time
Width of POL pulses
-
-
-
-
300
300
-
µs
µs
µs
-
CL = 1500pF, VBIꢀS = 5.4V, VPP = 200V
---
tPHV + tOR/tOF
3
HV528
Input and Output Equivalent Circuits
VPP
VDD
VDD
Input
GND
Data Out
HVOUT
VBIꢀS
GND
HVGND
Logic Inputs
High Voltage Outputs
Logic Data Output
VBIAS SUPPLY
The VBIꢀS supply operates from 5.4 to 6.6V. It is the gate The operating VDD range is 1.7 to 5.5V. ꢀ plot showing the
drive voltage for all of the output N-channel MOSFETs. This typical characteristics of ISINK vs VBIꢀS is shown below.
allows the output peak current sink to be set by varying the
V
voltage. ꢀ higher VBIꢀS voltage will increase the current
siBnIꢀkSing capability.
Typical HVOUT ISINK vs VBIAS
(VPP = 200V, CLOAD = 1.0nF)
20
18
16
14
12
10
5.0
5.5
6.0
6.5
VBIꢀS (V)
4
HV528
Switching Waveforms
5
HV528
Functional Block Diagram
VDD
DIN
Level
Translator
Logic
HVOUT1
GND
CLK
HVGND
16-bit
Shift
Register
16-bit
Latch
Level
Translator
Logic
HVOUT16
HVGND
GND
DOUT
HVGND
GND
LE
Level
Translator
&
BP
POL
Buffer
HVGND
Function Table
Inputs
Outputs
Function
DIN
Shift Reg
2...16
HV Outputs
CLK
LE
POL
BP
DOUT
1
1
2...16
Load S/R
H OR L
X
↑
H
L
X
H
H or L ●...●
●
●...●
X
L
●
●
L
*
*
*..........*
*..........*
●...●
*
*
*..........*
Transfer data in
latch
*..........*
(b)
X
X
X
L
X
X
L
H
H
L
H
L
H
L
●
●
●
●
●
●
●
●...●
Store data in latches
Transparent mode
●...●
(b)
●...●
H
L
↑
↑
L
L
H
H
L
●...●
●...●
L
H
●
●...●
●...●
L
L
●
●
H
H
●...●
(b)
X
X
X
X
H
H
L
●
●
●...●
●...●
H
L
X
X
Invert mode
H
●
●...●
Notes:
H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition
● = dependent on previous stage’s state before the last CLK or last LE low
* = data at the last CLK ↑
(b) = bar over all symbols
6
HV528
Pin Description
Pin #
Function
Description
1
HVOUT12
HVOUT11
HVOUT10
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
No connect
2
3
4
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
NC
9
8
7
6
5
4
3
2
1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VPP
High voltage supply
GND
NC
Logic ground
No connect
DIN
Data in
NC
No connect
CLK
Clock input logic
VDD
Logic supply voltage
POL
Polarity bar input logic
Latch enable bar input logic
No connect
LE
NC
DOUT
NC
Data out
No connect
VBIꢀS
HVGND
BP
Level translator bias voltage
High voltage ground
High voltage backplane output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
High voltage push-pull output
HVOUT16
HVOUT15
HVOUT14
HVOUT13
Center Pad
The center pad is at VPP potential. Leave floating or connect to VPP. Do not ground.
7
HV528
32-Lead QFN Package Outline (K6)
5x5mm body, 1.0mm height (max), 0.50mm pitch
D2
D
32
32
Note 1
(Index ꢀrea
D/2 x E/2)
1
1
Note 1
(Index ꢀrea
D/2 x E/2)
e
b
E
E2
View B
Top View
Bottom View
Note 3
θ
L
ꢀ
Seating
Plane
ꢀ3
L1
ꢀ1
Note 2
Side View
View B
Notes:
1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal
or marked feature.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
A
A1
A3
b
D
D2
1.05
-
E
E2
1.05
-
e
L
L1
0.00
-
θ
0O
-
MIN
NOM
MꢀX
0.80
0.90
1.00
0.00
0.02
0.05
0.18
0.25
0.30
4.85
5.00
5.15
4.85
5.00
5.15
0.45
0.50
0.55
Dimension
(mm)
0.20
REF
0.50
BSC
3.45
3.45
0.15
14O
JEDEC Registration MO-220, Variation VHHD-6, Issue K, June 2006.
Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.
supertex.com/packaging.html.)
Doc.# DSFP-HV528
NR042808
8
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