SMM205NR04_技术文档

SMM205

Preliminary Information¹(See Last Page)

Dual Channel Supply Voltage Marginer and Active DC Output Controller

FEATURES & APPLICATIONS

INTRODUCTION

• Extremely accurate (±0.1%) Active

DC Output Control (ADOC)

The SMM205 actively controls the output voltage level

of two DC/DC converters that use a Trim or VADJ/FB

pin to adjust the output. An Active DC Output Control

(ADOC) feature is used during normal operation to

maintain extremely accurate settings of supply

voltages and, during system test, to control margining

of the supplies using I²C commands. Total accuracy

with a ±0.1% external reference is ±0.2%, and ±0.5%

using the internal reference. The device can margin

supplies with either positive or negative trim pin control

within a range of 0.3V to VDD. The SMM105 supply

can be from 12V, 8V, 5V or 3.3V to as low as 2.7V to

accommodate any intermediate bus supply.

• ADOC Automatically adjusts supply output

voltage level under all load conditions

• Capable of margining supplies with trim inputs

using either positive or negative trim pin control

• Wide Margin/ADOC range from 0.3V to VDD

• Uses either an internal or external VREF

• Operates from any intermediate bus supply

from 8V to 15V and from 2.7V to 5.5V

• Programmable START and READY pins

• Two programmable general purpose monitor

sensors – UV and OV with FAULT Output Flag

• General Purpose 1k EEPROM with Write Protect

• I²C 2-wire serial bus for programming

configuration and monitoring status.

The voltage settings (margin high/low and nominal)

are programmed into nonvolatile memory through the

industry standard I²C 2-wire data bus. The I²C bus is

also used to enable margin high, margin low, ADOC or

normal operation. When margining, the SMM205

checks the voltage output of the converter and make

adjustments to the trim pin via a feedback loop to bring

the voltage to the margin setting. A margining status

register is set to indicate that the system is ready for

test. The SMM205 ADOC continues to monitor and

adjust the channel output at the specified level.

• 28 lead QFN package

Applications

• In-system test and control of Point-of-Load

(POL) Power Supplies for Multi-voltage

Processors, DSPs and ASICs

• Enterprise and edge routers, servers, Storage

Area Networks

SIMPLIFIED APPLICATIONS DRAWING

6V to 15V

2.7V to 5.5V

Intermediate

Bus Voltage

(IBA

WP#

Vin

FILT_CAP

V+

V1

SDA

SCL

A0

DC/DC

I²C

V–

On/Off

TRIM_CAPA

TRIM_CAPB

GND

BUS

Trim

A1

A2

Processor

VDD_CAP

TRIMA

VMA

SMM205

Vin

V+

V2

UV

OV

COMP1

VREF_CNTL

External or

DC/DC

Internal

VREF

V–

Trim

On/Off

TRIMB

READY

START

VMB

COMP2

Figure 1 – Applications Schematic showing the SMM205 ADOC actively control the DC output level of 2

DC/DC Converters as well as provide margin control. The SMM205 can operate over a wide supply range

Note: This is an applications example only. Some pins, components and values are not shown.

www.summitmicro.com

2069 1.4 6/23/03

1

SMM205

Preliminary Information

Figure 2 – Example Power Supply Margining using the SMM205. The waveform on the left is margin nominal

to high from 2.5V to 2.8V and 1.8V to 2.1V. The waveform on the right is margin nominal to low from 2.5V to

2.2V and 1.8V to 1.5V. The bottom waveform is the READY signal indicating when margining is complete.

GENERAL DESCRIPTION

The SMM205 is capable of controlling and margining

the DC output voltage of LDOs or DC/DC converters

that use a trim/adjust pin and to automatically change

the level using a unique Active DC Output Control

(ADOC). The ADOC function is programmable over a

standard 2-wire I²C serial data interface and can be

used to set the nominal DC output voltage as well as

the margin high and low settings. The part actively

controls the programmed set levels to maintain tight

control over load variations and voltage drops at the

point of load. The margin range will vary depending on

the supply manufacturer and model but the normal

range is 10% adjustment around the nominal output

setting. However, the SMM205 has the capability to

margin from VREF_CNTL to VDD.

When the SMM205 receives the command to margin

the Active DC Output Control will adjust the supply to

the selected margin voltage. Once the supply has

reached its margined set point the Ready bit in the

status register will set and the READY pin will go

active. If Active DC Control is disabled a margined

supply can return to its nominal voltage by writing to

the margin command register.

In order to obtain maximum accuracy the SMM205

requires an external voltage reference. An external

reference with ±0.1% accuracy will enable an overall

±0.2% accuracy for the device. A configuration option

also exists so that an internal voltage reference can be

used, but with less accuracy. Total accuracy using the

internal reference is ±0.5%. The SMM205 can be

powered from either a 12V or 8V input via an internal

regulator, or the VDD input (Figure 3).

The user can set the desired voltage settings

(nominal, margin high and margin low) into the EE

memory array for the device. Then, volatile registers

are used to select one of these settings. The registers

are accessed over the I²C bus.

The SMM205 has two additional input pins and one

additional output pin. The input pins, COMP1 and

COMP2, are high impedance inputs, each connected

In normal operation, Active DC Output Control is set to

adjust the nominal output voltage of one or two

trimmed converters. Typical converters have ±2%

accuracy ratings for their output voltage. Using the

Active DC Output Control feature of the SMM205 can

increase the accuracy to ±0.2%. This high accuracy

control of a converter output voltage is extremely

important in low voltage applications where deviations

in power supply voltage can result in lower system

performance. Active DC Output Control may be

turned off by de-selecting the function in the Control

Select Register. Active DC Output Control can also be

used for margining a supply during system test.

to

a

comparator and compared against the

VREF_CNTL input or the internal reference (VREF).

Each comparator can be independently programmed

to monitor for UV or OV. When either of the COMP1

or COMP2 inputs are in fault the open-drain FAULT#

output will be pulled low. A configuration option exists

to disable the FAULT# output during margining.

Programming of the SMM205 is performed over the

industry standard I²C 2-wire serial data interface. A

status register is available to read the state of the part,

and a Write Protect (WP#) pin is available to prevent

writing to the configuration registers and EE memory.

Summit Microelectronics, Inc

2069 1.4 6/23/03

2

SMM205

Preliminary Information

INTERNAL BLOCK DIAGRAM

9

VREF_CNTL

MUX

5

CMP

READY

VREF

11

FAULT#

OUTPUT

CONTROL

19

12

COMP1

COMP2

20

18

CMP

TRIM

TRIMA

DRIVE A

TRIM_CAPA

16

15

TRIMB

SDA 28

TRIM

DRIVE B

TRIM_CAPB

SCL

A0

1

6

4

2

3

8

INPUT VOLTAGE

SENSING AND

SIGNAL

14

17

VMA

VMB

I²C

INTER-

FACE

A1

A2

CONDITIONING

EE

CONFIGURATION

REGISTERS

START

WP#

AND MEMORY

21

23

VDD

SUPPLY

ARBITRATION

VDD_CAP

10 FILT_CAP

GND

3.6V / 5V

22

12VIN

7

REGULATOR

Figure 3 –Block Diagram.

PACKAGE AND PIN CONFIGURATION

28 Pin QFN

Top View

Pin 1

28

26 25

23 22

24

27

1

21

20

19

SCL

VDD

2

3

A2

TRIMA

START

COMP1

SMM205

4

18

17

16

15

A1

TRIM_CAPA

VMB

5

READY

6

A0

TRIMB

7

GND

TRIM_CAPB

13 14

12

8

9

10 11

Summit Microelectronics, Inc

2069 1.4 6/23/03

3

SMM205

Preliminary Information

PIN DESCRIPTIONS

Pin Name

Pin Description

Number

Type

DATA SDA

I²C Bi-directional data line.

I²C clock input.

28

1

CLK

SCL

A2

I

2

The address pins are biased either to VDD_CAP or GND. When

communicating with the SMM205 over the 2-wire bus these pins provide a

mechanism for assigning a unique bus address.

A1

4

A0

6

Write Protect active low input. When asserted writes to the configuration

registers and general purpose EE are not allowed.

I

WP#

8

CAP

External capacitor input used to filter the VM inputs.

10

FILT_CAP

External capacitor input used for Active Control and margining.

15, 18

TRIM_CAPx

Output voltage used to control and/or margin converter voltages. Connect

to the converter trim input.

O

I

16, 20

14, 17

TRIMx

VMx

Voltage monitor input. Connect to the DC/DC converter positive sense line

or its +Vout pin.

Voltage reference input used for DC output control and margining.

VREF_CNTL can be programmed to output the internal 1.25V reference

voltage. Pin should be left open if using VREF internal.

I

9

21

7

VREF_CNTL

VDD

PWR

GND

Power supply of the part.

Ground of the part. The SMM205 ground pin should be connected to the

ground of the device under control or to a star point ground. PCB layout

should take into consideration ground drops.

GND

12V power supply input internally regulated to either 3.6V or 5.5V. When

using the 3.6V internal regulator option the voltage input can be as low as

8V. It can be as high as 15V using the 5.5V internal regulator.

PWR

I

22

3

12VIN

Programmable active high/low input. The START input is used solely for

enabling Active Control and/or margining.

START

Programmable active high/low open drain output indicates that VM is at its

set point. When programmed as an active high output READY can also be

used as an input. When pulled low it will latch the state of the comparator

inputs.

I/O

5

READY

CAP

I

External capacitor input used to filter the internal supply rail.

23

19

VDD_CAP

COMP1

COMP1 and COMP2 are high impedance inputs, each connected internally

to a comparator and compared against the VREF_CNTL input. Each

comparator can be independently programmed to monitor for UV or OV.

The monitor level is set externally with a resistive voltage divider.

I

12

COMP2

When either of the COMP1 or COMP2 inputs are in fault the open-drain

FAULT# output will be pulled low. A configuration option exists to disable

the FAULT# output while the device is margining.

O

11

FAULT#

NC

No Connect. Leave floating; do not connect anything to the NC pins.

13, 24-27

Summit Microelectronics, Inc

2069 1.4 6/23/03

4

SMM205

Preliminary Information

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Temperature Under Bias ......................–55°C to 125°C

Temperature Range (Industrial) .......... –40°C to +85°C

Storage Temperature............................–65°C to 150°C

(Commercial)............ –5°C to +70°C

VDD Supply Voltage.................................. 2.7V to 5.5V

12VIN Supply Voltage (1)........................ 8.0V to 14.0V

VIN.............................................................GND to VDD

VOUT.......................................................GND to 15.0V

Package Thermal Resistance (θ_JA)

Terminal Voltage with Respect to GND:

VDD Supply Voltage .........................–0.3V to 6.0V

12VIN Supply Voltage.....................–0.3V to 15.0V

All Others ...............................–0.3V to V_DD+ 0.7V

Output Short Circuit Current ............................... 100mA

28 Lead QFN………………………………….…80^oC/W

Lead Solder Temperature (10 secs)……………….300°C

Junction Temperature.........................…….....…...150°C

ESD Rating per JEDEC……………………..……..2000V

Moisture Classification Level 1 (MSL 1) per J-STD- 020

Latch-Up testing per JEDEC………..……......…±100mA

Note (1) — Range depends on internal regulator set to 3.6V or 5.5V,

see 12VIN specification below.

Note - The device is not guaranteed to function outside its operating

rating. Stresses listed under Absolute Maximum Ratings may cause

permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions

outside those listed in the operational sections of the specification is

not implied. Exposure to any absolute maximum rating for extended

periods may affect device performance and reliability. Devices are

ESD sensitive. Handling precautions are recommended.

DC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol

VDD

Parameter

Supply Voltage

Notes

Min.

Typ.

Max

Unit

V

2.7

3.3

5.5

Internally regulated to 5.5V

Internally regulated to 3.6V

VM pin

10

6

15

14

VDD

5

V

12VIN

Supply Voltage

VM

Positive Sense Voltage

–0.3

V

Power Supply Current from

VDD

I_DD

All TRIM pins and 12VIN floating

3

mA

Power Supply Current from

12VIN

I_12VIN

I_TRIM

V_ADOC

V_IH

All TRIM pins and VDD floating

5

mA

TRIM output current

through 100Ω to 1.0V

Margin Control/ADOC

Range

TRIM Sourcing Max Current

TRIM Sinking Max Current

Depends on Trim range of DC-

DC Converter

1.5

mA

VREF_CNTL

VDD

V

VDD = 2.7V

0.9xVDD

0.7xVDD

VDD

Input High Voltage

VDD = 5.0V

VDD = 2.7V

0.1xVDD

0.3xVDD

V_IL

Input Low Voltage

VDD = 5.0V

Programmable Open Drain

Output (READY)

V_OL

ISINK = TBD

0.2

10

V

OV/UV

V_HYST

Monitor Voltage Range

COMP1 and COMP2 pins

COMP1 and COMP2 pins,

V_TH– V_TL— Note 1

–0.3

3

VDD

Base DC Hysteresis

mV

Note 1 – The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting

Threshold Low from Threshold High (V_TH– V_TL) while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual

DC Hysteresis is derived from the equation: (V_IN/V_REF)(Base Hysteresis). For example, if V_IN= 2.5V and V_REF= 1.25V then Actual DC Hysteresis =

(2.5V/1.25V) (0.003V) = 6mV.

Summit Microelectronics, Inc

2069 1.4 6/23/03

5

SMM205

Preliminary Information

DC OPERATING CHARACTERISTICS (CONTINUED)

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol

Parameter

1.25VREF Output

Voltage

Notes

Min.

Typ.

Max

Unit

VREF

1.24

1.25

1.26

V

R

_LOAD= 2KΩ to GND

External V_REFVoltage

V_{REF_CNTL}

0.25

-0.2

-0.5

VDD

+0.2

+0.5

V

%

Range

External VREF=1.25V, ±0.1%

ADOC trimmed to internal VREF

ADOC_ACCADOC/Margin Accuracy

AC OPERATING CHARACTERISTICS

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

Symbol

Parameter

Notes

Min.

Typ.

Max

Unit

Active DC Control

sampling period

Update period for Active DC

Control

t_{DC_CONTROl}

1.7

ms

+ 10% change in voltage with

0.1% ripple

Settling Time

100

20

ms

T_settling

Fast Margin, nom to high,

TRIM_CAP=1µF

T_TRIM

Trim Speed

Slow Margin, nom to high,

TRIM_CAP=1µF

200

Summit Microelectronics, Inc

2069 1.4 6/23/03

6

SMM205

Preliminary Information

I²C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz

Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram.

Conditions

100kHz

Min Typ

400kHz

Min Typ

Symbol Description

Max

Max Units

f_SCL

SCL Clock Frequency

0

100

0

400

KHz

t_LOW

t_HIGH

Clock Low Period

Clock High Period

4.7

4.0

1.3

0.6

µs

Before New Transmission

- Note 1/

t_BUF

Bus Free Time

4.7

1.3

µs

t_SU:STA

t_HD:STA

t_SU:STO

Start Condition Setup Time

Start Condition Hold Time

Stop Condition Setup Time

4.7

4.0

4.7

0.6

µs

SCL low to valid

SDA (cycle n)

t_AA

t_DH

Clock Edge to Data Valid

Data Output Hold Time

0.2

3.5

0.2

0.9

µs

SCL low (cycle n+1)

µs

to SDA change

Note 1/

t_R

t_F

t_SU:DAT

t_HD:DAT

TI

SCL and SDA Rise Time

SCL and SDA Fall Time

Data In Setup Time

Data In Hold Time

Noise Filter SCL and SDA

Write Cycle Time

1000

300

1000

300

ns

ms

250

0

150

0

Noise suppression

100

t_WR

5

Note: 1/ - Guaranteed by Design.

TIMING DIAGRAMS

t_{WR (For W rite Operation Only)}

t_HIGH

t_LOW

t_R

t_F

SCL

t_BUF

t_HD:DAT

t_SU:DAT

t_SU:SDA

t_SU:STO

t_HD:SDA

SDA

(IN)

t_AA

t_DH

SDA

(OUT)

Figure 4 . Basic I²C Serial Interface Timing

Summit Microelectronics, Inc

2069 1.4 6/23/03

7

SMM205

Preliminary Information

APPLICATIONS INFORMATION

DEVICE OPERATION

POWER SUPPLY

The voltage on the TRIM_CAP pins is buffered and

applied to the TRIM pin. The voltage adjustments on

the TRIM pin cause a slight ripple of less than 1mV on

the power supply voltage. The amplitude of this ripple

is a function of the TRIM_CAP capacitor and the trim

gain of the converter. Calculation of the TRIM_CAP

capacitor to achieve a desired minimum ripple is

detailed in Application Note 37.

The SMM205 can be powered by either an 8V to 15V

input through the 12VIN pin or by a 2.7V to 5.5V input

through the VDD pin. The 12VIN pin feeds an internal

programmable regulator that internally generates

either 5.5V or 3.6V. The internal regulator must be set

to 3.6V if using an 8V supply. A voltage arbitration

circuit allows the device to be powered by the highest

voltage from either the regulator output or the VDD

input. This voltage arbitration circuit continuously

checks for these voltages to determine which will

power the SMM205. The resultant internal power

supply rail is connected to the VDD_CAP pin that

allows both filtering and hold-up of the internal power

supply.

The device can be programmed to either enable or

disable the Active DC Control function.

When

disabled or not active the TRIM pin on the SMM205 is

a high impedance input. The voltage on the TRIM pin

is buffered and applied to the TRIM_CAP pin charging

the capacitor. This allows a smooth transition from the

converter’s nominal voltage to the SMM205 controlling

that voltage to the Active DC Control nominal setting.

VOLTAGE REFERENCE

The SMM205 can operate using either an internal or

external voltage reference, VREF. The internal VREF

is set to 1.25V. Total accuracy with a ±0.1% external

reference is ±0.2%, and ±0.5% using the internal

reference.

There is a programmable Speed-Up Convergence

option. As the name implies, this option decreases the

time required to bring a supply voltage from the

converter’s nominal output voltage to the Active DC

Output Control nominal voltage setting.

MODES OF OPERATION

MONITORING

The SMM205 has one key feature: Active DC Output

Control (ADOC), and two basic modes of operation:

UV/OV monitoring mode and supply margining mode.

A detailed description of each feature and mode

follows.

The SMM205 monitors the COMP1 and COMP2

inputs as well as the VM pins. COMP1 and COMP2

are high impedance inputs, each connected internally

to

a

comparator and compared against the

VREF_CNTL input.

Each comparator can be

ACTIVE DC OUTPUT CONTROL (ADOC)

independently programmed to monitor for either UV or

OV. The monitor level is set externally with a resistive

voltage divider. The part can be programmed to

trigger the FAULT# pin when either COMPx

comparator has exceeded the UV or OV range. The

READY and FAULT# outputs of the SMM205 are

active as long as the triggering limit remains in a fault

condition. The READY pin is programmable active

high/low open drain output indicates that VM is at its

set point. When programmed as an active high output

READY can also be used as an input. When pulled

low it will latch the state of the comparator inputs.

When either of the COMP1 or COMP2 inputs are in

fault the open-drain FAULT# output will be pulled low.

A configuration option exists to disable the FAULT#

output while the device is in margining mode.

The SMM205 can control the DC output voltage of

bricks or DC/DC converters that have a trim pin. The

TRIM pin on the SMM205 is connected to the trim

input pin on the power supply converter. A sense line

from the channel’s point-of-load connects to the VM

input. The Active DC Control function cycles every

1.7ms making slight adjustments to the voltage on the

TRIM output pin based on the voltage input on the VM

pin. This voltage adjustment allows the SMM205 to

control the output voltage of the power supply

converter to within ±0.2% when using a ±0.1%

external voltage reference.

Summit Microelectronics, Inc

2069 1.4 6/23/03

8

SMM205

Preliminary Information

APPLICATIONS INFORMATION (CONTINUED)

STATUS REGISTER

A status register exists for I²C polling of the status of

the COMP1 and COMP2 inputs. Two bits in this

status register reflect the current state of the inputs (1

= fault, 0 = no fault). Two additional bits show the

state of the inputs latched by one of two events

programmed in the configuration. The first event

option is the FAULT# output going active. The second

event option is the READY pin going low. The READY

pin is an I/O. As an output the READY output pin

goes active when the DC controlled voltages are at

their set point. As an input programmed to active high

it can be pulled low externally and latch the state of

the COMP inputs. This second event option allows

the state of the COMP inputs on multiple devices to be

latched at the same time while a host monitors their

FAULT# outputs.

The margin command registers contain two bits that

decode the commands to margin high, to margin low,

or to control to the nominal setting. Once the SMM205

receives the command to margin the supply voltage it

begins adjusting the supply voltage to move toward

the desired setting. When this voltage setting is

reached a bit is set in the margin status registers and

the READY signal becomes active.

Note: Configuration writes or reads of registers 00_HEX

to 03_HEXshould not be performed while the SMM205 is

margining.

WRITE PROTECTION

Write protection for the SMM205 is located in a volatile

register where the power-on state is defaulted to write

protect. There are separate write protect modes for

the configuration registers and memory. In order to

remove write protection the code 55_HEXis written to the

write protection register. Other codes will also enable

write protection. For example, writing 59_HEXwill allow

writes to the configuration register but not to the

memory, while writing 35_HEXwill allow writes to the

memory but not to the configuration registers. The

SMM205 also features a Write Protect pin (WP#)

which, when asserted, prevents writing to the

configuration registers and EE memory. In addition to

these two forms of write protection there is also a

configuration register lock bit which, once

programmed, does not allow the configuration

registers to be changed.

MARGINING

The SMM205 has two additional Active DC Output

Control voltage settings: margin high and margin low.

The margin high and margin low settings can be as

much as ±10% of the nominal setting depending on

the manufacturer. The SMM205 range can be as

large as VREF_CNTL to VDD. These settings are

stored in the configuration registers and are loaded

into the Active DC Output Control voltage setting by

margin commands issued via the I²C bus. The device

must be enabled for Active DC Output Control in order

to enable margining.

Figure 5 – SMM205 margin example. The nominal setting for channel 1 and 2 is 2.5V and 1.8V. The device

margins the DC/DC converters from nominal to high (2.8V and 2.1) then to nominal, then to low (2.3V and

1.5V), then to nominal, then to channel 1 high and channel 2 low, and then back to nominal. The READY

signals goes low when margining and high when complete.

Summit Microelectronics, Inc

2069 1.4 6/23/03

9

SMM205

Preliminary Information

APPLICATIONS INFORMATION (CONTINUED)

Figure 6 – SMM205 Applications schematic. The accuracy of the external (U4) or internal reference sets the

accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% and ±0.5% with the

internal reference. The 12V supply can go as low as 8V if the internal regulator is set to 3.6V.

Summit Microelectronics, Inc

2069 1.4 6/23/03

10

SMM205

Preliminary Information

APPLICATIONS INFORMATION (CONTINUED)

+12VIN (+10V to +15V)

RTRIM(R3) is calculated as follows:

VTRIMlow=0.3V, Regulator VREF=0.8V

The current through R3 is ITRIM=(0.8-0.3)/RTRIM

(ITRIM)(R4) > 15% of VOUT

C4

C7

0.1uF

0.01uF

C8

RTRIMmax should be < the calculated value

0.1uF

For Example:

If Vout=3.3V, R4=63.4K, 15% of Vout=0.5V

ITRIM=8uA, RTRIM=62.5K

Therefore Rtrim standard 1% value down

from 62.5K

R6 10K

R7 10K

R8 10K

C1 1uF

U3

START

READY

FAULT#

3

5

18

20

14

RTRIM

R3

START

READY

FAULT#

TRIM_CAPA

TRIMA

VOUT

11

VMA

U2 Switching Regulator

17

16

15

R4

RSET1

VMB

TRIMB

R2 10K

R1 10K

1

28

6

SCL

SDA

A0

TRIM_CAPB

+Vin

+Vout

10

SMM205 ^FILT_CAP

4

A1

A2

PGOOD

2

19

12

COMP1

COMP2

VADJ (VREF)

C5

0.02uF

8

R5

D1

WP#

20k

DIODE

START

J1

1

3

5

7

9

2

Gnd

SCL

SDA

MR

4

Gnd3

Rsrv5

6

8

+10V Rsrv8

+5V Rsrv10

10

The SMM205 START pin must be inactive during power-up so

that the TRIM pin is high impedence. Once power is nominal,

the START pin can be active to start margin and ADOC

functions

SMX3200 I2C Programming

Connector 10 pin Header

R1 and R2 need only be

placed once on the I2C bus

Figure 7 – SMM205 Applications schematic for an adjustable switching regulator (Full regulator circuit not

shown).

Summit Microelectronics, Inc

2069 1.4 6/23/03

11

SMM205

Preliminary Information

DEVELOPMENT HARDWARE & SOFTWARE

The end user can obtain the Summit SMX3200

The Windows GUI software will generate the data and

send it in I²C serial bus format so that it can be directly

downloaded to the SMM205 via the programming

Dongle and cable. An example of the connection

interface is shown in Figure 8.

programming

system

for

device

prototype

development. The SMX3200 system consists of a

programming Dongle, cable and Windows^TMGUI

software. It can be ordered on the website or from a

local representative.

The latest revisions of all

software and an application brief describing the

SMX3200 is available from the website

(www.summitmicro.com).

When design prototyping is complete, the software

can generate a HEX data file that should be

transmitted to Summit for approval. Summit will then

assign a unique customer ID to the HEX code and

program production devices before the final electrical

The SMX3200 programming Dongle/cable interfaces

directly between a PC’s parallel port and the target

application. The device is then configured on-screen

via an intuitive graphical user interface employing

drop-down menus.

test operations.

This will ensure proper device

operation in the end application.

Top view of straight 0.1" x 0.1 closed-side

connector. SMX3200 interface cable connector.

D1

Pin 10, Reserved

Pin 8, Reserved

Pin 6, MR#

Pin 9, 5V

Positive

1N4148

Supply

Pin 7, 10V

Pin 5, Reserved

Pin 3, GND

Pin 1, GND

Pin 4, SDA

VDD_CAP

Pin 2, SCL

10

8

9

7

5

3

1

C1

0.1 F

SMM205

6

WP#

4

2

SDA

SCL

GND

Common

Ground

Figure 8– SMX3200 Programmer I²C serial bus connections to program the SMM205. The SMM205 has a

Write Protect pin (WP#) which, when asserted, prevents writing to the configuration registers and EE

memory. In addition, there is a configuration register lock bit which, once programmed, does not allow the

configuration registers to be changed.

Summit Microelectronics, Inc

2069 1.4 6/23/03

12

SMM205

Preliminary Information

I²C PROGRAMMING INFORMATION

SERIAL INTERFACE

WRITE

Access to the configuration registers, general-purpose

memory and command and status registers is carried

out over an industry standard 2-wire serial interface

(I²C). SDA is a bi-directional data line and SCL is a

clock input. Data is clocked in on the rising edge of

SCL and clocked out on the falling edge of SCL. All

data transfers begin with the MSB. During data

transfers SDA must remain stable while SCL is high.

Data is transferred in 8-bit packets with an intervening

clock period in which an Acknowledge is provided by

Writing to the memory or a configuration register is

illustrated in Figures 9, 10, 11, 13, 14 and 16. A Start

condition followed by the address byte is provided by

the host; the SMM205 responds with an Acknowledge;

the host then responds by sending the memory

address pointer or configuration register address

pointer; the SMM205 responds with an acknowledge;

the host then clocks in one byte of data. For memory

and configuration register writes, up to 15 additional

bytes of data can be clocked in by the host to write to

consecutive addresses within the same page. After

the last byte is clocked in and the host receives an

Acknowledge, a Stop condition must be issued to

initiate the nonvolatile write operation.

the device receiving data. The SCL high period (t_HIGH

)

is used for generating Start and Stop conditions that

precede and end most transactions on the serial bus.

A high-to-low transition of SDA while SCL is high is

considered a Start condition, while a low-to-high

transition of SDA while SCL is high is considered a

Stop condition.

READ

The address pointer for the configuration registers,

memory, command and status registers and ADC

registers must be set before data can be read from the

SMM205. This is accomplished by issuing a dummy

write command, which is simply a write command that

is not followed by a Stop condition. The dummy write

command sets the address from which data is read.

After the dummy write command is issued, a Start

command followed by the address byte is sent from

the host. The host then waits for an Acknowledge and

then begins clocking data out of the slave device. The

first byte read is data from the address pointer set

during the dummy write command. Additional bytes

can be clocked out of consecutive addresses with the

host providing an Acknowledge after each byte. After

the data is read from the desired registers, the read

operation is terminated by the host holding SDA high

during the Acknowledge clock cycle and then issuing a

Stop condition. Refer to Figures 12, 15 and 17 for an

illustration of the read sequence.

The interface protocol allows operation of multiple

devices and types of devices on a single bus through

unique device addressing.

The address byte is

comprised of a 4-bit device type identifier (slave

address) and a 3-bit bus address. The remaining bit

indicates either a read or a write operation. Refer to

Table 1 for a description of the address bytes used by

the SMM205.

The device type identifier for the memory array, the

configuration registers and the command and status

registers are accessible with the same slave address.

It can be programmed to any four bit number 0000_BIN

through 1111_BIN

.

The bus address bits, A2, A1 and A0, are hard wired

though pins 2, 4 and 6 (A2, A1 and A0). The bus

address accessed in the address byte of the serial

data stream must match the setting on the SMM205

address pins.

WRITE PROTECTION

The SMM205 powers up into a write protected mode.

Writing a code to the volatile write protection register

(write only) can disable the write protection. The write

protection register is located at address 42_HEX. Writing

to the write protection register is shown in Figure 9.

Writing 0101_BINto bits [7:4] of the write protection

register allows writes to the general-purpose memory

while writing 0101_BINto bits [3:0] allows writes to the

configuration registers. The write protection can be re-

enabled by writing other codes (not 0101_BIN) to the

write protection register.

Summit Microelectronics, Inc

2069 1.4 6/23/03

13

SMM205

Preliminary Information

I²C PROGRAMMING INFORMATION (CONTINUED)

CONFIGURATION REGISTERS

COMMAND AND STATUS REGISTERS

The majority of the configuration registers are grouped

with the general-purpose memory. Writing and reading

the configuration registers is shown in Figures 10, 11

and 12.

Note: Configuration writes or reads of registers 00_HEX

to 03_HEXshould not be performed while the SMM205

is margining.

Writes and reads of the command and status registers

are shown in Figures 16 and 17.

GRAPHICAL USER INTERFACE (GUI)

Device configuration utilizing the Windows based

SMM205 graphical user interface (GUI) is highly

recommended. The software is available from the

Summit website (www.summitmicro.com). Using the

GUI in conjunction with this datasheet and Application

Note 38 simplifies the process of device prototyping

and the interaction of the various functional blocks. A

programming Dongle (SMX3200) is available from

Summit to communicate with the SMM205. The

Dongle connects directly to the parallel port of a PC

and programs the device through a cable using the I²C

bus protocol. See figure 8 and the SMX3200 Data

Sheet.

GENERAL-PURPOSE MEMORY

The 1k-bit general-purpose memory is located at any

slave address. The bus address bits are hard wired

by the address pins A2, A1 and A0. Memory writes

and reads are shown in Figures 13, 14 and 15.

Slave Address Bus Address Register Type

Configuration Registers are located in

00 _HEXthru 45_HEX

ANY

A2 A1 A0

General-Purpose Memory is located in

80 _HEXthru FF_HEX

Table 1 - Address bytes used by the SMM205.

Summit Microelectronics, Inc

2069 1.4 6/23/03

14

SMM205

Preliminary Information

I²C PROGRAMMING INFORMATION (CONTINUED)

S

T

S

T

A

Configuration

Register Address = 42_HEX

R

O

P

Master

Slave

Bus Address

Data = 55_HEX

T

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

W

0

1

0

1

0

1

0

1

0

1

0

1

A

C

K

A

C

K

A

C

K

4_HEX

2_HEX

Write Protection

Register Address

5_HEXUnlocks

Configuration

Registers

General Purpose

EE

Figure 9 – Write Protection Register Write

S

T

A

R

T

S

T

O

P

Configuration

Master

Slave

Bus Address

Data

Register Address

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

W

A

C

K

A

C

K

A

C

K

Figure 10 – Configuration Register Byte Write

S

T

A

R

T

Configuration

Register Address

Master

Bus Address

Data (1)

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

W

Slave

A

C

K

A

C

K

A

C

K

S

T

O

P

Master

Slave

Data (2)

Data (16)

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

C

K

A

C

K

A

C

K

Figure 11 – Configuration Register Page Write

Summit Microelectronics, Inc

2069 1.4 6/23/03

15

SMM205

Preliminary Information

I²C PROGRAMMING INFORMATION (CONTINUED)

S

T

S

T

A

R

T

A

Configuration

Register Address

R

T

Master

Slave

Bus Address

S

A

3

S

A

2

S

A

1

S

A

0

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

A

2

A

1

A

0

W

R

A

C

K

A

C

K

A

C

K

N

A

C

K

S

T

O

P

A

C

K

A

C

K

Master

Slave

Data (1)

Data (n)

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Figure 12 - Configuration Register Read

S

T

A

R

T

S

T

O

P

Configuration

Master

Slave

Bus Address

Data

Register Address

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

W

A

C

K

A

C

K

A

C

K

Figure 13 – General Purpose Memory Byte Write

S

T

A

R

T

Configuration

Register Address

Master

Bus Address

Data (1)

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

W

Slave

A

C

K

A

C

K

A

C

K

S

T

O

P

Master

Slave

Data (2)

Data (16)

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

C

K

A

C

K

A

C

K

Figure 14 - General Purpose Memory Page Write

Summit Microelectronics, Inc

2069 1.4 6/23/03

16

SMM205

Preliminary Information

I²C PROGRAMMING INFORMATION (CONTINUED)

S

T

S

T

A

R

T

A

Configuration

Register Address

R

T

Master

Slave

Bus Address

S

A

3

S

A

2

S

A

1

S

A

0

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

A

2

A

1

A

0

W

R

A

C

K

A

C

K

A

C

K

N

A

C

K

S

T

O

P

A

C

K

A

C

K

Master

Slave

Data (1)

Data (n)

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Figure 15 - General Purpose Memory Read

S

T

A

R

T

S

T

O

P

Command and Status

Master

Slave

Bus Address

Data

Register Address

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

W

A

C

K

A

C

K

A

C

K

Figure 16 – Command and Status Register Write

S

T

A

R

T

S

T

A

Command and Status

R

T

Master

Slave

Bus Address

Register Address

S

A

3

S

A

2

S

A

1

S

A

0

S

A

3

S

A

2

S

A

1

S

A

0

A

2

A

1

A

0

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

A

2

A

1

A

0

W

R

A

C

K

A

C

K

A

C

K

N

A

C

K

S

T

O

P

A

C

K

A

C

K

Master

Slave

Data (1)

Data (n)

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

7

D

6

D

5

D

2

D

1

D

0

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Figure 17 - Command and Status Register Read

Summit Microelectronics, Inc

2069 1.4 6/23/03

17

SMM205

Preliminary Information

DEFAULT CONFIGURATION REGISTER SETTINGS – SMM205F-167

Register

R00

Contents

Function

01

FF

Channel A Nominal Voltage is set to 2.503V (MSB)

R01

R02

02

Channel B Nominal Voltage is set to 1.801V (MSB)

R03

C6

Channel B Nominal Voltage is set to 1.801V (MSB)

Channel A and B ADOC is enabled, Trim polarity is inverse, Fast Convergence,

VREF External, Fault Latched by a Fault Condition

Slave address is 0101

R04

R05

AF

05

No Write Command Required to Activate ADOC, Internal Regulator set to 3.6V,

Fault Output Enabled While Margining, Configuration Registers Unlocked, COMP1

and COMP2 are set to sense UV

R06

28

R08

R0C

R0D

R20

R21

R22

R23

R30

R31

R32

R33

R40

R41

R42

R44

00

12

50

01

C8

02

61

02

45

03

54

00

03

FF

00

Margin Command Bits

Stores VREF_CNTL value set to 1.25

Channel A - Margin High Voltage is set to 2.805V (MSB)

Channel A - Margin High Voltage is set to 2.805V (LSB)

Channel B - Margin High Voltage is set to 2.100V (MSB)

Channel B - Margin High Voltage is set to 2.100V (LSB)

Channel A - Margin Low Voltage is set to 2.201V (MSB)

Channel A - Margin Low Voltage is set to 2.201V (LSB)

Channel B - Margin Low Voltage is set to 1.501V (MSB)

Channel B - Margin Low Voltage is set to 1.501V (LSB)

Margin Command Status Bits

READY and START pin Polarities set to Active High

Write Protect

Fault Status Bits

RC1

The default device ordering number — SMM205F-167 — is programmed as described

above and tested over the commercial temperature range. Application Note 41 contains a

complete description of the Windows GUI and the default settings of each of the 22

individual Configuration Registers.

Summit Microelectronics, Inc

2069 1.4 6/23/03

18

SMM205

Preliminary Information

PACKAGE

28 Pin QFN

Summit Microelectronics, Inc

2069 1.4 6/23/03

19

SMM205

Preliminary Information

PART MARKING

Summit Part Number

SUMMIT

Status Tracking Code

(Blank, MS, ES, 01, 02,...)

(Summit Use)

SMM205N

xx

AYYWW

Annn

Pin 1

Date Code (YYW W )

Lot tracking code (Summit use)

Part Number suffix

(Contains Customer specific ordering requirements)

Product Tracking Code (Summit use)

Drawing not to scale

ORDERING INFORMATION

Summit Part Number

nnn

SMM205

Package

N

Part Number Suffix (see page 18)

Specific requirements are contained in the suffix

such as Commercial or Industrial Temp Range,

Hex code, Hex code revision, etc.

N=28 Lead QFN

NOTICE

NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization.

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,

performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no

license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules

contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or

omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or

malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.

Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:

(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.

is adequately protected under the circumstances.

Revision 1.4 — This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site for data sheet updates

www.summitmicro.com.

2

I C is a trademark of Philips Corporation.

Summit Microelectronics, Inc

2069 1.4 6/23/03

20


型号：	SMM205NR04
厂家：	SUMMIT MICROELECTRONICS, INC.
描述：	Dual Channel Supply Voltage Marginer and Active DC Output Controller 双通道电源电压Marginer和有源直流输出控制器控制器
文件：	总20页 (文件大小：900K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SMM205NR04 [SUMMIT]

相关型号：

UL1042

ZXFV201

ZXFV201N14

ZXFV201N14TA

ZXFV201N14TC

ZXFV202E5

ZXFV202N8

ZXFV203N14

ZXFV301N16(1)

ZXFV302N16

ZXFV4089

ZXFV4089N8