SMH4042AGAKN [SUMMIT]
Distributed Power Hot-Swap Controller for CompactPCI; 分布式电源热插拔控制器的CompactPCI
| 型号： | SMH4042AGAKN |
| 厂家： | 
SUMMIT MICROELECTRONICS, INC. |
| 描述： | Distributed Power Hot-Swap Controller for CompactPCI |
| 文件： | 总28页 (文件大小：1819K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SUMMIT
SMH4042A
MICROELECTRONICS, Inc.
Distributed Power Hot-Swap Controller for CompactPCI
Preliminary
FEATURES
l Flexible Reset Control
w Low Voltage Resets
l Full Voltage Control for Hot Swap Applications
w 15V High Side Driver Generation Allows use
of Low On Resistance N-Channel FETs
w Host Reset Filtering
w Under-Voltage Lockout
w Electronic Circuit Breakers
w Card Insertion Detection
w Soft Reset
l Adjustable Power On Slew Rate
l Suppoprts Mixed Voltage Cards
w Host V Detection
CC
2
l Two Wire I C Serial Data Interface
w Card Voltage Sequencing
2
w 4k-Bit E PROM Memory
FUNCTIONAL BLOCK DIAGRAM
28
BD_SEL1#
13
VCC
BD_SEL2#
12
ISLEW
3
A0
8
1VREF
5
A1
VGATE3
22
10
EEPROM
A2
VGATE5
27
11
19
18
Memory
Array
SCL
SDA
CBI_3
LOCAL_PCI_RST
20
–
+
24
LOCAL_PCI_RST#
9
CBI_5
–
+
1
ASSOCIATE
MEMBER
SGNL_VLD#
16
15
2
CONTROL
+
–
HEALTHY#
DRVREN#
FAULT#
HST_3V_MON
+
–
23
CARD_3V_MON
CARD_5V_MON
+
–
21
25
4
+
–
1.25V
PWR_EN
PCI_RST#
VSEL
7
17
6
GND
14
©SUMMIT MICROELECTRONICS, Inc., 2003
•
1717 Fox Drive, San Jose, CA 95131
•
Phone 408-436-9890
•
FAX 408-436-9897
•
www.summitmicro.com
Characteristics subject to change without notice
2070 9.1 5/27/03
1
SMH4042A
DESCRIPTION
TheSMH4042Aisafullyintegratedhotswapcontrollerthat Theinternal512×8E2PROMcanbeusedasconfiguration
providescompletepowercontrolforadd-incardsrangingin memory for the individual card or as general purpose
use for basic hot swap systems to high availability
CompactPCI systems. It detects proper insertion of the
card and senses valid supply voltage levels at the
backplane. Utilizingexternallowon-resistanceN-channel
MOSFETs, card power is ramped by two high-side driver
outputs that are slew-rate limited at 250V/s.
memory. The proprietary Data Download mode provides
a more direct interface to the E2PROM, simplifying
access by the add-in card’s controller or ASIC.
Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapter and Windows GUI software obtainable from
Summit Microelectronics.
The SMH4042A continuously monitors the host supplies,
the add-in card supplies and the add-in card current. If
the SMH4042A detects the current is higher than the
programmed value it will shut down the MOSFETs and
issue a fault status back to the host.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
VGATE5
nc
CARD_5V_MON
CBI_3
HST_3V_MON
VGATE3
CARD_3V_MON
LOCAL_PCI_RST
SCL
CBI_5
DRVREN#
ISLEW
FAULT#
1VREF
VSEL
PWR_EN
A0
9
LOCAL_PCI_RST#
A1
10
11
12
13
14
SDA
A2
PCI_RST#
SGNL_VLD#
HEALTHY#
BD_SEL2#
BD_SEL1#
GND
2070 PCon
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SUMMIT MICROELECTRONICS, Inc.
2
SMH4042A
PIN DESCRIPTIONS
HST_3V_MON(23)
A0 (8)
Address 0 is not used by the memory array. It can be This input monitors the host 3.3V supply and it is used as
connected to ground or left floating. It must not be a reference for the circuit breaker comparator. If VCC3
connected VCC
.
falls below VTRIP then SGNL_VLD# is de-asserted, the
high side drivers are disabled, and LOCAL_PCI_RST# is
asserted.
A1, A2 (10, 11)
Address inputs 1 and 2 are used to set the two-bit device
address of the memory array. The state of these inputs
ISLEW (3)
will determine the device address for the memory if it is A Diode-connected NFET input. It may be used to adjust
on a two-wire bus with multiple memories with the same the 250V/s default slew rate of the high-side driver
device type identifier.
outputs.
SCL (19)
PCI_RST# (17)
The SCL input is used to clock data into and out of the A TTL level reset input signal from the host interface. A
memoryarray. Inthewritemode,datamustremainstable high to low transition (held low longer than 40ns) will
while SCL is HIGH. In the read mode, data is clocked out initiate a reset sequence. The LOCAL_PCI_RST# and
on the falling edge of SCL.
LOCAL_PCI_RST outputs will be driven active for a
minimum period of tPURST. If the PCI_RST# input is still
held low after tPURST times out the reset outputs will
SDA (18)
TheSDApinisabidirectionalpinusedtotransferdatainto continue to be driven until PCI_RST# is released.
and out of the memory array. Data changing from one
state to the other may occur only when SCL is LOW,
PWR_EN (7)
except when generating START or STOP conditions. A TTL level input that allows the host to enable or disable
SDA is an open-drain output and may be wire-ORed with the power to the individual card. During initial power up
any number of open-drain outputs.
this signal would start in a low state, and then be driven
high during software initialization. If this signal is driven
low then the power supply control outputs will be driven
CARD_3V_MON (21)
This input monitors the card-side 3.3V supply. If the input into the inactive state and the reset signals asserted. In
falls below VTRIP then the HEALTHY# and SGNL_VLD# a “non-High Availability” system this input can be tied
high. The PWR_EN input is also used to reset the
SMH4042A circuit breakers. After an over-current condi-
tion is detected the VGATE outputs can be turned back
on by first taking PWR_EN low then returning it high.
outputs are de-asserted and the reset outputs are driven
active.
CARD_5V_MON (25)
This input monitors the card-side 5V supply. If the input
falls below VTRIP then the HEALTHY# and SGNL_VLD#
VSEL (6)
outputs are de-asserted and the reset outputs are driven A TTL level input used to determine which of the host
active.
powersupplyinputswillbemonitoredforvalidvoltageand
reset generation. This is a static input and the pin should
be tied to VCC or ground through a resistor. VSEL is high
CBI_3 (24)
CBI_3 is the circuit breaker input for the low supply. With for 3.3V power. VSEL is low for 5V or mixed mode power.
a series resistor placed in the supply path between VCC3
and CBI_3, the circuit breaker will trip whenever the VCC (28)
voltage across the resistor exceeds 50mV.
Thepowersupplyinput. Itismonitoredforpowerintegrity.
If it falls below the 5V sense threshold (VTRIP) and the
VSEL input is low then the SGNL_VLD# and HEALTHY#
signals are de-asserted, the high side drivers disabled,
CBI_5 (1)
CBI_5 is the circuit breaker input for the supply voltage.
With a series resistor placed in the supply path between
andresetoutputsasserted. OnaCompactPCIboardthis
the 5V early power and CBI_5, the circuit breaker will trip
must be connected to early power.
whenever the voltage across the resistor exceeds 50mV.
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
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SMH4042A
GND(14)
LOCAL_PCI_RST#(9)
Powersupplyreturnline. Groundshouldbeappliedatthe
same time as early power.
An open-drain active-low output. It is used to reset the
backendcircuitryontheadd-incard. Itisactivewhenever
the card-side monitor inputs are below their respective
VTRIP levels. It may also be driven low by a low input on
the PCI_RST# pin.
BD_SEL1#, BD_SEL2# (13, 12)
These are active low TTL level inputs with internal pull-
ups to VCC. When pulled low they indicate full board
insertion. On the host side the signals should be directly LOCAL_PCI_RST (20)
tied to ground. In a “High Availability” application these
An open-drain (PFET) active-high output. It operates in
inputs can be the last pins to mate with the backplane.
Alternatively, they can be actively driven by the host, or
beconnectedtoswitchesinterfacedtotheboardejectors,
or any combination. Regardless, both inputs must be low
before the SMH4042A will begin to turn on the backend
voltage.
parallel with LOCAL_PCI_RST#, providing an active high
reset signal which is required by many 8051 style MCUs.
It is active whenever the card-side monitor inputs are
below their respective VTRIP levels. It may also be driven
active by a low input on the PCI_RST# pin.
SGNL_VLD# (16)
DRVREN# (2)
An open-drain, active-low output that indicates card side
power is valid and the internal card side PCI_RST# timer
has timed out.
An open-drain, active-low output that indicates the status
of the 3 volt and 5 volt high side driver outputs (VGATE5
and VGATE3). This signal may also be used as a
switching signal for the 12 volt supply.
VGATE3 (22)
FAULT# (4)
A slew rate limited high side driver output for the 3.3V
externalpowerFETgate. Theoutput-voltageisgenerated
by an on-board charge pump.
An open-drain, active-low output. It will be driven low
whenever an over-current condition is detected. It will be
reset at the same time that the VGATE outputs are turned VGATE5 (27)
backonafteraresetfromthehostonthePWR_ENsignal.
A slew rate limited high side driver output for the 5V
HEALTHY# (15)
externalpowerFETgate. Theoutputvoltageisgenerated
by an on-board charge pump.
An open-drain, active-low output indicating card side
power inputs are above their reset trip levels.
1VREF (5)
This output provides a 1V reference for pre-charging the
bus signal pins. Implementing a simple unity-gain ampli-
fier circuit will allow pre-charging a large number of pins.
RECOMMENDEDOPERATINGCONDITIONS*
ABSOLUTE MAXIMUM RATINGS*
TemperatureUnderBias......................... –55°Cto125°C
StorageTemperature .............................. –65°Cto150°C
LeadSolderTemperature(10secs) ..................... 300°C
TemperatureRange(Industrial)...……....-40°Cto+85°C
(Commercial)...……....-5° C to +70°C
Supply Voltage………………….....….………2.7V to 5.5V
Package Thermal Resistance (θ JA)
Terminal Voltage with Respect to GND:
CARD_3V_MON,CARD_5V_MON,
28 Lead SOIC/SSOP...…………………………80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
HST_3V_MON,SGNL_VLD#,HEALTHY#,
LOCAL_PCI_RET#,V ........................................ 7V
CC
VGATE3,VGATE5,DRVREN# .................. 16V
RELIABILITYCHARACTERISTICS
DataRetention……………………………..…..100Years
Endurance……………………….……….100,000Cycles
RESET ............................................ V + 0.7V
CC
All Others ........................................ V + 0.7V
CC
Junction Temperature..........................................150°C
Note * - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is
not implied. Exposure to any absolute maximum rating for extended
ESDRatingperJEDEC……………………………..2000V
Latch-Up testing per JEDEC………………......+/- 100mA
periods may affect device performance and reliability.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
4
SMH4042A
DCOPERATINGCHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to GND)
Symbol
Parameter
Supply voltage
Conditions (2)
Min.
Typ.
Max. Units
V
CC
(1)
1
V
I
Operating
Writing
500
3
µA
mA
V
CC1
Power Supply Current
I
CC2
V 5 A
CC
4.250
4.500
2.57
2.72
2.87
3.00
4.375
4.625
2.65
2.80
2.95
3.10
4.500
4.750
2.72
2.87
3.00
3.17
V 5 B
CC
V
HST_3V_MON G
HST_3V_MON H
HST_3V_MON K
HST_3V_MON L
CARD_5V_MON M
CARD_5V_MON N
V
V
V
V
V
(2) Threshold Levels
TRIP
V 5 + 50mV
CC
V
V 5 – 50mV
CC
V
HST_3V_MON +
50mV
CARD_3V_MON M
CARD_3V_MON N
V
V
HST_3V_MON –
50mV
V
Trip Point Hysteresis
7
mV
µA
µA
V
TRHYST
I
LI
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
LOCAL_PCI_RST# Low
RESET High
2
I
LO
10
0.8
V
IL
–0.1
2
V
IH
V
CC
+ 1V
V
V
OL
V
= 5.0V, I = 2.1mA
OL
0.4
V
CC
V
OH
V
I
= 5.0V, I = –400µA
OH
2.4
V
CC
V
OLRS
= 3.2mA
= –800µA
= 5µA
0.4
V
OL
V
OHRS
I
OH
V – 0.75V
CC
V
V
OHVG3
I
OH
12
13
13
14
15
15
V
VGATE3 High
V
OHVG5
I
OH
= 5µA
V
VGATE5 High
Reference Output Voltage No Load
V
0.95
40
1.00
50
1.05
60
V
REF
V
Circuit Breaker Trip Voltage (3)
mV
CB
2037 Elect Table 2.0
Notes:
(1) The SMH4042A will drive the Reset outputs and voltage control signals throughout the operating range of 1V to 5.5V. The balance
of the logic will not be guaranteed operational unless VCC is greater than 2.7V.
(2) A, B,G, H, K. L, M, & N refer to the Part Number Suffix.
(3) For TA = –10ºC to 85ºC.
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
5
SMH4042A
DEVICE OPERATION
andgroundorbyinjectingcurrentintotheISLEWinput. All
circuitry on the card is held in a reset condition until the 5V
(or 3.3V) supply is stable and the reset interval timer has
timed out the 150ms reset time. At this point, the reset
signals are de-asserted, and proper operation of the card
commences. See Figure 1, Table 1, and Flow Chart 1.
Power-UpSequence
TheSMH4042Aisanintegratedpowercontrollerforanyhot
swappable add-in card. It provides all the signals and
control functions to be compatible with CompactPCI Hot
Swap requirements for basic hot swap systems, full hot
swap boards, and high availability systems.
The SMH4042A will monitor the card’s backend voltages.
Once they are at or above the card VTRIP levels the
SMH4042A will drive the HEALTHY# output.
Insertion Process
As the add-in board is inserted into the backplane,
physical connections are made with the chassis in order
to properly discharge any voltage potentials to ground.
The board will first contact the long pins on the backplane
that provide early power (5V, 3.3V and ground). Depend-
ing upon the board configuration, early power should be
routedtotheVCC pinoftheSMH4042A. Assoonaspower
isappliedtheSMH4042Awillasserttheresetoutputstothe
backend circuits, turn off the VGATE3 and VGATE5
outputs (disabling the external power FETs) and assert
1VREF. Thissignalcanbeusedtopre-chargetheI/Opins
before they begin to mate with the bus signals. The open
collector HEALTHY# output will be de-asserted. It should
be actively pulled high by an external pull-up resistor
(minimum 10kΩ).
Card Removal Process
The card removal process operates in the opposite
sequence. For non-high-availability cards the action of
card removal disconnects the BD_SEL# (short pins) from
ground and the SMH4042A will instantly shutdown the
VGATE outputs, change the HEALTHY# status, and
assert the LOCAL_PCI_RST# output.
Because connectors to the host backplane employ stag-
geredpins,powerwillstillbeappliedtotheSMH4042Aand
the I/O interface circuits. The LOCAL_PCI_RST# signal
will place the interface circuits into a high impedance
condition. The pre-charge voltage will be applied to the
I/Os enabling a graceful disengagement from the active
bus. Once the I/O pins are free of the backplane, power
canberemovedfromtheSMH4042Aandotherearlypower
devices by releasing the long pins.
The next pins to mate are the I/Os, and the balance of the
power pins if they are not already mated. The I/Os will
have been pre-charged by the 1VREF output.
The BD_SEL# pins are the last inputs to be driven to their
true state. In most systems these will most likely be
driven to ground when the short pins are mated. This
would indicate the card is fully inserted and the power-up
sequence can begin. If, however, the design is based on
high availability requirements, the two pins can be ac-
tively driven by the host or combined with a switch input
indicating the ejector handles are fully engaged.
The removal process is slightly different for a high-
availability system. As the ejector handle is rotated the
ejectorswitchwillopen, causingachangeofstatethatwill
activate the ENUM# signal to the host. In response to this
notification the host will de-assert a hardware controlled
BD_SEL# signal. This action will turn on an indicator LED
onthecard,notifyingtheoperatoritisnowsafetoproceed
withtheremovalofthecard. Thesequencewillthenfollow
that outlined for the non-high-availability removal pro-
cess.
Sequencing
Once the proper card insertion has been assured the
SMH4042A will check the status of the Power Enable
signalfromthehost. Thisinputcanbeusedtopowerdown
individual cards on the bus via software control. It must
by held high in order for the SMH4042A to enable power
sequencing to the card.
Power Configurations
The SMH4042A can be used in 5V-only, 3.3V-only and
mixed voltage systems. For systems with a single power
supply, connect VCC and HST_3V_MON together to the
bus power line. Also connect CARD_3V_MON and
CARD_5V_MONtogethertothecardsidepower. Nowthe
state of VSEL determines the reset level that will be used
Whentheseconditionshavebeenmet,theSMH4042Awill
drive the VGATE3 and VGATE5 outputs to turn on the
external 3 volt and 5 volt power FETs. The slew rate of
these outputs is controlled to a slew rate of 250V/s.
Different slew rates can be accommodated by either
addinganadditionalcapacitorbetweentheMOSFETgate
to signal valid power. For 3.3V systems tie VSEL to VCC
for 5V systems tie VSEL to ground.
,
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
6
SMH4042A
V
V
&
TRIP
CC
HST_3V_MON
V
RVALID
LOCAL_PCI_RST#
RESET
t
HSE
BD_SEL1# &
BD_SEL2#
V
OHVG
VGATE3 &
VGATE5
t
SLEW
DRVREN#
CARD_3V_MON &
CARD_5V_MON
V
TRIP
t
PURST
HEALTHY#
SGNL_VLD#
2070 Fig01
Figure 1. Card Insertion Timing Diagram
Symbol
Description
Min.
Typ.
1
Max.
5
Units
µs
t
V
to Power Down Delay, Host Voltage Input
to Reset Output Delay, Card Voltage Input
TRIP
VTPD
TRIP
t
VTR
V
1
5
µs
t
PCI_RST# to LOCAL_PCI_RST#
Local Reset Output Valid
0.1
1
µs
PRLPR
V
1
V
RVALID
t
Slew Rate
250
200
200
40
V/s
ms
ms
ns
SLEW
t
HSE
BD_SEL# to Power On Delay, BD_SEL Noise Filter
Reset Timeout
100
100
150
150
t
PURST
t
Glitch Reject Pulse Width
GLITCH
t
Over-Current to Fault#
1
1
µs
OCF
t
Over-Current to VGATE Off
Circuit Breaker Time Constant, Power up
Circuit Breaker Time Constant, Operating
µs
OCVG
4
µs
t
CBTC
16
µs
2037 Table01 2.0
Table 1. Card Insertion Timing
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
7
SMH4042A
VCC ≥ 1V
Monitor
VCC
LOW
&
HOST_3V_MON
Input Level
Assert Outputs
LOCAL_PCI_RST &
LOCAL_PCI_RST#
OK
Turn On Signals
DRVREN#,
VGATE3 &
VGATE5
Shut Off Signals
DRVREN#,
HEALTHY#,
SGNL_VLD#,
VGATE3 &
VGATE5
Monitor
CARD_3V_MON &
CARD_3V_MON:
≥ VTRIP?
NO
Monitor
BD_SEL1# &
BD_SEL2#
For Insertion
HIGH
YES
LOW
Turn On
HEALTHY#
Start Timer
tPURST
Monitor
VSEL
LOW
Input Level
HIGH
NO
tPURST
Timeout?
YES
Monitor
HOST_3V_MON
Input Level
LOW
OK
NO
PCI_RST
Released?
YES
Release
Resets
Turn On
SGNL_VLD
2070 Flow01
Flow Chart 1. Sequence Diagram
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SUMMIT MICROELECTRONICS, Inc.
8
SMH4042A
MONITORING POWER SUPPLY HEALTH
MONITORINPUTS
VCC vs. HST_3V_MON
The VCC input is the supply input and in a CompactPCI
application this pin must connect to an early power pin on
the host connector. The HST_3V_MON input is strictly
a voltage monitoring input, it is not a supply input. The
operating supply voltage range on the VCC pin is 2.7V to
5.5V, but it will only monitor a 5V supply. This is not an
issuewithadualsupplyapplication. Butinasinglesupply
application these two pins must be shorted and VSEL
conditioned.
The SMH4042A has a total of six comparators that are
usedtomonitorthehealthofthehostplatformsuppliesand
thecard-side(backend)voltages. Inhotswapapplications
each supply going to the backend logic needs to be
monitored at three points.
The first point is at the source on the host connector, VCC
and HST_3V_MON. If this voltage is not within specifi-
cation, then the down stream sequencing of powering-on
the backend logic will not proceed.
The next stage (the CBI inputs) is one step closer to the
backend logic to monitor the current flowing into the
backend logic. This can not exceed the specification;
however, If it does, then the SMH4042A must turn off the
source to the backend logic.
Programmable VTRIP Thresholds
The host voltage monitors and the backend voltage
monitors are programmable (by the factory) and provide
anumberofoptionstotheenduser. TheVCCmonitorVTRIP
level can be selected for either a 5% or 10% supply with
The CARD_5V_MON and CARD_3V_MON inputs are default values of 4.25V or 4.625V. The HST_3V_MON
used to sense the actual voltage level in the backend VTRIP levelcanbeprogrammedto2.65V, 2.8V, 2.95Vand
logic. If either comparator detects a low voltage condition 3.1V.
the backend logic will be placed in a reset condition
The CARD_5V_MON and CARD_3V_MON thresholds
(LOCAL_PCI_RST# asserted), but the VGATE outputs
are set in relation to their corresponding host voltage
will remain active so long as the host voltage and current
monitor thresholds. Their offset can be either +50mV or
sense are valid.
–50mV. This allows the designer to select +50mV if they
want a collapse in the backend voltage to trigger a local
reset condition prior to the host supply collapsing and
powering down the board without warning. Alternatively
they can choose –50mV to trigger a board shutdown
V
TRIP
based on the host power supply falling out of spec.
V
or
CC
HST_3V_MON
Also see Figure 2
t
VTPD
DRVREN# &
SGNL_VLD#
t
CBTC
CBI_3 or
CBI_5
VGATE3 &
VGATE5
FAULT#
V
TRIP
CARD_3V_MON or
CARD_5V_MON
VGATE3 &
VGATE5
t
VTR
HEALTHY# &
LOCAL_PCI_RST#
PCI_RST#
2070 Fig02
2070 Fig03
Figure 2. Loss-of-Voltage Timing Sequence
Figure 3. Circuit Breaker Timing Sequence
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
9
SMH4042A
Over-current Circuit Breaker
RESET CONTROL
The SMH4042A provides a circuit breaker function to
protect against short circuit conditions or exceeding the
supply limits. By placing a series resistor between the
host supply and the CBI pins, the breakers will trip
whenever the voltage drop across the series resistor is
greater than 50mV for more than 16µs.
While in the power sequencing mode, the reset outputs
are the last to be released. When they are released all
conditions of a successful power-up sequence must have
been met:
1) VCC and HST_3V_MON are at or above their respec-
tive VTRIP levels;
The over-current detection circuit was designed to maxi-
mize protection while minimizing false alarms. The most
critical period of time is during the power-on sequence
when the backend circuits are first being energized. If the
card has a faulty component or shorted traces, the time
to shut off should be minimal. However, if the board has
been operational for a long period of time the likelihood of
a catastrophic failure occurring is quite low. Therefore,
theSMH4042Aemploystwodifferentsamplingschemes.
During power-up the device will sample the current every
500ns. If eight consecutive over-current conditions are
detected the VGATE outputs will immediately be shut
down. This provides an effective response time of 4µs.
Duringnormaloperation,aftertheFETshavebeenturned
on, the sampling rate will be adjusted to 2µs, thus
providing an effective response time of 16µs.
2) BD_SEL# inputs are low;
3) CARD_3V_MONandCARD_5V_MONareatorabove
their respective trip levels;
4) PWR_EN is high; and
5) PCI_RST is high.
The PCI-RST# input must be high for the reset outputs to
be released. Assuming all of the conditions listed above
have been met and PCI_RST# is high and tPURST has
expired, a low input of greater than 40ns duration on the
PCI_RST# input will initiate a reset cycle. The duration of
the reset cycle will be determined by the PCI_RST# input.
If PCI_RST# low is shorter than tPURST, the reset outputs
will be driven active for tPURST. If PCI_RST# is longer than
tPURST theresetoutputswillremainactiveuntilPCI_RST#
is released.
Also see Figure 3.
Also see Figure 4.
PCI_RST#
t
PRLPR
t
t
PURST
PURST
LOCAL_PCI_RST#
LOCAL_PCI_RST
2070 Fig04
Figure 4. Host-Initiated Reset Timing
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
10
SMH4042A
BUSINTERFACE
GENERAL DESCRIPTION
Check Table 2 for the value of fSCL. The SDA line must
The I2C bus is a two-way, two-line serial communication be connected to a positive supply by a pull-up resistor
between different integrated circuits. The two lines are: located on the bus. Summit parts have a Schmitt input on
a serial Data line (SDA) and a serial Clock line (SCL). All both lines. See Figure 5 and Table 2 for waveforms and
Summit Microelectronics parts support a 100kHz clock timing on the bus. One bit of Data is transferred during
rate, and some support the alternative 400kHz clock. each Clock pulse. The Data must remain stable when the
Clock is high.
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:SDA
SU:DAT
HD:SDA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2070 Fig05
Figure 5. I2C Timing Diagram
Symbol
Parameter
Conditions
Min. Typ. Max. Units
f
SCL clock frequency
Clock low period
0
100
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ms
SCL
t
4.7
4.0
4.7
4.7
4.0
4.7
0.2
LOW
t
Clock high period
HIGH
t
BUF
Bus free time (1)
Before new transmission
t
Start condition setup time
Start condition hold time
Stop condition setup time
SU:STA
t
HD:STA
t
SU:STO
t
AA
Clock edge to valid output SCL low to valid SDA (cycle n)
3.5
t
DH
Data Out hold time
SCL low (cycle n+1) to SDA change 0.2
t
R
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time
1000
300
t
F
t
250
SU:DAT
t
Data In hold time
0
HD:DAT
TI
Noise filter SCL and SDA
Write cycle time
Noise suppression
100
t
WR
5
Note1-GuaranteedbyDesign
2037 Table02 2.0
Table 2. I2C AC Operating Characteristics
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
11
SMH4042A
Start and Stop Conditions
3
9
1
2
8
SCL
BothDataandClocklinesremainhighwhenthebusisnot
busy. Datatransferbetweendevicesmaybeinitiatedwith
aStartconditiononlywhenSCLandSDAarehigh. Ahigh-
to-lowtransitionoftheDatalinewhiletheClocklineishigh
is defined as a Start condition. A low-to-high transition of
the Data line while the Clock line is high is defined as a
Stop condition. See Figure 6.
SDA
Trans
SDA
Rec
ACK
2070 Fig07
Figure 7. Acknowledge Timing
START
Condition
STOP
Condition
leave the Data line high for a NACK. This will cause the
Summit part to stop sending data, and the Master will
issue a Stop on the clock pulse following the NACK.
SCL
InthecaseofaWritetoaSummitparttheMasterwillsend
aStopontheclockpulseafterthelastAcknowledge. This
will indicate to the Summit part that it should begin its
internal non-volatile write cycle.
SDA In
2070 Fig06
Figure 6. I2C Start and Stop Timing
Basic Read and Write
Protocol
The first byte from a Master is always made up of a seven
bitSlaveaddressandtheRead/Writebit. TheR/Wbittells
the Slave whether the Master is reading data from the bus
or writing data to the bus (1 = Read, 0 = Write). The first
four of the seven address bits are called the Device Type
Identifier(DTI). TheDTIfortheSMH4042Ais1010BIN. The
next two bits are used to select one-of-four possible
devices on the bus. The next bit is the block select bit.
TheSMH4042AwillissueanAcknowledgeafterrecogniz-
ing a Start condition and its DTI.
The protocol defines any device that sends data onto the
bus as a Transmitter, and any device that receives data
as a Receiver. The device controlling data transmission
is called the Master, and the controlled device is called
the Slave. In all cases the Summit Microelectronic
devices are Slave devices, since they never initiate any
data transfers.
Acknowledge
In the Read mode the SMH4042A transmits eight bits of
Data is always transferred in 8-Bit bytes. Acknowledge
(ACK) is used to indicate a successful data transfer. The data, then releases the SDA line, and monitors the line for
Transmitting device will release the bus after transmitting an Acknowledge signal. If an Acknowledge is detected,
and no Stop condition is generated by the Master, the
SMH4042A will continue to transmit data. If an Acknowl-
edgeisnotdetected(NACK),theSMH4042Awillterminate
eight bits. During the ninth clock cycle the Receiver will
pull the SDA line low to Acknowledge that it received the
eight bits of data (See Figure 7). The termination of a
Master Read sequence is indicated by a non-Acknowl- further data transmission. See Figure 9.
edge (NACK), where the Master will leave the Data line
In the Write mode the SMH4042A receives eight bits of
data, then generates an Acknowledge signal. It will
high.
In the case of a Read from a Summit part, when the last continue to generate ACKs until a Stop condition is
byte has been transferred to the Master, the Master will generated by the Master. See Figure 10.
SCL
SDA
3
1
5
x
8
9
1
1
2
0
4
0
6
x
7
x
R/W
ACK
2070 Fig08
Figure 8. Typical Master Address Byte Transmission
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
12
SMH4042A
SequentialRead
Random Address Read
Random address Read operations allow the Master to Sequential Reads can be initiated as either a current
access any memory location in a random fashion. This address Read or a random access Read. The first word
operation involves a two-step process. First, the Master is transmitted as with the other byte read modes (current
issues a write command which includes the start condi- address byte Read or random address byte Read).
tion and the Slave address field (with the R/W bit set to However, the Master now responds with an Acknowl-
edge, indicating that it requires additional data from the
This procedure sets the internal address counter of the SMH4042A. The SMH4042A continues to output data for
SMH4042Atothedesiredaddress. Afterthewordaddress
Write) followed by the address of the word it is to read.
each Acknowledge received. The Master terminates the
Acknowledge is received by the Master, it immediately sequentialReadoperationwithaNACKandissuesaStop
reissues a start condition followed by another Slave condition. During a sequential read operation the internal
addressfieldwiththeR/WbitsettoRead. TheSMH4042A
address counter is automatically incremented with each
will respond with an Acknowledge and then transmit the Acknowledge signal. For read operations all address bits
8 data bits stored at the addressed location. At this point areincremented,allowingtheentirearraytobereadusing
the Master sets SDA high (NACK) and generates a Stop a single Read command. After a count of the last memory
condition. TheSMH4042Adiscontinuesdatatransmission
and reverts to its standby power mode.
address the address counter will roll-over and the
memory will continue to output data.
S
T
N S
A
R
T
R
/
W
A
C
K
A T
C O
K P
Optional
Master
SDA
x x x
x x x x x x x x
x x
x x
R
1 0 1 0
A
C
K
Slave
2070 Fig09
Figure 9. Basic Read
S
T
A
R
T
S
T
O
P
R
/
W
Master
SDA
x x x
x x x x x x x x
x x
x x
1 0 1 0
W
A
C
K
A
C
K
A
C
K
Slave
2070 Fig10
Figure 10. Basic Write
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
13
SMH4042A
MEMORY OPERATION
WRITEOPERATIONS
Write Cycle
In Progress
TheSMH4042AallowstwotypesofWriteoperationstoits
a 512 x 8 array: byte Write and page Write. A byte Write
operation writes a single byte during the nonvolatile Write
period (tWR). The page Write operation allows up to 16
Issue Start
bytes in the same page to be written during tWR
.
Issue Stop
Byte Write
Issue Slave
Address and
R/W = 0
After the slave address is sent (to identify the slave
device, and a Read or Write operation), a second byte is
transmitted which contains the 8 bit address of any one
of the 512 words in the array. Upon receipt of the word
address the SMH4042A responds with an Acknowledge.
Afterreceivingthenextbyteofdata,itagainrespondswith
anAcknowledge. Themasterthenterminatesthetransfer
by generating a Stop condition, at which time the
SMH4042A begins the internal write cycle. The
SMH4042A inputs are disabled while the internal write
cycle is in progress, and the device will not respond to any
requests from the Master.
No
ACK
Returned
Yes
Next
Operation
a Write?
No
Yes
Page Write
Issue Stop
TheSMH4042Aiscapableofa16-bytepageWriteopera-
tion. It is initiated in the same manner as the byte-Write
operation, but, instead of terminating the Write cycle after
the first data word, the Master can transmit up to 15 more
bytesofdata. AfterthereceiptofeachbytetheSMH4042A
will respond with an Acknowledge.
Issue
Address
Proceed
With
Write
Await
Next
Command
TheSMH4042Aautomaticallyincrementstheaddressfor
subsequentdatawords. Afterthereceiptofeachwordthe
low order address bits are internally incremented by one.
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generatingtheStopcondition,theaddresscounterwillroll
2070 Flow02
Flow Chart 2. Polling
READOPERATIONS
over and the previously written data will be overwritten. There are two different read options:
As with the byte-Write operation, all inputs are disabled
during the internal write cycle. Refer to Figure 5 for the
1. Current Address Byte Read
address, Acknowledge and data transfer sequence.
2. Random Address Byte Read
Acknowledge Polling
Current Address Read
When the SMH4042A is performing an internal Write The SMH4042A contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a Read or Write) was to address location n, the next Read
operationitwillignoreanynewStartconditions. Sincethe
device will only return an acknowledge after it accepts the
Start, the part can be continuously queried until an
acknowledge is issued, indicating that the internal write operation would access data from address location n+1
and increment the current address pointer. When the
SMH4042A receives the Slave address field with the R/W
cycle is complete. See Flow Chart 2 for the proper
sequence of operations for polling.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
14
SMH4042A
bit set to “1” it issues an acknowledge and transmits the 8-
Bit word stored at address location n+1. The current
address byte Read operation only accesses a single byte
of data. The Master holds the SDA line high (NACK) and
generates a Stop condition. At this point the SMH4042A
discontinues data transmission.
Sequential Read
Sequential Reads can be initiated as either a current
address Read or a random access Read. The first word
is transmitted as with the other byte Read modes (current
address byte Read or random address byte Read);
however,theMasternowrespondswithanAcknowledge,
indicating that it requires additional data from the
SMH4042A. The SMH4042A continues to output data for
Random Address Read
Random address Read operations allow the Master to each Acknowledge received. The Master terminates the
access any memory location in a random fashion. This sequential Read operation with a NACK and a Stop.
operation involves a two-step process. First, the Master During a sequential Read operation the internal address
issues a Write command which includes the Start condi- counter is automatically incremented with each Acknowl-
tion and the Slave address field (with the R/W bit set to edge signal. For Read operations all address bits are
Write) followed by the address of the word it is to read. incremented, allowing the entire array to be read using a
This procedure sets the internal address counter of the
SMH4042Atothedesiredaddress. Afterthewordaddress
single Read command. After a count of the last memory
addresstheaddresscounterwillrolloverandthememory
acknowledge is received by the Master, the Master will continue to output data.
immediately reissues a Start condition followed by an-
otherSlaveaddressfieldwiththeR/WbitsettoRead. The
SMH4042A will respond with an Acknowledge and then
transmit the 8 data bits stored at the addressed location.
At this point the Master issues a NACK and generates the
Stop condition. The SMH4042A discontinues data trans-
mission and reverts to its standby power mode.
Data Download
TheSMH4042Asupportsaproprietarymodeofoperation
specifically for the Hot Swap environment. After a power
on reset the internal address pointer is reset to 00. The
host or ASIC then only needs to issue a Read command
and then sequentially clock out data starting at address
00.
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
15
SMH4042A
APPLICATIONS
DESIGNCONSIDERATIONSFORACOMPACTPCI
BOARD
Figure 11 is a generic representation of a CompactPCI
board and it illustrates how the SMH4042A is the key
component in the board insertion/removal process. The
illustrations that follow show in more detail how the
various blocks interface to the SMH4042A.
Backend Power Plane
and Logic
P2
Current
sense
resistors
Backend Power
SwitchingCircuits
Precharge
Circuit
V(I/O)
eP
SGNL_VLD
CBI_3
1Vref
VCC5
ENUM#
CBI_5
V(I/O)
5V
HST_3V_MON
3.3V
CARD_3V_MON
CARD_5V_MON
Current
limiting
resistors
V(I/O)
V(I/O)
GND
GND
VGATE3
VGATE5
BD_SEL#
BD_SEL2#
GND
Capacitance
4.7µf each
eP
V(I/O)
GND
GND
GND
LOCAL_PCI_RST#
BD_SEL1#
RESET
3.3V
PCI_RST#
HEALTHY#
GND, PCI_RST#
HEALTHY#
5V
5V
SMH4042A
+12V, -12V
P1
2070 Fig11
Figure 11. Diagram of Typical CompactPCI Board
limitingresistors. Notetheplacementofthesense(shunt)
resistors. They are in series with the power FETs and no
voltage drop will be detected across the resistor until
VGATE is applied to the power FETs. The sense resistor
values are determined by dividing 50mV by the current
specification for that supply.
Power Busses
It is important in the design of the board to ensure the
backend logic is isolated from the power control circuits
and other early power circuits such as FPGAs and the I/
O interface circuits. In Figure 12 the early power busses
for 5V and 3V have series current limiting resistors.
These values should be calculated so as to limit the in-
rush current that will initially charge the capacitive load
of the early power circuits. As the card is inserted further,
the medium length pins engage and short out the current
It should be noted that there is an inherent delay from
VGATE5 turning on to VGATE3 turning on. The typical
delay is illustrated in Figure 13.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
16
SMH4042A
Power Control and Power Plane Isolation
Early
Power
Circuits
I/Os
Pre-Charge
Early
Power
Long Power Pin
VGATE5
CBI_5
Vref
SMH4042A
Medium Power Pin
VCC5
Backend
Power Plane
CARD_5V_MON
CARD_3V_MON
Early
Power
HST_3V_MON
Long Power Pin
CBI_3
VGATE3
Medium Power Pin
Sense
Resistor
Current
Limit
Resistor
Medium Ground Pin
Long Ground Pins
2070 Fig12
Figure 12. Power Control and Power Plane Isolation
15
10
VGATE5
VGATE3
5
0
0
10
20
30
TIME (ms)
40
50
60
Figure 13. Typical Delay: VGATE5 to VGATE3
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
17
SMH4042A
POWERSWITCHINGOPTIONS
rightexamplebothVGATEoutputsarebeingusedsothat
The figures below illustrate four possible methods for
wiringtheSMH4042A. Intheupperleftexamplebothpower the 3.3V slew lags the 5V slew. The two bottom circuits
FETs are connected to a single VGATE output. This illustrate the wiring for single power supply boards. Note
should be used when the design requires the backend how the VSEL pin is biased differently for the two
voltages to be powered-up simultaneously. In the upper applications.
VCC
VCC
CBI_5
CBI_5
10Ω
10Ω
10Ω
47nF
VGATE5
VGATE5
5V 5ꢀ
5A max
5V 5ꢀ
5A max
CARD_5V_MON
CARD_5V_MON
VSEL
VSEL
3.3V 0.3V
7.6A max
3.3V 0.3V
7.6A max
CARD_3V_MON
VGATE3
CARD_3V_MON
VGATE3
10Ω
47nF
47nF
CBI_3
CBI_3
0.0065Ω
HST_3V_MON
0.0065Ω
HST_3V_MON
Dual Voltage, Single Slew Rate Implementation
Dual Voltage, Dual Slew Rate Implementation
VCC
VCC
CBI_5
CBI_5
10Ω
VGATE5
VGATE5
47nF
5V 5ꢀ
5A max
CARD_5V_MON
VSEL
CARD_5V_MON
VSEL
3.3V 0.3V
7.6A max
CARD_3V_MON
VGATE3
CARD_3V_MON
VGATE3
10Ω
47nF
CBI_3
CBI_3
0.0065Ω
HST_3V_MON
HST_3V_MON
Single 5V Implementation
Single 3.3V Implementation
Figure 14. Four Power Switching Implementations
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
18
SMH4042A
using a QuickSwitch® from Quality Semiconductor. This
I/O Buffers
Depending upon the application requirements there are a particular device exhibits very Flat RON characteristics
number of silicon solutions that employ low on-resistance from 0 to 5V. The only drawback is the extra space
CMOS switches. Figure 15 shows one implementation required for the external pull-up resistors.
Early Power
SMH4042A
–
+
1V
REF
LMV321
SGNL_VLD#
OE#
Bn
Bx
An
Ax
IDTQS34XVH245
2070 Fig15
Figure 15. Bus Buffers with External Pull-ups
Figure 16 shows another implementation, but the pull-up edge of the card. The board designer should evaluate
resistor structure is incorporated in the switch. The requirements and design goals to determine the best
circuit also automatically switches the bias voltage out of solution. The bus switches are available from both Texas
thecircuitastheCMOSswitchesareenabled. Apotential Instruments and Pericom Semiconductor.
advantage is the ability to place the interface closer to the
Early Power
SMH4042A
–
+
1V
REF
LMV321
SGNL_VLD#
BIASV
ON#
Bn
Bx
An
Ax
SN74CBT6800
or PI5C6800
2070 Fig16
Figure 16. Bus Buffers with Integrated Pull-ups
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
19
SMH4042A
I/OPre-charge
is accurate and stable prior to the medium length pins
The CompactPCI specs require the add-in board to pre-
charge the board’s I/Os before making contact with bus making contact. The 1VREF output should be the
pins, and sets the pre-charge voltage at 1V 0.1V. The
SMH4042Aprovidesanaccurate1Vreferenceoutputthat
reference input to a unity gain op amp circuit. Figure 17
is a typical implementation utilizing a common op amp.
Early Power
V
5
CC
SMH4042A
Resistor Array
–
+
1V
REF
LMV321
2070 Fig17
Figure 17. I/O Pre-charge Circuit
SPECIAL CONSIDERATIONS
•
“A blue LED, located on the board is illuminated when
The example application shown in Figure 11 shows both
of the BD_SEL inputs being used independently. These
two inputs are effectively ANDed internally and they must
both be low before any sequencing will proceed. In most
design cases the BD_SEL1# connection to an injector
switch is redundant and realistically can be grounded.
it is permissible to extract a board.”
Figure 18 illustrates a possible implementation of the
circuits needed. It should be noted this will require a
status register that works in conjunction with the switch
logic to generate the ENUM# signal. Notice the blue LED
circuit and the active high reset output used to activate a
current boost circuit for the LED. The sequence of
operations is as follows:
The CompactPCI Hot Swap specification does provide a
mechanism for implementing high availability systems
using “Full Hot Swap” boards. This capability entails
integrating the injector/ejector handle, the blue LED and
a board status signal. Section 2.3.2 of the CompactPCI
Hot Swap specification states the following.
• The long pins engage.
•
PowerissuppliedtotheSMH4042A,theLEDand
the BD_SEL pull-up resistor.
•
“A signal (ENUM#) is provided to notify the system
•
V(I/O) is either the early 5V or the early 3V,
host that either a board has been freshly inserted or is
about to be extracted.”
dependent upon the interface operating levels.
•
The LED is illuminated by LOCAL_PCI_RST#
•
“A switch, actuated with the lower ejector handle of
going low.
the board, is used to signal the insertion or impending
extraction of a board.”
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
20
SMH4042A
• The medium length pins contact.
•
BD_SEL#makescontact(optional:thepull-upon
the board indicates to the host the presence of a board.)
The host responds to the ENUM# signal and
drives BD_SEL# low.
•
The ENUM# signal should not be active at this
point.
•
• The board is fully inserted and the injector switch
•
This provides the last gating item to the
is closed.
SMH4042A before it will begin the power-on sequence.
•
ENUM# is driven low.
BD_SEL1#
LOCAL_PCI_RST#
LOCAL_PCI_RST
Power
On
3.9kΩ
10kΩ
R
LIM
SMH4042A
m
BD_SEL2#
ro
oBrad
lPtaf
PCI_RST#
ENUM#
OC
CARD
SWITCH
Board
Status
2070 Fig19
Figure 18. Full Hot Swap Board/Host Interface
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
21
SMH4042A
12V to Backend Logic
SMH4042A
0.1µF
1N4148
DRVREN#
10Ω
330kΩ
4.7kΩ
0.33µF
12V
–12V to Backend Logic
1.5kΩ
1N4148
5V
0.1µF
1N4148
10Ω
330kΩ
4.7kΩ
0.33µF
–12V
2070 Fig19
Figure 19. Using DRVREN# to switch 12V and –12V to the Backend Logic
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
22
SMH4042A
Signal Source
Platform
Early Power
LOCAL_PCI_RST#
1VREF
SMH4042A
SMH4042A
Platform
BD_SEL#
VGATE3 & VGATE5
DRVREN#
SMH4042A
SMH4042A
SMH4042A
HEALTHY#
Platform
Bus Power
Hot Swap Bd.
Backend Power
Short
Pin
Long
Pin
Mid
Length
Pin
Insertion Process
Operational
Removal
2070 Fig 20
Figure 20. Typical CompactPCI Power On Sequence for a Non-High Availability System
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
23
SMH4042A
Signal Source
Platform
Early Power
LOCAL_PCI_RST#
BD_SEL#
SMH4042A
System Host
SMH4042A
VGATE3 & VGATE5
Backend Power
Hot Swap Bd.
SMH4042A
HEALTHY#
PCI_RESET#
System Host
LED
ON
SMH4042A
Hot Swap Bd.
Ejector Switch
Short
Pin
Long
Pin
Mid
Length
Pin
2070 Fig 21
Figure 21. Typical CompactPCI Power On Sequence for a Full Hot Swap Board Using the S39421
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
24
SMH4042A
Although the primary application for the SMH4042A is as of the CompactPCI implementation but they are now
a voltage controller for CompactPCI or VME boards, it is resident on the motherboard. The same circuits shown
versatile enough to be used as a Hot Plug controller on a for switching the voltages on the card can also be used
host PCI card. The functional blocks are similar to those for controlling the slot voltages.
Power Supply
12V
+12V and -12V
DRVREN#
–12V
MOSFETs
5V
VGATE3
+5V and +3V
MOSFETs
VGATE5
SMH4042A
CBI 3
CBI 5
3.3V
PWR_EN
PCI_RST#
FAULT#
CARD_3V_MON
CARD_5V_MON
LOCAL_PCI_RST#
HEALTHY#
[SGNL_VLD]
PCI Bus
BUFFERED PCI BUS
SLOT CONTROL
2070 Fig22
Figure 22. Diagram for a PCI Hot Plug Slot Implementation
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
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SMH4042A
PACKAGES
28 PIN SOIC PACKAGE
0.697 - 0.713
(17.70 - 18.10)
Ref. JEDEC MS-013
0.394 - 0.419
(10.00 - 10.65)
Inches
(Millimeters)
1
0.291 - 0.299
(7.40 - 7.60)
0.093 - 0.104
(2.35 - 2.65)
0.010 - 0.029
´45º
(0.25 - 0.75)
0º to 8º
max.
0.05
0.016 - 0.050
(0.40 - 1.27)
0.009 - 0.013
(0.23 - 0.32)
0.004 - 0.012
(0.10 - 0.30)
(1.27)
0.013 - 0.020
(0.33 - 0.51)
28 Pin SOIC
28 PIN SSOP PACKAGE
0.386 - 0.394
(9.80 - 10.00)
0.228 - 0.244
(5.79 - 6.20)
Ref. JEDEC MO-137
Pin 1
0.150 - 0.157
(3.81 - 3.99)
0.053 - 0.069
(1.35 - 1.75)
0.059
(1.50)
MAX
0.007 - 0.010
(0.18 - 0.25)
0º to 8º
max.
0.016 - 0.050
(0.41 - 1.27)
0.004 - 0.010
(0.10 - 0.25)
0.025
0.008 - 0.012
(0.20 - 0.31)
(0.635)
28 Pin SSOP
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
26
SMH4042A
ORDERING INFORMATION
Summit Part Number
SUM M IT
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
SM H4042AG
xx
AYYW W
Package Designator
Pin 1
Date Code (YYW W )
Lot tracking code (Summit use)
Drawing not to scale
ORDERING INFORMATION
SMH4042A
G
A
G
M
Sum m it Part Num ber
V
TRIPOFFSET
Package
M=+50mV
N=-50mV
G=28 Lead SSOP
S=28 Lead SOIC
VTRIPHST_3V_MON
VTRIPVCC
5
G=2.65V
H=2.80V
K=2.95V
L=3.10V
A=4.375V
B=4.625V
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
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SMH4042A
NOTICE
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in
order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for
the use of any circuits described herein, conveys no license under any patent or other right, and makes no
representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect
representative operating parameters, and may vary depending upon a user’s specific application. While the
information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any
damages arising as a result of any error or omission.
SUMMITMicroelectronics,Inc.doesnotrecommendtheuseofanyofitsproductsinlifesupportoraviationapplications
where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to
significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless
SUMMITMicroelectronics, Inc. receiveswrittenassurances, toitssatisfaction, that:(a)theriskofinjuryordamagehas
been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is
adequately protected under the circumstances.
This document supersedes all previous versions.
© Copyright 2003 SUMMIT Microelectronics, Inc.
2
I C is a trademark of Philips Corporation.
PICMG & CompactPCI are trademarks of the PCI Industrial Computer Manufacturer's Group.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
28
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