VS6955CA [STMICROELECTRONICS]
5.0 megapixel fixed-focus camera module;
| 型号： | VS6955CA |
| 厂家： | 
ST |
| 描述： | 5.0 megapixel fixed-focus camera module |
| 文件： | 总90页 (文件大小：1384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VS6955CA
5.0 megapixel fixed-focus camera module
Datasheet - production data
Description
The VS6955CA is a high performance
5.0 megapixel fixed-focus camera module. It is
designed for use across a range of mobile phone
handsets and accessories. The sensor supports
high quality still camera functions as well as video
modes.
The VS6955CA is compliant with the MIPI CSI-2
specification. It is capable of generating raw
Bayer 5.0 megapixel images up to 23 fps with a
single CSI-2 lane. The VS6955CA offers an ultra
low power consumption hardware standby mode.
Table 1. Ordering information
Features
Order code
Package
Packing
• 5.0 megapixel resolution sensor (2600 x 1952)
VS6955CAQ05I/1
SMIA65
Tape and reel
inclusive of 4 border pixels each sides
• SMIA Profile 1 compliant
• compact size 6.5 mm x 6.5 mm x 4.6 mm
• MIPI CSI-2 single lane interface (up to 1Gbps)
• CCI command interface, supports up to
400 kHz
• 2.8V analog and 1.8V digital operation
• supports 2 x 2 and 4 x 4 pixel binning
• integrated 8-kbit OTP memory
• ultra low power standby mode
• on board couplet correction
• Flex compatible
November 2015
DocID028071 Rev 2
1/90
This is information on a product in full production.
www.st.com
Contents
VS6955CA
Contents
1
2
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Module specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1
3.1.2
3.1.3
3.1.4
Power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hardware standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Software standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Streaming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1
3.2.2
Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
3.4
3.5
Ultra low power mode option (only for CSI-2) . . . . . . . . . . . . . . . . . . . . . 18
Internal power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.1
3.5.2
PLL and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6
Control and video interface formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.1
3.6.2
CCP/CSI-2 serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CCI serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
Camera control interface (CCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
4.2
Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
Status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frame format description registers [0x0040 to 0x0049] . . . . . . . . . . . . 25
Analogue gain description registers [0x0080 to 0x0093] . . . . . . . . . . . . 26
Data format description registers [0x00C0 to 0x00C9] . . . . . . . . . . . . . 27
Setup registers [0x0100 to 0x0137] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Integration and gain registers [0x0200 to 0x0215] . . . . . . . . . . . . . . . . . 30
Video timing registers [0x0300 to 0x0387] . . . . . . . . . . . . . . . . . . . . . . . 31
Scaler and digital crop registers [0x0400 to 0x040F] . . . . . . . . . . . . . . . 32
Compression setup registers [0x0500] . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Contents
4.2.10 Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.11
CSI2 registers [0x808] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.12 DPHY registers [0x820 to 0x823] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.13 Binning registers [0x900 to 0x902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2.14 Data transfer registers [0x0A00 to 0x0A43] . . . . . . . . . . . . . . . . . . . . . . 36
4.2.15 Ideal raw registers [0x0B04 to 0x0B05] . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.16 Bracketing LUT registers [0x0E00 to 0x0E55] . . . . . . . . . . . . . . . . . . . . 37
4.2.17 Integration and gain limit registers [0x1000 to 0x1089] . . . . . . . . . . . . . 40
4.2.18 Video timing limit registers [0x1100 to 0x11C7] . . . . . . . . . . . . . . . . . . . 41
4.2.19 Scaling limit registers [0x1200 to 0x120F] . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.20 Compression capability registers [0x1300] . . . . . . . . . . . . . . . . . . . . . . 45
4.2.21 Derate capability registers [0x1500 to 0x1502] . . . . . . . . . . . . . . . . . . . 45
4.2.22 DPHY capability registers [0x1600 to 0x1604] . . . . . . . . . . . . . . . . . . . 46
4.2.23 Bitrate limit registers [0x1608] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.24 Binning capability registers [0x1700 to 0x1714] . . . . . . . . . . . . . . . . . . 47
5
Optical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1
5.2
Lens characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
User precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6
7
Video data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1
Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1
Output size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
Programmable addressable region of the pixel array . . . . . . . . . . . . . . 53
Programmable width and height for output image data . . . . . . . . . . . . . 53
Analog pixel binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Subsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Digital crop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Output crop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.1.10 Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Image and video size capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2
7.3
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VS6955CA
7.4
7.5
Image compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Exposure and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5.1
7.5.2
7.5.3
Analogue gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Integration and gain parameter re-timing . . . . . . . . . . . . . . . . . . . . . . . . 67
8
Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.1
Full frame deterministic test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.1.1
8.1.2
8.1.3
8.1.4
Solid color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
100% color bars pattern mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
‘Fade to gray’ color bar mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
PN9 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
8.2
Test cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9
Defect categorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.1
Pixel defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Defect detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Defect categorisation: Single pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Defect categorisation: Couplets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Defect categorisation: Clusters and blobs . . . . . . . . . . . . . . . . . . . . . . . 72
9.2
Mapped couplet correction (Bruce filter) . . . . . . . . . . . . . . . . . . . . . . . . . 73
10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.1 Power supply - VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.2 CCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.4 AC electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.1 Power supply (peak current) - VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . 76
10.4.2 System clock - EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.3 EXTCLK - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.4 CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.5 CSI interface - DATA+, DATA-, CLK+, CLK- . . . . . . . . . . . . . . . . . . . . . 78
4/90
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Contents
Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Cosmetic inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Packaging and delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11
12
13
14
15
16
17
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ECOPACK
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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List of tables
VS6955CA
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-up sequence timing constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 16
POR cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
System input clock frequency range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frame format description registers [0x0040 to 0x0049] . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Analogue gain description [0x0080 to 0x0093]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data format description registers [0x00C0 to 0x00C9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Setup registers [0x0100 to 0x0137] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Integration and gain registers [0x0200 to 0x0215] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Video timing registers [0x0300 to 0x0387] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Scaler and digital crop registers [0x0400 to 0x040F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Compression setup registers [0x0500] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CSI2 registers [0x808] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DPHY registers [0x820 to 0x823] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Binning registers [0x900 to 0x902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Data transfer registers [0x0A00 to 0x0A43] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ideal raw registers [0x0B04 to 0x0B05] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bracketing LUT registers [0x0E00 to 0x0E55] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Integration and gain limit registers [0x1000 to 0x1089] . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Video timing limit registers [0x1100 to 0x11C7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Scaling limit registers [0x1200 to 0x120F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Compression capability registers [0x1300] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Derate capability registers [0x1500 to 0x1502]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DPHY capability registers [0x1600 to 0x1604] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bitrate limit registers [0x1608] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Binning capability registers [0x1700 to 0x1714] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Lens design characteristics for first source lens supplier . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External clock frequency example - 5.0 Mpixel RAW10 18 fps (CSI-2 single lane) . . . . . . 61
External clock frequency examples - 5.0 Mpixel 10-8 23 fps (CSI-2 single lane). . . . . . . . 61
Examples of video mode capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Analogue gain control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Registers used to define the output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Pixel defect specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Image settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Power supply - VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
CCI interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
In-rush current - VDIG, VANA (CSI-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
External clock timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
CCI interface timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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VS6955CA
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
CSI interface - DATA+, DATA-, CLK+, CLK- characteristics . . . . . . . . . . . . . . . . . . . . . . . 78
Surface class definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Demerit points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Examples of pass/fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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7
List of figures
VS6955CA
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
VS6955CA in system with software image processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VS6955CA module pinout (viewed from bottom of camera module) . . . . . . . . . . . . . . . . . 10
System state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VS6955CA power-up sequence for CCP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VS6955CA power-up sequence for CSI-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VS6955CA power-down sequence for CSI-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ULPS sequence for CSI-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock input types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. VS6955CA CCP2 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 11. VS6955CA CSI-2 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 12. Data flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 13. Programmable addressable region of the pixel array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Output size within a CCP data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. Output size within a dedicated CSI-2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 16. Subsample readout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. Digital crop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. Scaling modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 19. Scaler quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 20. Example image horizontal scaled by a downscale factor of 2 . . . . . . . . . . . . . . . . . . . . . . 58
Figure 21. Output size within a CCP data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 22. VS6955CA clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 23. Timing block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 24. SMIA output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 25. Bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 26. Analogue gain register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 27. 100% color bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 28. ‘Fade to gray’ color bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 29. PN9 linear feedback filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 30. Pixel numbering notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 31. Single pixel fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 32. Couplet pixel fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 33. External clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 34. CCI AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 35. VS6955CA outline drawing - 1 of 3 - All dimensions in mm . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 36. VS6955CA outline drawing - 2 of 3 - All dimensions in mm . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 37. VS6955CA outline drawing - 3 of 3 - All dimensions in mm . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 38. Inspection areas on the VS6955CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 39. Marking diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 40. Example of ST inner box label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 41. Mobile camera application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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Overview
1
Overview
The VS6955CA image sensor produces raw digital video data at up to 23 frames per
second. The sensor supports horizontal flip and vertical mirroring. Output frequency
can be derated as defined in the specification for power saving. Higher frame rate can
be achieved through analog binning and subsampling modes.
The image data is digitized using an internal 10-bit column ADC. The resulting pixel
data is output together with checksums and embedded codes for synchronization. The
interface conforms to MIPI CSI-2 interface standards.
The sensor is fully configurable through a CCI serial interface. Both the CSI-2 and CCI
interfaces are specified in a separate document: MIPI alliance standard for camera
serial interface 2 (CSI-2).
Table 2. Technical specification
Feature
Pixel resolution
Detail
2600 x 1952 with border pixels
Sensor technology
Pixel size
ST IMG140 FSI Gen2 based CMOS imaging process
1.4 µm x 1.4 µm
+ 24 dB
Analog gain
Digital gain
+ 6 dB
Dynamic range
Signal to noise
60 dB
36 dB (@ 100 lux)
Analog: 2.6 to 2.9V
Digital: 1.7 to 1.9 V
Supply voltages
Typical power consumption
15 fps
100 mA (typical)
Operating temperature
Storage temperature
Average dark current (60C)
Shading (60C)
-30°C to +70°C
-40°C to +85°C
25 e/s
12 e/s
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Module specification
VS6955CA
VS6955CA interface
The VS6955CA image sensor can be directly connected to a baseband or multimedia
processor. The image processing is done in software or hardware within the baseband
processor.
Figure 1. VS6955CA in system with software image processing
Mobile
Video engine
Derating
Output data I/F
baseband
processor
CSI-2
Defect Corr.
Dark cal
CCI
Video timing
Test ctrl
Sys ctrl
Col ADC
Clk mngt
Pixel
array
PLL
EXTCLK
Power
Module
2
Module specification
Figure 2 shows the position of the pins on the module and Table 3 provides the signal
descriptions.
Figure 2. VS6955CA module pinout (viewed from bottom of camera module)
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VS6955CA
Module specification
Table 3. Pin description
I/O type
Pad number
Pad name
Description
Power supplies
1
GND
PWR
PWR
PWR
PWR
Ground (combined)
Ground (combined)
7
GND
VANA
VDIG
2
Analog power
Digital power
10
System
3
4
XSHUTDOWN
EXTCLK
I
I
Power down control(1)
System clock input
Control
5
6
SCL
SDA
I
Serial communication clock
Serial communication data
I/O
Data
8
CLK-
SubLVDS output Output qualifying clock
SubLVDS output Output qualifying clock
SubLVDS output Serial output data
SubLVDS output Serial output data
9
CLK+
DATA-
DATA+
11
12
ST test
TP
ST test pins
Do not connect(2)
1. Signal is active low.
2. Test pins are not floating.
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Functional description
VS6955CA
3
Functional description
3.1
Device operating modes
The mode changes in VS6955CA are shown in Figure 3. Further details are provided in
Section 3.2.1 to Section 3.2.
Figure 3. System state diagram
POWER-OFF
CSI-2
Power supplies OFF
Power supplies ON
Power supplies OFF
HW-STANDBY
CSI-2
XSHUTDOWN is low
XSHUTDOWN is high
XSHUTDOWN is low
CCI
CCI
SW-STANDBY
CSI-2
SW-STANDBY
CCP2
CCI
CCI
CCI
CCI
STREAMING
CSI-2
STREAMING
CCP2
3.1.1
3.1.2
Power off
The power off state is defined as either or both of the digital and analog supplies not
present.
Hardware standby
This is the lowest power consumption mode. CCI communications are not supported in this
mode. The PLL and the video blocks are powered down. This state is entered by pulling the
control pin XSHUTDOWN down (active low). All registers are returned to their default values
3.1.3
Software standby
Software standby mode preserves the contents of the CCI register map. CCI
communications are supported in this mode. The software standby mode is selected using a
serial interface command. If this state is entered from hardware standby, the data pads
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Functional description
remain at LP-00. If this state is entered from streaming then the data pads go to LP-11 at the
end of the current frame. The internal video timing is reset to the start of a video frame in
preparation for the enabling of active video. The values of the serial interface registers such
as exposure and gain are preserved. The system clock must remain active when
communicating with the sensor.
This state is entered by releasing the device from hard reset by writing 0x00 to the mode
control register (0x0100) or commanding a soft reset by writing 0x01 to the software reset
register (0x0103).
Note:
After a soft reset or the transition of XSHUTDOWN to high, all registers are returned to their
default values.
3.1.4
Streaming
The VS6955CA streams live video. This mode is entered by writing 0x01 to the mode
control register (0x0100).
3.2
Power management
3.2.1
Power-up procedure
The digital and analog supply voltages can be powered up in any order, for example, VDIG
then VANA or VANA then VDIG.
On power-up the on-chip power-on reset cell ensures that the CCI register values are
initialized correctly to their default values.
The EXTCLK clock can either be initially low and then enabled during software standby
mode or EXTCLK can be a free running clock.
The power-up sequence timing constraints are shown in Table 4.
Table 4. Power-up sequence timing constraints
Symbol
t0
Parameter
VANA rising – VDIG rising
VDIG rising – VANA rising
Min.
Max.
Units
ns
VANA and VDIG may rise in any
order. The rising separation can
vary from 0 ns to indefinite.
t1
ns
XSHUTDOWN must rise later
than or coincident with the later
rising supply (VDIG or VANA)
VDIG / VANA rising –
XSHUTDOWN rising
t2
µs
XSHUTDOWN – First I2C
transaction
t3
28,500
28,500
EXTCLK cycles
Minimum number of EXTCLK cycles
prior to the first I2C transaction
t4
t5
t6
EXTCLK cycles
PLL start up/lock time
-
-
1
ms
ms
Entering streaming mode – First
frame start sequence (fixed part)
10
Entering streaming mode – First
frame start sequence (variable part)
= Integration time
fine_integration_
time_min
t7
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Functional description
VS6955CA
Figure 4. VS6955CA power-up sequence for CCP2
VDIG
This is an example of
VANA rising after VDIG
t1
t0
VANA
t2
XSHUTDOWN
t3
EXTCLK (Free running)
EXTCLCK may be free running or gated
EXTCLK (Gated)
t4
CCI
Enter
Configure
Device
Read
Device
ID
Streaming
t5
CLK+/-
High Z (tri-state)
Mode changed
to CCP2
DATA+/-
LP00 (CSI-2 mode)
t6
t7
0x01
0xFF
Frame count register
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Functional description
Figure 5. VS6955CA power-up sequence for CSI-2 mode
VDIG
This is an example of
VANA rising after VDIG
t1
t0
VANA
t2
XSHUTDOWN
t3
EXTCLK (Free running)
EXTCLK may be free running or gated
EXTCLK (Gated)
t4
CCI
Configure
device
Enter
streaming
Read
device
ID
t5
CLK+/-
High-Speed
LP11
LP01
TX
DATA+/-
t6
t7
0xFF
0x01
Frame count register
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Functional description
VS6955CA
3.2.2
Power-down procedure
The power-down sequence timing constraints are shown in Table 5.
Table 5. Power-down sequence timing constraints for CSI2 communications
Symbol
Parameter
Min.
Max.
Units
Last I2C transaction to software
standby(1)
t8
-
1 frame
Last I2C transaction or MIPI frame
end to XSHUTDOWN falling
t9
512
-
clock cycles
XSHUTDOWN must fall at the
same time as, or earlier than, both
power supplies (VDIG and VANA)
XSHUTDOWN to VANA/VDIG
falling
t10
VANA and VDIG may fall in any
order, the rising separation can
vary from 0 ns to indefinite
VANA to VDIG or VDIG to VANA
falling
t11
1. If fast standby is enabled, then the power down sequence will not wait for the frame to end.
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Functional description
Figure 6. VS6955CA power-down sequence for CSI-2 mode
VDIG
VANA
This is an example of
VANA falling after VDIG
t11
t10
XSHUTDOWN
t9
EXTCLK (Free running)
EXTCLK may be free running or gated
EXTCLK (Gated)
CCI
Configure
device
Stop
streaming
High-Speed
TX
t8
LP11
CLK+/-
CSI output is disabled
after XSHUTDOWN=0
or clock is stopped
High-Speed
TX
LP11
DATA+/-
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Functional description
VS6955CA
3.3
Ultra low power mode option (only for CSI-2)
It is possible to reduce the power consumption of the system while the camera is not being
used while allowing it to be restarted at any time with a short time to streaming mode. This
can be achieved using the ultra low power standby (ULPS) mode.
ULPS mode can be entered and exited from software standby only. To enter ULPS, the user
needs to write to the sensor a specific list of settings through CCI. ST will provide the list of
CCI commands to enter or exit ULPS upon demand.
Figure 7. ULPS sequence for CSI-2 mode
STREAMING
SW_STANDBY
SW_STANDBY
SW_STANDBY
VANA, VDIG, VBAT, XSHUTDOWN at HIGH LEVEL
EXTCLK (Free running)
SDA
Configure
device to
Configure
device to
ENTER ULPS
EXIT ULPS
SCL
CLKP/-
High-Speed
TX
ULPS entry sequence
ULPS exit sequence
See D-PHY spec (v1.0) for details
See D-PHY spec (v1.0) for details
ULPS
ULPS
DATAP/-
High-Speed
TX
ULPS entry sequence
ULPS exit sequence
See D-PHY spec (v1.0) for details
See D-PHY spec (v1.0) for details
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Functional description
3.4
Internal power-on reset (POR)
The VS6955CA internally performs a power-on reset (POR) when the 1V2 VDD digital
supply rises through the trigger level, Vtrig_rising. Similarly, if the 1V2 VDD digital power
supply falls through the trigger level, Vtrig_falling, then the power-on reset also triggers.
Definitions
Rise threshold voltage (VTRIGR) This is the supply voltage level that is recognized by the
POR as voltage “HIGH”. Only after the supply reaches
this level does the output of POR change to high level if
it is off, after a specified amount of delay.
Fall threshold voltage (VTRIGF)
Burst width (pw)
This is the supply voltage level that is recognized by the
POR as voltage “LOW”. Only after the supply reaches
this level does the output of POR change to low
(ground) level if it is on.
Burst is the negative pulse riding the supply signal. The
burst width is measured as the amount of duration for
which the supply signal dropped beyond the threshold
levels.
Delay duration (TPOR)
Delay duration is defined as the time duration for which
POR stays off before re-powering. Each reset of POR
imparts a specified delay duration before POR re-
powers.
Figure 8. POR timing
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Functional description
Symbol
VS6955CA
Table 6. POR cell characteristics
Constraint
Minimum
Typical
Maximum
Units
VTRIGR
VTRIGF
POR rise voltage detection
POR fall voltage detection
0.95
V
V
0.4
Tburst (pw) Burst filter
2
8
µs
µs
Tpor
Delay duration
20
45
3.5
External clock
3.5.1
PLL and clock input
The VS6955CA has an embedded PLL block. This block generates all necessary internal
clocks from an input range defined in Table 7.
Table 7. System input clock frequency range
Minimum (MHz)
Maximum (MHz)
6
27
The value of the external clock frequency must be written to the register 0x0136
(extclk_frequency_mhz).
3.5.2
Clock input type
The external clock provided by the host to the VS6955CA must be a DC coupled square
wave and may also be RC-filtered.
Figure 9. Clock input types
Camera module
Host processor
Host processor
Extclk
Pad
Pad
extclk
1st option
DC-coupled
pwrdn
pwrdn
Camera module
Extclk
Pad
Pad
extclk
2nd option
DC-coupled
and filtered
pwrdn
pwrdn
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Functional description
3.6
Control and video interface formats
Image data is transferred from the VS6955CA using a high speed subLVDS serial link.The
serial control data is transferred to and from the VS6955CA using a CCI bus.
3.6.1
CCP/CSI-2 serial data link
Data signals (DATA+ and DATA-) and clock signals (CLK+ and CLK-) are transferred from
VS6955CA using two pairs of balanced 100 Ω impedance transmission lines.
The transmission line pairs and custom transmitters/receivers realize a very low voltage
differential (subLVDS) signalling scheme that can transfer information in a potentially noisy
environment.
For the CCP link or CSI-2 single lane interface, the VS6955CA supports the transmission of
raw Bayer data at 5.0 Mpixel resolution up to 23 fps in RAW8 or 10-8 bit format.
3.6.2
CCI serial control bus
The internal registers in VS6955CA can be configured by a master device via a CCI bus
(SDA, SCL). VS6955CA sends and receives commands over this bus at up to 400 Kbits/s.
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Camera control interface (CCI)
VS6955CA
4
Camera control interface (CCI)
2
This chapter specifies the camera control interface (CCI). The I C-type interface uses 1.8 V
I/O with two signals: serial data line (SDA) and serial clock line (SCL). CCI is used for
control data transfer. Clock signal (SCL) generation is performed by the master device (the
camera module is a slave device). The master device initiates data transfer. The CCI bus on
the camera module has a maximum speed of 400 Kbits/s and has a software switchable
device address. The default device address is 0x20.
Any internal register that can be written to, can also be read from. There are also read only
registers that contain device status information, for example, design revision details. A read
instruction from an unused register location returns the value 0x00. A read instruction from a
reserved address may return any value. A write instruction to a reserved or unused register
location is illegal and the effect of such a write is undefined. It is the responsibility of the host
system to only write to register locations which have been defined.
4.1
Valid register data types
The contents of the registers can represent a number of different data types (see Table 8).
The register map uses this coding to help with the interpretation of the contents of each
register.
Table 8. Valid register data types
Data type
Name
Range
Description
8UI
8-bit unsigned integer 0 to 255
-
8SI
8-bit signed integer
-128 to 127
Two’s complement notation
16UI
16SI
16-bit unsigned integer 0 to 65535
-
16-bit signed integer
16-bit unsigned iReal
-32768 to 32767
Two’s complement notation
08.08 fixed point number. 8 integer
bits (MS Byte), 8 fractional bits (LS
Byte)
16UR
16SR
32UR
32SF
0 to 255.99609375
-128 to 127.9960375
0 to 65535.99998474
As per IEEE 754
-
Two’s complement notation,
8 fractional bits
16-bit signed iReal
16.16 fixed point number.
16 integer bits (MS 2 Bytes),
16 fractional bits (LS 2 Bytes)
32-bit unsigned iReal
32-bit IEEE floating-
point number
As per IEEE 754. 1 sign bit,
8 exponent bits, 23 fractional bits
This indicates that the value is
decoded to select one of several
functions or modes.
8C or 16C 8-bit or 16-bit coded
8B or 16B 8 or 16 bits
Each bit represents a specific
function or mode.
-b
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Camera control interface (CCI)
4.2
Register default values
The registers default values are expressed as hexadecimal numbers.
4.2.1
Status registers [0x0000 to 0x001F]
Table 9. Status registers [0x0000 to 0x001F]
Data
Index
Byte
Register name
Default Type
Comment
type
0000
Hi
0B
2955
Camera model identification number.
module_model_id
16UI
RO
8B
Default values depend on NVM
content.
0001
0002
Lo
Revision identifier of the camera for
DCC change.
revision_number_major
manufacturer_id
8UI
8UI
00
01
RO
RO
Module manufacturer number.
0003
0004
0005
Default value depends on NVM
content.
SMIA version that sensor complies
with
smia_version
frame_count
8UI
8UI
0A
FF
RO
RW
10 - Version 1.0
Frame count register. Increments
from 1 to 254 when streaming.
Reports 255 when idle.
Color pixel readout order. Changes
with mirror and flip (register 0x0101).
0x00 - GR/BG normal.
0006
pixel_order
8UI
00
RO
0x01 - RG/GB horizontal mirror.
0x02 - BG/GR vertical flip.
0x03 - GB/RG vertical flip and
horizontal mirror.
0008
0009
000C
Hi
00
40
0A
data_pedestal
pixel_depth
16UI
8UI
RO
RO
Offset applied to the video data.
Lo
Pixel depth resolution of the sensor.
Revision identifier of the camera for
minor changes.
Default value depends on NVM
content.
0010
revision_number_minor
8UI
00
RO
1: TS
2: ES
3: CS
4: MP
0011
0012
additional_spec_ver
module_date_year
8UI
8UI
08
00
RO
RO
Additional specification identifier.
Last digit of manufacturing year.
Default value depends on NVM
content.
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Camera control interface (CCI)
VS6955CA
Table 9. Status registers [0x0000 to 0x001F] (continued)
Data
type
Index
Byte
Register name
Default Type
Comment
Manufacturing month.
0013
module_date_month
8UI
00
00
RO
RO
RO
Default value depends on NVM
content.
Manufacturing day.
0014
module_date_day
8UI
8UI
Default value depends on NVM
content.
Manufacturing phase identification.
0015
0016
module_date_phase
01
03
Default value depends on NVM
content.
Silicon identification number.
This may not be the same as the
module identification number, for
example, in the case where the same
silicon is used in two different
modules.
sensor_model_id
16UI
8UI
RO
RO
0017
0018
BB
Bits 3:0 Silicon NVM revision number.
sensor_nvm_revision_id
00
Default value depends on NVM
content.
sensor_mask_set_revision_id
sensor_manufacturer_id
01
01
RO
RO
Bits 7:4 Silicon mask revision code.
Silicon manufacturer number -
ST Microelectronics.
0019
001A
8UI
8UI
Silicon firmware version with format
“[7:4].[3:0]”, for example 0x11 = “1.1”.
sensor_firmware_version
11
RO
001C
001D
001E
001F
Hi
00
00
00
00
Sequential number starting at 0 and
incrementing by 1. Specification
identifier.
3rd
2nd
Lo
serial_number
32UI
RO
Default value depends on NVM
content.
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Camera control interface (CCI)
4.2.2
Frame format description registers [0x0040 to 0x0049]
For a full description of the frame format description refer to Section 6.1: Frame format on
page 49.
Table 10. Frame format description registers [0x0040 to 0x0049]
Data
Index
Byte
Register name
Default Type
Comment
type
0040
frame_format_model_type
8UI
01
RO
Generic frame format.
Contains the number of 2-byte data
format descriptors used.
frame_format_model_
subtype
The upper nibble defines the number
of column descriptors.
0041
8UI
22
RO
The lower nibble defines the number
of row descriptors.
0042
0043
0044
0045
0046
0047
0048
0049
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
5A
28
20
08
10
03
57
A0
frame_format_descriptor_0_
req
16UI
RO
RO
RO
RO
number of visible columns.
8 dummy columns.
frame_format_descriptor_1 16UI
frame_format_descriptor_2 16UI
3 embedded rows (SOF).
number of visible rows
frame_format_descriptor_3_
req
16UI
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Camera control interface (CCI)
VS6955CA
4.2.3
Analogue gain description registers [0x0080 to 0x0093]
For a full description of the analogue gain description registers refer to Section 7.5.1:
Analogue gain model on page 66.
Table 11. Analogue gain description [0x0080 to 0x0093]
Data
type
Index
Byte
Hi
Register name
analogue_gain_capability
analogue_gain_code_min
analogue_gain_code_max
analogue_gain_code_step
analogue_gain_type
analogue_gain_m0
Default
Type
Comment
0080
0081
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093
00
Analogue gain capability - single
global gain only.
16UI
RO
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
00
00
00
00
F0
00
10
00
00
00
00
01
00
FF
FF
01
00
Minimum recommended analogue
gain code.
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
RO
RO
RO
RO
RO
RO
RO
RO
Maximum recommended analogue
gain code.
Analogue gain code step size.
Analogue gain type.
Analogue gain constant M0.
Analogue gain constant C0.
Analogue gain constant M1.
Analogue gain constant C1.
analogue_gain_c0
analogue_gain_m1
analogue_gain_c1
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Camera control interface (CCI)
4.2.4
Data format description registers [0x00C0 to 0x00C9]
Table 12. Data format description registers [0x00C0 to 0x00C9]
Data
Index
Byte
Register name
Default
Type
Comment
type
2-byte generic data format model
type
00C0
00C1
data_format_model_type
8UI
01
RO
data_format_model_
subtype
8UI
04
RO
RO
Number of data format descriptors.
00C2
00C3
00C4
00C5
00C6
Hi
Lo
Hi
Lo
Hi
08
08
0A
0A
0A
RAW8 mode - transmit top 8 bits of
pixel data.
data_format_descriptor_0
data_format_descriptor_1
16UI
RAW10 mode - transmit top 10 bits
of pixel data.
16UI
16UI
RO
RO
10-8 compressed mode - transmit
top 10 bits of pixel data, compressed
to 8 bits.
data_format_descriptor_2
data_format_descriptor_3
00C7
00C8
00C9
Lo
Hi
08
0A
06
10-6 compressed mode - transmit
top 10 bits of pixel data, compressed
to 6 bits.
16UI
RO
Lo
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Camera control interface (CCI)
VS6955CA
4.2.5
Setup registers [0x0100 to 0x0137]
Table 13. Setup registers [0x0100 to 0x0137]
Data
Index
Byte
Register name
Default Type
Comment
type
Mode select.
0100
mode_select
8UI
00
RW
RW
0 = Software standby.
1 = Streaming.
Image orientation
Bit0: 0 - No mirror, 1 - horizontal
mirror enable
0101
0103
image_orientation
8B
00
00
Bit1:0 = No flip, 1- vertical flip enable
Software reset returns the sensor to
its power-on defaults.
soft_reset
8UI
RW
RW
0 = Normal operation.
1 = Software reset enabled.
The grouped parameter hold register
disables the consumption of
integration, gain and video timing
parameters.
0104
0105
grouped_parameter_hold
8UI
8UI
00
00
0 = Consume values as normal.
1 = Do not consume values whilst set
high.
Setting this register to 1 prevents the
sensor out-putting frames that have
been corrupted by video timing
parameter changes.
mask_corrupted_frames
RW
0 = Output as normal.
1 = Mask corrupted frames.
SMIA fast standby control
0 = Frame completes before SW-
STBY mode entry.
1 = Frame may be truncated before
SW-STBY mode entry.
0106
0107
fast_standby_ctrl
cci_addr
8UI
8UI
00
20
RW
RW
Device address.
Bit0:
0 - 2nd_cci_if_disable
1 - 2nd_cci_if_enable
Bit1:
0108
second_i2c_if_control
8UI
00
RW
0 - 2nd_cci_if_ack_disable
1 - 2nd_cci_if_ack_enable
Additional device address that can be
responded to.
0109
0110
cci_2nd_addr
8UI
8UI
20
00
RW
RW
The DMA (CCP2) or virtual (CSI2)
channel identifier.
csi_channel_identifier
Valid range = 0 to 7 for CCP2.
Valid range = 0 to 3 for CSI2.
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Camera control interface (CCI)
Table 13. Setup registers [0x0100 to 0x0137] (continued)
Data
type
Index
Byte
Register name
Default Type
Comment
Determines which transmission
signalling mode is to be used.
0111
csi_signalling_mode
8UI
02
RW
0 = CCP2 data-clock signalling.
1 = CCP2 data-strobe signalling.
2 = CSI2.
The value of this register contains the
pixel width of the uncompressed pixel
data.
0112
0113
0114
Hi
0A
0A
01
Valid values are 0xA and 0x8.
csi_data_format
csi_lane_mode
16UI
RW
RW
The value of this register contains the
pixel width of the compressed pixel
data.
Lo
Valid values are 0xA and 0x8.
Number of data lanes in use.
0 = 1-lane.
1 = 2-lane.
8UI
Note: This register must be set to 0.
CSI-2 data type for 10-to-8
compression.
0115
0117
0120
csi2_10_to_8_dt
csi2_10_to_6_dt
gain_mode
8UI
8UI
8UI
30
31
00
RW
RW
RO
CSI-2 data type for 10-to-6
compression.
Global gain mode - this device only
supports 0x00.
0130
0131
0132
0133
0134
0135
0136
0137
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
02
vana_voltage
vdig_voltage
vio_voltage
ext_clkfreq
16UR
16UR
16UR
16UR
RW
RW
RW
RW
Typical supplied VANA voltage.
Typical supplied VDIG voltage.
Typical IO voltage.
CC
01
CC
01
CC
06
8.8 fixed-point representation of the
external clock-frequency, in MHz.
00
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VS6955CA
4.2.6
Integration and gain registers [0x0200 to 0x0215]
These registers are used to control the image exposure. See Section 7.5: Exposure and
gain control on page 65 for more information.
Table 14. Integration and gain registers [0x0200 to 0x0215]
Data
Index
Byte
Hi
Register name
Default
Type
Comment
type
0200
0201
0202
0203
0204
0205
020e
020f
02
fine_exp_req
16UI
RW
Fine integration time in pixels.
Coarse integration time in lines.
Gain code for all channels.
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
AE
00
00
coarse_exp_req
gain_req
16UI
RW
RW
RW
RW
RW
RW
00
00
16UI
01
00
01
00
01
00
01
00
Green (red row) channel digital gain
value
digital_gain_greenR
digital_gain_red
digital_gain_blue
digital_gain_greenB
16UR
16UR
16UR
16UR
0210
0211
0212
0213
0214
0215
Red channel digital gain value
Blue channel digital gain value
Green (blue row) channel digital gain
value.
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Camera control interface (CCI)
4.2.7
Video timing registers [0x0300 to 0x0387]
For a full description of the video timing registers refer to Chapter 6: Video data interface on
page 49.
Table 15. Video timing registers [0x0300 to 0x0387]
Data
Index
Byte
Register name
Default
Type
Comment
type
0300
0301
0302
Hi
Lo
Hi
00
vt_pix_clk_div
16UI
RW
Video timing pixel clock divider.
Video timing system clock divider.
0A
00
01
vt_sys_clk_div
pre_pll_div
16UI
16UI
RW
RW
Note: This value must be even for
single lane modules
0303
Lo
0304
0305
0306
Hi
Lo
Hi
00
01
Pre-PLL clock divider value.
PLL multiplier value.
Odd and even values can be used,
but odd values result in the nearest
lower even value being used (for
example, 133 becomes 132).
00
85
pll_mult
16UI
RW
0307
Lo
0308
0309
030A
Hi
Lo
Hi
00
0A
op_pix_clk_div
op_sys_clk_div
16UI
16UI
RW
RW
Output timing pixel clock divider.
Output timing system clock divider.
00
01
Note: This value must be even for
single lane modules
030B
Lo
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
034A
034B
034C
034D
034E
034F
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
08
24
0A
BE
00
00
00
00
0A
27
07
9F
0A
28
07
A0
frame_length_req
line_length_req
x_start_req
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
RW
RW
RW
RW
RW
RW
RW
RW
Length of the video frame in lines.
Length of a line of video in pixels.
X pixel address of the top left corner
of the visible pixel data.
Y line address of the top left corner of
the visible pixel data.
y_start_req
X pixel address of the bottom right
corner of the visible pixel data.
x_end_req
Y line address of bottom right corner
of the visible pixel data.
y_end_req
Width in pixels of the output image
from the sensor.
x_op_size_req
y_op_size_req
Height in lines of the output image
from the sensor.
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Camera control interface (CCI)
VS6955CA
Table 15. Video timing registers [0x0300 to 0x0387] (continued)
Data
type
Index
Byte
Hi
Register name
Default
Type
Comment
0380
0381
0382
0383
0384
0385
0386
0387
00
x_even_inc_req
16UI
RW
X address increment for even pixels.
X address increment for odd pixels.
Y address increment for even lines.
Y address increment for odd lines.
01
Lo
Hi
00
01
x_odd_inc_req
y_even_inc_req
y_odd_inc_req
16UI
16UI
16UI
RW
RW
RW
Lo
Hi
00
01
Lo
Hi
00
01
Lo
4.2.8
Scaler and digital crop registers [0x0400 to 0x040F]
Table 16. Scaler and digital crop registers [0x0400 to 0x040F]
Data
Index
Byte
Register name
Default
Type
Comment
type
0400
0401
0402
Hi
Lo
Hi
Scaling mode
00
scale_mode_req
16UI
RW
0 = No scaling
1 = Horizontal scaling
00
Spatial sampling
00
00
0 = Bayer sampling
1 = Co-sited (2- or 4-component)
2 = Co-sited (3-component)
scale_cosite_req
16UI
RW
0403
Lo
0404
0405
0406
0407
0408
Hi
Lo
Hi
Lo
Hi
00
10
scale_m_req
scale_n
16UI
16UI
RW
RO
Down scale factor. M component.
Down scale factor. N component.
00
10
00
Offset from X-address of the top left
corner of the visible pixel data after
analog crop, bin and subsample.
Even numbers only (pixels).
digital_crop_x_offset
digital_crop_y_offset
16UI
16UI
RW
RW
0409
040A
040B
Lo
Hi
00
00
00
Offset from Y-address of the top left
corner of the visible pixel data after
analog crop, bin and subsample.
Even numbers only (lines).
Lo
040C
040D
040E
040F
Hi
Lo
Hi
Lo
0A
28
07
A0
Image width after digital crop. Even
numbers only (pixels).
digital_crop_image_width
digital_crop_image_height
16UI
16UI
RW
RW
Image height after digital crop. Even
numbers only (lines).
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Camera control interface (CCI)
4.2.9
Compression setup registers [0x0500]
Table 17. Compression setup registers [0x0500]
Data
type
Index
Byte
Register name
Default
Type
Comment
00
01
0500
0501
Compression algorithm is
DPCM/PCM.
compression_algorithm
16UI
RO
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Camera control interface (CCI)
VS6955CA
4.2.10
Index
0600
Test pattern registers [0x0600 to 0x0611]
Table 18. Test pattern registers [0x0600 to 0x0611]
Data
Byte
Register name
Default
Type
Comment
type
Enables maufacturer-specific test
patterns.
man_spec_patt_req
8UI
00
RW
0 = Enable SMIA test patterns.
1 = Enable manufacturer-specific
test patterns.
SMIA test pattern selector.
Note that the PN9 test pattern
replaces data at output TX stage.
bit0 = No pattern
bit1 = Solid color
0601
test_pattern_req
8UI
00
RW
bit2 = 100% color bars
bit3 = Fade-to-grey color bars
bit4 = Pseudo random-PN9
0602
0603
0604
Hi
00
00
00
Test data used to replace Red pixel
data - range 0 to 1023.
test_data_red
16UI
16UI
16UI
16UI
RW
RW
RW
RW
Lo
Hi
Test data used to replace Green pixel
data on lines that also have Red
pixels - range 0 to 1023.
test_data_greenr
test_data_blue
test_data_greenb
0605
Lo
00
0606
0607
0608
Hi
Lo
Hi
00
00
00
Test data used to replace Blue pixel
data - range 0 to 1023.
Test data used to replace Green pixel
data on lines that also have Blue
pixels - range 0 to 1023.
0609
Lo
00
060A
060B
060C
060D
060E
060F
0610
Hi
Lo
Hi
Lo
Hi
Lo
Hi
00
00
00
00
00
00
00
Defines the width in pixels of the
horizontal cursor.
test_hcur_width
test_hcur_posn
test_vcur_width
16UI
16UI
16UI
RW
RW
RW
Defines the position of the top edge
of the horizontal cursor.
Defines the width in pixels of the
vertical cursor.
Defines the left hand edge of the
vertical cursor
The value can be set to 0xFFFF
which enables an automatic mode
whereby the cursor advances every
frame.
test_vcur_posn
16UI
RW
0611
Lo
00
Can be used to visually check the
frame count.
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Camera control interface (CCI)
4.2.11
CSI2 registers [0x808]
Table 19. CSI2 registers [0x808]
Data
type
Index
Byte
Register name
Default
Type
Comment
CSI2 DPHY control
0808
dphy_ctrl
8UI
00
RW
1 = Use UI control.
2 = Use register control.
4.2.12
DPHY registers [0x820 to 0x823]
Table 20. DPHY registers [0x820 to 0x823]
Data
Index
Byte
Hi
Register name
Default
Type
Comment
type
0820
0821
0822
CSI2 DPHY requested (target)
channel rate in Mbps (16.16 fixed-
point representation)
3rd
2nd
This is used to calculate the DPHY
unit-interval (UI) value.
It does not control the sensor clock
setup, but should normally
correspond to those settings.
00.00
00.00
dphy_channel_mbps_for_ui 32UR
RW
0 = Sensor automatically calculates
UI from host-programmed EXTCLK
and clock divider values and reports
in MAN_SPEC_DPHY__CLKLANE_
UIX4 register.
0823
Lo
80-1000 = Sensor calculates UI from
Mbps value.
4.2.13
Binning registers [0x900 to 0x902]
Table 21. Binning registers [0x900 to 0x902]
Data
Index
Byte
Register name
Default
Type
Comment
type
Binning mode.
0900
binning_mode
8UI
00
RW
0 = Disabled
1 = Enabled
High-nibble = Column binning factor.
High-nibble = Row binning factor.
0901
0902
binning_type
8UI
8UI
00
00
RW
RW
Binning weighting type:
0 = Averaged.
binning_weighting
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VS6955CA
4.2.14
Data transfer registers [0x0A00 to 0x0A43]
Table 22. Data transfer registers [0x0A00 to 0x0A43]
Data
Index
Byte
Register name
Default
Type
Comment
type
bit0:
0 = Disable Xfer IF1.
1 = Enable Xfer IF1.
bit1:
0A00
data_xfer_if1_ctrl
8UI
00
RW
0 = Read enable on IF1
1 = Write enable on IF1
bit2:
0 = Disabled
1 = Clear error bits on IF1
bit0: Read IF ready
bit1: Write IF ready.
bit2: Data corrupt.
0A01
0A02
data_xfer_if1_status
8UI
00
RO
bit3: Improper IF usage.
Select RW Pages from 0 to 255 for
IF1.
data_xfer_if1_page_select 8UI
00
00
RW
RW
0A04
--
DataXfer_Data0
--
8UI
8UI
Data Xfer Interface - DataLoc0
--
0A43
DataXfer_Data63
00
RW
Data Xfer Interface - DataLoc63
4.2.15
Ideal raw registers [0x0B04 to 0x0B05]
Table 23. Ideal raw registers [0x0B04 to 0x0B05]
Data
Index
Byte
Register name
Default
Type
Comment
type
Black level correction.
black_level_correction_
enable
0B04
8UI
01
RW
0 = Disabled
1 = Enabled
Mapped couplet correction enable.
mapped_couplet_correct_
enable
0B05
8UI
01
RW
0 = Disabled
1 = Enabled
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Camera control interface (CCI)
4.2.16
Bracketing LUT registers [0x0E00 to 0x0E55]
Table 24. Bracketing LUT registers [0x0E00 to 0x0E55]
Data
Index
Byte
Register name
Default
Type
Comment
type
Bracketing LUT Ctrl.
0E00
bracketing_lut_ctrl
8UI
00
RW
1-n - Bracketing over n frames
Bit[0] - Bracketing LUT Mode:
0 = return to SW standby after
bracketing.
0E01
bracketing_lut_mode
8UI
00
RW
1 = continue in streaming after
bracketing
0E02
0E03
0E10
0E11
0E12
0E13
0E14
0E15
0E16
0E17
0E18
0E19
0E1A
0E1B
0E1C
0E1D
0E1E
0E1F
0E20
0E21
0E22
0E23
0E24
0E25
0E26
0E27
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
bracketing_lut_entry_
control
Bracketing LUT entry control
(Reserved).
16UI
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
bracketing_lut_frame_a_
coarse_int_time
Bracketing LUT frame A coarse
integration time
16UI
bracketing_lut_frame_a_
analog_gain_code
Bracketing LUT frame A analog gain
code
16UI
bracketing_lut_frame_a_
digital_gain_gr
Bracketing LUT frame A digital gain
GR
16SR
16SR
16SR
16SR
16UI
bracketing_lut_frame_a_
digital_gain_r
Bracketing LUT frame A digital gain
R
bracketing_lut_frame_a_
digital_gain_b
Bracketing LUT frame A digital gain
B
bracketing_lut_frame_a_
digital_gain_gb
Bracketing LUT frame A digital gain
GB
bracketing_lut_frame_a_
bracketing_lut_entry
Bracketing LUT frame A bracketing
LUT entry
bracketing_lut_frame_b_
coarse_int_time
Bracketing LUT frame B coarse
integration time
16UI
bracketing_lut_frame_b_
analog_gain_code
Bracketing LUT frame B analog gain
code
16UI
bracketing_lut_frame_b_
digital_gain_gr
Bracketing LUT frame B digital gain
GR
16SR
16SR
16SR
bracketing_lut_frame_b_
digital_gain_r
Bracketing LUT frame B digital gain
R
bracketing_lut_frame_b_
digital_gain_b
Bracketing LUT frame B digital gain
B
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48
Camera control interface (CCI)
VS6955CA
Table 24. Bracketing LUT registers [0x0E00 to 0x0E55] (continued)
Data
type
Index
Byte
Hi
Register name
Default
Type
Comment
0E28
0E29
0E2A
0E2B
0E2C
0E2D
0E2E
0E2F
0E30
0E31
0E32
0E33
0E34
0E35
0E36
0E37
0E38
0E39
0E3A
0E3B
0E3C
0E3D
0E3E
0E3F
0E40
0E41
0E42
0E43
0E44
0E45
0E46
0E47
0E48
0E49
00
bracketing_lut_frame_b_
digital_gain_gb
Bracketing LUT frame B digital gain
GB
16SR
16UI
16UI
16UI
16SR
16SR
16SR
16SR
16UI
16UI
16UI
16SR
16SR
16SR
16SR
16UI
16UI
RW
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
bracketing_lut_frame_b_
bracketing_lut_entry
Bracketing LUT frame B bracketing
LUT entry
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
bracketing_lut_frame_c_
coarse_int_time
Bracketing LUT frame C coarse
integration time
bracketing_lut_frame_c_
analog_gain_code
Bracketing LUT frame C analog gain
code
bracketing_lut_frame_c_
digital_gain_gr
Bracketing LUT frame C digital gain
GR
bracketing_lut_frame_c_
digital_gain_r
Bracketing LUT frame C digital gain
R
bracketing_lut_frame_c_
digital_gain_b
Bracketing LUT frame C digital gain
B
bracketing_lut_frame_c_
digital_gain_gb
Bracketing LUT frame C digital gain
GB
bracketing_lut_frame_c_
bracketing_lut_entry
Bracketing LUT frame C bracketing
LUT entry
bracketing_lut_frame_d_
coarse_int_time
Bracketing LUT frame D coarse
integration time
bracketing_lut_frame_d_
analog_gain_code
Bracketing LUT frame D analog gain
code
bracketing_lut_frame_d_
digital_gain_gr
Bracketing LUT frame D digital gain
GR
bracketing_lut_frame_d_
digital_gain_r
Bracketing LUT frame D digital gain
R
bracketing_lut_frame_d_
digital_gain_b
Bracketing LUT frame D digital gain
B
bracketing_lut_frame_d_
digital_gain_gb
Bracketing LUT frame D digital gain
GB
bracketing_lut_frame_d_
bracketing_lut_entry
Bracketing LUT frame D bracketing
LUT entry
bracketing_lut_frame_e_
coarse_int_time
Bracketing LUT frame E coarse
integration time
38/90
DocID028071 Rev 2
VS6955CA
Camera control interface (CCI)
Table 24. Bracketing LUT registers [0x0E00 to 0x0E55] (continued)
Data
type
Index
Byte
Register name
Default
Type
Comment
0E4A
0E4B
0E4C
0E4D
0E4E
0E4F
0E50
0E51
0E52
0E53
0E54
0E55
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
00
bracketing_lut_frame_e_
analog_gain_code
Bracketing LUT frame E analog gain
code
16UI
RW
00
00
00
00
00
00
00
00
00
00
00
bracketing_lut_frame_e_
digital_gain_gr
Bracketing LUT frame E digital gain
GR
16SR
16SR
16SR
16SR
16UI
RW
RW
RW
RW
RW
bracketing_lut_frame_e_
digital_gain_r
Bracketing LUT frame E digital gain
R
bracketing_lut_frame_e_
digital_gain_b
Bracketing LUT frame E digital gain
B
bracketing_lut_frame_e_
digital_gain_gb
Bracketing LUT frame E digital gain
GB
bracketing_lut_frame_e_
bracketing_lut_entry
Bracketing LUT frame E bracketing
LUT entry
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48
Camera control interface (CCI)
VS6955CA
4.2.17
Integration and gain limit registers [0x1000 to 0x1089]
Table 25. Integration and gain limit registers [0x1000 to 0x1089]
Data
Index
Byte
Hi
Register name
integration_capability
min_coarse
Default
Type
Comment
type
1000
1001
1004
1005
1006
1007
1008
1009
100a
100b
1080
1081
1084
1085
1086
1087
1088
1089
00
This device supports coarse and
smooth (1 pixel) integration.
16UI
RO
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
01
00
00
00
09
02
AE
08
02
00
01
00
08
01
F8
00
08
Minimum coarse integration time (in
line periods).
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
RO
RO
RO
RO
RO
RO
RO
RO
Current frame length - current max
coarse exposure (in line periods).
coarse_margin
Minimum fine integration time (in
pixels).
min_fine
Current line length - maximum fine
exposure (pixel periods).
fine_margin
digital_gain_capability
digital_gain_min
digital_gain_max
digital_gain_step_size
This device supports digital gain.
Minimum supported digital gain
value.
Maximum supported digital gain
value
Digital gain step size.
40/90
DocID028071 Rev 2
VS6955CA
Camera control interface (CCI)
4.2.18
Video timing limit registers [0x1100 to 0x11C7]
Table 26. Video timing limit registers [0x1100 to 0x11C7]
Data
Index
Byte
Register name
Default
Type
Comment
type
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
110A
110B
110C
110D
110E
110F
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
111A
111B
111C
111D
111E
111F
Hi
40
3rd
2nd
Lo
C0
00
00
41
D8
00
00
00
01
00
04
40
C0
00
00
41
40
00
00
00
4C
01
4C
44
61
00
00
44
FA
00
00
min_ext_clk_freq
32UI
RO
Minimum external clock frequency.
Hi
3rd
2nd
Lo
max_ext_clk_freq
32UI
RO
Maximum external clock frequency.
Hi
Minimum value of pre-PLL clock
divider.
min_pre_pll_clk_div
max_pre_pll_clk_div
16UI
16UI
RO
RO
Lo
Hi
Maximum value of pre-PLL clock
divider.
Lo
Hi
3rd
2nd
Lo
Minimum input clock frequency to the
PLL.
min_pll_ip_freq
max_pll_ip_freq
32UI
32UI
RO
RO
Hi
3rd
2nd
Lo
Maximum input clock frequency to
the PLL.
Hi
min_pll_multiplier
max_pll_multiplier
16UI
16UI
RO
RO
Minimum PLL multiplier value.
Maximum PLL multiplier value.
Lo
Hi
Lo
Hi
3rd
2nd
Lo
min_pll_op_freq
max_pll_op_freq
32UI
32UI
RO
RO
Minimum PLL output frequency.
Maximum PLL output frequency.
Hi
3rd
2nd
Lo
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48
Camera control interface (CCI)
VS6955CA
Table 26. Video timing limit registers [0x1100 to 0x11C7] (continued)
Data
type
Index
Byte
Hi
Register name
min_vt_sys_clk_div
max_vt_sys_clk_div
Default
00
Type
Comment
1120
Minimum video timing system clock
divider value.
16UI
RO
Note: This value should be 2 for
single lane modules.
1121
Lo
01
1122
1123
1124
1125
1126
1127
1128
1129
112A
112B
112C
112D
112E
112F
1130
1131
1132
1133
1134
1135
1136
1137
1140
1141
1142
1143
1144
1145
1146
1147
Hi
00
04
43
61
00
00
44
FA
00
00
41
F0
00
00
43
28
00
00
00
04
00
0A
00
D9
FF
FF
0A
BE
3F
FF
Maximum video timing system clock
divider value.
16UI
32UI
RO
RO
Lo
Hi
3rd
2nd
Lo
Hi
Minimum video timing system clock
frequency.
min_vt_sys_clk_freq
max_vt_sys_clk_freq
min_vt_pix_clk_freq
max_vt_pix_clk_freq
Maximum video timing system clock
frequency. 2000Mhz
3rd
2nd
Lo
Hi
32UI
32UI
32UI
RO
RO
RO
Note: This value should be 1000Mhz
3rd
2nd
Lo
Hi
Minimum video timing pixel clock
frequency.
3rd
2nd
Lo
Hi
Maximum video timing pixel clock
frequency.
Minimum video timing pixel clock
divider value.
min_vt_pix_clk_div
max_vt_pix_clk_div
min_frame_length
max_frame_length
min_line_length
16UI
16UI
16UI
16UI
16UI
16UI
RO
RO
RO
RO
RO
RO
Lo
Hi
Maximum video timing pixel clock
divider value.
Lo
Hi
Minimum frame length in lines.
Maximum frame length in lines.
Minimum line length in pixel clocks.
Maximum line length in pixel clocks.
Lo
Hi
Lo
Hi
Lo
Hi
max_line_length
Lo
42/90
DocID028071 Rev 2
VS6955CA
Camera control interface (CCI)
Table 26. Video timing limit registers [0x1100 to 0x11C7] (continued)
Data
type
Index
Byte
Register name
Default
Type
Comment
1148
1149
114A
114B
114C
114D
1160
Hi
Lo
Hi
Lo
Hi
Lo
Hi
00
Minimum line blanking in pixel
clocks.
min_line_blanking
16UI
RO
86
00
16
00
01
00
min_frame_blanking
16UI
16UI
RO
RO
Minimum frame blanking in lines.
min_line_length_pck_
step_size
Minimum step size of line length pck.
Minimum output timing system clock
divider value.
min_op_sys_clk_div
max_op_sys_clk_div
16UI
16UI
RO
RO
Note: This value should be 2 for
single lane modules.
1161
Lo
01
1162
1163
1164
1165
1166
1167
1168
1169
116A
116B
116C
116D
116E
116F
1170
1171
1172
1173
1174
1175
1176
1177
1180
1181
Hi
00
14
42
34
00
00
44
FA
00
00
00
06
00
0A
40
90
00
00
43
28
00
00
00
00
Maximum output timing system clock
divider value.
Lo
Hi
3rd
2nd
Lo
Hi
Minimum output timing system clock
frequency.
min_op_sys_clk_freq
max_op_sys_clk_freq
32UI
32UI
RO
RO
Maximum output timing system clock
frequency.2000MHz
3rd
2nd
Lo
Hi
Note: This value should be 1000Mhz
Minimum output timing pixel clock
divider value.
min_op_pix_clk_div
max_op_pix_clk_div
16UI
16UI
RO
RO
Lo
Hi
Maximum output timing pixel clock
divider value.
Lo
Hi
3rd
2nd
Lo
Hi
Minimum output timing pixel clock
frequency.
min_op_pix_clk_freq
32UI
RO
3rd
2nd
Lo
Hi
Maximum output timing pixel clock
frequency.
max_op_pix_clk_freq
x_addr_min
32UI
16UI
RO
RO
Minimum XADDR value.
Lo
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48
Camera control interface (CCI)
VS6955CA
Table 26. Video timing limit registers [0x1100 to 0x11C7] (continued)
Data
type
Index
Byte
Hi
Register name
Default
Type
Comment
Minimum YADDR value.
Maximum XADDR value.
Maximum YADDR value.
1182
1183
1184
1185
1186
1187
1188
1189
118A
118B
118C
118D
118E
118F
11C0
11C1
11C2
11C3
11C4
11C5
11C6
11C7
00
y_addr_min
16UI
RO
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
00
0A
27
07
9F
01
00
00
C0
0A
28
07
A0
00
01
00
01
00
01
00
13
x_addr_max
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
y_addr_max
x_op_size_min
y_op_size_min
x_op_size_max
y_op_size_max
even_inc_min
even_inc_max
odd_inc_min
Minimum X output size in pixels.
Minimum Y output size in lines.
Maximum X output size in pixels.
Maximum Y output size in lines.
Minimum even increment used in
subsampling.
Maximum even increment used in
subsampling.
Minimum odd increment used in
subsampling.
Maximum odd increment used in
subsampling.
odd_inc_max
44/90
DocID028071 Rev 2
VS6955CA
Camera control interface (CCI)
4.2.19
Scaling limit registers [0x1200 to 0x120F]
Table 27. Scaling limit registers [0x1200 to 0x120F]
Data
Index
Byte
Register name
scaling_capability
scale_m_min
Default
Type
Comment
type
1200
1201
1204
1205
1206
1207
1208
1209
120A
120B
120C
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
00
VS6955CA supports horizontal
digital scaling
16UI
RO
01
00
10
00
A3
00
10
00
10
00
16UI
16UI
16UI
16UI
RO
RO
RO
RO
Minimum M value for downscale.
Maximum M value for downscale.
Minimum N value for downscale.
Maximum N value for downscale.
scale_m_max
scale_n_min
scale_n_max
Spatial sampling capability
spatial_sampling_
capability
16UI
16UI
RO
RO
Bayer sampling supported
120D
120E
Lo
Hi
03
00
2 or 4 component co-sited supported
Digital crop is supported.
Note. This should be a 8 bit register.
i.e. The value for 0x120E should be
01
digital_crop_capability
120F
Lo
01
4.2.20
Compression capability registers [0x1300]
Table 28. Compression capability registers [0x1300]
Data
Index
Byte
Register name
Default
Type
Comment
type
1300
1301
Hi
00
01
Compression capability is
DPCM/PCM.
compression_capability
16UI
RO
Lo
4.2.21
Derate capability registers [0x1500 to 0x1502]
Table 29. Derate capability registers [0x1500 to 0x1502]
Data
Index
Byte
Register name
Default
Type
Comment
type
16UI
8UI
1500
1501
1502
Hi
00
FIFO size in pixels (derate sync
RAM).
fifo_size_pixels
fifo_support_capability
RO
RO
Lo
00
01
VS6955CA supports derating
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48
Camera control interface (CCI)
VS6955CA
4.2.22
DPHY capability registers [0x1600 to 0x1604]
Table 30. DPHY capability registers [0x1600 to 0x1604]
Data
Index
Byte
Register name
Default
Type
Comment
type
CSI2 DPHY control capability:
1600
dphy_ctrl_capability
8UI
03
RO
Automatic DPHY control supported.
UI based DPHY control supported.
1 and 2 lane supported.
1601
csi_lane_mode_capability 8UI
03
RO
Note: This register should be 1 (Only
1 lane supported)
CCP2 data/clock supported.
CCP2 data/strobe supported.
CSI2 supported.
csi_signalling_mode_
capability
1602
1603
8UI
07
01
RO
RO
Fast standby is supported for rolling
shutter).
fast_standby_capability
8UI
8UI
VS6955CA supports:
– SW changeable CCI address
– 2nd CCI address.
cci_address_control_
capability
1604
07
RO
– 2nd SW changeable CCI address.
4.2.23
Bitrate limit registers [0x1608]
Table 31. Bitrate limit registers [0x1608]
Data
Index
Byte
Hi
Register name
Default
Type
Comment
type
1608
1609
160A
160B
03
3rd
2nd
Lo
E8
00
00
max_per_lane_bitrate_1_
lane_mode_mbps
Maximum bitrate for a 1 lane
configuration.
32UR
RO
46/90
DocID028071 Rev 2
VS6955CA
Camera control interface (CCI)
4.2.24
Binning capability registers [0x1700 to 0x1714]
Table 32. Binning capability registers [0x1700 to 0x1714]
Data
Index
Byte
Register name
Default
Type
Comment
type
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
170A
170B
170C
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
00
min_frame_length_lines_
bin
Minimum frame length (lines)
allowed in binning mode.
16UI
RO
D9
FF
FF
0A
BE
3F
FF
00
86
02
51
09
max_frame_length_lines_
bin
Maximum possible number of lines
per frame in binning mode.
16UI
16UI
RO
RO
RO
RO
RO
Minimum line length (pixel clocks)
allowed in binning mode.
min_line_length_pck_bin
Maximum possible number of pixel
clocks per line in binning mode.
max_line_length_pck_bin 16UI
min_line_blanking_pck_
bin
Minimum line blanking time in pixel
clocks in binning mode.
16UI
fine_integration_time_
min_bin
Minimum fine integration time
allowed in binning mode (in pixels).
16UI
Margin used to determine the
maximum fine integration time
allowed in binning mode (in pixels).
fine_integration_time_
16UI
RO
max_margin_bin
170D
1710
Lo
D8
01
binning_capability
8UI
8UI
RO
RO
Binning supported
Binning weighting capability:
Averaged weighting supported
binning_weighting_
capability
1711
1712
01
02
Number of binning subtypes
available.
binning_sub_types
8UI
RO
1713
1714
binning_type_1
binning_type_2
8UI
8UI
22
44
RO
RO
Binning type is 2 x 2 (Col x Row).
Binning type is 4 x 4 (Col x Row).
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48
Optical specification
VS6955CA
5
Optical specification
5.1
Lens characteristics
Table 33. Lens design characteristics for first source lens supplier
Parameter Value
Construction
F/number
4-element plastic lens
2.4
Effective focal length
Diagonal FOV
3 mm (primary wavelength 530 nm used)
74° +/- 1°
TV: <|2%|
Distortion
Absolute: <|1.0%| across whole field (by design)
Relative illumination (lens only)
Spectral weighting:
40% at full image height, typical design value
Wavlength (nm) 656.28 587.56 546.07 486.13 435.84 404.66
Weight
151
318
312
157
49
13
Lateral chromatic aberration from 435 nm
to 656 nm
<2.8um
Coating reflectance - All surfaces are
coated.
<1%
Maximum chief ray angle
28.4°
IR coating filter cut-off wavelength
670 nm +/-8 nm
5.2
User precaution
As is common with many CMOS imagers, the camera should not be pointed at bright static
objects for long periods of time as permanent damage to the sensor may occur.
48/90
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VS6955CA
Video data interface
6
Video data interface
The video stream output from the VS6955CA through the compact camera port (CCP) or
camera serial interface (CSI) contains both video data and other auxiliary information. This
section describes the frame formats.
The selection of the video data format is controlled using the following register:
CSI_SIGNALLING_MODE (0x0111)
0 - CCP2 data/clock
1 - CCP2 data/strobe
2 - CSI-2 (default)
Changing the video data format must be performed when the sensor is in software standby.
•
The VS6955CA supports maximum output data rate of 1.0 Gbps when operated in CSI-
2 single lane mode.
•
•
The VS6955CA CCP lane is capable of transmitting at 640 Mbps.
The CSI-2 data lane transmitter supports:
–
–
–
–
unidirectional master
HS-TX
LP-TX (ULPS)
CIL-MUYN function
•
The CSI-2 clock lane transmitter supports:
–
–
–
–
unidirectional master
HS-TX
LP-TX (ULPS)
CIL-MCNN function
6.1
Frame format
The frame format for the VS6955CA is described by the frame format description registers,
see Table 10 on page 25. For CCP2 this results in a frame as shown in Figure 10 and for
CSI-2 it results in a frame as shown in Figure 11.
Figure 10. VS6955CA CCP2 frame format
FS
3 embedded data lines
Frame start code
Bayer pixel data
FE
Interframe padding
Frame end code
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Figure 11. VS6955CA CSI-2 frame format
FS
Embedded data
Frame start packet
Bayer pixel
data
Line
blanking
FE
Frame
Frame end packet
blanking
Embedded data lines
The embedded data lines provide a mechanism to embed non-image data such as sensor
configuration details within the output data stream. The number of embedded data lines at
the start and end of the frame is specified as part of the frame format description.
VS6955CA has three embedded data lines.
Dummy pixel data
This is invalid pixel data. The receiver should always ignore dummy pixel data. The
VS6955CA has eight dummy columns.
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Visible pixel data
The visible pixels contain valid image data.The correct integration time and analog gain for
the visible pixels is specified in the blank lines at the start of the frame.The number of visible
pixels can be varied with the requested frame size.
Dark pixel data (light shielded pixels)
The VS6955CA has 0 dark pixels.
Black pixel data (zero integration time)
The VS6955CA has 0 black pixels.
Manufacturer specific pixel data
The VS6955CA has 0 manufacturer specific pixels.
Interline padding/line blanking
During interline padding all bits in the data stream in a CCP2 frame are set to 1.
In a CSI-2 frame there is no concept of line blanking being transmitted, the sensor simply
spends a longer time in the LP state between active line data.
Interframe padding/frame blanking
During interframe padding all bits in the data stream in a CCP2 frame are set to 1.
In a CSI-2 frame there is no concept of frame blanking being transmitted, the sensor simply
spends a longer time in the LP state at the end of the active data for a frame.
7
Video timing
This section specifies the timing for the image data that is read out from the pixel array and
the output image data. These are not necessarily the same size.
The application of all of the video timing read/write parameters must be re-timed to the start
of the frame boundary to ensure that the parameters are consistent within a frame.
The video stream which is output from the VS6955CA contains both video data and other
auxiliary information.
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7.1
Output size
The VS6955CA has the following methods available to achieve the required output size,
these can be used independently or in conjunction with any other:
•
•
•
•
•
•
analog crop, see Section 7.1.1 on page 53
subsampling, see Section 7.1.4 on page 55
binning, see Section 7.1.3 on page 55
digital cropping, see Section 7.1.5 on page 56
scaling, see Section 7.1.6 on page 56
output crop, see Section 7.1.7 on page 58
The programmable image size and output size are independent functions. It is the
responsibility of the host to ensure that these functions are programmed correctly for the
intended application. These functions also reduce the amount of data and therefore reduce
the peak data rate of CCP2/CSI-2.
Figure 12. Data flow
Imaging array
Analog crop
Binning/subsampling
Digital crop
Scaler
Output crop
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7.1.1
Programmable addressable region of the pixel array
The native size for the VS6955CA is 2592 x 1944, the maximum addressable array is
2600 x 1952 which gives border pixels (outer 4 rows and 4 columns) for the color
reconstruction algorithms to use at the edges of the array.
By programming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers it is
possible to use the full size of the array as you would do for a native size output or you can
select a “window of interest”. The addressed region of the array is used in any subsequent
subsampling or scaling.
Figure 13. Programmable addressable region of the pixel array
x_addr_min, y_addr_min
x_addr_min = 0
y_addr_min = 0
x_addr_start, y_addr_start
x_addr_max = 2600
y_addr_max = 1952
Addressed
pixel array region
x_addr_end, y_addr_end
x_addr_max, y_addr_max
The host must ensure the following rules are kept;
•
•
the end address must be greater than the start address
the x and y start addresses are restricted to even numbers only, and the x and y end
addresses are restricted to odd numbers only, to ensure that there is always a even
number of pixels read out
7.1.2
Programmable width and height for output image data
The x_output_size and y_output_size registers are not intended as the primary cropping
controls.
They are intended to define the position of the LE/FE codes in the CCP or CSI-2 data frame
so that the sensor does not need to calculate this based on region of interest or
subsampling settings. It should be expected that the host will set the output sizes to exactly
enclose the output image data. If the host should not do this, the VS6955CA will treat the
output sizes as being calculated from the top left hand corner of the output array. So in the
case where output sizes are smaller than the output data, the data shall be cropped from its
right hand and lower limits. In the case where larger than the output data, the lines shall be
padded out to the defined output size with undefined data.
Note:
Eight additional columns of dummy data are added to all output images. This should be
taken into account when defining output widths.
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Figure 14. Output size within a CCP data frame
CCP output active line length
Embedded data lines
x_output_size
FS
Output data
FE
Interframe padding
Note:
CCP2 requires that the CCP output active line length (between start and end sync codes)
for:
•
•
RAW8 is a multiple of 4 pixels
RAW10 is a multiple of 16 pixels
The host must control the x_output_size to ensure that the CCP output active line length
(x_output_size + 8) meets the above criteria.
Figure 15. Output size within a dedicated CSI-2 data format
FS
Embedded data
Frame start packet
x_output_size
Bayer pixel
data
Line
blanking
FE
Frame
Frame end packet
blanking
Note:
CSI-2 requires that the CSI-2 output active line length (between start and end sync codes)
for:
•
•
RAW8 is a multiple of 2 pixels
RAW10 is a multiple of 4 pixels
The host must control the x_output_size to ensure that the CSI-2 output active line length
(x_output_size + 8) meets the above criteria.
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7.1.3
Analog pixel binning
The VS6955CA also has a binning mode, sometimes also referred to as analogue Bayer
scaling, that offers a reduced size full field of view image. The pixel binning mode averages
row and column pixel data.
The binning mode results in a reduced number of lines and so can be used to give a higher
image frame rate. Compared to subsampling, analog binning makes use of the light
gathered from the whole pixel array and it results in higher image quality.
The binning mode is scaled by 2 x 2 or by 4 x 4 in the X and Y direction.
7.1.4
Subsampling
Subsampling is achieved by programming the x_odd_inc and y_odd_inc registers.
If the pixel being readout has an even address then the address is incremented by the even
increment value either x_even_inc or y_even_inc. If the pixel being readout has an odd
address then the address is incremented by the odd increment value either x_odd_inc or
y_odd_inc.
The subsampled readout is disabled by setting the odd and even increment values to 1.
(The even increment must always be set to 1.)
Subsampling acts upon the addressed region of the array which is determined by the
x_addr_start, y_addr_start, x_addr_end and y_addr_end registers.
The equation for the sub-sampling factor is given below:
even_inc + odd_inc
sub_sampling_factor = --------------------------------------------------
2
Figure 16. Subsample readout example
1
3
1
3
1
3
Example:
0 1 2 3 4 5 6 7 8 9 10
x_even_inc=1
x_odd_inc=3
y_even_inc=1
y_odd_inc=3
0
1
2
3
4
5
6
7
8
9
10
Gr R
B G
Gr R
B G
Gr R
B G
1
3
Gr R
B G
Gr R
B G
Gr R
B G
1
3
Control range:
Gr R
B G
Gr R
B G
Gr R
B G
min_even_inc=1
min_odd_inc=1
max_even_inc=1
max_odd_inc=19
1
3
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7.1.5
Digital crop
Digital crop can be used in addition to or instead of the analog crop function. It occurs after
the subsampling function. It is affected by the amount of subsampling as well as by the
analog crop. Since the input to the digital crop block is variable, there are no limit registers
associated with digital crop.
Figure 17. Digital crop
digital_crop_y_offset
digital_crop_image_width
digital_crop
digital_crop_image_height
_x_offset
The host must ensure the following rule is kept:
•
the x and y offsets and the image width and height are restricted to even numbers only
Note:
In VS6955CA it is mandatory to maintain a consistency between y_output_size and
digital_crop_image_height to have a similar value.
7.1.6
Scaling
The image scaling function within the sensor provides a flexible way of generating lower
resolution full field of view image data, at a reduced data rates, for viewfinder and video
applications.
The scaler is able to scale the full resolution of the sensor down to within 10% of a the target
image size (the smallest output size is 256x192). This flexibility means that the VS6955CA
can support a wide range of LCD viewfinder sizes and different codec resolutions.
The VS6955CA has two scaling modes which are controlled by the scale_mode_req
register shown in Figure 18.
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Figure 18. Scaling modes
scaling_mode register
Pixel array output
VS6955CA output
0- no scaling
1- horizontal scaling
Scaler quality
The scaler supports two options for the spatial sampling of the scaled image data (see
Figure 19).
•
Bayer sampled scaled image data
The sampling point for the scaler for the output Gr value appears to be in the centre of
the Gr pixel (that is between the first and second pixels and between the first and
second rows of the original input Bayer pixel data). The R (or B) sampling points are
similarly in the centre of the R pixel (or B pixel).
•
Co-sited scaled image data
The sampling point for the Gr, R. Gb and B vales in each output ‘quad’ are functions of
the same color input array pixels such that the spatial sampling point for all four
appears to be in the centre of the ‘quad’ that is between the second and third pixels and
between the first and second rows.
The spatial sampling mode is controlled by the scale_cosite_req register.
Figure 19. Scaler quality
Pixel array output
Bayer sampled scaling
Co-sited sampling
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Down scaler factor
The down scaler factor is controlled by an M/N ratio, scale_m is >= 16 and scale_n is fixed
at 16. scale_m is in the range 16 to 164.
scale_m
scale_n
scale_m
16
down_scale_factor =
=
This single down scale factor is used by the horizontal scalers. The scaler acts upon the
addressed region of the array which is determined by the x_addr_start, y_addr_start,
x_addr_end and y_addr_end registers.
Figure 20. Example image horizontal scaled by a downscale factor of 2
Raw Bayer Image
Horizontal Scaling
Downscale by 2
7.1.7
Output crop
The x_output_size and y_output_size registers are not intended as the primary cropping
controls.
They are intended to define the position of the LE/FE codes in the CCP2 and CSI-2 data
frame to comply with SMIA CCP2 and MIPI CSI-2 data format rules. It is expected that the
host sets the output sizes to exactly enclose the output image data. If the host does not do
this, the VS6955CA treats the output sizes as being calculated from the top left hand corner
of the output array. So in the case where output sizes are smaller than the output data, the
data is cropped from its right hand and lower limits. In the case where larger than the output
data, the lines are padded out to the defined output size with undefined data.
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Figure 21. Output size within a CCP data frame
CCP output active line length
Embedded data lines
x_output_size
FS
Output data
FE
Interframe padding
Note:
CCP2 requires that the CCP output active line length (between start and end sync codes)
for RAW8 is a multiple of 4 and for RAW10 is a multiple of 16.
CSI-2 requires that RAW8 is a multiple of 2 pixels (actual definition is 1 pixel but 2 are
required to preserve the Bayer pattern) and RAW10 is a multiple of 4 pixels (40 bits).
The host must control the x_output_size to ensure that the CCP output active line length
meets the above criteria.
7.1.8
PLL block
The VS6955CA contains a phase locked loop (PLL) block, which generates all the
necessary internal clocks from the external clock input. Changes to the PLL settings on the
VS6955CA are only consumed on the software standby to streaming mode transition.
Figure 22 shows the internal functional blocks, which define the relationship between the
external input clock frequency and the pixel clock frequency.
The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is
clocked by the external input clock.
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Figure 22. VS6955CA clock relationships
PLL output clock
Video timing system clock Video timing pixel clock
pll_op_clk_freq_mhz
vt_sys_clk_freq_mhz
vt_pix_clk_freq_mhz
Max
1000MHz
Max
168MHz
vt_sys_clk
_div
vt_pix_clk
_div
External input clock
ext_clk_freq_mhz
PLL input clock
pll_ip_clk_freq_mhz
Range
2, 4
Min Max
Min
225MHz
Min
30MHz
4
10
Max
27MHz
Max
12MHz
Max
2000MHz
pre_pll_
clk_div
pll_multiplier
Ext.
input
clock
Output Timing Pixel clock
op_pix_clk_freq_mhz
Output Timing System clock
op_sys_clk_freq_mhz
Range
1, 2, 4
Max
332
Min
76
Min
6MHz
Min
900MHz
Min
6MHz
Max
168MHz
Max
1000MHz
op_sys_
clk_div
op_pixel
_clk_div
Min Max
Min
6
Max
10
Min
45MHz
Min
4.5MHz
2
20
The equations relating the input clock frequency to pixel clock frequencies are given below.
ext_clk_freq_mhz × pll_multiplier
vt_pix_clk_freq_mhz = -------------------------------------------------------------------------------------------------------------------------------
pre_pll_clk_div × vt_sys_clk_div × vt_pix_clk_div
ext_clk_freq_mhz × pll_multiplier
op_pix_clk_freq_mhz = -------------------------------------------------------------------------------------------------------------------------------------
pre_pll_clk_div × op_sys_clk_div × op_pix_clk_div
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7.1.9
Framerate
The framerate of the array readout and therefore the output framerate is governed by the
line length, frame length and the video timing pixel clock frequency.
•
•
•
Line length is specified as a number of pixel clocks, line_length_pck.
Frame length is specified as a number of lines, frame_length_lines.
Video timing pixel clock is specified in MHz, vt_pix_clk_freq_mhz.
The equation relating the framerate to the Line length, frame length and the video timing
pixel clock frequency is given below:.
vt_pix_clk_freq_mhz
Framerate = --------------------------------------------------------------------------------------------------
line_length_pck × frame_length_lines
The maximum frame rate that can be achieved in profile 0 for RAW10 is 18 fps with CSI2
single lane. Table 34 provides an example of frame timing for RAW10 mode for 18 fps.
Table 34. External clock frequency example - 5.0 Mpixel RAW10 18 fps (CSI-2 single lane)
Ext clk Pre-PLL PLL VT sys VTpixel VTpixel OP sys OP pixel OP pixel Line Frame
freq
clk div multiplier clk div clk div
clock
clk div
Integer Integer
10
clk div
clock
length length
Integer
(Dec)
Pixel
Clks
Lines
(Dec)
MHz
Integer
Integer Integer
MHz
MHz
9.60
1
208
2
10
99.84
2
99.84
2750
1976
Table 35 provides an example of frame timing for 10-8 mode for 23 fps with CSI-2 single
lane.
Table 35. External clock frequency examples - 5.0 Mpixel 10-8 23 fps (CSI-2 single lane)
Ext clk Pre-PLL PLL VT sys VTpixel VTpixel OP sys OP pixel OP pixel Line Frame
freq
clk div multiplier clk div clk div
clock
clk div
clk div
clock
length length
Integer
(Dec)
Pixel
Clks
Lines
(Dec)
MHz
Integer
Integer Integer
MHz
Integer Integer
MHz
9.60
1
208
2
8
124.8
2
8
124.8
2750
1976
7.1.10
Derating
To provide a wide range of data rate reduction options, the full image scaler is able to
reduce the data and therefore data rates in both the horizontal and vertical directions. In the
VS6955CA this is achieved by the use of a FIFO between video timing and output clock
domains.
It is therefore necessary for the host to configure the OP clock domain to ensure that the
FIFO neither over flows or under flows.
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Figure 23. Timing block diagram
FIFO
Scaler
Pixel array
Tx Logic
Video timing clock domain
Output clock domain
Pre
PLL
VT
Pixel
VT
sys
OP
sys
OP
pixel
PLL
Derating shows the difference between the video timing domain and the output clock
domain.
op_sys_clk_div *
vt_sys_clk_div *
op_pix_clk_div
vt_pix_clk_div
derating =
FIFO
The FIFO is used to implement the data rate reduction required for profile 1 operation.
The concept of an output frame length and a line length for the output timing domain does
not exist for SMIA devices such as the VS6955CA. This is a result of the FIFO input data
patterns being different depending on scaling factor and if the data is co-sited or Bayer
sampled, which results in variable interframe and interline blanking time between lines and
between frames.
Figure 24. SMIA output timing
Line Blanking
CCP Active video
output data:
2600 pixels
By
1952 lines
Output line length
Does Not exist in SMIA
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7.2
Image and video size capabilities
The VS6955CA supports various video modes ranging from VGA@120 fps to HD formats
like 3.8 Mpixel @ 42 fps, 1080p30 and 720p30.
Table 36. Examples of video mode capabilities
Resolution
2600 x 1952
FPS
Mode
Format
23 (max)
18 (max)
5 Mpixel 4:3
5 Mpixel 4:3
RAW8, 10/8
RAW10
Full FOV
2600 x 1952
1080p
16:9 (full horizontal + vertical
crop)
41 (max)
RAW8, 10/8
HD video
capture
16:9 (full horizontal + vertical
crop)
1080p
33 (max)
61 (max)
89(max)
RAW10
720p
3.8 Mpixel 16:9 + Binning 2x2
RAW8, 10/8
RAW8, 10/8
5 Mpixel 4:3 with Binning 2x2 +
2x2 subsampling
VGA
VGA (648x488)
7.3
Bayer pattern
The three color (Red, Green, Blue) filters are arranged over the pixel array in a repeated
2 x 2 arrangement known as the Bayer Pattern. When the pixel array is read, the output
order of red, green, blue depends on the settings of vertical flip and horizontal mirror.
Figure 25 shows the read-out order for the default settings of vertical flip and horizontal
mirror both turned off. Vertical flip changes the first line to be output from a green/red line to
a blue/green line and horizontal mirror changes the sequence within a line, for example,
green/red to red/green.
As shown in Figure 25, the first pixel to be readout from the imaging array is green followed
by red.
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Figure 25. Bayer pattern
6
7
0
1
2
3
4
5
0
Green Red Green Red Green Red Green Red
Blue Green Blue Green Blue Green Blue Green
1
2
3
Green Red Green Red Green Red Green Red
Blue Green Blue Green Blue Green Blue Green
4
5
Green Red Green Red Green Red Green Red
Blue Green Blue Green Blue Green Blue Green
1952 active rows
2600 active columns
1946
1947
1948
1949
1950
1951
Green Red Green Red Green Red Green Red
Blue Green Blue Green Blue Green Blue Green
Green Red Green Red Green Red Green Red
Blue Green Blue Green Blue Green Blue Green
Green Red Green Red Green Red Green Red
Blue Green Blue Green Blue Green Blue Green
2598 2599
2592 2593 2594 2595 2596 2597
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7.4
Image compression
The objective of image compression is to reduce the required bandwidth in transmission
between the sensor and the host.
The key features of the DPCM/PCM compression algorithm are:
•
•
•
visually lossless
low cost implementation (no line memories are required)
fixed rate compression
The 10-bit to 8-bit DPCM/PCM image compression algorithm is supported by VS6955CA.
10-bit to 8-bit compression has the additional advantage that one pixel value equals
one byte of data.
The level of compression is controlled through the CSI_data_format register. The same
register is also used to enable and disable compression.
The compression_mode register is used to select which compression algorithm is used.
Currently only the DPCM/PCM technique is supported. Therefore the value of this register is
always 0x01.
The compression_capability register tells the host whether a sensor does or does not have
compression and if it has compression then what is the compression technique. Currently
only the DPCM/PCM technique is supported.
Also refer to section 10 of the SMIA1.0 specification document.
7.5
Exposure and gain control
VS6955CA does not contain any form of automatic exposure control. To produce a correctly
exposed image the integration period and analogue gain for the pixels must be calculated
by an exposure control algorithm implemented externally. The parameters are then written
to the VS6955CA through the CCI interface.
The exposure control parameters available on VS6955CA are:
•
•
•
•
fine integration time
coarse integration time
analog gain
digital gain
The exposure control parameter registers are defined in Section 4.2.6: Integration and gain
registers [0x0200 to 0x0215] on page 30.
Integration time and analogue gain capability registers should be used to determine the
exposure control parameter limits for a given video timing configuration. See Section 6.7 of
the SMIA 1.0 part 1 specification for more information on how to interpret the integration and
gain capability registers and how to calculate exposure and gain limits.
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7.5.1
Analogue gain model
VS6955CA only supports the single global analogue gain mode. VS6955CA has a 16-bit
register (0x0204 and 0x0205) to control analogue gain.
Figure 26 shows the way the analogue gain bits are used for VS6955CA. Use only Coarse
Gain bits for standard 1/x functionality.
Figure 26. Analogue gain register format
A15 A14 A13 A12 A11 A10 A9 A8
Not used
A7 A6 A5 A4
Coarse gain
A3 A2
A1 A0
Fine gain Not used
The following generic equation describes VS6955CA coarse gain behavior specified by the
analogue gain description registers 0x008A to 0x0093:
gain = c0 ⁄ (m1 ⋅ x + c1)
where:
m1 = -1
c0 = 256
c1 = 256
Table 37 specifies the valid analogue gain values for VS6955CA.
Table 37. Analogue gain control
Gain value
(0x0204/0x0205)
Coarse gain code Coarse analogue Fine gain code
Fine analogue
gain
[A7:A4]
gain
[A3:A2]
0x0000
0x0010
0x0020
0x0030
0x0040
0x0050
0x0060
0x0070
0x0080
0x0090
0x00A0
0x00B0
0x00C0
0x00D0
0x00E0
0x00E4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1110
0.0 dB (x1.00)
0.6 dB (x 1.07)
1.1 dB (x1.14)
1.8 dB (x1.23)
2.5 dB (x1.33)
3.2 dB (x1.45)
4.1 dB (x1.60)
5.0 dB (x1.78)
6.0 dB(x2.00)
7.2 dB (x2.29)
8.5 dB (x2.66)
10.1 dB (x3.20)
12.0 dB (x4.00)
14.5 dB (x5.33)
18.1 dB (x8.00)
fine ctrl
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
19.2 dB (x9.14)
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Table 37. Analogue gain control (continued)
Coarse gain code Coarse analogue Fine gain code
Gain value
(0x0204/0x0205)
Fine analogue
gain
[A7:A4]
gain
[A3:A2]
0x00E8
0x00EC
0x00F0
1110
1110
1111
fine ctrl
fine ctrl
10
11
00
20.6 dB (x10.66)
22.1 dB (x12.80)
N/A
24.1 dB (x16.00)
Also refer to section 6.3 of the SMIA1.0 specification document.
7.5.2
Digital gain
To help compensate for the relatively coarse analogue gain steps, VS6955CA contains a
digital multiplier to “fill” in the missing steps. By mixing analogue and digital gain it is
possible to implement 3% gain steps across the full 1x to 16x gain range
The details of the digital gain implementation are listed below:
•
four individual 16-bit digital channel gains - one per Bayer channel
–
–
–
–
digital_gain_greenR (0x020E and 0x020F)
digital_gain_red (0x0210 and 0x0211)
digital_gain_blue (0x0212 and 0x0213)
digital_gain_greenB (0x0214 and 0x0215)
•
the digital gain range for each channel is 1.000 to 1.96875 in steps of 0.03125 (1/32),
that is, 5 fractional bits
–
–
–
digital_gain_min {0x1084:0x1085} = 0x0100 (1.00)
digital_gain_max {0x1086:0x1087} = 0x01F8 (1.96875)
digital_gain_step {0x1088:0x1089} = 0x0008 (0.03125)
7.5.3
Integration and gain parameter re-timing
The modification of exposure parameter (integration time, analog and digital gain) register
values does not take effect immediately.
The exact time at which changes to certain parameters take effect is controlled both to
ensure that each frame of image data produced has consistent settings and that changes in
groups of related parameters can be synchronized.
A group of parameter changes is marked by the host using a dedicated Boolean control
parameter, grouped_parameter_hold (register 0x0104). Any changes made to ‘retimed’
parameters while the grouped_parameter_hold signal is in the ‘hold’ state will be considered
part of the same group. Only when the grouped_parameter_hold control signal is moved
back to the default ‘no-hold’ state will the group of changes be executed.
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Test modes
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8
Test modes
This chapter describes the test modes supported by the VS6955CA.
8.1
Full frame deterministic test patterns
Two types of full frame deterministic test patterns are defined. The Bayer test patterns are
more suitable for some deterministic tests than real image data and are injected early in the
sensor data path. The only exception to this is the PN9 test pattern that is intended to test
sensor-host link integrity, the data in this pattern is not Bayer data and is injected into the
data stream just prior to CSI framing.
Use of these full frame test patterns is controlled by the test_pattern_mode parameter
(register 0x0600 and 0x0601). The available modes are:
•
•
•
•
•
0 – Normal operation (default)
1 – Solid color
2 – 100% color bars
3 – ‘Fade to gray’ color bars
4 – PN9
In both the default parameter state and in any undefined parameter states, normal array
data should be output rather than a test pattern.
8.1.1
8.1.2
Solid color mode
In the solid color test pattern mode, all active pixel data is replaced with fixed Bayer test data
that is defined by the four 16-bit test data color parameters registers (0x0602 to 0x609).
These are 10-bit values.
100% color bars pattern mode
In the ‘100% color bar’ test pattern mode, all pixel data is replaced with a Bayer version of
an 8-bar color bar pattern. In each bar all pixels are either 0% or 100% full scale (for
example, 100/0/100/0 bars).
Figure 27. 100% color bars
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Test modes
8.1.3
‘Fade to gray’ color bar mode
In the ‘fade to gray’ color bar test pattern mode, all pixel data is replaced with a color bar that
fades vertically from 100% color bars to mid gray. The ‘fade to gray’ color bar pattern is
designed to exercise more of the color space than 100% bars whilst still requiring minimal
hardware overhead. Figure 28 gives an indication of the pattern (although the pattern is
generated as Bayer data).
Figure 28. ‘Fade to gray’ color bars
The pattern is made up of eight vertical bars that fade vertically from one of the 100% color
bar colors towards a mid-gray at the bottom. The bars follow the same order as standard
color bars. Each of the bars is sub-divided vertically into a left hand side that contains a
smooth gradient and a right hand size that contains a quaintest version.
The aim of the quaintest portion is to offer areas of flat-field Bayer data that should be large
enough to result in known data values even after demosiac (independently of the demosiac
algorithm). To ensure maximum dynamic range in the quaintest data, the LSBs of the
quaintest data is generated by copying the MSBs of the unquantized data (rather than
forcing them to 0). The pattern may roll over and repeat if the frames is long enough.
8.1.4
PN9 mode
In the ‘PN9’ test pattern mode, all data on all lines between FS and LS code and the LE or
FE code is replaced with data from internally generated 511-bit pseudo-random ‘PN9’
sequence.
Figure 29. PN9 linear feedback filter
X9 + X5 + 1
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0 = 1
D1
D2
D3
D4
D5
D6
D7
D8
D9
The PN9 test pattern is included to ease testing of sensor-link integrity (for example,
measurement of bit error rate). The standard PN9 linear feedback shift register with
9
5
polynomial X +X +1 in Fibonacci-type notation is shown in Figure 29. The PN9 sequence
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Test modes
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generator is reset at the start of the frame, the sequence is then in a known state (0x1FF) at
the first replaced pixel of each frame.
Note:
The frame format descriptors do not correctly report the frame format in this mode.
8.2
Test cursors
In addition to generation of full frame deterministic test patterns, VS6955CA sensor can
superimpose simple ‘cursors’ on the image. These cursors don’t appear on the PN9 test
mode.
The cursors are generated by replacing Bayer pixel data with fixed Bayer data within narrow
vertical and/or horizontal bands of the image. Injection of the test cursors must be arranged
such that the cursors can be superimposed on top of the full frame test patterns as well as
array image data.
Two cursors are defined, one vertical cursor and one horizontal. The four parameters
described in Table 38 are used to control the cursors. The position and width of each cursor
can be controlled manually. Each cursor can be inhibited by setting its width parameter to
zero. A value of 0xFFFF in register vertical_cursor_position switches the vertical cursor into
automatic mode where it automatically advances every frame (the initial position of the
automatic cursor is undefined). The first pixel of the cursor replaces the pixel data at the
horizontal_cursor_position-1 pixel. the width of the cursor can incremented in steps of one.
The maximum valid value for horizontal_cursor_position and vertical_cursor_position is the
associated x output size.
Table 38. Registers used to define the output data
Index
Byte
Register name
0x060A
0x060B
0x060C
0x060D
0x060E
0x060F
0x0610
0x0611
Hi
Lo
Hi
horizontal_cursor_width
horizontal_cursor_position
vertical_cursor_width
Lo
Hi
Lo
Hi
vertical_cursor_position
Lo
The four registers used to define the output data in solid color mode also define the Bayer
data used for the image cursors.
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Defect categorization
9
Defect categorization
9.1
Pixel defects
9.1.1
Overview
Pixel defect density measures the average number of defective pixels per color channel
under “Diffuse” and “Dark” conditions, refer to Table 39: Pixel defect specification.
Table 39. Pixel defect specification
Reference Area
Full Channel
9x9
Threshold
64 codes
+/-12%
Dark
Light
9.1.2
Defect detection
Defect detection is performed in two parts; once in diffuse conditions and once in dark
conditions, as defined in Table 40: Image settings. The methods used for these differ to
account for the differing conditions and for the difference in the failure modes detected by
each.
Table 40. Image settings
Dark
Diffuse
Exposure
100ms
x8
33ms(1)
x1
Analog gain
Digital gain
x1
x1
1. Image exposure targets 75% of full-scale deflection in the green channels at
the centre of the image.
In both the dark and light cases, two images are averaged pixel-by-pixel in order to reduce
the impact of temporal noise. Detection is performed individually on the four colour
channels.
“Dark defects” are those which appear too bright in a dark image, either due to dark current
or a stuck-at fault. These are measured by thresholding against the difference between the
actual pixel value and the local or full-frame average (this is dependent on the uniformity of
the dark image). The threshold is defined such that it can identify gain error above the
normal noise distribution of photon shot noise and sensor noise and so pixels that deviate
by more than the dark threshold are declared defective.
“Light defects” tend to be caused by small foreign material or damage to the die surface.
The diffused image is processed to remove very low frequency variation by gaining the
image towards the centre peak value for each colour channel, mimicking the lens shading
gains applied in the application. Pixels that deviate from the local average by more than the
light threshold in either direction are defined as defective. The 64-code pedestal is not
removed from this relative calculation.
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9.1.3
Defect categorisation: Single pixels
Figure 30. shows the numbering of the neighboring pixels in a 3x3 grid within a single color
channel; all the pixels will either be red, green-red, green-blue or blue. The pixel under test
is X. If a pixel under test is on the edge on the image, the array is reduced to its existing
neighbor pixels (i.e. the top-left pixel uses only a 2x2 array).
Figure 30. Pixel numbering notation
[0] [1] [2]
[7]
X
[3]
[6] [5] [4]
A single pixel fail is defined as a failing pixel with no adjacent failing pixels in the neighboring
pixels 0 to 7. A single pixel fail can be a stuck at white, where the output of the pixel is
permanently saturated regardless of the level of incident light and exposure level, a stuck at
black where the pixel output is zero regardless of the level of incident light and exposure
level (major fail) or simply a pixel that differs from its immediate neighbors by more than the
test threshold (minor fail).
In the example in Figure 31, shown, we assume that pixel X is a failing pixel. For this pixel to
be categorised as a single pixel fail, the pixels at positions [0], [1], [2], [3], [4], [5], [6] and [7]
must be "good" pixels that pass final test. The test program will pass a sensor with up to the
defined limit of single pixel faults per colour channel.
Figure 31. Single pixel fault
[0] [1] [2]
[7]
X
[3]
[6] [5] [4]
9.1.4
Defect categorisation: Couplets
A couplet is formed by a failing pixel at X neighboring a failing pixel at position [0] or [1] or [2]
or [3] or [4] or [5] or [6] or [7], such that there is a maximum of 2 failing pixels from the group
of 9 pixels. The example shown in Figure 32: Couplet pixel fault has the centre pixel and the
pixel at position [7] failing the test criteria.
Figure 32. Couplet pixel fault
[0] [1] [2]
[7]
X
[3]
[6] [5] [4]
This product has on-chip mapped couplet correction capable of storing up to 14 defect
locations. No unmapped couplets are allowed in a full resolution image.
9.1.5
Defect categorisation: Clusters and blobs
If pixel X is a failure and between 2 and 7 of the surrounding pixels are also defective, then
the pixels are categorised as a cluster. If all nine pixels are defective then the failure is
classified as a blob. Neither clusters nor blobs are allowed.
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9.2
Mapped couplet correction (Bruce filter)
The mapped couplet defect correction filter is designed to intelligently correct the first defect
in a couplet thereby changing a couplet into a single pixel defect. Single pixel correction is
achieved by the host (coprocessor, MMP or baseband). The mapped couplet correction filter
only operates in full resolution mode.
The mapped couplet correction filter requires exact coordinate information for each of the
couplets to be repaired. The couplet coordinates are stored in non-volatile-memory (NVM)
during production test.
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Electrical characteristics
VS6955CA
10
Electrical characteristics
10.1
Absolute maximum ratings
Table 41. Absolute maximum ratings
Symbol
Parameter
Minimum
Maximum
Unit
VDIGMAX Digital power supply
VANAMAX Analog power supply
-0.5
-0.5
-0.5
-40
2.2
3.2
V
V
VIHMAX
TSTO
CCI signals, system clock input
2.2
V
Storage temperature
+85(1)
oC
Electrostatic discharge model
Human body model
Charge device model(2)
-2.0
2.0
kV
V
VESD
-250
250
1. This is a maximum long term standard storage temperature, see soldering profile for short term high
temperature tolerance.
2. CDM tests are performed in compliance with JESD22-C101D.
Caution:
Stresses above those listed under “Absolute maximum ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of the
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
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Electrical characteristics
10.2
Operating conditions
Table 42. Operating conditions
Symbol
Voltage
Parameter
Minimum
Typical
Maximum
Unit
VDIG
VANA
Digital power supply
Analog power supply
1.62
2.6
1.80
2.80
1.98
2.9
V
V
Temperature
TAS
TAF
TAN
TAO
TAT
Temperature (storage)(1)
-40
-30
-25
+5
-
-
-
-
-
+85
+70
+55
+40
+25
°C
°C
°C
°C
°C
Temperature (functional operating)(2)
Temperature (normal operating)(3)
Temperature (optimal operating)(4)
Temperature (test)(5)
+21
1. Device has no permanent degradation.
2. Device is electrically functional.
3. Device produces ‘acceptable’ images.
4. Device produces optimal optical performance.
5. 100% tested parameters are measured at this temperature.
10.3
DC electrical characteristics
In this section, typical values are quoted for nominal voltage, process and temperature and
maximum values are quoted for worst case conditions (process, voltage and functional
temperature) unless otherwise specified.
10.3.1
Power supply - VDIG, VANA
Table 43. Power supply - VDIG, VANA
Digital
Analog
Typical
Parameter
Unit
Typical
Max
Max
Hardware standby
5.0 Mpixel 4:3 streaming(1)
10
30
45
40
3
35
90
µA
:
68
mA
1. Profile 0, 15 fps, CSI-2 single lane, 10-10 data, 9.6 MHz external clock.
10.3.2
CCI interface
Table 44. CCI interface
Symbol
VIL
VIH
Parameter
Minimum
Maximum
Unit
Low level input voltage
High level input voltage
-0.5
0.3*VDIG
VDIG+0.5
V
V
0.7*VDIG
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Electrical characteristics
Symbol
VS6955CA
Unit
Table 44. CCI interface (continued)
Parameter
Low level output voltage(1)
Minimum
Maximum
VOL
VOH
IIL
0
0.2*VDIG
VDIG
-10
V
V
High level output voltage
Low level input current
High level input current
0.8*VDIG
-
-
µA
µA
IIH
10
1. 3 mA sink current.
10.4
AC electrical and timing characteristics
In this section, typical values are quoted for nominal voltage, process and temperature and
maximum values are quoted for worst case conditions (process, voltage and functional
temperature).
10.4.1
Power supply (peak current) - VDIG, VANA
The peak current (in-rush) consumption of the sensor module is defined as any current
pulse >= 10µs. The duty cycle of the peak to the low part of the current profile is 33% with a
worst-case period of 500 µs.
Table 45. In-rush current - VDIG, VANA (CSI-2)
Digital
Analog
Parameter
Unit
Typical
Maximum
Typical
Maximum
Boot clock peak current(1)
Start streaming current(2)
Stop streaming current(3)
80
80
80
100
100
105
200
200
100
230
210
140
mA
mA
mA
1. This corresponds to the transient current when the module is powered up and the sensor is being set to
SW_Standby mode. Maximum value is given for maximum supply voltages and 70°C ambient temperature.
Typical value is for 25°C ambient temperature and supply voltages set to nominal value.
2. When the sensor is changed from software standby to streaming mode. Maximum value is given for
maximum supply voltages and 70°C ambient temperature. Typical value is for 25°C ambient temperature
and supply voltages set to nominal value.
3. When the sensor is changed from streaming to software standby. Maximum value is given for maximum
supply voltages and 70°C ambient temperature. Typical value is for 25°C ambient temperature and supply
voltages set to nominal value.
10.4.2
System clock - EXTCLK
Table 46. System clock
Symbol
VCL
Parameter
Minimum
Maximum
Unit
DC coupled square wave low level
DC coupled square wave high level
Clock frequency input
-0.5
0.3*VDIG
VDIG+0.5
27 + 1%(1)
V
V
VCH
0.7*VDIG
6.0 - 1%(1)
fEXTCLK
MHz
1. Nominal frequencies are 6.0 to 27 MHz with a 1% centre frequency tolerance.
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Electrical characteristics
10.4.3
EXTCLK - timing characteristics
Table 47. External clock timing characteristics
Symbol
Tjitter
Parameter
Input clock jitter
Minimum
Maximum
Unit
-
100
ps
Figure 33. External clock timing
EXTCLK
T
jitter
10.4.4
CCI interface - timing characteristics
Table 48. CCI interface timing characteristics
Symbol
tSCL
Parameter
SCL clock frequency
Minimum
Maximum
Unit
0
400
kHz
ms
ms
ms
ms
ms
ms
ns
tLOW
tHIGH
tBUF
Clock pulse width low
Clock pulse width high
Bus free time between transmissions
Start hold time
1.3
0.6
1.3
0.6
0.6
0
-
-
-
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
-
-
Start set-up time
Data in hold time
0.9
-
Data in set-up time
100
(1)
SCL/SDA rise time
20+0.1 Cb
300
300
-
ns
(1)
tF
SCL/SDA fall time
20+0.1 Cb
ns
tSU.STO
Ci/o
Stop set-up time
0.6
ms
pF
pF
Input/output capacitance (SDA)
Input capacitance (SCL)
-
-
8
Cin
6
1. Cb = total capacitance of one bus line in pF
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Figure 34. CCI AC characteristics
stop
start
start
stop
0.9 VDIG
0.1 VDIG
SDA
...
tHD.STA
tBUF
tLOW tR
tF
0.9 VDIG
0.1 VDIG
SCL
...
tHD.STA
tHD.DAT
tHIGH
tSU.DAT
tSU.STA
tSU.STO
All timings are measured from either 0.1 VDIG or 0.9 VDIG.
For further information on the CCI interface, refer to the following specification documents:
MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2).
10.4.5
CSI interface - DATA+, DATA-, CLK+, CLK-
Table 49. CSI interface - DATA+, DATA-, CLK+, CLK- characteristics
Symbol
VOD
Parameter
Minimum
Typical
Maximum
Unit
HS transmit differential voltage(1)
140
200
270
mV
HS transmit static common mode
voltage
VCMTX
150
200
50
250
mV
ZOS
Single ended output impedance
20% to 80% rise time and fall time
40
62.5
Ω
tr and tf
150
0.3UI(2)
ps
1. Value when driving into load impedance anywhere in the ZID range (80 to 125Ω).
2. UI is equal to 1/(2*fh) where fh is the fundamental frequency of the transmission for a certain bit rate. For
example, for 600 Mbps fh is 300 MHz.
Note:
For further information on the D-PHY, refer to the following specification document:
MIPI Alliance Standard for D_PHY.
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Mechanical
11
Mechanical
Figure 35. VS6955CA outline drawing - 1 of 3 - All dimensions in mm
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Mechanical
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Figure 36. VS6955CA outline drawing - 2 of 3 - All dimensions in mm
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Mechanical
Figure 37. VS6955CA outline drawing - 3 of 3 - All dimensions in mm
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Cosmetic inspection
VS6955CA
12
Cosmetic inspection
The cosmetic inspection criteria used for the camera module is based on the demerit
system to gauge the length and width of imperfections. It should be noted that the depth or
height of an imperfection does not affect the form, fit or function of the camera module
particularly with regard to the camera socket on the phone platform.
Areas of the camera module are given a surface class of A, B or C. This is detailed in
Table 50 and Figure 38.
Note:
The camera module comprises of class A and C surfaces, none are class B.
The camera module is inspected, in normal lighting conditions using the naked eye at
30 cm, for scratches, chips, marks, foreign material inclusions and discoloration. The length
and width of these imperfections are measured and awarded demerit points. If there is more
than one imperfection, the demerit points are accumulated.
Figure 38. Inspection areas on the VS6955CA
Class A face
3.2 mm diameter
around lens centre.
Area outside Class A
is Class C
Class C faces
Cosmetic inspection should be carried out using the naked eye at 30 cm in normal office
lighting. Scratches and marks are permitted on the shield.
Refer to the outline drawing for the definition of the cosmetic class A surface.
Table 50. Surface class definitions
Surface class
Surface description
Reject demerit level
Primary surface exposed to direct view in ordinary use by
customer – top face only.
‘A’
1 or more
Secondary surface exposed, but not in direct view in
ordinary use. No class B surfaces for this camera module.
‘B’
‘C’
6 or more
Surface not visible in ordinary use – all other surfaces other
than A above.
10 or more
The demerit system covers - scratches, chips, marks, foreign material inclusions,
discoloration of parts and is detailed in Table 51. The depth or height of an imperfection
does not affect the form, fit or function of the camera module particularly with regard to the
camera socket on the phone platform.
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Cosmetic inspection
Demerit points
Table 51. Demerit points
Length/width of imperfection
>3.5mm
8
6
5
4
3
2
1
0
2.5mm - 3.5mm
2.0mm - 2.5mm
1.5mm - 2.0mm
1.0mm - 1.5mm
0.8mm - 1.0mm
0.4mm - 0.8mm
< 0.4mm
Examples of pass/fail
Table 52. Examples of pass/fail
Imperfection
Surface class
Pass/Fail
A
A
C
0.3mm scratch, 0 demerit
Pass
Fail
0.5mm scratch, 1 demerit
3.4mm mark, 6 demerits
Pass
0.9mm scratch, 2 demerits; 1.4mm mark, 3 demerits
- Total 5 demerits
C
C
Pass
Fail
2 * 2.6mm scratches, 2 * 6 demerits = 12 demerits
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Packaging and delivery
VS6955CA
13
Packaging and delivery
Figure 39. Marking diagram
2955
PLLL
YWWA
Substrate marking codification
Line one:
Line two:
Product code
P is the assembly plant
LLL is the B/E sequence
Line three:
Y is the year
WW is the week number
A is the module revision
The VS6955CA packing is tape and reel.
Inner box labeling
Figure 40. Example of ST inner box label
The labeling follows the ST standard packing acceptance specification.
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Application
The information on the inner box label is the following:
•
•
•
•
•
•
•
assembly site
moisture sensitivity level (Jedec Level 0)
order code
quantity
trace code
marking (product name + NMP code for NMP products)
QA number
14
Application
Figure 41. Mobile camera application
External clock
VS6955CA
EXTCLK
.
.
.
1.8V
VDIG
DATA+
27pF
1.5uF
100R
100R
SubLVDS data
DATA-
CLK+
.
.
.
2.8V
VANA
1.5uF
27pF
SubLVDS clock
CLK-
Power down signal
XSHUTDOWN
1.8V
4.7k
SCL
SDA
CCI control lines
GND
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Acronyms and abbreviations
VS6955CA
15
Acronyms and abbreviations
Table 53. Acronyms and abbreviations
Definition
Acronym/
abbreviation
CCI
Camera control interface
CMI
CSI
Camera module integrator
Camera serial interface
Differential pulse code modulation
Electromagnetic compatibility
Electromagnetic interference
End of frame
DPCM
EMC
EMI
EOF
EOT
FE
End of transmission
Frame end
fps
Frames per second
FS
Frame start
HS
High speed; identifier for operation mode
High speed receiver (low-swing differential)
High speed transmitter (low-swing differential)
Inter ICbus
HS-RX
HS-TX
I2C
LE
Line end
LLP
LS
Low level protocol
Line start
LSB
LP
Least significant byte
Low power; identifier for operation mode
Low power receiver (large-swing single ended)
Low power transmitter (large-swing single ended)
Low voltage differential signaling
Megabits per second
LP-RX
LP-TX
LVDS
Mbps
MIPI
MSB
PCK
PCM
PF
Mobile industry processor interface
Most significant byte
Pixel clock
Pulse code modulation
Packet footer
PH
Packet header
PI
Packet identifier
PT
Packet type
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Acronyms and abbreviations
Table 53. Acronyms and abbreviations (continued)
Definition
Acronym/
abbreviation
PHY
Physical layer
PLL
Phase locked loop
Read only
RO
RW
Read/write
SCL
Serial clock (for CCI)
Serial data (for CCI)
SDA
SMIA
SOT
Standard mobile imaging architecture
Start of transmission
SOF
Start of frame
SSCG
SubLVDS
WDR
ULPM
Spread spectrum clock generator
Sub-low voltage differential signaling
Wide dynamic reconstruction
Ultra low power mode
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®
ECOPACK
VS6955CA
®
16
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
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Revision history
17
Revision history
Table 54. Document revision history
Date
Revision
Changes
10-Sep-2015
02-Nov-2015
1
2
Initial release.
update Table 9: Status registers [0x0000 to 0x001F]
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